Texas Instruments | TCA9548A-Q1 Automotive 8-Channel I2C Switch with Reset (Rev. A) | Datasheet | Texas Instruments TCA9548A-Q1 Automotive 8-Channel I2C Switch with Reset (Rev. A) Datasheet

Texas Instruments TCA9548A-Q1 Automotive 8-Channel I2C Switch with Reset (Rev. A) Datasheet
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TCA9548A-Q1
SCPS273A – MAY 2019 – REVISED NOVEMBER 2019
TCA9548A-Q1 Automotive 8-Channel I2C Switch with Reset
1 Features
3 Description
•
The TCA9548A-Q1 device has eight bidirectional
translating switches that can be controlled through
the I2C bus. The SCL/SDA upstream pair fans out to
eight downstream pairs, or channels. Any individual
SCn/SDn channel or combination of channels can be
selected, determined by the contents of the
programmable control register. These downstream
channels can be used to resolve I2C slave address
conflicts. For example, if eight identical digital
temperature sensors are needed in the application,
one sensor can be connected at each channel: 0-7.
1
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•
•
•
•
•
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•
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AEC-Q100 Qualified for automotive applications:
– Temperature grade 3: -40°C to +85°C, TA
1-to-8 Bidirectional translating switches
I2C Bus and SMBus compatible
Active-low reset input
Three address pins, allowing up to eight
TCA9548A-Q1 devices on the I2C bus
Channel selection through an I2C Bus, in any
combination
Power up with all switch channels deselected
Low RON switches
Allows voltage-level translation between 1.8-V,
2.5-V, 3.3-V, and 5-V buses
No glitch on power up
Supports hot insertion
Low quiescent current
Operating power-supply voltage range of
1.65 V to 5.25 V
5-V Tolerant Inputs
0- to 400-kHz clock frequency
Latch-up performance exceeds 100 mA per JESD
78, class II
The system master can reset the TCA9548A-Q1 in
the event of a time-out or other improper operation by
asserting a low in the RESET input. Similarly, the
power-on reset deselects all channels and initializes
the I2C/SMBus state machine. Asserting RESET
causes the same reset and initialization to occur
without powering down the part. This allows recovery
should one of the downstream I2C buses get stuck in
a low state.
The pass gates of the switches are constructed so
that the VCC pin can be used to limit the maximum
high voltage, which is passed by the TCA9548A-Q1.
Limiting the maximum high voltage allows the use of
different bus voltages on each pair, so that 1.8-V, 2.5V or 3.3-V parts can communicate with 5-V parts,
without any additional protection. External pull-up
resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5-V tolerant.
2 Applications
•
•
•
•
•
Infotainment
Body and control
Routers (telecom switching equipment)
Factory automation
Products with I2C slave address conflicts (such as
multiple, identical temperature sensors)
Device information(1)
PART NUMBER
TCA9548A-Q1
PACKAGE
BODY SIZE (NOM)
VQFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified application diagram
VCC
I2C or SMBus
Master
Channel 0
SDA
SCL
SD0
SC0
RESET
SD1
SC1
(processor)
Slaves A0, A1...A N
Channel 1
Slaves B0, B1...B N
TCA9548A-Q1
A0
A1
A2
GND
SD2
SC2
Channel 2
Slaves C0, C1...CN
Channel 7
SD7
SC7
Slaves H0, H1...HN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA9548A-Q1
SCPS273A – MAY 2019 – REVISED NOVEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
6
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C InterfaceTiming Requirements............................
Reset Timing Requirements .....................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 13
8.5 Programming........................................................... 13
9
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application .................................................. 19
10 Power Supply Recommendations ..................... 23
10.1 Power-On Reset Requirements ........................... 23
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (May 2019) to Revision A
•
2
Page
VCC value missing, added VCC = 2.5 V in Figure 12 ............................................................................................................. 20
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SCPS273A – MAY 2019 – REVISED NOVEMBER 2019
5 Pin Configuration and Functions
RESET
A1
A0
VCC
SDA
SCL
24
23
22
21
20
19
RGE Package
24-Pin VQFN
Top View
SD0
1
18
A2
SC0
2
17
SC7
SD1
3
16
SD7
15
SC6
Thermal
Pad
11
12
SD5
SC5
SC4
13
10
6
SD4
SC2
9
SD6
8
14
SC3
5
GND
SD2
7
4
SD3
SC1
Not to scale
Pin Functions
PIN
QFN
(RGE)
TYPE
A0
22
I
Address input 0. Connect directly to VCC or ground
A1
23
I
Address input 1. Connect directly to VCC or ground
A2
18
I
Address input 2. Connect directly to VCC or ground
GND
9
—
RESET
24
I
SD0
1
I/O
Serial data 0. Connect to VDPU0 (1) through a pull-up resistor
SC0
2
I/O
Serial clock 0. Connect to VDPU0 (1) through a pull-up resistor
SD1
3
I/O
Serial data 1. Connect to VDPU1 (1) through a pull-up resistor
SC1
4
I/O
Serial clock 1. Connect to VDPU1 (1) through a pull-up resistor
SD2
5
I/O
Serial data 2. Connect to VDPU2 (1) through a pull-up resistor
SC2
6
I/O
Serial clock 2. Connect to VDPU2 (1) through a pull-up resistor
SD3
7
I/O
Serial data 3. Connect to VDPU3 (1) through a pull-up resistor
SC3
8
I/O
Serial clock 3. Connect to VDPU3 (1) through a pull-up resistor
SD4
10
I/O
Serial data 4. Connect to VDPU4 (1) through a pull-up resistor
SC4
11
I/O
Serial clock 4. Connect to VDPU4 (1) through a pull-up resistor
SD5
12
I/O
Serial data 5. Connect to VDPU5 (1) through a pull-up resistor
SC5
13
I/O
Serial clock 5. Connect to VDPU5 (1) through a pull-up resistor
SD6
14
I/O
Serial data 6. Connect to VDPU6 (1) through a pull-up resistor
SC6
15
I/O
Serial clock 6. Connect to VDPU6 (1) through a pull-up resistor
SD7
16
I/O
Serial data 7. Connect to VDPU7 (1) through a pull-up resistor
SC7
17
I/O
Serial clock 7. Connect to VDPU7 (1) through a pull-up resistor
SCL
19
I/O
Serial clock bus. Connect to VDPUM (1) through a pull-up resistor
SDA
20
I/O
Serial data bus. Connect to VDPUM (1) through a pull-up resistor
VCC
21
Power
NAME
(1)
DESCRIPTION
Ground
Active-low reset input. Connect to VCC or VDPUM (1) through a pull-up resistor, if not used
Supply voltage
VDPUX is the pull-up reference voltage for the associated data line. VDPUM is the master I2C reference voltage and VDPU0-VDPU7 are the
slave channel reference voltages.
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SCPS273A – MAY 2019 – REVISED NOVEMBER 2019
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage
–0.5
7
VI
Input voltage (2)
–0.5
7
V
II
Input current
–20
20
mA
IO
Output current
–25
ICC
Supply current
–100
100
mA
Tstg
Storage temperature
–65
150
°C
TJ
Max Junction Temperature
90
℃
(1)
(2)
UNIT
V
mA
VCC ≤ 5.25 V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 2
±2000
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
VCC
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
MIN
MAX
UNIT
1.65
5.25
V
SCL, SDA
0.7 × VCC
6
A2–A0, RESET
0.7 × VCC
VCC + 0.5
SCL, SDA
–0.5
0.3 × VCC
A2–A0, RESET
–0.5
0.3 × VCC
1.65 V ≤ VCC ≤ 5.25 V
–40
85
-40 ℃ ≤ TA ≤ 85 ℃
Supply voltage
V
V
°C
6.4 Thermal Information
TCA9548A
THERMAL METRIC (1)
RGE (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
57.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
62.5
°C/W
RθJB
Junction-to-board thermal resistance
34.4
°C/W
ψJT
Junction-to-top characterization parameter
3.8
°C/W
ψJB
Junction-to-board characterization parameter
34.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
15.5
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SCPS273A – MAY 2019 – REVISED NOVEMBER 2019
6.5 Electrical Characteristics (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VPORR
Power-on reset voltage, VCC rising
No load, VI = VCC or GND (2)
VPORF
Power-on reset voltage, VCC falling (3)
No load, VI = VCC or GND (2)
VCC
MIN
TYP
MAX
1.2
1.5
0.8
5V
2.6
3.3 V
Switch output voltage
Vi(sw) = VCC, ISWout = –100 μA
3 V to 3.6 V
1.1
SCL, SDA
SC7–SC0, SD7–SD0
II
A2–A0
VI = VCC or GND
(2)
1.65 V to 5.25 V
RESET
VI = VCC or GND (2), IO = 0
Operating mode
fSCL = 100 kHz
VI = VCC or GND (2), IO = 0
ICC
Low inputs
VI = GND (2), IO = 0
Standby mode
High inputs
Supply-current
change
ΔICC
SCL, SDA
A2–A0
Ci
RESET
SCL
Cio(off) (4)
SDA
SC7–SC0, SD7–SD0
VI = VCC, IO = 0
SCL or SDA input at 0.6 V,
Other inputs at VCC or GND (2)
SCL or SDA input at VCC – 0.6 V,
Other inputs at VCC or GND (2)
VI = VCC or GND (2)
VI = VCC or GND (2), Switch OFF
Switch-on resistance
VO = 0.4 V, IO = 10 mA
(1)
(2)
(3)
(4)
0.6
1.25
3
6
5
9
mA
–1
1
–1
1
–1
1
50
80
3.6 V
20
35
2.7 V
11
20
1.65 V
6
10
5.25 V
9
30
3.6 V
6
15
2.7 V
4
8
1.65 V
2
4
5.25 V
0.2
4
3.6 V
0.1
2
2.7 V
0.1
2
1.65 V
0.1
1
5.25 V
0.2
4
3.6 V
0.1
2
2.7 V
0.1
2
1.65 V
0.1
1
3
20
3
20
4
5
1.65 V to 5.25 V
μA
μA
1.65 V to 5.25 V
1.65 V to 5.25 V
4
5
20
28
20
28
5.5
7.5
4.5 V to 5.25 V
4
10
25
3 V to 3.6 V
5
12
35
2.3 V to 2.7 V
7
15
45
10
25
70
1.65 V to 1.95 V
μA
1
5.25 V
VI = VCC or GND (2), Switch OFF
VO = 0.4 V, IO = 15 mA
RON
2
–1
fSCL = 400 kHz
V
1.1
1.65 V to 5.25 V
VOL = 0.6 V
2.8
1.5
1.65 V to 1.95 V
VOL = 0.4 V
4.5
1.6
2.5 V
1.8 V
SDA
V
1.9
2.3 V to 2.7 V
IOL
V
3.6
4.5 V to 5.25 V
Vo(sw)
1
UNIT
pF
pF
Ω
For operation between specified voltage ranges, refer to the worst-case parameter in both applicable ranges.
RESET = VCC (held high) when all other input voltages, VI = GND.
The power-on reset circuit resets the I2C bus logic with VCC < VPORF.
Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
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6.6 I2C InterfaceTiming Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4)
MIN
MAX
UNIT
0
100
kHz
STANDARD MODE
I2C clock frequency
fscl
tsch
2
4
2
4.7
I C clock high time
tscl
I C clock low time
tsp
I2C spike time
tsds
I2C serial-data setup time
μs
μs
50
250
2
0
ns
ns
(1)
tsdh
I C serial-data hold time
ticr
I2C input rise time
1000
ns
ticf
I2C input fall time
300
ns
300
ns
μs
2
tocf
I C output (SDn) fall time (10-pF to 400-pF bus)
tbuf
I2C bus free time between stop and start
4.7
μs
tsts
I2C start or repeated start condition setup
4.7
μs
4
μs
2
tsth
I C start or repeated start condition hold
2
tsps
I C stop condition setup
tvdL(Data)
Valid-data time (high to low) (2)
SCL low to SDA output low valid
4
tvdH(Data)
Valid-data time (low to high) (2)
SCL low to SDA output high valid
tvd(ack)
Valid-data time of ACK condition
ACK signal from SCL low
to SDA output low
Cb
I2C bus capacitive load
μs
1
μs
0.6
μs
1
μs
400
pF
400
kHz
FAST MODE
fscl
I2C clock frequency
tsch
I2C clock high time
0
2
tscl
I C clock low time
0.6
μs
1.3
μs
2
tsp
I C spike time
tsds
I2C serial-data setup time
100
ns
tsdh
I2C serial-data hold time
0 (1)
μs
ticr
50
ns
2
20
300
ns
2
300
ns
300
ns
I C input rise time
ticf
I C input fall time
20 × (VCC /
5.5 V)
tocf
I2C output (SDn) fall time (10-pF to 400-pF bus)
20 × (VCC /
5.5 V)
2
tbuf
I C bus free time between stop and start
1.3
μs
tsts
I2C start or repeated start condition setup
0.6
μs
μs
2
tsth
I C start or repeated start condition hold
0.6
tsps
I2C stop condition setup
0.6
tvdL(Data)
Valid-data time (high to low) (2)
SCL low to SDA output low valid
tvdH(Data)
Valid-data time (low to high) (2)
SCL low to SDA output high valid
tvd(ack)
Valid-data time of ACK condition
ACK signal from SCL low
to SDA output low
Cb
I2C bus capacitive load
(1)
(2)
μs
1
μs
0.6
μs
1
μs
400
pF
A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), to bridge
the undefined region of the falling edge of SCL.
Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 5)
6.7 Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tW(L)
Pulse duration, RESET low
6
ns
tREC(STA)
Recovery time from RESET to start
0
ns
6
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6.8 Switching Characteristics
over recommended operating free-air temperature range, CL ≤100 pF (unless otherwise noted) (see Figure 4)
FROM
(INPUT)
PARAMETER
tpd (1)
Propagation delay time
trst (2)
RESET time (SDA clear)
(1)
(2)
RON = 20 Ω, CL = 15 pF
RON = 20 Ω, CL = 50 pF
TO
(OUTPUT)
SDA or SCL
SDn or SCn
RESET
SDA
MIN
MAX
0.3
1
500
UNIT
ns
ns
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by anideal voltage source (zero output impedance).
trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,
signaling a stop condition. It must be a minimum of tWL.
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6.9 Typical Characteristics
800
VCC = 5.5V
VCC = 3.3V
VCC = 1.65V
700
VOL (mV)
600
500
400
300
200
100
0
0
2
4
6
IOL (mA)
8
10
12
D003
Figure 1. SDA Output Low Voltage (VOL) vs Load Current (IOL) at Three VCC Levels
1.8
30
25
1.4
20
1.2
RON (Ω)
ICC, Standby Mode (µA)
1.6
1
0.8
10
0.6
25ºC (Room Temperature)
85ºC
-40ºC
0.4
0.2
1.5
25ºC (Room Temperature)
85ºC
-40ºC
5
0
2
2.5
3
3.5
VCC (V)
4
4.5
5
5.5
0
0.5
1
D004
Figure 2. Standby Current (ICC) vs Supply Voltage (VCC) at
three temperatures
8
15
1.5
2
2.5
3
VCC (V)
3.5
4
4.5
5
5.5
D001
Figure 3. On-Resistance (RON) vs Supply Voltage (VCC) at
three temperatures
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7 Parameter Measurement Information
VCC
R L = 1 kW
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Address
Stop
Start
Bit 7 Address
Condition Condition
Bit 6
(MSB)
(P)
(S)
R/W
Bit 0
(LSB)
Address
Bit 1
tscl
ACK
(A)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
tsch
0.7 ´ VCC
SCL
0.3 ´ VCC
ticr
tvd(ack)
ticf
tbuf
tsp
tsts
tvdH(Data)
0.7 ´ VCC
SDA
0.3 ´ VCC
ticr
ticf
tsth
tvdL(Data)
tsdh
tsds
tsps
Repeat Start
Condition
Start or
Repeat Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I C address
2, 3
P-port data
2
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
Not all parameters and waveforms are applicable to all devices.
Figure 4. I2C Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VCC
RL = 1 kW
DUT
SDA
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3
VCC
tRESET
RESET
VCC/2
tREC
tw
SDn, SCn
0.3
VCC
tRESET
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
I/Os are configured as inputs.
D.
Not all parameters and waveforms are applicable to all devices.
Figure 5. Reset Load Circuit and Voltage Waveforms
10
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8 Detailed Description
8.1 Overview
The TCA9548A-Q1 is an 8-channel, bidirectional translating I2C switch. The master SCL/SDA signal pair is
directed to eight channels of slave devices, SC0/SD0-SC7/SD7. Any individual downstream channel can be
selected as well as any combination of the eight channels.
The device offers an active-low RESET input which resets the state machine and allows the TCA9548A-Q1 to
recover if one of the downstream I2C buses get stuck in a low state. The state machine of the device can also be
reset by cycling the power supply, VCC, also known as a power-on reset (POR). Both the RESET function and a
POR cause all channels to be deselected.
The connections of the I2C data path are controlled by the same I2C master device that is switched to
communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware
selectable by A0, A1, and A2 pins), a single 8-bit control register is written to or read from to determine the
selected channels.
The TCA9548A-Q1 may also be used for voltage translation, allowing the use of different bus voltages on each
SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using
external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel.
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8.2 Functional Block Diagram
TCA9548A-Q1
SC0
SC1
SC2
SC3
SC4
SC5
SC6
SC7
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
Switch Control Logic
GND
VCC
RESET
SCL
Reset Circuit
A0
Input Filter
SDA
2
I C Bus Control
A1
A2
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8.3 Feature Description
The TCA9548A-Q1 is an 8-channel, bidirectional translating switch for I2C buses that supports Standard-Mode
(100 kHz) and Fast-Mode (400 kHz) operation. The TCA9548A-Q1 features I2C control using a single 8-bit
control register in which each bit controls the enabling and disabling of one of the corresponding 8 switch
channels for I2C data flow. Depending on the application, voltage translation of the I2C bus can also be achieved
using the TCA9548A-Q1 to allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the
event that communication on the I2C bus enters a fault state, the TCA9548A-Q1 can be reset to resume normal
operation using the RESET pin feature or by a power-on reset which results from cycling power to the device.
8.4 Device Functional Modes
8.4.1 RESET Input
The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal
is asserted low for a minimum of tWL, the TCA9548A-Q1 resets its registers and I2C state machine and deselects
all channels. The RESET input must be connected to VCC through a pull-up resistor.
8.4.2 Power-On Reset
When power is applied to the VCC pin, an internal power-on reset holds the TCA9548A-Q1 in a reset condition
until VCC has reached VPORR. At this point, the reset condition is released, and the TCA9548A-Q1 registers and
I2C state machine are initialized to their default states, all zeroes, causing all the channels to be deselected.
Thereafter, VCC must be lowered below VPORF to reset the device.
8.5 Programming
8.5.1 I2C Interface
The TCA9548A-Q1 has a standard bidirectional I2C interface that is controlled by a master device in order to be
configured or read the status of this device. Each slave on the I2C bus has a specific device address to
differentiate between other slave devices that are on the same I2C bus. Many slave devices require configuration
upon startup to set the behavior of the device. This is typically done when the master accesses internal register
maps of the slave, which have unique register addresses. A device can have one or multiple registers where
data is stored, written, or read.
The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines
must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by the amount
of capacitance on the I2C lines. (For further details, see the I2C Pull-up Resistor Calculation application report.
Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are
high after a STOP condition (See Figure 6 and Figure 7).
The following is the general procedure for a master to access a slave device:
1. If a master wants to send data to a slave:
– Master-transmitter sends a START condition and addresses the slave-receiver.
– Master-transmitter sends data to slave-receiver.
– Master-transmitter terminates the transfer with a STOP condition.
2. If a master wants to receive or read data from a slave:
– Master-receiver sends a START condition and addresses the slave-transmitter.
– Master-receiver sends the requested register to read to slave-transmitter.
– Master-receiver receives data from the slave-transmitter.
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Programming (continued)
– Master-receiver terminates the transfer with a STOP condition.
SCL
SDA
Data Transfer
START
Condition
STOP
Condition
Figure 6. Definition of Start and Stop Conditions
SDA line stable while SCL line is high
SCL
1
0
1
0
1
0
1
0
ACK
MSB
Bit
Bit
Bit
Bit
Bit
Bit
LSB
ACK
SDA
Byte: 1010 1010 ( 0xAAh )
Figure 7. Bit Transfer
8.5.2 Device Address
Figure 8 shows the address byte of the TCA9548A-Q1.
Slave Address
1
1
1
Fixed
0
A2
A1
A0 R/W
Hardware
Selectable
Figure 8. TCA9548A-Q1 Address
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Programming (continued)
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
Table 1 shows the TCA9548A-Q1 address reference.
Table 1. Address Reference
INPUTS
A0
I2C BUS SLAVE ADDRESS
A2
A1
L
L
L
112 (decimal), 70 (hexadecimal)
L
L
H
113 (decimal), 71 (hexadecimal)
L
H
L
114 (decimal), 72 (hexadecimal)
L
H
H
115 (decimal), 73 (hexadecimal)
H
L
L
116 (decimal), 74 (hexadecimal)
H
L
H
117 (decimal), 75 (hexadecimal)
H
H
L
118 (decimal), 76 (hexadecimal)
H
H
H
119 (decimal), 77 (hexadecimal)
8.5.3 Bus Transactions
Data must be sent to and received from the slave devices, and this is accomplished by reading from or writing to
registers in the slave device.
Registers are locations in the memory of the slave which contain information, whether it be the configuration
information or some sampled data to send back to the master. The master must write information to these
registers in order to instruct the slave device to perform a task.
While it is common to have registers in I2C slaves, note that not all slave devices have registers. Some devices
are simple and contain only 1 register, which may be written to directly by sending the register data immediately
after the slave address, instead of addressing a register. The TCA9548A-Q1 is example of a single-register
device, which is controlled via I2C commands. Since it has 1 bit to enable or disable a channel, there is only 1
register needed, and the master merely writes the register data after the slave address, skipping the register
number.
8.5.3.1 Writes
To write on the I2C bus, the master sends a START condition on the bus with the address of the slave, as well
as the last bit (the R/W bit) set to 0, which signifies a write. The slave acknowledges, letting the master know it is
ready. After this, the master starts sending the control register data to the slave until the master has sent all the
data necessary (which is sometimes only a single byte), and the master terminates the transmission with a STOP
condition.
There is no limit to the number of bytes sent, but the last byte sent is what is in the register.
Figure 9 shows an example of writing a single byte to a slave register.
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Master controls SDA line
Slave controls SDA line
Write to one register in a device
Control Register (8 bits)
Device (Slave) Address (7 bits)
S
1
1
1
0
START
A2 A1 A0
0
R/W=0
A
B7 B6 B5 B4 B3 B2 B1 B0
ACK
A
P
ACK STOP
Figure 9. Write to Register
8.5.3.2 Reads
Reading from a slave is very similar to writing, but the master sends a START condition, followed by the slave
address with the R/W bit set to 1 (signifying a read). The slave acknowledges the read request, and the master
releases the SDA bus but continues supplying the clock to the slave. During this part of the transaction, the
master becomes the master-receiver, and the slave becomes the slave-transmitter.
The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data.
At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for
more data. Once the master has received the number of bytes it is expecting, it sends a NACK, signaling to the
slave to halt communications and release the bus. The master follows this up with a STOP condition.
Figure 10 shows an example of reading a single byte from a slave register.
Master controls SDA line
Slave controls SDA line
Control Register (8 bits)
Device (Slave) Address (7 bits)
S
1
1
1
0
START
A2 A1 A0
1
R/W=1
A
B7 B6 B5 B4 B3 B2 B1
ACK
B0 NA
P
NACK STOP
Figure 10. Read from Control Register
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8.5.4 Control Register
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the TCA9548A-Q1 (see Figure 11). This register can be written and read via the
I2C bus. Each bit in the command byte corresponds to a SCn/SDn channel and a high (or 1) selects this channel.
Multiple SCn/SDn channels may be selected at the same time. When a channel is selected, the channel
becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in
a high state when the channel is made active, so that no false conditions are generated at the time of
connection. A stop condition always must occur immediately after the acknowledge cycle. If multiple bytes are
received by the TCA9548A-Q1, it saves the last byte received.
Channel Selection Bits (Read/Write)
B7
B6
B5
B4
B3
B2
B1
B0
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Figure 11. Control Register
Table 2 shows the TCA9548A-Q1 Command Byte Definition.
Table 2. Command Byte Definition
CONTROL REGISTER BITS
B7
B6
B5
B4
B3
B2
B1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
X
0
Channel 0 enabled
X
X
X
1
Channel 0 disabled
1
X
X
0
0
1
0
1
X
X
0
X
0
1
1
0
1
1
COMMAND
0
X
X
X
X
0
B0
Channel 1 disabled
Channel 1 enabled
Channel 2 disabled
Channel 2 enabled
Channel 3 disabled
Channel 3 enabled
Channel 4 disabled
Channel 4 enabled
Channel 5 disabled
Channel 5 enabled
Channel 6 disabled
Channel 6 enabled
Channel 7 disabled
Channel 7 enabled
No channel selected, power-up/reset
default state
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8.5.5 RESET Input
The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal
is asserted low for a minimum of tWL, the TCA9548A-Q1 resets its registers and I2C state machine and deselects
all channels. The RESET input must be connected to VCC through a pull-up resistor.
8.5.6 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9548A-Q1 in a reset condition
until VCC has reached VPOR. At that point, the reset condition is released and the TCA9548A-Q1 registers and I2C
state machine initialize to their default states. After that, VCC must be lowered to below VPOR and then back up to
the operating voltage for a power-reset cycle.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Applications of the TCA9548A-Q1 contain an I2C (or SMBus) master device and up to eight I2C slave devices.
The downstream channels are ideally used to resolve I2C slave address conflicts. For example, if eight identical
digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0-7.
When the temperature at a specific location needs to be read, the appropriate channel can be enabled and all
other channels switched off, the data can be retrieved, and the I2C master can move on and read the next
channel.
In an application where the I2C bus contains many additional slave devices that do not result in I2C slave address
conflicts, these slave devices can be connected to any desired channel to distribute the total bus capacitance
across multiple channels. If multiple switches are enabled simultaneously, additional design requirements must
be considered (see the Design Requirements section and Detailed Design Procedure section).
9.2 Typical Application
Figure 12 shows an application in which the TCA9548A-Q1 can be used.
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Typical Application (continued)
VDPUM = 1.65 V to 5.25 V
VCC = 2.5 V
VDPU0 = 1.65 V to 5.25 V
VCC
SDA
SDA
I2C/SMBus
SCL
Master
SCL
RESET
SD0
SC0
Channel 0
VDPU1 = 1.65 V to 5.25 V
RESET
SD1
SC1
Channel 1
VDPU2 = 1.65 V to 5.25 V
SD2
SC2
Channel 2
VDPU3 = 1.65 V to 5.25 V
SD3
SC3
Channel 3
VDPU4 = 1.65 V to 5.25 V
SD4
SC4
Channel 4
VDPU5 = 1.65 V to 5.25 V
SD5
SC5
Channel 5
VDPU6 = 1.65 V to 5.25 V
SD6
SC6
Channel 6
A2
VDPU7 = 1.65 V to 5.25 V
A1
A0
GND
SD7
SC7
Channel 7
Figure 12. Typical Application Schematic
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Typical Application (continued)
9.2.1 Design Requirements
A typical application of the TCA9548A-Q1 contains one or more data pull-up voltages, VDPUX, one for the master
device (VDPUM) and one for each of the selectable slave channels (VDPU0 – VDPU7). In the event where the master
device and all slave devices operate at the same voltage, then VDPUM = VDPUX = VCC. In an application where
voltage translation is necessary, additional design requirements must be considered to determine an appropriate
VCC voltage.
The A0, A1, and A2 pins are hardware selectable to control the slave address of the TCA9548A-Q1. These pins
may be tied directly to GND or VCC in the application.
If multiple slave channels are activated simultaneously in the application, then the total IOL from SCL/SDA to
GND on the master side is the sum of the currents through all pull-up resistors, Rp.
The pass-gate transistors of the TCA9548A-Q1 are constructed such that the VCC voltage can be used to limit
the maximum voltage that is passed from one I2C bus to another.
Figure 13 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using
data specified in the Electrical Characteristics table). In order for the TCA9548A-Q1 to act as a voltage translator,
the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the main bus is running
at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V to effectively clamp
the downstream bus voltages. As shown in Figure 13, Vpass(max) is 2.7 V when the TCA9548A-Q1 supply voltage
is 4 V or lower, so the TCA9548A-Q1 supply voltage could be set to 3.3 V. Pull-up resistors then can be used to
bring the bus voltages to their appropriate levels (see Figure 12).
9.2.2 Detailed Design Procedure
Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up
resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a
function of VDPUX, VOL,(max), and IOL as shown in Equation 1:
Rp(min)
VDPUX
VOL(max)
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL =
400 kHz) and bus capacitance, Cb as shown in Equation 2:
Rp(max)
tr
0.8473 u Cb
(2)
2
The maximum bus capacitance for an I C bus must not exceed 400 pF for fast-mode operation. The bus
capacitance can be approximated by adding the capacitance of the TCA9548A-Q1, Cio(OFF), the capacitance of
wires, connections and traces, and the capacitance of each individual slave on a given channel. If multiple
channels are activated simultaneously, each of the slaves on all channels contribute to total bus capacitance.
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Typical Application (continued)
9.2.3 Application Curves
25
5
20
Rp(max) (kOhm)
4
Vpass (V)
Standard-mode
Fast-mode
25ºC (Room Temperature)
85ºC
-40ºC
3
2
15
10
5
1
0
0
0
0.5
1
1.5
2
2.5
3
VCC (V)
3.5
4
4.5
5
0
5.5
50
100
150
200
250
Cb (pF)
D007
Standard-mode
(fSCL = 100 kHz, tr = 1 µs)
Figure 13. Pass-Gate Voltage (Vpass) vs Supply Voltage
(VCC) at Three Temperature Points
300
350
400
450
D008
Fast-mode
(fSCL = 400 kHz, tr = 300 ns)
Figure 14. Maximum Pull-up Resistance (Rp(max)) vs Bus
Capacitance (Cb)
1.8
1.6
Rp(min) (kOhm)
1.4
1.2
1
0.8
0.6
0.4
VDPUX > 2V
VDPUX <= 2
0.2
0
0
0.5
1
1.5
2
2.5
3
3.5
VDPUX (V)
4
4.5
5
5.5
D009
VOL = 0.2 x VDPUX, IOL = 2 mA when VDPUX ≤ 2 V
VOL = 0.4 V, IOL = 3 mA when VDPUX > 2 V
Figure 15. Minimum Pullup Resistance (Rp(min)) vs Pull-up Reference Voltage (VDPUX)
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10 Power Supply Recommendations
The operating power-supply voltage range of the TCA9548A-Q1 is 1.65 V to 5.25 V applied at the VCC pin.
When the TCA9548A-Q1 is powered on for the first time or anytime the device must be reset by cycling the
power supply, the power-on reset requirements must be followed to ensure the I2C bus logic is initialized
properly.
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA9548A-Q1 can be reset to its default conditions by using the
power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset.
This reset also happens when the device is powered on for the first time in an application.
A power-on reset is shown in Figure 16.
VCC
Ramp-Up
Ramp-Down
VCC_TRR
VCC drops below VPORF – 50 mV
Time
Time to Re-Ramp
VCC_FT
VCC_RT
VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Figure 16. Power-On Reset Waveform
Table 3 specifies the performance of the power-on reset feature for TCA9548A-Q1 for both types of power-on
reset.
Table 3. Recommended Supply Sequencing and Ramp Rates (1)
PARAMETER
MIN
MAX
UNIT
VCC_FT
Fall time
See Figure 16
1
100
ms
VCC_RT
Rise time
See Figure 16
0.1
100
ms
VCC_TRR
Time to re-ramp (when VCC drops below VPORF(min) – 50 mV or
when VCC drops to GND)
See Figure 16
40
VCC_GH
Level that VCC can glitch down to, but not cause a functional
disruption when VCC_GW = 1 μs
See Figure 17
1.2
V
VCC_GW
Glitch width that does not cause a functional disruption when
VCC_GH = 0.5 × VCC
See Figure 17
10
μs
(1)
μs
All supply sequencing and ramp rate values are measured at TA = 25°C
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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 17 and Table 3 provide more
information on how to measure these specifications.
VCC
VCC_GH
Time
VCC_GW
Figure 17. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 18 and Table 3 provide more details on this specification.
VCC
VPORR
VPORF
Time
POR
Time
Figure 18. VPOR Example
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11 Layout
11.1 Layout Guidelines
For PCB layout of the TCA9548A-Q1, common PCB layout practices must be followed but additional concerns
related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C
signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and pins that are
connected to ground must have a low-impedance path to the ground plane in the form of wide polygon pours and
multiple vias. Bypass and decoupling capacitors are commonly used to control the voltage on the VCC pin, using
a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller capacitor
to filter out high-frequency ripple.
In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same
potential and a single copper plane could connect all of the pull-up resistors to the appropriate reference voltage.
In an application where voltage translation is required, VDPUM and VDPU0 – VDPU7, may all be on the same layer of
the board with split planes to isolate different voltage potentials.
To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn and SDn) must be a short as
possible and the widths of the traces must also be minimized (for example, 5-10 mils depending on copper
weight).
11.2 Layout Example
Top
Plane
GND
Bottom VCC Plane
19 SCL
20 SDA
21 VCC
22 A0
23 A1
24 RESET
VPU0
SD0 1
18
SC0 2
17
A2
VPU7
SC7
VPU1
SD1 3
16
SC1 4
SC6
SD2 5
14 SD6
SC2
13 SC5
VPU6
SD5 12
SC4 11
SD4 10
GND 9
SC3
8
6
SD3 7
VPU2
SD7
Top
Plane
GND
VPU4
VPU3
VPU5
Figure 19. Layout Schematic
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• I2C Bus Pull-Up Resistor Calculation
• Maximum Clock Frequency of I2C Bus Using Repeaters
• Introduction to Logic
• Understanding the I2C Bus
• Choosing the Correct I2C Device for New Designs
• TCA9548AEVM User's Guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
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12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TCA9548A-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
TCA9548ARGERQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN
RGE
24
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
T9548A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TCA9548A-Q1 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Oct-2019
• Catalog: TCA9548A
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TCA9548ARGERQ1
Package Package Pins
Type Drawing
VQFN
RGE
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
4.25
B0
(mm)
K0
(mm)
P1
(mm)
4.25
1.15
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TCA9548ARGERQ1
VQFN
RGE
24
3000
367.0
367.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
2.5
SYMM
1
PIN 1 ID
(OPTIONAL)
18
24X 0.30
0.18
24
19
SYMM
24X 0.48
0.28
0.1
0.05
C A B
C
4219016 / A 08/2017
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
(
2.7)
19
24
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
TYP
6
13
(R0.05)
12
7
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
19
24
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
(R0.05) TYP
METAL
TYP
25
7
SYMM
12
(0.694)
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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