Texas Instruments | TUSB1064 USB TYPE-C™ DP Alt Mode 10 Gbps Sink-Side Linear Redriver Crosspoint Switch (Rev. C) | Datasheet | Texas Instruments TUSB1064 USB TYPE-C™ DP Alt Mode 10 Gbps Sink-Side Linear Redriver Crosspoint Switch (Rev. C) Datasheet

Texas Instruments TUSB1064 USB TYPE-C™ DP Alt Mode 10 Gbps Sink-Side Linear Redriver Crosspoint Switch (Rev. C) Datasheet
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TUSB1064
SLLSF48C – MARCH 2018 – REVISED SEPTEMBER 2019
TUSB1064 USB TYPE-C™ DP Alt Mode 10 Gbps Sink-Side Linear Redriver Crosspoint
Switch
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
USB Type-C™ crosspoint switch supporting
– USB 3.1 Gen 2 + 2 DP 1.4 lanes
– 4 DP 1.4 lanes
USB 3.1 Gen 2 up to 10 Gbps
DisplayPort 1.4 up to 8.1 Gbps (HBR3)
VESA DisplayPort™ alt mode UFP_D redriving
crosspoint switch supporting c, d, and e pin
assignments
Ultra-low-power architecture
Linear redriver with up to 12 dB equalization
Transparent to DisplayPort link training
Automatic LFPS de-emphasis control to meet
USB 3.1 certification requirements
Configuration through GPIO or I2C
Hot-plug capable
Industrial temperature range: –40ºC to 85ºC
(TUSB1064I)
Commercial temperature range: 0ºC to 70ºC
(TUSB1064)
4 mm x 6 mm, 0.4 mm Pitch WQFN package
Monitors
HDTV
Projectors
Docking stations
3 Description
The TUSB1064 s a VESA USB Type-C™ Alt Mode
redriving switch supporting USB 3.1 data rates up to
10 Gbps and DisplayPort 1.4 up to 8.1 Gbps for
upstream facing port (Sink). The device is used for
UFP_D pin assignments C, D, and E from the VESA
DisplayPort Alt Mode on USB Type-C Standard.
The TUSB1064 provides several levels of receive
linear equalization to compensate for inter symbol
interference (ISI) due to cable and board trace loss.
Operates on a single 3.3-V supply and comes in a
commercial temperature range and industrial
temperature range.
Device Information(1)
PART NUMBER
TUSB1064
PACKAGE
WQFN (40)
TUSB1064I
BODY SIZE (NOM)
4.00 mm x 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematics
TUSB1064 Use-Case Example
D+/-
TUSB1064
TUSB1064
SSRX
USB Hub
SSTX
Type-C Receptacle
TX1
RX1
RX2
DP0
TX2
DP1
DP2
DP3
SBU1
AUXn
SBU2
AUXp
DP RX
HPDIN
CC1
CC2
CTL 1 0 FLIP
HPD
PD Controller
Control
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB1064
SLLSF48C – MARCH 2018 – REVISED SEPTEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
8
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
ELECTRICAL CHARACTERISTICS ......................... 6
Switching Characteristics .......................................... 9
Timing Requirements .............................................. 10
Typical Characteristics ............................................ 11
Parameter Measurement Information ................ 13
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 18
8.5 Programming........................................................... 23
8.6 Register Maps ......................................................... 25
9
Application and Implementation ........................ 30
9.1 Application Information............................................ 30
9.2 Typical Application ................................................. 30
9.3 System Examples .................................................. 35
10 Power Supply Recommendations ..................... 40
11 Layout................................................................... 41
11.1 Layout Guidelines ................................................. 41
11.2 Layout Example .................................................... 41
12 Device and Documentation Support ................. 42
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
42
42
42
42
42
13 Mechanical, Packaging, and Orderable
Information ........................................................... 42
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2019) to Revision C
•
Page
Added note to disable AUX snoop to resolve interop issues with a non-compliant AUX source. ....................................... 17
Changes from Revision A (November 2018) to Revision B
Page
•
Added following to pin 38 description: If I2C_EN = “F”, then this pin must be set to “F” or “0”. ........................................... 4
•
Changed GLF min, typ, and max from -1, 0, 1 to -2.5, 0.5, and 3.5 respectively. .................................................................. 8
•
Added GLF_LFPS_TX1/2 to AC electrical ...................................................................................................................................... 8
Changes from Original (March 2018) to Revision A
Page
•
Changed the RNQ pin image appearance ............................................................................................................................ 3
•
Changed the column on EN From: I To: 2 Level I (PD) ........................................................................................................ 4
•
Changed the EN pin Description in the Pin Functions table .................................................................................................. 4
•
Changed the HPDIN pin From: I/O To: 2 Level I .................................................................................................................. 4
•
Added pull-down indicator (PD) in the I/O column on FLIP/SCL and CTL0/SDA pins ......................................................... 4
•
Added Junction temperature to absolute maximum ratings table. ........................................................................................ 5
•
From: Internal pull-down resistance for CTL1. To: Internal pull-down resistance for CTL1, CTL0, FLIP, and EN. ........... 6
•
Deleted EN from Note 1 of Table 8 ..................................................................................................................................... 23
2
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SLLSF48C – MARCH 2018 – REVISED SEPTEMBER 2019
5 Pin Configuration and Functions
DP0p
DP0n
SSEQ0/A0
DP1p
DP1n
DPEQ0/A1
DP2p
DP2n
HPDIN
DP3p
DP3n
EN
40
39
38
37
36
35
34
33
32
31
30
29
RNQ Package
40-Pin (WQFN)
Top View
NC
1
28
VCC
DPEQ1
2
27
AUXn
SSEQ1
3
26
AUXp
SSRXn
4
25
SBU2
SSRXp
5
24
SBU1
VCC
6
23
CTL1
SSTXn
7
22
CTL0/SDA
SSTXp
8
21
FLIP/SCL
Thermal
20
VCC
19
TX2p
18
TX2n
17
I2C_EN
16
RX2p
15
RX2n
14
EQ1
13
RX1n
12
RX1p
11
EQ0
10
TX1n
TX1p
9
Pad
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
DP0p
40
Diff O
DP Differential positive output for DisplayPort Lane 0.
DP0n
39
Diff O
DP Differential negative output for DisplayPort Lane 0.
DP1p
37
Diff O
DP Differential positive output for DisplayPort Lane 1.
DP1n
36
Diff O
DP Differential negative output for DisplayPort Lane 1.
DP2p
34
Diff O
DP Differential positive output for DisplayPort Lane 2.
DP2n
33
Diff O
DP Differential negative output for DisplayPort Lane 2.
DP3p
31
Diff O
DP Differential positive output for DisplayPort Lane 3.
DP3n
30
Diff O
DP Differential negative output for DisplayPort Lane 3.
TX1n
10
Diff I/O
Differential negative input for DisplayPort or differential negative output for USB3.1 upstream
facing port.
TX1p
9
Diff I/O
Differential positive input for DisplayPort or differential positive output for USB3.1 upstream facing
port.
RX1n
13
Diff I
Differential negative input for DisplayPort or USB3.1 upstream facing port.
RX1p
12
Diff I
Differential positive input for DisplayPort or USB 3.1 upstream facing port.
RX2p
16
Diff I
Differential positive input for DisplayPort or USB 3.1 upstream facing port.
RX2n
15
Diff I
Differential negative input for DisplayPort or USB 3.1 upstream facing port.
TX2p
19
Diff I/O
Differential positive input for DisplayPort or differential positive output for USB3.1 upstream Facing
port.
TX2n
18
Diff I/O
Differential negative input for DisplayPort or differential negative output for USB3.1 upstream
Facing port.
SSTXp
8
Diff I
Differential positive input for USB3.1 downstream facing port.
SSTXn
7
Diff I
Differential negative input for USB3.1 downstream facing port.
SSRXp
5
Diff O
Differential positive output for USB3.1 downstream facing port.
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
SSRXn
4
Diff O
EQ1
14
4 Level I
This pin along with EQ0 sets the USB receiver equalizer gain for upstream facing RX1 and RX2
when USB used. Up to 11dB of EQ available.
EQ0
11
4 Level I
This pin along with EQ1 sets the USB receiver equalizer gain for upstream facing RX1 and RX2
when USB used. Up to 11 dB of EQ available.
EN
29
2 Level I
(PD)
Device Enable, when I2C_EN = '0'. Device disable function not used when I2C_EN ≠ '0'.
L = Device Disabled
H = Device Enabled
On rising edge of EN pin, the device will sample all 4-level inputs including the I2C_EN pin. EN pin
will not reset the I2C registers.
HPDIN
32
2 Level I
Hot Plug Detect. This pin is an input for Hot Plug Detect received from DisplayPort sink. When
HPDIN is Low for greater than 2ms, all DisplayPort lanes are disabled while the AUX to SBU
switch will remain closed.
Differential negative output for USB3.1 downstream facing port.
I2C_EN
17
4 Level I
I2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is ‘0'.
0 = GPIO mode (I2C disabled)
R = TI Test Mode (I2C enabled at 3.3 V)
F = I2C enabled at 1.8 V
1 = I2C enabled at 3.3 V.
SBU1
24
I/O, CMOS
SBU1. This pin should be DC coupled to the SBU1 pin on the Type-C receptacle. A 2-M ohm
resistor to GND is also recommended.
SBU2
25
I/O, CMOS
SBU2. This pin should be DC coupled to the SBU2 pin on the Type-C receptacle. A 2-M ohm
resistor to GND is also recommended.
AUXp
26
I/O, CMOS
AUXp. DisplayPort AUX positive I/O connected to the DisplayPort sink through a AC coupling
capacitor. In addition to AC coupling capacitor, this pin also requires a 1M resistor to DP_PWR
(3.3 V). This pin along with AUXN is used by the TUSB1064 for AUX snooping and is routed to
SBU1/2 based on the orientation of the Type-C.
AUXn
27
I/O, CMOS
AUXn. DisplayPort AUX negative I/O connected to the DisplayPort sink through a AC coupling
capacitor. In addition to AC coupling capacitor, this pin also requires a 1M resistor to GND. This
pin along with AUXP is used by the TUSB1064 for AUX snooping and is routed to SBU1/2 based
on the orientation of the Type-C.
DPEQ1
2
4 Level I
DisplayPort Receiver EQ. This along with DPEQ0 will select the DisplayPort receiver equalization
gain.
DPEQ0/A1
35
4 Level I
DisplayPort Receiver EQ. This along with DPEQ1 will select the DisplayPort receiver equalization
gain. When I2C_EN ≠ '0', this pin will also set the TUSB1064 I2C address.
SSEQ1
3
4 Level I
Along with SSEQ0, sets the USB receiver equalizer gain for downstream facing SSTXP/N.
SSEQ0/A0
38
4 Level I
Along with SSEQ1, sets the USB receiver equalizer gain for downstream facing SSTXP/N. When
I2C_EN ≠ '0', this pin will also set the TUSB1064 I2C address. If I2C_EN = “F”, then this pin must
be set to “F” or “0”.
FLIP/SCL
21
2 Level I
(Failsafe)
(PD)
When I2C_EN = ’0’ this is Flip control pin, otherwise this pin is I2C clock. . When used for I2C clock
pullup to I2C master's VCC I2C supply.
CTL0/SDA
22
2 Level I
(Failsafe)
(PD)
When I2C_EN = '0' this is a USB3.1 Switch control pin, otherwise this pin is I2C data. When used
for I2C data pullup to I2C master's VCC I2C supply.
CTL1
23
2 Level I
(Failsafe)
(PD)
DP Alt mode Switch Control Pin. When I2C_EN = ‘0’, this pin will enable or disable DisplayPort
functionality. Otherwise, when I2C_EN ≠ '0', DisplayPort functionality is enabled and disabled
through I2C registers.
L = DisplayPort Disabled.
H = DisplayPort Enabled.
VCC
6, 20, 28
P
1
NC
Thermal Pad
G
NC
GND
4
3.3-V Power Supply
No connect pin. Leave open.
Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature and voltage range (unless otherwise noted) (1)
MIN
MAX
-0.3
4
V
±2.5
V
4
V
4
V
TUSB1064 Junction Temperature
110
°C
TUSB1064I Junction Temperature
125
°C
150
°C
VCC
Supply Voltage Range
VIN_DIFF
Differential Voltage at Differential Inputs
VIN_SE
Input Voltage at Differential Inputs
-0.5
VIN_CMOS
Input Voltage at CMOS Inputs
-0.3
TJ
TSTG
(1)
Storage temperature
-65
UNIT
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±5000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature and voltage range (unless otherwise noted)
MIN
TA
Ambient temperature for TUSB1064
0
TA
Ambient temperature for TUSB1064I
-40
VCC
Supply voltage
VCC_RAMP
Power supply ramp
0.1
VI2C
Supply that external resistors on SDA and SCL are pulled up to
1.7
VPSN
Power supply noise on VCC
NOM
3
3.3
MAX
UNIT
70
°C
85
°C
3.6
V
100
ms
3.6
V
100
mV
6.4 Thermal Information
TUSB1064
THERMAL METRIC (1)
RNQ (WQFN)
UNIT
40 PINS
RθJA
Junction-to-ambient thermal resistance
37.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
20.7
°C/W
RθJB
Junction-to-board thermal resistance
9.5
°C/W
ΨJT
Junction-to-top characterization parameter
0.2
°C/W
ΨJB
Junction-to-board characterization parameter
9.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 ELECTRICAL CHARACTERISTICS
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power
PCCACTIVEUSB
PCCACTIVEUSB-DP
PCCACTIVE-DP
PCC-NCUSB
PCC-U2U3
Average active power in USB-only mode
while in U0.
CTL1 = L; CTL0 = H; Link in U0 at
10Gbps;
330
mW
Average active power in USB + 2 lane
DP mode.
CTL1 = H; CTL0 = H; USB in U0 at
10Gbps; DP at 8.1Gbps;
660
mW
Average active power in 4 lane DP
mode.
CTL1 = H; CTL0 = L; Four DP lanes at
8.1Gbps
660
mW
Average power in USB mode while in
disconnect state.
CTL1 = L; CTL0 = H; No USB device
detected;
2.5
mW
Average power in USB mode while in
U2/U3 state
CTL1 = L; CTL0 = H; Link in U2 or U3;
2.5
mW
Average power in Shutdown mode.
CTL1 = L; CTL0 = L; I2C_EN = "0";
0.7
mW
PCCSHUTDOW
N
4-State CMOS Inputs(EQ[1:0], SSEQ[1:0], DPEQ[1:0], I2C_EN)
IIH
High-level input current
VCC = 3.6 V; VIN = 3.6 V
IIL
Low-level input current
VCC = 3.6 V; VIN = 0 V
Threshold 0 / R
VCC = 3.3 V
0.55
V
Threshold R/ Float
VCC = 3.3 V
1.65
V
Threshold Float / 1
VCC = 3.3 V
2.7
V
4-Level
VTH
20
80
µA
-160
-40
µA
RPU
Internal pull up resistance
45
kΩ
RPD
Internal pull-down resistance
95
kΩ
2-State CMOS Input (CTL0, CTL1, FLIP, EN, HPDIN) CTL1, CTL0 and FLIP are Failsafe
VIH
High-level input voltage
2
3.6
V
VIL
Low-level input voltage
0
0.8
V
RPD
Internal pull-down resistance for CTL1,
CTL0, FLIP, and EN.
IIH
High-level input current
VIN = 3.6 V
-25
25
µA
IIL
Low-level input current
VIN = GND, VCC = 3.6 V
-25
25
µA
500
kΩ
I2C Control Pins SCL, SDA
VIH
High-level input voltage
I2C_EN ! = 0
0.7 x
VI2C
3.6
V
VIL
Low-level input voltage
I2C_EN ! = 0
0
0.3 ×
VI2C
V
VOL
Low-level output voltage
I2C_EN ! = 0; IOL = 3 mA
0
0.4
IOL
Low-level output current
I2C_EN ! = 0; VOL = 0.4 V
20
Ii_I2C
Input current on SDA pin
0.1 × VI2C < Input voltage < 3.3 V
Ci_I2C
Input capacitance
V
mA
-10
10
µA
10
pF
USB Differential Receiver (RX1P/N, RX2P/N, SSTXP/N)
VRX-DIFFPP
VRX-DC-
Input differential peak-peak voltage
swing linear dynamic range
2000
Common-mode voltage bias in the
receiver (DC)
CM
RRX-DIFFRRX-CM-
mVpp
0
V
Differential input impedance (DC)
Present after a USB3.1 device is
detected on TXP/TXN
72
120
Ω
Receiver DC Common Mode impedance
Present after a USB3.1 device is
detected on TXP/TXN
18
30
Ω
DC
DC
6
AC-coupled differential peak-to-peak
signal measured post CTLE through a
reference channel
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
ZRX-HIGHIMP-DCPOS
VSIGNALDET-DIFFPP
VRX-IDLEDET-DIFFPP
VRX-LFPSDET-DIFFPP
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Common-mode input impedance with
termination disabled (DC)
Present when no USB3.1 device is
detected on TXP/TXN. Measured over
the range of 0-500 mV with respect to
GND.
Input Differential peak-to-peak Signal
Detect Assert Level
at 10Gbps, No loss and bit rate PRBS7
pattern
79
mV
Input Differential peak-to-peak Signal
Detect De-assert Level
at 10 Gbps, No loss and bit rate PRBS7
pattern
58
mV
Low-frequency Periodic Signaling (LFPS)
Below the minimum is squelched.
Detect Threshold
25
kΩ
100
300
mV
1
pF
CRX
RX input capacitance to GND
At 2.5 GHz
0.5
RLRX-
Differential Return Loss
50 MHz – 1.25 GHz at 90 Ω
-13
dB
Differential Return Loss
5 GHz at 90 Ω
-9
dB
RLRX-CM
Common Mode Return Loss
50 MHz – 5 GHz at 90 Ω
-8
dB
EQSSP
Receiver equalization
SSEQ[1:0] and EQ[1:0] at 5 GHz.
12
dB
DIFF
RLRXDIFF
USB Differential Transmitter (TX1P/N, TX2P/N, SSRXP/N)
VTX-DIFFPP
VTX-RCVDETECT
VTX-CMIDLEDELTA
VTX-DCCM
Transmitter dynamic differential voltage
swing range.
1300
Amount of voltage change allowed
during Receiver Detection
at 3.3 V
Transmitter idle common-mode voltage
change while in U2/U3 and not actively
transmitting LFPS
measured at the connector side of the
AC coupling caps with 50 Ω load
Common-mode voltage bias in the
transmitter (DC)
VTX-CMTx AC Common-mode voltage active
At 3.3V; Max mismatch from Txp+Txn for
both time and amplitude
AC Electrical idle differential peak-topeak output voltage
At package pins
DC Electrical idle differential output
voltage
At package pins after low-pass filter to
remove AC component
DCACTIVEIDLEDELTA
Absolute DC common mode voltage
between U1 and U0
CTX
TX input capacitance to GND
RTX-DIFF
Differential impedance of the driver
CAC-
AC Coupling capacitor
AC-PPACTIVE
VTX-IDLEDIFF-ACPP
VTX-IDLEDIFF-DC
mVpp
600
mV
-600
600
mV
0
2
V
100
mVpp
0
10
mV
0
14
mV
At package pin
200
mV
At 2.5 GHz
1.25
pF
75
120
Ω
75
265
nF
18
30
Ω
67
mA
VTX-CM-
COUPLING
RTX-CM
Common-mode impedance of the driver
Measured with respect to AC ground
over 0-500 mV
ITX-SHORT TX short circuit current
TX+/- shorted to GND
RLTX-DIFF Differential Return Loss
50 MHz – 1.25 GHz at 90 Ω
-17
dB
RLTX-
Differential Return Loss
5 GHz at 90 Ω
-12
dB
Common Mode Return Loss
50 MHz – 5 GHz at 90 Ω
-9
dB
DIFF-5G
RLTX-CM
AC Electrical Characteristics for USB and DP
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Crosstalk
Differential Cross Talk between TX and
RX signal Pairs
at 5 GHz
GLF
Low-frequency voltage gain.
at 100 MHz, 600 mVpp VID
MIN
MAX
-27
GLF_LFPS Low-frequency voltage gain for SSTX>TX1/TX2 path.
_TX1/2
at 10 to 50MHz sine wave; 1.0Vpp VID;
EQ = 0; FLIP = 0 and 1;
CP1 dB-LF Low-frequency 1-dB compression point
at 100 MHz, 200 mVpp < VID < 2000
mVpp
CP1 dB-
TYP
UNIT
dB
-2.5
0.5
3.5
dB
0
0.8
1.6
dB
1000
mVpp
770
mVpp
High-frequency 1-dB compression point
at 5 GHz, 200 mVpp < VID < 2000 mVpp
Low-frequency cutoff
200 mVpp < VID < 2000 mVpp
DJ_10G
TX output deterministic jitter
200 mVpp < VID < 2000 mVpp, PRBS7,
10 Gbps
0.10
UIpp
DJ_8.1G
TX output deterministic jitter
200 mVpp < VID < 2000 mVpp, PRBS7,
8.1 Gbps
0.08
UIpp
TJ_10G
TX output total jitter
200 mVpp < VID < 2000 mVpp, PRBS7,
10 Gbps
0.13
UIpp
TJ_8.1G
TX output total jitter
200 mVpp < VID < 2000 mVpp, PRBS7,
8.1 Gbps
0.12
UIpp
2000
mV
HF
fLF
20
50
kHz
DisplayPort Receiver (TX1P/N, TX2P/N, RX1P/N, RX2P/N)
VID_PP
Peak-to-peak input differential dynamic
voltage range
VIC
Input Common Mode Voltage
CAC
AC coupling capacitance
EQDP
Receiver Equalizer
DPEQ1, DPEQ0 at 4.05 GHz
dR
Data rate
HBR3
Rti
Input Termination resistance
0
75
V
265
12
80
100
nF
dB
8.1
Gbps
120
Ω
DisplayPort Transmitter (DP[3:0]P/N)
VTX-
VOD dynamic range
1300
mV
DIFFPP
ITX-SHORT TX short circuit current
TX+/- shorted to GND
67
mA
10
Ω
AUXP/N and SBU1/2
RON
Output ON resistance
VCC = 3.3 V; VIN = 0 to 0.4 V for AUXP;
VIN = 2.7 V to 3.6 V for AUXN
RON-
ΔON resistance mismatch within pair
VCC = 3.3 V; VIN = 0 to 0.4 V for AUXP;
VIN= 2.7 V to 3.6 V for AUXN
1
Ω
VCC = 3.3 V; VIN = 0 to 0.4 V for AUXP;
VIN = 2.7 V to 3.6 V for AUXN
2
Ω
MISMATCH
ON resistance flatness (RONmax–RON
RON_FLAT min) measured at identical VCC and
temperature
VAUXP_D
5
AUX Channel DC common mode voltage
VCC = 3.3 V
for AUXP and SBU2.
0
0.4
V
AUX Channel DC common mode voltage
VCC = 3.3 V
for AUXN and SBU1
2.7
3.6
V
C_CM
CAUX_ON
ON-state capacitance
C_CM
VAUXN_D
CAUX_OFF OFF-state capacitance
8
VCC = 3.3 V; CTL1 = 1; VIN = 0 V or 3.3
V
4
7
pF
VCC = 3.3 V; CTL1 = 0; VIN = 0 V or 3.3
V
3
6
pF
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6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUXp/n and SBU1/2
TAUX_PD
Switch propagation delay
1400
ps
TAUX_SW
Switching time CTL1 to switch OFF. Not
including TCTL1_DEBOUNCE.
7500
ns
Switching time CTL1 to switch ON
3000
ns
400
ps
_OFF
TAUX_SW
_ON
TAUX_INT
Intra-pair output skew
RA
USB3.1 and DisplayPort mode transition requirement (GPIO mode)
TGP_USB_
4DP
TCTL1_DE
BOUNCE
Min overlap of CTL0 and CTL1 when
transitioning from USB 3.1 only mode to
4-Lane DisplayPort mode or vice versa
4
CTL1 and HPDIN debounce time when
transitioning from H to L
3
µs
10
ms
1
MHz
I2C (SDA and SCL)
fSCL
I2C clock frequency
tBUF
Bus free time between START and
STOP conditions
tHDSTA
Hold time after repeated START
condition. After this period, the first clock
pulse is generated
tLOW
0.5
µs
0.26
µs
Low period of the I2C clock
0.5
µs
tHIGH
High period of the I2C clock
0.26
µs
tSUSTA
Setup time for a repeated START
condition
0.26
µs
tHDDAT
Data hold time
0
µs
tSUDAT
Data setup time
50
tR
Rise time of both SDA and SCL signals
tF
Fall time of both SDA and SCL signals
tSUSTO
Setup time for STOP condition
Cb
Capacitive load for each bus line
20 ×
(VI2C/5.5
V)
ns
120
ns
120
ns
0.26
µs
100
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6.7 Timing Requirements
MIN
NOM
MAX
UNIT
USB 3.1
tIDLEEntry,
Delay from U0 to electrical idle
tIDLEExit_U1
U1 exist time: break in electrical idle to the transmission of LFPS
tIDLEExit_U2
U2/U3 exit time: break in electrical idle to transmission of LFPS
10
ns
6
ns
10
µs
U3
tRXDET_INT
RX detect interval while in Disconnect
12
ms
VL
tIDLEExit_DIS
Disconnect Exit Time
10
µs
1
ms
C
tExit_SHTDN
Shutdown Exit Time (CTL0 = VCC/2 to U2/U3)
tDIFF_DLY
Differential Propagation Delay (20%-80% of differential voltage measured
1.7 inch from the output pin)
tPWRUPACTI
Time when Vcc reaches 70% to device active
300
ps
1
ms
VE
tR, tF
Output Rise/Fall Time
tRF-MM
Output Rise/Fall time mismatch (20%-80% of differential voltage measured
1.7 inch from the output pin)
10
40
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5
ps
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6.8 Typical Characteristics
Figure 1. DisplayPort EQ Settings Curves
Figure 2. USB RX (DFP) EQ Settings Curves
1600
Differential Output Voltage (mV)
1400
1200
1000
800
600
400
EQ0
EQ6
EQ12
200
0
0
200
400
600
800
1000
1200
1400
EQ2
EQ7
EQ15
1600
EQ4
EQ10
1800
2000
Differential Input Voltage (mV)
Figure 3. USB TX (UFP) EQ Settings Curves
Figure 4. DisplayPort Linearity Curves at 4.05 GHz
1200
1200
Differential Output Voltage (mV)
Differential Output Voltage (mV)
1400
1000
800
EQ0
EQ2
EQ4
EQ6
EQ8
EQ10
EQ12
EQ15
600
400
200
0
1000
800
600
EQ0
EQ2
EQ4
EQ6
EQ8
EQ10
EQ12
EQ15
400
200
0
0
500
1000
1500
Differential Input Voltage (mV)
2000
0
D002
Figure 5. USB TX (DFP) Linearity Curves at 5 GHz
500
1000
1500
Differential Input Voltage (mV)
2000
D001
Figure 6. USB RX (UFP) Linearity Curves at 5 GHz
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Typical Characteristics (continued)
0
-5
-5
-10
-10
SD D 11 (d B )
SD D 11 (dB)
0
-15
-15
-20
-20
-25
-25
RX1
-30
0.01
0.1
TX1
1
DP0
SSTX
10
-30
0.01
0.1
SSRX
TX1
10
Frequency (GHz)
Frequency (GHz)
Figure 8. Output Return Loss Performance
Output Voltage (200 mV/Div)
Output Voltage (150 mV/Div)
Figure 7. Input Return Loss Performance
Time (20.57 ps/Div)
Time (16.67 ps/Div)
Figure 9. DisplayPort HBR3 Eye-Pattern Performance with
12-inch Input PCB Trace at 8.1 Gbps
12
1
DP3
Figure 10. USB 3.1 Gen2 Eye-Pattern Performance with
12-inch Input PCB Trace at 10 Gbps
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7 Parameter Measurement Information
70%
SDA
30%
tLOW
tBUF
tR
tHIGH
tHDSTA
tF
70%
SCL
P
30%
S
S
tHDDAT
tHDSTA
P
tSUDAT
tSUSTA
tSUSTO
Figure 11. I2C Timing Diagram Definitions
4us
(min)
CTL1 pin
CTL0 pin
Figure 12. USB3.1 to 4-Lane DisplayPort in GPIO Mode
IN
TDIFF_DLY
TDIFF_DLY
OUT
Figure 13. Propagation Delay
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Parameter Measurement Information (continued)
IN+
VRX-LFPS-DET-DIFF-PP
Vcm
INTIDLEExit
TIDLEEntry
OUT+
Vcm
OUT-
Figure 14. Electrical Idle Mode Exit and Entry Delay
80%
20%
tr
tf
Figure 15. Output Rise and Fall Times
50%
50%
CTL1
90%
10%
VOUT
TAUX_SW_ON
TAUX_SW_OFF + TCTL1_DEBOUNCE
Figure 16. AUX and SBU Switch ON and OFF Timing Diagram
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8 Detailed Description
8.1 Overview
The TUSB1064 is a VESA USB Type-C Alt Mode redriving switch supporting data rates up to 8.1 Gbps for
upstream facing port. This device uses 5th generation USB redriver technology. The device is used for UFP pin
assignments C and D from the VESA DisplayPort Alt Mode on USB Type-C Standard.
The TUSB1064 provides several levels of receive equalization to compensate for cable and board trace loss
which if not equalized causes inter-symbol interference (ISI) when USB 3.1 Gen 2 or DisplayPort 1.4 signals
travel across a PCB or cable. This device requires a 3.3-V power supply. It comes in a commercial temperature
range and industrial temperature range.
For a sink application, the TUSB1064 enables the system to pass both transmitter compliance and receiver jitter
tolerance tests for USB 3.1 Gen 2 and DisplayPort version 1.4 HBR3. The re-driver recovers incoming data by
applying equalization that compensates for channel loss, and drives out signals with a high differential voltage.
Each channel has a receiver equalizer with selectable gain settings. The equalization should be set based on the
amount of insertion loss in the channels connected to the TUSB1064. Independent equalization control for each
channel can be set using EQ[1:0], SSEQ[1:0], and DPEQ[1:0] pins.
The TUSB1064 advanced state machine makes it transparent to hosts and devices. After power up, the
TUSB1064 periodically performs receiver detection on the TX pairs. If it detects a USB 3.1 receiver, the RX
termination is enabled, and the TTUSB1064 is ready to re-drive.
The device ultra-low-power architecture operates at a 3.3-V power supply and achieves Enhanced performance.
The automatic LFPS De-Emphasis control further enables the system to be USB3.1 compliant.
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8.2 Functional Block Diagram
Term
Detect
SSRXp
Driver
Term
DPEQ_SEL
EQ
SSRXn
SSEQ_SEL
Detect
Term
EQ
TX1n
Term
SSTXp
TX1p
SSTXn
Driver
EQ_SEL
DP0p
RX1p
Term
EQ
Term
Driver
EQ
Term
DPEQ_SEL
DP0n
RX1n
MUX
RX2n
RX2p
Driver
EQ_SEL
TX2p
Driver
Term
DP1n
DP2p
Driver
Term
Detect
Term
TX2n
Term
DP1p
DPEQ_SEL
DP2n
EQ
DPEQ_SEL
EQ_SEL
Term
DP3p
Driver
DP3n
SSEQ_SEL
DPEQ_SEL
DPEQ[1:0]/A1
EQ[1:0]
I2C_EN
FLIP/SCL
CTL0/SDA
SSEQ[1:0]/A0
FSM, Control Logic and
Registers
HPDIN
I2C
Slave
EN
AUX
RX
CTL1
M
U
X
SBU1
SBU2
AUXn
AUXp
VREG
VCC
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8.3 Feature Description
8.3.1 USB 3.1
The TUSB1064 supports USB 3.1 Gen 2 datarates up to 10 Gbps. The TUSB1064 supports all the USB defined
power states (U0, U1, U2, and U3). Because the TUSB1064 is a linear redriver, it can’t decode USB3.1 physical
layer traffic. The TUSB1064 monitors the actual physical layer conditions like receiver termination, electrical idle,
LFPS, and SuperSpeed signaling rate to determine the USB power state of the USB 3.1 interface.
The TUSB1064 features an intelligent low frequency periodic signaling (LFPS) detector. The LFPS detector
automatically senses the low frequency signals and disables receiver equalization functionality. When not
receiving LFPS, the TUSB1064 enables receiver equalization based on the EQ[1:0] and SSEQ[1:0] pins or
values programmed into EQ1_SEL, EQ2_SEL, and SSEQ_SEL registers.
8.3.2 DisplayPort
The TUSB1064 supports up to 4 DisplayPort lanes at datarates up to 8.1Gbps (HBR3). The TUSB1064, when
configured in DisplayPort mode, monitors the native AUX traffic as it traverses between DisplayPort source and
DisplayPort sink. For the purposes of reducing power, the TUSB1064 manages the number of active DisplayPort
lanes based on the content of the AUX transactions. The TUSB1064 snoops native AUX writes to DisplayPort
sink’s
DPCD
registers
0x00101
(LANE_COUNT_SET)
and
0x00600
(SET_POWER_STATE).
TUSB1064disables/enables lanes based on value written to LANE_COUNT_SET. The TUSB1064 disables all
lanes when SET_POWER_STATE is in the D3. Otherwise, active lanes are based on value of
LANE_COUNT_SET.
DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE
register. Once AUX snoop is disabled, management of TUSB1064 DisplayPort lanes are controlled through
various configuration registers.
NOTE
AUX snooping feature is only supported when TUSB1064 is configured for I2C mode.
When TUSB1064 is configured for GPIO mode, the AUX snoop feature is disabled and all
four DP lanes are enabled if HPDIN is asserted high.
When TUSB1064’s AUX snoop feature is enabled, the syncs defined by the DisplayPort
standard must be received in order for AUX snoop feature to function properly. AUX writes
to panel’s DPCD address 0x00600 and 0x00101 should result in SET_POWER_STATE
and LANE_COUNT_SET fields at TUSB1064’s offset 0x12 to get set to the appropriate
value. If these fields do not get set correctly, then incoming AUX may not be compliant. If
this is the case, then it is best to disable AUX snoop by setting the
AUX_SNOOP_DISABLE field at offset 0x13.
8.3.3 4-level Inputs
The TUSB1064 has (I2C_EN, EQ[1:0], DPEQ[1:0], and SSEQ[1:0]) 4-level inputs pins that are used to control
the equalization gain and place TUSB1064 into different modes of operation. These 4-level inputs utilize a
resistor divider to help set the 4 valid levels and provide a wider range of control settings. There is an internal 35
kΩ pull-up and a 95 kΩ pull-down. These resistors, together with the external resistor connection combine to
achieve the desired voltage level.
Table 1. 4-Level Control Pin Settings
LEVEL
SETTINGS
0
Option 1: Tie 1 KΩ 5% to GND.
Option 2: Tie directly to GND.
R
Tie 20 KΩ 5% to GND.
F
Float (leave pin open)
1
Option 1: Tie 1 KΩ 5%to VCC.
Option 2: Tie directly to VCC.
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NOTE
All four-level inputs are latched on rising edge of internal reset. After tcfg_hd, the internal
pull-up and pull-down resistors will be isolated in order to save power.
8.3.4 Receiver Linear Equalization
The purpose of receiver equalization is to compensate for channel insertion loss and the resulting inter-symbol
interference in the system before the input or after the output of the TUSB1064. The receiver overcomes these
losses by attenuating the low frequency components of the signals with respect to the high frequency
components. The proper gain setting should be selected to match the channel insertion loss. Two 4-level input
pins enable up to 16 possible equalization settings. USB3.1 upstream path, USB3.1 downstream path, and
DisplayPort each have their own two 4-level inputs. The TUSB1064 also provides the flexibility of adjusting
settings through I2C registers.
8.4 Device Functional Modes
8.4.1 Device Configuration in GPIO Mode
The TUSB1064 is in GPIO configuration when I2C_EN = “0”. The TUSB1064 supports the following
configurations: USB 3.1 only, 2 DisplayPort lanes + USB 3.1, or 4 DisplayPort lanes (no USB 3.1). The CTL1 pin
controls whether DisplayPort is enabled. The combination of CTL1 and CTL0 selects between USB 3.1 only, 2
lanes of DisplayPort, or 4-lanes of DisplayPort as detailed in Table 2. The AUXp or AUXn to SBU1 or SBU2
mapping is controlled based on Table 3.
After power-up (VCC from 0 V to 3.3 V), the TUSB1064 defaults to USB3.1 mode. The USB PD controller upon
detecting no device attached to Type-C port or USB3.1 operation not required by attached device must take
TUSB1064 out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.
Table 2. GPIO Configuration Control
FLIP PIN
CONFIGURATION
VESA DisplayPort ALT MODE
UFP_D CONFIGURATION
L
L
Power Down
—
L
H
Power Down
—
L
H
L
One Port USB 3.1 - No Flip
—
CTL1 PIN
CTL0 PIN
L
L
L
H
H
One Port USB 3.1 – With Flip
—
H
L
L
4 Lane DP - No Flip
C
H
L
H
4 Lane DP – With Flip
C
H
H
L
One Port USB 3.1 + 2 Lane DP- No Flip
D
H
H
H
One Port USB 3.1 + 2 Lane DP– With Flip
D
Table 3. GPIO AUXp or AUXn to SBU1 or SBU2 Mapping
CTL1 PIN
FLIP PIN
MAPPING
H
L
SBU1 → AUXn
SBU2 → AUXp
H
H
SBU2 → AUXn
SBU1 → AUXp
L > 2 ms
X
Open
Table 4 details the TUSB1064 mux routing. This table is valid for both I2C and GPIO configuration modes.
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Table 4. INPUT to OUTPUT Mapping
CTL1 PIN
CTL0 PIN
L
L
L
L
L
L
H
H
H
H
H
H
L
L
H
H
FROM
TO
INPUT PIN
OUTPUT PIN
L
NA
NA
H
NA
NA
RX1p
SSRXp
RX1n
SSRXn
SSTXp
TX1p
FLIP PIN
L
H
L
H
L
H
SSTXn
TX1n
RX2p
SSRXp
RX2n
SSRXn
SSTXp
TX2p
SSTXn
TX2n
TX2p
DP0p
TX2n
DP0n
RX2p
DP1p
RX2n
DP1n
RX1p
DP2p
RX1n
DP2n
TX1p
DP3p
TX1n
DP3n
TX1p
DP0p
TX1n
DP0n
RX1p
DP1p
RX1n
DP1n
RX2p
DP2p
RX2n
DP2n
TX2p
DP3p
TX2n
DP3n
RX1p
SSRXp
RX1n
SSRXn
SSTXp
TX1p
SSTXn
TX1n
TX2p
DP0p
TX2n
DP0n
RX2p
DP1p
RX2n
DP1n
RX2p
SSRXp
RX2n
SSRXn
SSTXp
TX2p
SSTXn
TX2n
TX1p
DP0p
TX1n
DP0n
RX1p
DP1p
RX1n
DP1n
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8.4.2 Device Configuration In I2C Mode
The TUSB1064 is in I2C mode when I2C_EN is not equal to “0”. The same configurations defined in GPIO mode
are also available in I2C mode. The TUSB1064 USB3.1 and DisplayPort configuration is controlled based on
Table 5. The AUXp or AUXn to SBU1 or SBU2 mapping control is based on Table 6.
Table 5. I2C Configuration Control
REGISTERS
CONFIGURATION
VESA DisplayPort ALT MODE
UFP_D CONFIGURATION
0
Power Down
—
1
Power Down
—
1
0
One Port USB 3.1 - No Flip
—
0
1
1
One Port USB 3.1 – With Flip
—
1
0
0
4 Lane DP - No Flip
C
1
0
1
4 Lane DP – With Flip
C
1
1
0
One Port USB 3.1 + 2 Lane DP- No Flip
D
1
1
1
One Port USB 3.1 + 2 Lane DP– With Flip
D
CTLSEL1
CTLSEL0
FLIPSEL
0
0
0
0
0
Table 6. I2C AUXp or AUXn to SBU1 or SBU2 Mapping
REGISTERS
MAPPING
AUX_SBU_OVR
CTLSEL1
FLIPSEL
00
1
0
SBU1 → AUXn
SBU2 → AUXp
00
1
1
SBU2 → AUXn
SBU1 → AUXp
00
0
X
Open
01
X
X
SBU1 → AUXn
SBU2 → AUXp
10
X
X
SBU2 → AUXn
SBU1 → AUXp
11
X
X
Open
8.4.3 DisplayPort Mode
The TUSB1064 supports up to four DisplayPort lanes at datarates up to 8.1 Gbps. TUSB1064 can be enabled for
DisplayPort through GPIO control pin CTL1 or through I2C register CTLSEL1. When I2C_EN is ‘0’, DisplayPort is
controlled based on Table 2. When not in GPIO mode, DisplayPort functionality is controlled through I2C
registers. Data transfer through the DisplayPort lanes is further controlled by the HPDIN pin. DisplayPort needs
to be enabled using CTL1 pin or CTLSEL1 register and also HPDIN needs to be pulled high for the DisplayPort
data trasfer to be enabled through the DisplayPort lanes.
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8.4.4 Linear EQ Configuration
Each of the TUSB1064 receiver lanes has individual controls for receiver equalization. The receiver equalization
gain value can be controlled either through I2C registers or through GPIOs. details the gain value for each
available combination when TUSB1064 is in GPIO mode. These same options are also available in I2C mode by
updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, DP3EQ_SEL, EQ1_SEL, EQ2_SEL, and
SSEQ_SEL. Each of the 4-bit EQ configuration registers is mapped to the configuration pins as follows: x_SEL =
{x1[1:0],x0[1:0]} where xn[1:0] are the EQ configuration pins with pin levels mapped to 2-bit values as: 0 = 00, R
= 01, F = 10, 1 = 11.
Table 7. TUSB1064 Receiver Equalization GPIO Control
USB3.1 UPSTREAM FACING PORTS
Equalization
Setting #
EQ1 PIN
LEVEL
USB 3.1 DOWNSTREAM FACING PORT
EQ0 PIN LEVEL
EQ GAIN at
5 GHz (dB)
SSEQ1 PIN
LEVEL
ALL DISPLAYPORT LANES
SSEQ0 PIN
LEVEL
EQ GAIN at 5
GHz (dB)
DPEQ1 PIN
LEVEL
DPEQ0 PIN
LEVEL
EQ GAIN at
4.05 GHz (dB)
0
0
0
-1.5
0
0
-3.0
0
0
-0.3
1
0
R
0.7
0
R
-0.8
0
R
1.6
2
0
F
2.2
0
F
-0.7
0
F
3.0
3
0
1
3.7
0
1
2.2
0
1
4.4
4
R
0
4.7
R
0
3.3
R
0
5.4
5
R
R
5.8
R
R
4.3
R
R
6.5
6
R
F
6.6
R
F
5.1
R
F
7.3
7
R
1
7.4
R
1
6.0
R
1
8.1
8
F
0
8.1
F
0
6.7
F
0
8.9
9
F
R
8.7
F
R
7.3
F
R
9.5
10
F
F
9.2
F
F
7.8
F
F
10.0
11
F
1
9.7
F
1
8.3
F
1
10.6
12
1
0
10
1
0
8.6
1
0
11.0
13
1
R
10.4
1
R
9.0
1
R
11.4
14
1
F
10.7
1
F
9.3
1
F
11.8
15
1
1
11.1
1
1
9.7
1
1
12.1
8.4.5 USB3.1 Modes
The TUSB1064 monitors the physical layer conditions like receiver termination, electrical idle, LFPS, and
SuperSpeed signaling rate to determine the state of the USB3.1 interface. Depending on the state of the USB
3.1 interface, the TUSB1064 can be in one of four primary modes of operation when USB 3.1 is enabled (CTL0 =
H or CTLSEL0 = 1b1): Disconnect, U2/U3, U1, and U0.
The Disconnect mode is the state in which TUSB1064 has not detected far-end termination on upstream facing
port (UFP) or downstream facing port (DFP). The disconnect mode is the lowest power mode of each of the four
modes. The TUSB1064 remains in this mode until far-end receiver termination has been detected on both UFP
and DFP. The TUSB1064 immediately exits this mode and enter U0 once far-end termination is detected.
Once in U0 mode, the TUSB1064 will redrive all traffic received on UFP and DFP. U0 is the highest power mode
of all USB3.1 modes. The TUSB1064 remains in U0 mode until electrical idle occurs on both UFP and DFP.
Upon detecting electrical idle, the TUSB1064 immediately transitions to U1.
The U1 mode is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB1064 UFP
and DFP receiver termination remains enabled. The UFP and DFP transmitter DC common mode is maintained.
The power consumption in U1 is similar to power consumption of U0.
Next to the disconnect mode, the U2/U3 mode is next lowest power state. While in this mode, the TUSB1064
periodically performs far-end receiver detection. Anytime the far-end receiver termination is not detected on
either UFP or DFP, the TUSB1064 leaves the U2/U3 mode and transitions to the Disconnect mode. It also
monitors for a valid LFPS. Upon detection of a valid LFPS, the TUSB1064 immediately transitions to the U0
mode. In U2/U3 mode, the TUSB1064 receiver terminations remain enabled but the TX DC common mode
voltage is not maintained.
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8.4.6 Operation Timing – Power Up
Tctl_db
DISABLED
In I2C mode
USB3.1- only
FLIP = 0
DISABLED
In GPIO mode
Mode of operation
determined by value of
FLIPSEL bit and CTLSEL[1:0]
bits at offset0x0A. Default
is USB3.1- only no Flip.
USB3.1- only
FLIP = 0
If (( CTL[1:0 ] == 2'b 00 | CTL[1:0 ] == 2'b 01 ) & FLIP == 0 ) {
USB3.1- only no FLIP;
} ELSEIF((CTL[1:0 ] == 2'b 00 | CTL[1:0 ] == 2'b01 ) & FLIP == 1 ) {
USB3.1- only with FLIP ;
} ELSEIF(CTL[1:0 ] == 2'b 10 & FLIP == 0 ) {
4-Lane DP no FLIP;
} ELSEIF(CTL[1:0 ] == 2'b 10 & FLIP == 1 ) {
4-Lane DP with FLIP;
} ELSEIF(CTL[1:0 ] == 2'b 11 & FLIP == 0 ) {
2-Lane DP USB3.1 no FLIP;
} ELSE{
2-Lane DP USB3.1 with FLIP ;
};
CTL[1:0 ] pins
FLIP pin
VCC (min)
VCC
Td_pg
Internal
Power
Good
T Cfg_su
TCfg_hd
CFG pins
Figure 17. Power-Up Timing
Table 8. Power-Up Timing (1) (2)
PARAMETER
MIN
td_pg
VCC (minimum) to Internal Power Good asserted high
tcfg_su
CFG(1) pins setup(2)
50
tcfg_hd
CFG(1) pins hold
10
tCTL_DB
CTL[1:0] and FLIP pin debounce
tVCC_RAMP
VCC supply ramp requirement
(1)
(2)
22
0.1
MAX
UNIT
500
µs
µs
µs
16
ms
100
ms
Following pins comprise CFG pins: I2C_EN, EQ[1:0], SSEQ[1:0], and DPEQ[1:0].
Recommend CFG pins are stable when VCC is at minimum value.
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8.5 Programming
For further programmability, the TUSB1064 can be controlled using I2C. The SCL and SDA pins are used for I2C
clock and I2C data respectively.
Table 9. TUSB1064 I2C Target Address
DPEQ0/A1
PIN LEVEL
SSEQ0/A0
PIN LEVEL
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (W/R)
0
0
1
0
0
0
1
0
0
0/1
0
R
1
0
0
0
1
0
1
0/1
0
F
1
0
0
0
1
1
0
0/1
0
1
1
0
0
0
1
1
1
0/1
R
0
0
1
0
0
0
0
0
0/1
R
R
0
1
0
0
0
0
1
0/1
R
F
0
1
0
0
0
1
0
0/1
R
1
0
1
0
0
0
1
1
0/1
F
0
0
0
1
0
0
0
0
0/1
F
R
0
0
1
0
0
0
1
0/1
F
F
0
0
1
0
0
1
0
0/1
F
1
0
0
1
0
0
1
1
0/1
1
0
0
0
0
1
1
0
0
0/1
1
R
0
0
0
1
1
0
1
0/1
1
F
0
0
0
1
1
1
0
0/1
1
1
0
0
0
1
1
1
1
0/1
The following procedure should be followed to write to TUSB1064 I2C registers:
1. The master initiates a write operation by generating a start condition (S), followed by the TUSB1064 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB1064 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TUSB1064) to be written, consisting of one byte of
data, MSB-first.
4. The TUSB1064 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The TUSB1064 acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the TUSB1064.
8. The master terminates the write operation by generating a stop condition (P).
The following procedure should be followed to read the TUSB1064 I2C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the
address and a one-value “W/R” bit to indicate a read cycle.
2. The TUSB1064 acknowledges the address cycle.
3. The TUSB1064 transmit the contents of the memory registers MSB-first starting at register
sub-address+1. If a write to the I2C register occurred prior to the read, then the TUSB1064
sub-address specified in the write.
4. The TUSB1064 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK)
after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the TUSB1064 transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
TUSB1064 7-bit
00h or last read
shall start at the
from the master
The following procedure should be followed for setting a starting sub-address for I2C reads:
1. The master initiates a write operation by generating a start condition (S), followed by the TUSB1064 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB1064 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TUSB1064) to be written, consisting of one byte of
data, MSB-first.
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4. The TUSB1064 acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).
NOTE
If no sub-addressing is included for the read procedure, and reads start at register offset
00h and continue byte by byte through the registers until the I2C master terminates the
read operation. If a I2C address write occurred prior to the read, then the reads start at the
sub-address specified by the address write.
Table 10. Register Legend
24
ACCESS TAG
NAME
R
Read
The field may be read by software
W
Write
The field may be written by software
S
Set
C
Clear
U
Update
NA
No Access
MEANING
The field may be set by a write of one. Writes of zeros to the field have no effect.
The field may be cleared by a write of one. Write of zero to the field have no effect.
Hardware may autonomously update this field.
Not accessible or not applicable
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8.6 Register Maps
8.6.1 General Register (address = 0x0A) [reset = 00000001]
Figure 18. General Registers
7
Reserved
6
5
Reserved
R
R
4
EQ_OVERRID
E
R/W
3
HPDIN_OVRRI
DE
R/W
2
FLIPSEL
1
0
CTLSEL[1:0].
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. General Registers
Bit
Field
Type
Reset
Description
7:5
Reserved.
R
00
Reserved.
0
Setting of this field will allow software to use EQ settings from
registers instead of value sample from pins.
0 – EQ settings based on sampled state of the EQ pins
(SSEQ[1:0], EQ[1:0], and DPEQ[1:0]).
1 – EQ settings based on programmed value of each of the EQ
registers
4
EQ_OVERRIDE
R/W
3
DP_EN_CTRL
R/W
0
Controls whether DisplayPort functionality is controlled by
CTLSEL1 register or CTL1 pin.
0 – DisplayPort enable/disable is based on CTLSEL1 register.
1 – DisplayPort enable/disable is based on state of CTL1 pin.
2
FLIPSEL
R/W
0
FLIPSEL. Refer to Table 5 and Table 6 for this field functionality.
01
00 – Disabled. All RX and TX for USB3 and DisplayPort are
disabled.
01 – USB3.1 only enabled. (Default)
10 – Four DisplayPort lanes enabled.
11 – Two DisplayPort lanes and one USB3.1
1:0
CTLSEL[1:0].
R/W
8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
Figure 19. DisplayPort Control/Status Registers (0x10)
7
6
5
4
3
DP1EQ_SEL
R/W/U
2
1
0
DP3EQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. DisplayPort Control/Status Registers (0x10)
Bit
Field
Type
Reset
Description
7:4
DP1EQ_SEL
R/W/U
0000
Field selects EQ level for DP lane 1. When EQ_OVERRIDE =
1’b0, this field reflects the sampled state of DPEQ[1:0] pins.
When EQ_OVERRIDE = 1’b1, software can change the EQ
setting for DP lane 1 based on value written to this field.
3:0
DP3EQ_SEL
R/W/U
0000
Field selects EQ level for DP lane 3. When EQ_OVERRIDE =
1’b0, this field reflects the sampled state of DPEQ[1:0] pins.
When EQ_OVERRIDE = 1’b1, software can change the EQ
setting for DP lane 3 based on value written to this field.
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8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
Figure 20. DisplayPort Control/Status Registers (0x11)
7
6
5
4
3
2
DP0EQ_SEL
R/W/U
1
0
DP2EQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. DisplayPort Control/Status Registers (0x11)
Bit
7:4
3:0
Field
Type
DP0EQ_SEL
R/W/U
DP2EQ_SEL
R/W/U
Reset
Description
0000
Field selects EQ level for DP lane 0. When EQ_OVERRIDE =
1’b0, this field reflects the sampled state of DPEQ[1:0] pins.
When EQ_OVERRIDE = 1’b1, software can change the EQ
setting for DP lane 0 based on value written to this field.
0000
Field selects EQ level for DP lane 2. When EQ_OVERRIDE =
1’b0, this field reflects the sampled state of DPEQ[1:0] pins.
When EQ_OVERRIDE = 1’b1, software can change the EQ
setting for DP lane 2 based on value written to this field.
8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
Figure 21. DisplayPort Control/Status Registers (0x12)
7
Reserved
R
6
5
SET_POWER_STATE
RU
4
3
2
LANE_COUNT_SET
RU
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. DisplayPort Control/Status Registers (0x12)
Bit
7
6:5
4:0
26
Field
Type
Reset
Description
Reserved
R
0
Reserved
00
This field represents the snooped value of the AUX write to
DPCD address 0x00600. When AUX_SNOOP_DISABLE = 1’b0,
the TUSB1064 will enable/disable DP lanes based on the
snooped value. When AUX_SNOOP_DISABLE = 1’b1, then DP
lane enable/disable are determined by state of DPx_DISABLE
registers, where x = 0, 1, 2, or 3. This field is reset to 2’b00 by
hardware when CTLSEL1 changes from a 1’b1 to a 1’b0.
00000
This field represents the snooped value of AUX write to DPCD
address 0x00101 register. When AUX_SNOOP_DISABLE =
1’b0, TUSB1064 will enable DP lanes specified by the snoop
value. Unused DP lanes will be disabled to save power. When
AUX_SNOOP_DISABLE = 1’b1, then DP lanes enable/disable
are determined by DPx_DISABLE registers, where x = 0, 1, 2, or
3. This field is reset to 0x0 by hardware when CTLSEL1
changes from a 1’b1 to a 1’b0.
SET_POWER_STATE
LANE_COUNT_SET
R/U
R/U
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8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
Figure 22. DisplayPort Control/Status Registers (0x13)
7
AUX_SNOOP_
DISABLE
R/W
6
Reserved
5
4
AUX_SBU_OVR
3
DP3_DISABLE
2
DP2_DISABLE
1
DP1_DISABLE
0
DP0_DISABLE
R
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. DisplayPort Control/Status Registers (0x13)
Bit
Field
Type
Reset
Description
7
AUX_SNOOP_DISABLE
R/W
0
0 – AUX snoop enabled. (Default)
1 – AUX snoop disabled.
6
Reserved
R
0
Reserved
00
This field overrides the AUXp or AUXn to SBU1 or SBU2
connect and disconnect based on CTL1 and FLIP. Changing this
field to 2’b01 or 2'b10 will allow traffic to pass through AUX to
SBU regardless of the state of CTLSEL1 and FLIPSEL register
00 – AUX to SBU connect/disconnect determined by CTLSEL1
and FLIPSEL (Default)
01 – AUXn -> SBU1 and AUXp -> SBU2 connection always
enabled.
10 – AUXn -> SBU2 and AUXp -> SBU1 connection always
enabled.
11 – AUX to SBU open.
0
When AUX_SNOOP_DISABLE = 1’b1, this field can be used to
enable or disable DP lane 3. When AUX_SNOOP_DISABLE =
1’b0, changes to this field will have no effect on lane 3
functionality.
0 – DP Lane 3 Enabled (default)
1 – DP Lane 3 Disabled.
0
When AUX_SNOOP_DISABLE = 1’b1, this field can be used to
enable or disable DP lane 2. When AUX_SNOOP_DISABLE =
1’b0, changes to this field will have no effect on lane 2
functionality.
0 – DP Lane 2 Enabled (default)
1 – DP Lane 2 Disabled.
0
When AUX_SNOOP_DISABLE = 1’b1, this field can be used to
enable or disable DP lane 1. When AUX_SNOOP_DISABLE =
1’b0, changes to this field will have no effect on lane 1
functionality.
0 – DP Lane 1 Enabled (default)
1 – DP Lane 1 Disabled.
0
DISABLE. When AUX_SNOOP_DISABLE = 1’b1, this field can
be used to enable or disable DP lane 0. When
AUX_SNOOP_DISABLE = 1’b0, changes to this field will have
no effect on lane 0 functionality.
0 – DP Lane 0 Enabled (default)
1 – DP Lane 0 Disabled.
5:4
AUX_SBU_OVR
3
R/W
DP3_DISABLE
2
R/W
DP2_DISABLE
1
R/W
DP1_DISABLE
0
R/W
DP0_DISABLE
R/W
8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
Figure 23. USB3.1 Control/Status Registers (0x20)
7
6
5
4
3
EQ2_SEL
R/W/U
2
1
0
EQ1_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 16. USB3.1 Control/Status Registers (0x20)
Bit
Field
7:4
Type
EQ2_SEL
3:0
R/W/U
EQ1_SEL
R/W/U
Reset
Description
0000
Field selects EQ level for USB3.1 RX2 receiver. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
EQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for USB3.1 RX2 receiver based on value
written to this field.
0000
Field selects EQ level for USB3.1 RX1 receiver. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
EQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for USB3.1 RX1 receiver based on value
written to this field.
8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
Figure 24. USB3.1 Control/Status Registers (0x21)
7
6
5
4
3
Reserved
R
2
1
0
SSEQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. USB3.1 Control/Status Registers (0x21)
Bit
Field
Type
Reset
Description
7:4
Reserved
R
0000
Reserved
0000
Field selects EQ for USB3.1 SSTXP/N receiver. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
SSEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for USB3.1 SSTXP/N receiver based on
value written to this field.
3:0
28
SSEQ_SEL
R/W/U
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8.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
Figure 25. USB3.1 Control/Status Registers (0x22)
7
CM_ACTIVE
6
LFPS_EQ
R/U
R/W
5
U2U3_LFPS_D
EBOUNCE
R/W
4
DISABLE_U2U
3_RXDET
R/W
3
2
DFP_RXDET_INTERVAL
1
0
USB3_COMPLIANCE_CTRL
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. USB3.1 Control/Status Registers (0x22)
Bit
7
Field
Type
Reset
Description
CM_ACTIVE
R/U
0
0 –device not in USB 3.1 compliance mode. (Default)
1 –device in USB 3.1 compliance mode
6
LFPS_EQ
R/W
0
Controls whether settings of EQ based on EQ1_SEL, EQ2_SEL
and SSEQ_SEL applies to received LFPS signal.
0 – EQ set to zero when receiving LFPS (default)
1 – EQ set to EQ1_SEL, EQ2_SEL, and SSEQ_SEL when
receiving LFPS.
5
U2U3_LFPS_DEBOUNCE
R/W
0
0 – No debounce of LFPS before U2/U3 exit. (Default)
1 – 200us debounce of LFPS before U2/U3 exit.
4
DISABLE_U2U3_RXDET
R/W
0
0 – Rx.Detect in U2/U3 enabled. (Default)
1 – Rx.Detect in U2/U3 disabled.
00
This field controls the Rx.Detect interval for the Downstream
facing port (TX1P/N and TX2P/N).
00 – 8 ms
01 – 12 ms (default)
10 – Reserved
11 – Reserved
00
00 – FSM determined compliance mode. (Default)
01 – Compliance Mode enabled in DFP direction (SSTX ->
TX1/TX2)
10 – Compliance Mode enabled in UFP direction (RX1/RX2 ->
SSRX)
11 – Compliance Mode Disabled.
3:2
1:0
DFP_RXDET_INTERVAL
USB3_COMPLIANCE_CTRL
R/W
R/W
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TUSB1064 is a linear redriver designed specifically to compensation for intersymbol interference (ISI) jitter
caused by signal attenuation through a passive medium like PCB traces and cables. Because the TUSB1064
has four independent DisplayPort 1.4 inputs, one upstream facing USB 3.1 Gen 2 input, and two downstream
facing USB 3.1 Gen 2 inputs, it can be optimized to correct ISI on all those seven inputs through 16 different
equalization choices. Placing the TUSB1064 between a USB3.1 Host/DisplayPort 1.4 GPU and a USB3.1 TypeC receptacle can correct signal integrity issues resulting in a more robust system.
9.2 Typical Application
E
A
F
PCB Trace of Length XEF
B
PCB Trace of Length XAB
SSRXP
SSRXN
USB3.1
Hub
SSTXP
RX2P
SSTXN
RX2N
TX2P
Type-C Receptacle
TX2N
TUSB1064
DP0P
DP0N
TX1N
DP1P
TX1P
DP1N
RX1N
DP2P
DP 1.4
RX
DP2N
RX1P
DP3P
DP3N
PCB Trace of Length XGH
G
PCB Trace of Length XCD
H
D
C
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Figure 26. TUSB1064 in a Host Application
30
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters shown in Table 19.
Table 19. Design Parameters
PARAMETER
VALUE
A to B PCB trace length, XAB
12 inches
C to D PCB trace length, XCD
12 inches
E to F PCB trace length, XEF
2 inches
G to H PCB trace length, XGH
2 inches
PCB trace width
4 mils
AC-coupling capacitor (75 nF to 265 nF)
100 nF
VCC supply (3 V to 3.6 V)
3.3 V
I2C Mode or GPIO Mode
I2C Mode. (I2C_EN pin != "0")
1.8V or 3.3V I2C Interface
3.3V I2C. Pull-up the I2C_EN pin to 3.3V with a 1K ohm resistor.
CTL1, EQ[1:0], SSEQ[1:0], and DPEQ[1:0] pin unconnected.
EQ setting for DisplayPort Lanes
EQ Setting # 5 (Register 0x0A[4] = 1'b1, 0x10 = 0x55; 0x11 = 0x55)
EQ setting for Downstream USB Data Path
EQ Setting # 6 (Register 0x0A[4] = 1'b1, 0x20 = 0x66)
EQ setting for Upstream USB Data Path
EQ Setting # 6 (Register 0x0A[4] = 1'b1, 0x21 = 0x08)
9.2.2 Detailed Design Procedure
A typical usage of the TUSB1064 device is shown in Figure 27. The device can be controlled either through its
GPIO pins or through its I2C interface. In the example shown below, a Type-C PD controller is used to configure
the device through the I2C interface. In I2C mode, the equalization settings for each receiver can be
independently controlled through I2C registers. For this reason, the configuration pin CTL1 and all of the
equalization pins (EQ[1:0], SSEQ[1:0], and DPEQ[1:0]) can be left unconnected. If these pins are left
unconnected, the TUSB1064 7-bit I2C slave address will be 0x12 because both DPEQ/A1 and SSEQ0/A0 will be
at pin level "F". If a different I2C slave address is desired, DPEQ/A1 and SSEQ0/A0 pins should be set to a level
which produces the desired I2C slave address.
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3.3V
10PF
RX2p
SSTXp
TXN2
VBUS
CC2
DP2
DN2
SBU2
100nF
SSTXP
100nF
SSTXN
SSTXn
TX2n
DP_PWR (3.3V)
A11
B2
1M (± 5%)
RXN2
A10
VBUS
A9
DP1.4 RX
NC
SRC_DET#
B3
B4
SBU1
A8
SBU1
DN1
A7
SBU2
AUXp
100nF
AUXP
AUXn
100nF
AUXN
SRC_DET
B5
1M (± 5%)
100nF
B6
DP1
A6
CC1
A5
TUSB1064
TXP2
A12
SSRXN
100nF
B1
RXP2
SSRXP
SSRXn
RX2n
100nF
TX2p
GND
100nF
SSRXp
100nF
USB Type-C
Receptacle
GND
USB 3.1 Hub
VCC
100nF
VCC
100nF
VCC
100nF
2M
2M
B7
B8
DP0p
DP_ML0P
100nF
DP0n
DP1p
DP_ML0N
100nF
DP_ML1P
100nF
DP1n
VBUS
VBUS
A4
TXN1
A3
100 nF
B9
TX1n
DP2p
TX1p
DP2n
RX1n
DP3p
100 nF
RXN1
DP_ML2P
100nF
DP_ML2N
100nF
B10
TXP1
RXP1
DP_ML1N
100nF
A2
DP_ML3P
100nF
RX1p
B11
DP_ML3N
DP3n
3.3V
GND
GND
A1
B12
I2C_EN
SSEQ0/A0
VI2C
3.3V
3.3V
3.3V
3.3V
SSEQ1
R
R
DPEQ0/A1
FLIP/SCL
3.3V
3.3V
EQ0
CTL1
EQ1
HPDIN
EN
TP
Type-C
PD
Controller
DPEQ1
CTL0/SDA
Copyright © 2017, Texas Instruments Incorporated
Figure 27. Application Circuit
32
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9.2.3 Support for DisplayPort UFP_D Pin Assignment E
The TUSB1064 device can be used in a system that handles DisplayPort UFP_D Pin Assignment E use-case if
special measures are taken as described below. With UFP_D Pin Assignment E, the polarity of both the main
link and AUX signals is inverted on the Type-C receptacle pins relative to Pin Assignment C. Moreover, on the
Type-C receptacle, the location of Lane 0 is swapped with Lane 1 and that of Lane 2 is swapped with Lane 3
relative to Pin Assignment C. For correct reception of the DisplayPort video signal, the system has to
comprehend the above-described signaling variation.
The use of the TUSB1064 device in a system that handles Pin Assignment E depends on whether AUX-to-SBU
switching of the DisplayPort AUX signal is performed internally by the TUSB1064 or by external devices such as
a PD controller. It also depends on the configuration mode used: I2C Mode or GPIO Mode. In all those scenarios
the TUSB1064 passes the polarity of the Main Link signals as received. The DisplayPort sink has to handle the
polarity inversion of those signals. Moreover, the DisplayPort sink has to handle the lane swapping with the
following lane-to-pin mapping as received by the TUSB1064 device: Lane 0 → DP1, Lane 1 → DP0, Lane 2 →
DP3, and Lane 3 → DP2.
The use-case with the AUX-to-SBU switching performed internally by the TUSB1064 device is shown in
Figure 28. If the TUSB1064 device configuration is through the I2C Mode, AUX snooping has to be disabled by
setting AUX_SNOOP_DISABLE register 0x13[7] = 1'b1, and manual AUX-to-SBU switching has to be performed
through the AUX_SBU_OVR register 0x13[5:4]: AUX_SBU_OVR = 2’b01 for normal USB Type-C plug
orientation, or AUX_SBU_OVR = 2’b10 for flipped USB Type-C plug orientation when Pin Assignment E signals
are received. If the TUSB1064 device configuration is through the GPIO Mode, all 4 DisplayPort lanes are
automatically activated. The DisplayPort sink device has to handle the polarity inversion of both the AUX and
Main Link signals as well as main link lane swapping.
TX1
RX1
RX2
TX2
DP0
DP1
DP2
DP3
ML0
ML1
ML2
ML3
TUSB1064
SBU1
AUXn
SBU2
AUXp
Type-C Receptacle
DP SINK
3.3V
1M (+/-5%)
Make AUX connections as short as
possible to minimize stub effects
SRC_DET#
100nF
SBU2
SBU2
AUXP
AUXP
PD Controller
100nF
SBU1
SBU1
AUXN
AUXN
SRC_DET
2M
1M (+/-5%)
2M
Copyright © 2017, Texas Instruments Incorporated
Figure 28. DisplayPort AUX Connections for UFP_D Pin Assignment E with Internal AUX Switching
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The use-case with the AUX-to-SBU switching performed by an external device is shown in Figure 29. In this
case, it is assumed that the PD controller is capable of correcting the polarity inversion of the AUX signal and the
TUSB1064 is provided with the corrected polarity of the AUX signal through its AUXp/AUXn pins. If the
TUSB1064 device configuration is through the I2C Mode, AUX snooping should be disabled by setting
AUX_SNOOP_DISABLE register 0x13[7] = 1'b1. The DisplayPort sink device has to handle the polarity inversion
of the Main Link signals as well as the Main Link lane swapping.
TX1
RX1
RX2
TX2
DP0
DP1
DP2
DP3
ML0
ML1
ML2
ML3
TUSB1064
SBU1
AUXn
SBU2
AUXp
Type-C Receptacle
DP SINK
3.3V
1M (+/-5%)
Make AUX connections as short as
possible to minimize stub effects
SRC_DET#
100nF
SBU2
SBU2
AUXP
AUXP
PD Controller
100nF
SBU1
AUXN
AUXN
SBU1
SRC_DET
2M
1M (+/-5%)
2M
Copyright © 2017, Texas Instruments Incorporated
Figure 29. DisplayPort AUX Connections for UFP_D Pin Assignment E with External AUX Switching
9.2.4 PCB Insertion Loss Curves
0
-5
-10
Insertion Loss (dB)
-15
-20
-25
-30
-35
Length=12in, Width=6mil
Length=16in, Width=6mil
Length=20in, Width=6mil
Length=24in, Width=6mil
Length=4in, Width=4mil
Length=8in, Width=10mil
Length=8in, Width=6mil
-40
-45
-50
-55
-60
0
2
4
6
8
10
Frequency (GHz)
12
14
16
D009
Figure 30. Insertion Loss of FR4 PCB Traces
34
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9.3 System Examples
9.3.1 USB 3.1 Only
The TUSB1064 is in USB3.1 only when the CTL1 pin is low and CTL0 pin is high.
D+/-
USB Host
SSTX
D+/-
1 Port USB
TUSB1046A-DCI
TUSB1064
SSRX
SSTX
TX2
RX1
TX1
DP1
RX1
DP2
GPU
DP3
Type-C Receptacle
TX1
Type-C Receptacle
RX2
DP0
RX2
DP0
TX2
DP1
DP2
DP RX
DP3
AUXp
SBU1
SBU2
AUXn
SBU2
SBU1
AUXn
AUXp
HPDIN
HPDIN
FLIP 0 1 CTL
HPD
Control
USB Hub
SSRX
PD Controller
FLIP 0 1 CTL
CC1
CC1
CC2
CC2
CTL1/0/FLIP=L/H/L
HPD
PD Controller
Control
CTL1/0/FLIP=L/H/L
Copyright © 2017, Texas Instruments Incorporated
Figure 31. USB3.1 Only – No Flip (CTL1 = L, CTL0 = H, FLIP = L)
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System Examples (continued)
D+/-
USB Host
SSTX
D+/-
1 Port USB
TUSB1064
TUSB1046A-DCI
SSTX
SSRX
TX2
RX1
TX1
DP1
RX1
DP2
GPU
DP3
AUXp
SBU1
AUXn
SBU2
Type-C Receptacle
TX1
Type-C Receptacle
RX2
DP0
RX2
DP0
TX2
DP1
DP2
DP RX
DP3
SBU2
AUXp
CC1
PD Controller
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
AUXn
SBU1
HPDIN
Control
USB Hub
SSRX
CC2
CC1
CC2
HPD
PD Controller
Control
CTL1/0/FLIP=L/H/H
CTL1/0/FLIP=L/H/H
Copyright © 2017, Texas Instruments Incorporated
Figure 32. USB3.1 Only – With Flip (CTL1 = L, CTL0 = H, FLIP = H)
36
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System Examples (continued)
9.3.2 USB 3.1 and 2 Lanes of DisplayPort
The TUSB1064 operates in USB3.1 and 2 Lanes of DisplayPort mode when the CTL1 pin is high and CTL0 pin
is high.
1 Port USB &
2 Lane DP
D+/-
USB Host
SSTX
D+/-
TUSB1046A-DCI
TUSB1064
SSTX
SSRX
TX2
RX1
TX1
DP1
RX1
DP2
GPU
DP3
Type-C Receptacle
TX1
Type-C Receptacle
RX2
DP0
RX2
DP0
TX2
DP1
DP2
DP RX
DP3
AUXp
SBU1
SBU1
AUXn
SBU2
SBU2
AUXn
AUXp
HPDIN
HPD
Control
USB Hub
SSRX
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
CC1
PD Controller
CC2
HPD
CC1
CC2
CTL1/0/FLIP=H/H/L
PD Controller
Control
CTL1/0/FLIP=H/H/L
Copyright © 2016, Texas Instruments Incorporated
Figure 33. USB3.1 + 2 Lane DP – No Flip (CTL1 = H, CTL0 = H, FLIP = L)
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System Examples (continued)
1 Port USB &
2 Lane DP
D+/-
USB Host
D+/-
TUSB1046A-DCI
SSTX
TUSB1064
SSRX
SSTX
SSRX
TX2
RX1
TX1
DP1
RX1
DP2
GPU
DP3
Type-C Receptacle
TX1
Type-C Receptacle
RX2
DP0
RX2
DP0
TX2
DP1
DP2
DP RX
DP3
AUXp
SBU1
SBU1
AUXn
SBU2
SBU2
AUXn
AUXp
HPDIN
HPDIN
FLIP 0 1 CTL
HPD
Control
USB Hub
PD Controller
FLIP 0 1 CTL
CC1
CC1
CC2
CC2
HPD
PD Controller
Control
CTL1/0/FLIP=H/H/H
CTL1/0/FLIP=H/H/H
Copyright © 2016, Texas Instruments Incorporated
Figure 34. USB 3.1 + 2 Lane DP – Flip (CTL1 = H, CTL0 = H, FLIP = H)
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System Examples (continued)
9.3.3 DisplayPort Only
The TUSB1064 operates in 4 Lanes of DisplayPort only mode when the CTL1 pin is high and CTL0 pin is low.
D+/-
USB Host
SSTX
D+/-
4 Lane DP
TUSB1064
TUSB1046A-DCI
SSRX
SSTX
SSRX
TX2
RX1
TX1
DP1
RX1
DP2
GPU
DP3
Type-C Receptacle
TX1
Type-C Receptacle
RX2
DP0
RX2
DP0
TX2
DP1
DP2
DP RX
DP3
AUXp
SBU1
SBU1
AUXn
AUXn
HPDIN
SBU2
SBU2
AUXp
HPDIN
HPD
Control
USB Hub
FLIP 0 1 CTL
FLIP 0 1 CTL
CC1
PD Controller
CC2
HPD
CC1
CC2
PD Controller
Control
CTL1/0/FLIP=H/L/L
CTL1/0/FLIP=H/L/L
Copyright © 2017, Texas Instruments Incorporated
Figure 35. Four Lane DP – No Flip (CTL1 = H, CTL0 = L, FLIP = L)
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System Examples (continued)
D+/-
USB Host
SSTX
D+/-
4 Lane DP
TUSB1046A-DCI
TUSB1064
SSRX
SSTX
TX2
RX1
TX1
DP1
RX1
DP2
GPU
DP3
Type-C Receptacle
TX1
Type-C Receptacle
RX2
DP0
RX2
DP0
TX2
DP1
DP2
DP RX
DP3
AUXp
SBU1
SBU1
AUXn
HPDIN
SBU2
SBU2
AUXn
AUXp
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
Control
USB Hub
SSRX
CC1
PD Controller
CC2
CTL1/0/FLIP=H/L/H
CC1
CC2
PD Controller
HPD
Control
CTL1/0/FLIP=H/L/H
Copyright © 2017, Texas Instruments Incorporated
Figure 36. Four Lane DP – With Flip (CTL1 = H, CTL0 = L, FLIP = H)
10 Power Supply Recommendations
The TUSB1064 is designed to operate with a 3.3-V power supply. Levels above those listed in the table should
not be used. If using a higher voltage system power supply, a voltage regulator can be used to step down to 3.3
V. Decoupling capacitors should be used to reduce noise and improve power supply integrity. A 0.1-µF capacitor
should be used on each power pin.
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11 Layout
11.1 Layout Guidelines
1.
2.
3.
4.
5.
6.
RXP/N and TXP/N pairs should be routed with controlled 90-Ω differential impedance (±15%).
Keep away from other high speed signals.
Intra-pair routing should be kept to within 2 mils.
Length matching should be near the location of mismatch.
Each pair should be separated at least by 3 times the signal trace width.
The use of bends in differential traces should be kept to a minimum. When bends are used, the number of
left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This
will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on
EMI.
7. Route all differential pairs on the same of layer.
8. The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.
9. Keep traces on layers adjacent to ground plane.
10. Do NOT route differential pairs over any plane split.
11. Adding Test points will cause impedance discontinuity, and therefore, negatively impact signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes a stub on the differential pair.
11.2 Layout Example
SSRX
AC Coupling
capacitors
TX1
DP0
RX1
DP1
RX2
GND
DP2
To DP Sink
To USB Type-C
Receptacle
SSTX
To USB Hub
TX2
AUX
SBU
DP3
Figure 37. Layout Example
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
USB Type-C is a trademark of USB Implementers Forum.
DisplayPort is a trademark of VESA.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TUSB1064IRNQR
ACTIVE
WQFN
RNQ
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TUSB64
TUSB1064IRNQT
ACTIVE
WQFN
RNQ
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TUSB64
TUSB1064RNQR
ACTIVE
WQFN
RNQ
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
TUSB64
TUSB1064RNQT
ACTIVE
WQFN
RNQ
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
TUSB64
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TUSB1064IRNQR
WQFN
RNQ
40
TUSB1064IRNQT
WQFN
RNQ
TUSB1064RNQR
WQFN
RNQ
TUSB1064RNQT
WQFN
RNQ
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
4.3
6.3
1.1
8.0
12.0
Q2
40
250
180.0
12.4
4.3
6.3
1.1
8.0
12.0
Q2
40
3000
330.0
12.4
4.3
6.3
1.1
8.0
12.0
Q2
40
250
180.0
12.4
4.3
6.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TUSB1064IRNQR
WQFN
RNQ
40
3000
367.0
367.0
35.0
TUSB1064IRNQT
WQFN
RNQ
40
250
210.0
185.0
35.0
TUSB1064RNQR
WQFN
RNQ
40
3000
367.0
367.0
35.0
TUSB1064RNQT
WQFN
RNQ
40
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RNQ0040A
WQFN - 0.8 mm max height
SCALE 2.500
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
A
B
PIN 1 INDEX AREA
4.1
3.9
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08
4.7±0.1
2X 4.4
(0.2) TYP
9
36X 0.4
20
8
EXPOSED
THERMAL PAD
21
2X
2.8
2.7±0.1
1
PIN 1 ID
(OPTIONAL)
28
29
40
40X
0.5
0.3
0.25
0.15
0.1
C A
0.05
40X
B
4222125/B 01/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.7)
2X (2.1)
6X (0.75)
40
29
40X (0.6)
1
28
40X (0.2)
4X
(1.1)
SYMM
(3.8)
(2.7)
36X (0.4)
8
21
(R0.05) TYP
9
20
SYMM
( 0.2) TYP
VIA
(5.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222125/B 01/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (1.5)
40
29
40X (0.6)
1
28
40X (0.2)
6X
(0.695)
SYMM
(3.8)
6X
(1.19)
36X (0.4)
8
21
(R0.05) TYP
METAL
TYP
9
6X (1.3)
20
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
73% PRINTED SOLDER COVERAGE BY AREA
SCALE:18X
4222125/B 01/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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