Texas Instruments | TPS2583x-Q1 USB Type-C and BC1.2 5-V 3.5-A Output, 36-V Input Synchronous Step-Down DC/DC Regulator with Cable Compensation (Rev. D) | Datasheet | Texas Instruments TPS2583x-Q1 USB Type-C and BC1.2 5-V 3.5-A Output, 36-V Input Synchronous Step-Down DC/DC Regulator with Cable Compensation (Rev. D) Datasheet

Texas Instruments TPS2583x-Q1 USB Type-C and BC1.2 5-V 3.5-A Output, 36-V Input Synchronous Step-Down DC/DC Regulator with Cable Compensation (Rev. D) Datasheet
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TPS25830-Q1, TPS25831-Q1
SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
TPS2583x-Q1 USB Type-C and BC1.2 5-V 3.5-A Output, 36-V Input
Synchronous Step-Down DC/DC Regulator with Cable Compensation
1 Features
•
1
•
•
•
•
AEC-Q100 Qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
– HBM ESD classification level H2
– CDM ESD classification level C5
Synchronous buck DC/DC regulator
– Input voltage range: 4.5 V to 36 V
– Output current: 3.5 A
– 5.1-V Output voltage with ±1% accuracy
– Current mode control
– Adjustable frequency: 300 kHz to 2.2 MHz
– Frequency synchronization to external clock
– FPWM with spread-spectrum dithering
– Internal compensation for ease of use
Compliant to USB-IF standards
– USB Type-C Rev 1.3
– CC logic, VCONN source and discharge
– USB cable polarity detection (POL)
– CDP/SDP mode per USB BC1.2
– Automatic DCP modes (TPS25831-Q1 only)
– DCP shorted mode and YD/T 1591-2009
– 2.7-V Divider 3 mode
– 1.2-V Mode
Optimized for USB power and communication
– User-programmable USB current limit
– Cable droop compensation up to 1.5 V
– High bandwidth data switches on DP and DM
(TPS25830-Q1 only)
– NTC input for intelligent thermal management
(TPS25831-Q1 only)
Integrated protection
Simplified Schematic TPS2583x-Q1
–
–
–
–
•
•
VBUS Short-to-VBAT protection
DP_IN and DM_IN Short-to-VBAT and VBUS
CC1 and CC2 Short-to-VBAT protection
DP_IN, DM_IN, CCx IEC 61000-4-2 rated
– ±8kV Contact and ±15kV air discharge
Fault flag reports
32-Pin QFN package with Wettable Flank
2 Applications
•
•
•
Automotive Infotainment
USB Media Hubs
USB Charger Ports
3 Description
The TPS2583x-Q1 is a USB Type-C and BC1.2
charging port controller that includes a synchronous
DC/DC converter. With cable droop compensation,
the VBUS voltage remains constant regardless of load
current, ensuring connected portable devices are
charged at optimal current and voltage.
The TPS2583x-Q1 also integrates short to battery
protection on VBUS, CC1, CC2, DM_IN and DP_IN
pins. These pins can withstand voltage up to 18 V.
The TPS25830-Q1 includes high bandwidth analog
switches for DP and DM pass-through, while the
TPS25831-Q1 includes a thermistor input pin and
thermal warning flag for user programmable thermal
overload protection.
Device Information(1)
PART NUMBER
BOOT
IN
5.00 mm x 5.00 mm
TPS25831-Q1
VQFN (32)
5.00 mm x 5.00 mm
(1) For detail part numbers for all available different options, see
the orderable addendum at the end of the data sheet.
Buck Efficiency vs Output Current fsw = 400 kHz
100
95
L
90
RSNS
RSET
CSP
RT/SYNC
CSN/OUT
VCC
TPS2583x-Q1
LS_GD
FAULT
Optional
Efficiency (%)
SW
EN/UVLO
BODY SIZE (NOM)
VQFN (32)
CBOOT
VIN
PACKAGE
TPS25830-Q1
85
80
75
BUS
CTRL1
CC1
CTRL2
CC2
DP_OUT (THERM_WARN)
DP_IN
DM_OUT (NTC)
IMON
DM_IN
ILIMIT
AGND PGND
Type-C Connector
LD_DET
POL
70
VIN = 6V
VIN = 13.5V
VIN = 18V
VIN = 36V
65
60
0.1
1
OUT Current (A)
4
A001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS25830-Q1, TPS25831-Q1
SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
1
1
1
2
3
4
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Electrical Characteristics........................................... 8
Timing Requirements .............................................. 13
Switching Characteristics ........................................ 13
Typical Characteristics ............................................ 15
9 Parameter Measurement Information ................ 21
10 Detailed Description ........................................... 22
10.1 Overview ............................................................... 22
10.2 Functional Block Diagram ..................................... 23
10.3 Feature Description............................................... 23
10.4 Device Functional Modes...................................... 47
11 Application and Implementation........................ 51
11.1 Application Information.......................................... 51
11.2 Typical Application ................................................ 51
12 Power Supply Recommendations ..................... 63
13 Layout................................................................... 63
13.1 Layout Guidelines ................................................. 63
13.2 Ground Plane and Thermal Considerations.......... 64
13.3 Layout Example .................................................... 65
14 Device and Documentation Support ................. 66
14.1
14.2
14.3
14.4
14.5
14.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
66
66
66
66
66
66
15 Mechanical, Packaging, and Orderable
Information ........................................................... 66
4 Revision History
Changes from Revision C (July 2019) to Revision D
Page
•
Changed the High-Bandwidth Analog Switch RDS_ON MAX from 5.6 to 6.3 and from 6.8 to 7.7 in the Specifications
Electrical Characteristics table .............................................................................................................................................. 6
•
Added content for the TPS25830-Q1 timing requirement and Figure 43 in the Enable/UVLO and Start-up section .......... 26
•
Updated the LS_GD requirements in the Current Limit Setting using RILIMIT section........................................................... 32
Changes from Revision B (June 2019) to Revision C
Page
•
Changed TPS25830-Q1 to Production Data .......................................................................................................................... 1
•
Changed Supply Voltage (IN PIN) IQ from 800 to 990 in the Specifications Electrical Characteristics table ........................ 6
Changes from Revision A (November 2018) to Revision B
•
Page
Changed TPS25831-Q1 from Advance Information to Production Data ............................................................................... 1
Changes from Original (June 2018) to Revision A
•
2
Page
Changed device status from Product Preview to Advanced Information .............................................................................. 1
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SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
5 Description (continued)
The synchronous buck regulator operates with current mode control and is internally compensated to simplify
design. A resistor on the RT pin sets the switching frequency between 300 kHz and 2.2 MHz. Operating below
400 kHz results in better system efficiency. Operation above 2.1 MHz avoids the AM radio bands and allows for
use of a smaller inductor.
The TPS2583x-Q1 integrates standard USB Type-C port controller functionality including Configuration Channel
(CC) logic for 3-A and 1.5-A current advertisement. Battery Charging (Rev. 1.2) integration provides the required
electrical signatures necessary for non-Type-C, legacy USB devices which use USB data line signaling to
determine USB port current sourcing capabilities.
A precision current sense amplifier is included for user programmable cable droop compensation and current
limit tuning. Cable compensation aids portable devices in charging at optimum current and voltage under heavy
loads by changing the buck regulator output voltage linearly with load current to counteract the voltage drop due
to wire resistance in automotive cabling. The VBUS voltage measured at a connected portable device remains
approximately constant, regardless of load current, allowing the portable device's battery charger to work
optimally.
The USB specifications require current limiting of USB charging ports, but give system designers reasonable
flexibility to choose overcurrent protection levels based on system requirements. The TPS25830x-Q1 uses a
novel two-threshold current limit circuit allowing system designers to either program average current limit
protection of the buck regulator, or optionally, current limit using an external NMOS between the CSN/OUT and
BUS pins. The NFET implementation enables the TPS2583x-Q1 buck regulator to supply a 5-V output for other
loads during an overcurrent fault condition on the USB port.
The TPS25830-Q1 includes high bandwidth analog switches for DP and DM pass-through. The TPS25831-Q1
includes a thermistor input pin and thermal warning flag for user programmable thermal overload protection.
Integrated protection features include cycle-by-cycle current limit, hiccup short-circuit protection, undervoltage
lockout, VBUS overvoltage and overcurrent, CC overvoltage and overcurrent, data line (Dx) short to VBUS and
VBAT, and die overtemperature protection.
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS25830-Q1 TPS25831-Q1
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6 Device Comparison Table
PACKAGE
DCP AUTO
DP AND DM
SWITCHES
NTC INPUT
THERMAL
WARNING FLAG
TPS25830-Q1
VQFN (32)
No
Yes
No
No
TPS25831-Q1
VQFN (32)
Yes
No
Yes
Yes
PART NUMBER
7 Pin Configuration and Functions
TPS25830-Q1 RHB Package
32-Pin (VQFN)
Top View
SW
SW
PGND
PGND
PGND
28
27
26
25
PGND
25
29
PGND
26
SW
PGND
27
30
SW
28
SW
SW
29
31
SW
30
BOOT
SW
31
A1
32
BOOT
32
TPS25831-Q1 RHB Package
32-Pin (VQFN)
Top View
A4
A1
IN
1
24
FAULT
IN
1
24
FAULT
IN
2
23
LD_DET
IN
2
23
LD_DET
IN
3
22
POL
IN
3
22
POL
EN
4
21
VCC
EN
4
21
VCC
A4
Thermal Pad
Thermal Pad
19
CC2
DP_OUT
7
18
DP_IN
THERM_WARN
7
18
DP_IN
DM_OUT
8
17
DM_IN
NTC
8
17
DM_IN
9
AGND
BUS
CSP
CSN/OUT
ILIMIT
As of 11/14/2017
NOTES:
1) A1, A2, A3, and A4 are corner anchors for enhanced package stress
performance.
2) A1, A2, A3, and A4 are electrically connected to the thermal pad.
3) A1, A2, A3, and A4 PCB lands should be electrically isolated or
electrically connected to thermal pad and PGND.
IMON
A3
LS_GD
AGND
BUS
CSP
CSN/OUT
ILIMIT
IMON
LS_GD
RT/SYNC
As of 11/14/2017
A2
A3
RT/SYNC
9
A2
16
6
15
CTRL2
14
CC2
13
19
12
6
11
CTRL2
10
CC1
16
20
15
5
14
CTRL1
13
CC1
12
20
11
5
10
CTRL1
NOTES:
1) A1, A2, A3, and A4 are corner anchors for enhanced package stress
performance.
2) A1, A2, A3, and A4 are electrically connected to the thermal pad.
3) A1, A2, A3, and A4 PCB lands should be electrically isolated or
electrically connected to thermal pad and PGND.
Pin Functions
830Q1
NO.
831Q1
NO.
AGND
16
BOOT
NAME
TYPE
(1)
I/O
DESCRIPTION
16
G
–
32
32
P
BUS
15
15
A
I
CC1
20
20
A
I/O
Analog input/output. Connect to Type-C CC1 pin.
CC2
19
19
A
I/O
Analog input/output. Connect to Type-C CC2 pin.
CSN/OUT
13
13
A
I
Negative input of current sense amplifier, also buck output for internal voltage regulation
CSP
14
14
A
I
Positive input of current sense amplifier.
CTRL1
5
5
A
I
Logic-level control inputs for device/system configuration. (See Table 10)
CTRL2
6
6
A
I
Logic-level control inputs for device/system configuration. (See Table 10)
DM_IN
17
17
A
DM data line. Connect to USB connector.
Analog ground terminal. Ground reference for internal references and logic. All electrical
parameters are measured with respect to this pin. Connect to system ground on PCB.
Boot-strap capacitor connection for HS FET driver. Connect a high quality 100-nF
capacitor from this pin to the SW pin.
VBUS discharge input. Connect to VBUS on USB Connector.
DM_OUT
8
–
A
DM data line. Connect to USB host controller.
DP_IN
18
18
A
DP data line. Connect to USB connector.
(1)
4
A = Analog, P = Power, G = Ground.
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SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
Pin Functions (continued)
830Q1
NO.
831Q1
NO.
DP_OUT
7
–
A
DP data line. Connect to USB host controller.
EN/UVLO
4
4
A
Enable pin. Do not float. High = on, Low = off. Can be tied to VIN. Precision enable input
allows adjustable UVLO by external resistor divider.
FAULT
24
24
A
ILIMIT
12
12
A
External resistor used to set the current-limit threshold. (See Table 2)
IMON
11
11
A
External resistor used to set the max cable comp voltage at full load current.
1, 2,
3
1, 2,
3
P
I
Input Supply to regulator. Connect a high-quality bypass capacitor(s) directly to this pin and
PGND.
LD_DET
23
23
A
O
Active LOW open-drain output. Asserted when a Type-C UFP is identified on the CC lines.
LS_GD
10
10
A
NTC
–
8
PGND
25,
26,
27
25,
26,
27
POL
22
22
NAME
IN
TYPE
(1)
I/O
O
DESCRIPTION
Active LOW open-drain output. Asserted during fault conditions. (See Table 4)
External NMOS gate driver. For TPS25830-Q1, LS_GD pin must be pulled up through
2.2kΩ resistor under average current limit mode. (See Current Limit Setting using RILIMIT)
I
Input for negative temperature coefficient resistor divider. Use to monitor external PCB
temperature. (See Thermal Sensing with NTC (TPS25831-Q1))
G
–
Power ground terminal. Connect to system ground and AGND. Connect to bypass
capacitor with short wide traces.
A
O
Active LOW open-drain output. Signals which Type-C CC pin is connected to the CC line.
This gives cable orientation information needed to mux the super speed lines. Asserted
when the CC2 pin is connected to the CC line in the cable.
9
9
A
Resistor Timing or External Clock input. An internal amplifier holds this terminal at a fixed
voltage when using an external resistor to ground to set the switching frequency. If the
terminal is pulled above the PLL upper threshold, a mode change occurs and the terminal
becomes a synchronization input. The internal amplifier is disabled and the terminal is a
high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier
is re-enabled and the operating mode returns to resistor frequency programming.
28,
29,
30,
31
28,
29,
30,
31
P
Switching output of the regulator. Internally connected to source of the HS FET and drain
of the LS FET. Connect to power inductor.
THERM_WARN
–
7
A
VCC
21
21
P
RT/SYNC
SW
O
Active LOW open-drain output. Asserted when voltage at the NTC pin increases above the
thermal warning threshold.
Output of internal bias supply. Used as supply to internal control circuits. Connect a high
quality 2.2 µF capacitor from this pin to GND.
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Product Folder Links: TPS25830-Q1 TPS25831-Q1
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8 Specifications
8.1 Absolute Maximum Ratings
Voltages are with respect to GND (unless otherwise noted) (1)
PARAMETER
Input voltage
Output voltage
Voltage range
MIN
MAX
IN to PGND
–0.3
40
OUT to PGND
–0.3
20
EN to AGND
–0.3
VIN + 0.3
CSP to AGND
–0.3
20
CSN to AGND
–0.3
20
BUS to AGND
–0.3
18
RT/SYNC to AGND
–0.3
6
CTRL1 or CTRL2 to AGND
–0.3
6
AGND to PGND
–0.3
0.3
SW to PGND
–0.3
VIN + 0.3
SW to PGND (less than 10 ns transients)
–3.5
40
BOOT to SW
–0.3
6
VCC to AGND
–0.3
6
LS_GD
–0.3
18
CC1 or CC2 to AGND
–0.3
18
DP_IN, DM_IN to AGND
–0.3
18
DP_OUT, DM_OUT to AGND (TPS25830-Q1 only)
–0.3
6
FAULT, POL, LD_DET to AGND
–0.3
6
THERM_WARN, NTC to AGND (TPS25831-Q1 only)
–0.3
6
ILIMIT or IMON to AGND
–0.3
6
Pin positive source current,
IVCC
VCC Source Current
Pin positive source current,
ISRC
CC1, CC2
5
Pin positive sink current, ISNK CC1, CC2 (while applying VCONN)
I/O current
V
V
V
mA
Internally
Limited
A
1
A
FAULT, POL, LD_DET
Internally
Limited
THERM_WARN (TPS25831-Q1 only)
Internally
Limited
Pin positive sink current, ISNK
UNIT
DP_IN to DP_OUT, or DM_IN to DM_OUT in SDP, CDP
(TPS25830-Q1 only)
–100
100
DP_IN to DM_IN in DCP Auto Mode (TPS25831-Q1 only)
–35
35
A
mA
TJ
Junction temperature
-40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
6
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
8.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
(2)
(3)
(4)
Electrostatic discharge
Charged device model (CDM), per
AEC Q100-011
UNIT
±2000 (2)
Corner pins (1, 8, 9, 17, 25 and 32)
±750 (3)
Other pins
±750 (3)
V
(4)
IEC 61000-4-2 contact discharge
DP_IN, DM_IN, CC1 and CC2 pins
±8000
IEC 61000-4-2 air-gap discharge
DP_IN, DM_IN, CC1 and CC2 pins
±15000 (4)
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
The passing level per AEC-Q100 Classification H2.
The passing level per AEC-Q100 Classification C5
Surges per IEC61000-4-2, 1999 applied between DP_IN, DM_IN, CC1, CC2 and output ground of the TPS2583x-Q1 evaluation module.
Addition 0.22u cap is needed on CCx pins.
8.3 Recommended Operating Conditions
Voltages are with respect to GND (unless otherwise noted)
MIN
IN to PGND
VI
Input voltage
VPU
Pull up voltage
VO
Output voltage
IO
Output current
EN
0
VIN
VCC when driven from external regulator
0
5.5
DP_IN, DM_IN
0
3.6
DP_OUT, DM_OUT (TPS25830-Q1 only)
0
3.6
NTC (TPS25831-Q1 only)
0
VCC
CTRL1, CTRL2
0
VCC
RT/SYNC when driven by external clock
0
VCC
FAULT, LD_DET, POL
0
VCC
THERM_WARN (TPS25831-Q1 only)
0
VCC
CSN/OUT
0
6.5
Buck regulator output current
0
3.5
DP_IN to DP_OUT or DM_IN to DM_OUT
Continuous current in SDP, CDP
–30
30
DP_IN to DM_IN Continuous current in BC1.2 DCP
Mode
–15
15
Source current
ISNK
Sink current
II
Input current
Continuous current into the CSP pin
REXT
External resistnace
RIMON, RILIMIT
(1)
MAX
36
ISRC
TJ
NOM
4.5
UNIT
V
A
mA
CC1 or CC2 source current when supplying VCONN
250
FAULT, LD_DET, POL
10
THERM_WARN (TPS25831-Q1 only)
10
Operating junction temperature
200
µA
0
100
kΩ
–40
125 (1)
°C
Operating at junction temperatures greater than 125°C is possible, however lifetime will be degraded.
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8.4 Thermal Information
TPS2583x-Q1
THERMAL METRIC (1)
RHB (VQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
28.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
17.6
°C/W
RθJB
Junction-to-board thermal resistance
7.2
°C/W
ΨJT
Junction-to-top characterization parameter
0.2
°C/W
ΨJB
Junction-to-board characterization parameter
7.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS =
15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTATE (IN PIN)
VIN
Operating input voltage range
4.5
IQ
Operating quiescent current (non
switching)
VEN/UVLO = VIN, CTRL1 = CTRL2 =
VCC, VCSN = 8V, CC1 or CC2 = RD,
CC2 or CC1 = open
IQ-SB
Standby quiescent current
VEN/UVLO = VIN, CTRL1 = CTRL2 =
VCC, CC1 and CC2 = open
ISD
Shutdown quiescent current; measured
EN= 0
at IN pin.
700
10
36
V
990
µA
290
µA
16
µA
1.14
V
ENABLE and UVLO (EN/UVLO PIN)
VEN/UVLO_VCC_H
EN/UVLO input level required to turn
on internal LDO
VEN/UVLO rising threshold
VEN/UVLO_VCC_L
EN/UVLO input level required to turn
off internal LDO
VEN/UVLO falling threshold
0.3
VEN/UVLO_H
EN/UVLO input level required to turn
on state machine
VEN/UVLO rising threshold
1.140
VEN/UVLO_HYS
Hysteresis
VEN/UVLO falling threshold
90
mV
ILKG_EN/UVLO
Enable input leakage current
VEN/UVLO = 3.3 V
0.5
uA
2.2
V
V
1.200
1.260
V
INTERNAL LDO
VBOOT_UVLO
Bootstrap voltage UVLO threshold
VCC
Internal LDO output voltage appearing
on VCC pin
VCC_UVLO_R
Rising UVLO threshold
VCC_UVLO_HYS
Hysteresis
6 V ≤ VIN ≤ 36 V
4.75
3.4
5
5.25
3.6
3.8
600
V
V
mV
CURRENT LIMIT VOLTAGE (CSP - CSN/OUT PINS) TO ACTIVATE BUCK AVG CURRENT LIMITING
(VCSP –
VCSN/OUT)
Current limit voltage buck regulator
control loop
VCSN = 5 V, RSET = 300 Ω, RILIMIT = 13
kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤
125°C
43.5
46
48.5
mV
(VCSP –
VCSN/OUT)
Current limit voltage buck regulator
control loop
VCSN = 5 V, RSET = 300 Ω, RILIMIT = 13
kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤
150°C
42.5
46
49.5
mV
(VCSP –
VCSN/OUT)
Current limit voltage buck regulator
control loop
VCSN = 5 V, RSET = 300 Ω, RILIMIT =
26.1 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤
125°C
20
22.5
25
mV
8
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TPS25830-Q1, TPS25831-Q1
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SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
Electrical Characteristics (continued)
Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS =
15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
(VCSP –
VCSN/OUT)
TEST CONDITIONS
Current limit voltage buck regulator
control loop
VCSN = 5 V, RSET = 300 Ω, RILIMIT =
26.1 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤
150°C
MIN
TYP
MAX
UNIT
19
22.5
26
mV
CURRENT LIMIT VOLTAGE (CSP - CSN/OUT PINS) TO ACTIVATE EXTERNAL NFET CURRENT LIMITING
(VCSP –
VCSN/OUT)
VCSN = 5 V, RSET = 300 Ω, RILIMIT =
Current limit voltage NFET control loop 6.8 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤
125°C
40
43
46
mV
(VCSP –
VCSN/OUT)
VCSN = 5 V, RSET = 300 Ω, RILIMIT =
Current limit voltage NFET control loop 6.8 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤
150°C
38.5
43
47.5
mV
(VCSP –
VCSN/OUT)
VCSN = 5 V, RSET = 300 Ω, RILIMIT =
Current limit voltage NFET control loop 13.7 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤
125°C
18
21
24
mV
(VCSP –
VCSN/OUT)
VCSN = 5 V, RSET = 300 Ω, RILIMIT =
Current limit voltage NFET control loop 13.7 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤
150°C
17
21
25
mV
4.6
5.4
6.2
A
CURRENT LIMIT - BUCK REGULATOR PEAK CURRENT LIMIT
IL-SC-HS
High-side current limit
IL-SC-LS
Low-side current limit
IL-NEG-LS
Low-side negative current limit
3.5
4
4.5
A
–3.1
–2.1
–1.3
A
CABLE COMPENSATION VOLTAGE
VIMON
Cable compensation voltage
(VCSP – VCSN) = 46 mV, RSET = 300 Ω,
RILIMIT = 13 kΩ, RIMON = 13 kΩ
0.935
1
1.065
V
VIMON
Cable compensation voltage
(VCSP – VCSN) = 23 mV, RSET = 300 Ω,
RILIMIT = 13 kΩ, RIMON = 13 kΩ
0.435
0.5
0.565
V
VIMON
Cable compensation voltage (internal
clamp)
(VCSP –VCSN) = 46 mV, RSET = 300 Ω,
RILIMIT = 13 kΩ, RIMON = open
1.8
V
BUCK OUTPUT VOLTAGE (CSN/OUT PIN)
VCSN/OUT
Output voltage
CC1 or CC2 pulldown resistance = Rd,
RIMON = 0 Ω, RILIMIT = 0 Ω
5.05
VCSN/OUT
Output voltage accuracy
CC1 or CC2 pulldown resistance = Rd,
RIMON = 0 Ω, RILIMIT = 0 Ω
–1
VCSN/OUT_OV
Overvoltage level on CSN/OUT pin
which buck regulator stops switching
VCSN/OUT rising
7.1
VCSN/OUT_OV_HYS
Hysteresis
VHC
CSN / OUT pin voltage required to
trigger short circuit hiccup mode
VDROP
Dropout voltage ( VIN-VOUT )
5.10
7.5
5.15
V
1
%
7.9
V
500
mV
2
VIN = VOUT + VDROP, VOUT = 5.1V,
IOUT = 3A
V
150
mV
BUCK REGULATOR INTERNAL RESISTANCE
RDS-ON-HS
High-side MOSFET ON-resistance
Load = 3 A, TJ = 25°C
40
45
mΩ
RDS-ON-HS
High-side MOSFET ON-resistance
Load = 3 A, -40°C ≤ TJ ≤ 125°C
40
68
mΩ
RDS-ON-HS
High-side MOSFET ON-resistance
Load = 3 A, -40°C ≤ TJ ≤ 150°C
40
75
mΩ
RDS-ON-LS
Low-side MOSFET ON-resistance
Load = 3 A, TJ = 25C
35
41
mΩ
RDS-ON-LS
Low-side MOSFET ON-resistance
Load = 3 A, -40°C ≤ TJ ≤ 125°C
35
60
mΩ
RDS-ON-LS
Low-side MOSFET ON-resistance
Load = 3 A, -40°C ≤ TJ ≤ 150°C
35
68
mΩ
9.5
11
12.5
V
2
3
4
µA
NFET GATE DRIVE (LS_GD PIN)
VLS_GD
NFET gate drive output voltage
VCSN/OUT = 5.1 V, CG = 1000 pF (see
Figure 37)
ILS_DR_SRC
NFET gate drive output source current
VCSN/OUT = 5.1 V, CG = 1000 pF
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Electrical Characteristics (continued)
Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS =
15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
TEST CONDITIONS
ILS_DR_SNK
NFET gate drive output sink current
VCSN/OUT = 5.1 V, CG = 1000 pF
VLS_GD_UVLO_R
VCSN/OUT rising threshold for LS_GD
operation
VCSN/OUT rising
VLS_GD_UVLO_HYS
Hysteresis
MIN
TYP
MAX
20
35
50
µA
2.85
3
3.15
V
80
UNIT
mV
BUS DISCHARGE (BUS PIN)
RBUS_DCHG
BUS discharge resistance
VBUS = 4 V
250
VBUS_NO_DCHG
Falling threshold for VBUS not
discharged
RBUS_DCHG_BLEED
BUS bleed resistance
VBUS = 4 V, No sink termination on CC
lines, Time > tW_BUS_DCHG
100
VBUS_OV
Rising threshold for BUS pin
overvoltage protection
VBUS rising
6.6
VBUS_OV_HYS
Hysteresis
RBUS_DCHG_18V
Discharge resistance for BUS
RBUS_DCHG_8V
Discharge resistance for BUS
320
550
Ω
0.8
V
130
200
kΩ
7
7.3
V
180
mV
VBUS = 18V, measure leakage current
29
kΩ
VBUS = 8V, measure leakage current
35
kΩ
CC1 AND CC2 - VCONN POWER SWITCH (CC1 AND CC2 PINS)
RDS-ON
On-state resistance
ICCn = 250 mA, TJ = 25°C
500
540
mΩ
RDS-ON
On-state resistance
ICCn = 250 mA, –40°C ≤ TJ ≤ 125°C,
500
830
mΩ
RDS-ON
On-state resistance
ICCn = 250 mA, –40°C ≤ TJ ≤ 150°C,
500
920
mΩ
IOS_CCn
VCONN short circuit current limit
Short circuit current limit
350
430
550
mA
RVCONN_DCHG
Discharge resistance
CC pin that was providing VCONN
before detach: VCCX = 4V
650
850
1100
Ω
VTH
Falling threshold for discharged
CC pin that was providing VCONN
before detach
570
600
630
mV
VTH
Discharged threshold hysteresis
VCCx_OV
Rising threshold for CCn pin
overvoltage protection
VCCx_OV_HYS
Hysteresis
100
CC pin voltage VCCn rising
5.8
RCCn_DCHG_18V
Discharge resistance for CCn
CC pin voltage VCCn = 18V, measure
leakage current
RCCn_DCHG_8V
Discharge resistance for CCn
CC pin voltage VCCn = 8V, measure
leakage current
6.1
mV
6.4
V
150
mV
40
kΩ
86
kΩ
CC1/CC2 CONNECT MANAGEMENT: DANGLING ELECTRONICALLY MARKED CABLE MODE
ISRC_CCn
Sourcing current on the passthrough
CC line
CC pin voltage 0 V ≤ VCCn ≤ 1.5 V
64
80
96
µA
ISRC_CCn
Sourcing current on the Ra CC line
CC pin voltage 0 V ≤ VCCn ≤ 1.5 V
64
80
96
µA
CC1/CC2 CONNECT MANAGEMENT: UFP MODE (TPS25830-Q1)
ISRC_CCn
Sourcing current
VCTRL1 = VCC and VCTRL2 = VCC, CC
pin voltage: 0 V ≤ VCCn ≤ 1.5 V (with
CDP mode)
308
330
354
µA
ISRC_CCn
Sourcing current
VCTRL1 = VCC and VCTRL2 = GND, CC
pin voltage: 0 V ≤ VCCn ≤ 1.5 V (with
SDP mode)
168
180
192
µA
308
330
354
µA
CC1/CC2 CONNECT MANAGEMENT: UFP MODE (TPS25831-Q1)
ISRC_CCn
10
Sourcing current
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VCTRL1 = VCC and VCTRL2 = VCC, CC
pin voltage: 0 V ≤ VCCn ≤ 1.5 V (with
CDP mode)
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS25830-Q1 TPS25831-Q1
TPS25830-Q1, TPS25831-Q1
www.ti.com
SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
Electrical Characteristics (continued)
Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS =
15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
168
180
192
µA
308
330
354
µA
ISRC_CCn
Sourcing current
VCTRL1 = VCC and VCTRL2 = GND, CC
pin voltage: 0 V ≤ VCCn ≤ 1.5 V (with
SDP mode)
ISRC_CCn
Sourcing current
VCTRL1 = GND and VCTRL2 = VCC, CC
pin voltage: 0 V ≤ VCCn ≤ 1.5 V (with
DCP auto mode)
IREV
Reverse leakage current
CCx is the CC pin under test, CCy is
the other CC pin. CC pin voltage VCCx
= 5.5 V, CCy = 0V or floating, VEN = 0
V, IREV is current into CCx pin
0
5
µA
IREV
Reverse leakage current
CCx is the CC pin under test, CCy is
the other CC pin. CC pin voltage VCCx
= 5.5 V, CCy = 0, VEN = VIN, IREV is
current into CCx pin under test
6
10
µA
250
mV
FAULT, LD_DET, POL
VOL
FAULT Output low voltage
ISNK_PIN = 0.5 mA
IOFF
FAULT Off-state leakage
VPIN = 5.5 V
VOL
LD_DET, POL Output low voltage
ISNK_PIN = 0.5 mA
IOFF
LD_DET, POL Off-state leakage
VPIN = 5.5 V
1
µA
250
mV
1
µA
250
mV
1
µA
2
V
THERM_WARN (TPS25831-Q1)
VOL
THERM_WARN Output low voltage
ISNK_PIN = 0.5 mA
IOFF
THERM_WARN Off-state leakage
VPIN = 5.5 V
CTRL1, CTRL2 - LOGIC INPUTS
VIH
Rising threshold voltage
VIL
Falling threshold voltage
VHYS
Hysteresis
IIN
Input current
1.48
0.85
1.30
V
180
mV
–1
1
µA
4.15
V
DP_IN AND DM_IN OVERVOLTAGE PROTECTION
VDx_IN_OV
Rising threshold for Dx_IN overvoltage
protection
DP_IN or DM_IN rising
Hysteresis
3.7
3.9
100
mV
RDx_IN_DCHG_18V
Discharge resistance for Dx_IN
VDx_IN = 18V, measure leakage
current
94
kΩ
RDx_IN_DCHG_5V
Discharge resistance for Dx_IN
VDx_IN = 5V, measure leakage
current
416
kΩ
HIGH-BANDWIDTH ANALOG SWITCH (TPS25830-Q1)
RDS_ON
DP and DM switch on-resistance
VDP_OUT = VDM_OUT = 0 V, IDP_IN =
IDM_IN = 30 mA
3.4
6.3
Ω
RDS_ON
DP and DM switch on-resistance
VDP_OUT = VDM_OUT = 2.4 V, IDP_IN =
IDM_IN = –15 mA
4.3
7.7
Ω
|ΔRDS_ON|
Switch resistance mismatch between
DP and DM channels
VDP_OUT = VDM_OUT = 0 V, IDP_IN =
IDM_IN = 30 mA
0.05
0.15
Ω
|ΔRDS_ON|
Switch resistance mismatch between
DP and DM channels
VDP_OUT = VDM_OUT = 2.4 V, IDP_IN =
IDM_IN = –15 mA
0.05
0.15
Ω
CIO_OFF
DP/DM switch off-state capacitance
VEN = 0 V, VDP_IN = VDM_IN = 0.3 V,
Vac = 0.03 VPP , f = 1 MHz
6.7
pF
CIO_ON
DP/DM switch on-state capacitance
VDP_IN = VDM_IN = 0.3 V, Vac = 0.03
VPP, f = 1 MHz
10
pF
OIRR
Off-state isolation
VEN = 0 V, f = 250 MHz
9
dB
XTALK
On-state cross-channel isolation
f = 250 MHz
29
dB
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Electrical Characteristics (continued)
Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS =
15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
Ilkg(OFF)
Off-state leakage current, DP_OUT
and DM_OUT
VEN = 0 V, VDP_IN = V DM_IN = 3.6 V,
VDP_OUT = VDM_OUT = 0 V,
measure IDP_OUT and IDM_OUT
BW
Bandwidth (–3 dB)
RL = 50 Ω
TYP
MAX
0.1
1.5
800
UNIT
µA
MHz
CHARGING DOWNSTREAM PORT (CDP) DETECT
VDM_SRC
DM_IN CDP output voltage
VDAT_REF
DP_IN rising lower window threshold
for VDM_SRC activation
VDAT_REF
Hysteresis
VLGC_SRC
DP_IN rising upper window threshold
for VDM_SRC deactivation
VLGC_SRC_HYS
Hysteresis
IDP_SINK
DP_IN sink current
VDP_IN = 0.6 V, –250 µA < IDM_IN < 0
µA
0.5
0.6
0.7
V
0.36
0.38
0.4
V
50
0.8
0.84
mV
0.88
100
VDP_IN = 0.6 V
40
V
mV
70
100
µA
135
200
Ω
V
BC 1.2 DOWNSTREAM CHARGING PORT (TPS25831-Q1)
RDPM_SHORT
DP_IN and DM_IN shorting resistance
DIVIDER3 MODE (TPS25831-Q1)
VDP_DIV3
DP_IN output voltage
2.57
2.7
2.84
VDM_DIV3
DM_IN output voltage
2.57
2.7
2.84
V
RDP_DIV3
DP_IN output impedance
IDP_IN = –5 µA
24
30
36
kΩ
RDM_DIV3
DM_IN output impedance
IDM_IN = –5 µA
24
30
36
kΩ
1.12
1.2
1.26
V
1.2-V MODE (TPS25831-Q1)
VDP_1.2V
DP_IN output voltage
VDM_1.2V
DM_IN output voltage
1.12
1.2
1.26
V
RDP_1.2V
DP_IN output impedance
IDP_IN = –5 µA
84
100
126
kΩ
RDM_1.2V
DM_IN output impedance
IDM_IN = –5 µA
84
100
126
kΩ
3.5
RT/SYNC THRESHOLD (RT/SYNC PIN)
VIH_RT/SYNC
RT/SYNC high threshold for external
clock synchronization
Amplitude of SYNC clock AC signal
(measured at SYNC pin)
VIL_RT/SYNC
RT/SYNC low threshold for external
clock synchronization
Amplitude of SYNC clock AC signal
(measured at SYNC pin)
V
0.8
V
VCC ×
0.525
V
NTC TEMPERATURE SENSING (TPS25831-Q1)
VWARN_HIGH
Temperature warning threshold rising
VWARN_HYS
Hysteresis
VSD_HIGH
Temperature shutdown threshold rising
VSD_HYS
Hysteresis
VCC ×
0.475
VCC ×
0.5
VCC x
0.1
VCC ×
0.618
VCC ×
0.65
V
VCC ×
0.683
V
VCC x
0.1
V
Shutdown threshold
160
°C
Recovery threshold
140
°C
THERMAL SHUTDOWN
TSD
12
Thermal shutdown
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SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
8.6 Timing Requirements
Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS =
15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
MIN
NOM
MAX
UNIT
2300
kHz
SYNC (RT/SYNC PIN) WITH EXTERNAL CLOCK
fSYNC
Switching frequency using external clock on
RT/SYNC pin
TSYNC_MIN
Minimum SYNC input pulse width
TLOCK_IN
PLL lock time
300
fSYNC = 400kHz, VRT/SYNC > VIH_RT/SYNC,
VRT/SYNC < VIL_RT/SYNC
100
ns
100
µs
8.7 Switching Characteristics
Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS =
15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3
5
7
UNIT
SOFT START
TSS
The time of internal reference to
increase from 0 V to 1.0 V
Internal soft-start time
ms
HICCUP MODE
NOC
Number of cycles that LS current limit
is tripped to enter Hiccup mode
128
Cycles
TOC
Hiccup retry delay time
118
ms
TON_MIN
Minimum turnon-time
105
ns
TON_MAX
Maximum turnon-time, HS timeout in
dropout
7.5
µs
TOFF_MIN
Minimum turnoff time
80
ns
Dmax
Maximum switch duty cycle
98
%
SW (SW PIN)
TIMING RESISTOR AND INTERNAL CLOCK
fSW_RANGE
fSW
FSSS
Switching frequency range using RT
mode
300
2300
kHz
Switching frequency
RT = 49.9 kΩ
360
400
440
kHz
Switching frequency
RT = 8.87 kΩ
1953
2100
2247
kHz
Frequency span of spread spectrum
operation
±6
%
BUS DISCHARGE
tDEGA_OUT_DCHG
Discharge asserting deglitch
tW_BUS_DCHG
VBUS discharge time after sink
termination removed from CC lines
VBUS = 1 V, time ISNK_OUT > 1 mA after
sink termination removed from CC
lines
5.0
12.5
23.4
ms
150
266
400
ms
0.78
1.1
1.95
0.18
0.32
0.37
4.1
6.2
8.5
0.5
1
1.6
CC1/CC2 - VCONN POWER SWITCH 5.1 kΩ on one CC pin and 1 kΩ on the other
tr
Output voltage rise time
tf
Output voltage fall time
ton
Output voltage turnon-time
toff
Output voltage turnoff time
CL = 1 µF, RL = 100 Ω (measured from
10% to 90% of final value)
CL = 1 µF, RL = 100 Ω
ms
ms
CC1/CC2 VCONN POWER SWITCH: CURRENT LIMIT
tIOS
Short circuit response time
15
µs
CC1/CC2 - CONNECT MANAGEMENT - ATTACH AND DETACH DEGLITCH
tDEGA_CC_ATT
Attach asserting deglitch
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1.1
2.08
3.29
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ms
13
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Switching Characteristics (continued)
Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS =
15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
tDEGD_CC_DET
TEST CONDITIONS
Detach asserting deglitch for exiting
UFP state
MIN
TYP
MAX
UNIT
6.98
12.7
19.4
ms
CC1/CC2 - CONNECT MANAGEMENT - ATTACHED MODE 5.1 kΩ or 1 kΩ termination on at least one CC pin
tDEGA_CC_SHORT
Detach, Rd and Ra asserting deglitch
78
195
366
µs
tDEGA_CC_LONG
Long deglitch
87
150
217
ms
37
66
99
ms
CC1/CC2 - CONNECT MANAGEMENT - VCONN DISCHARGED MODE
tW_CC_DCHG
Discharge wait time
NFET DRIVER
tr
VLS_DR rise time
VOUT = 5.1V, NFET = CSD87502Q2,
time from LS_GD 10% to 90%
1000
µs
tf
VLS_DR fall time
VOUT = 5.1V, NFET = CSD87502Q2,
time from LS_GD time 90% to 10%
100
µs
CURRENT LIMIT - EXTERNAL NFET CONNECTED BETWEEN CSN/OUT AND BUS, LS_GD CONNECTED TO FET GATE
tOC_HIC_ON
ON-time during hiccup mode
tOC_HIC_OFF
OFF-time during hiccup mode
2
ms
263
ms
FAULT DUE TO VBUS OC, VBUS OV, DP OV, DM OV, CC OV, CC OC
tDEGLA
Asserting deglitch time
5.5
8.2
11.5
ms
tDEGLD
De-asserting deglitch time
5.5
8.2
11.5
ms
tDEGLA
Asserting deglitch time
88
150
220
ms
tDEGLD
De-asserting deglitch time
7.0
12.7
19.4
ms
LD_DET, POL
THERM_WARN (TPS25831-Q1)
tDEGLA
Asserting deglitch time
0
ms
tDEGLD
De-asserting deglitch time
0
ms
HIGH-BANDWIDTH ANALOG SWITCH (TPS25830-Q1)
tpd
Analog switch propagation delay
0.14
ns
tSK
Analog switch skew between opposite
transitions of the same port (tPHL
– tPLH)
0.02
ns
tOV_Dn
DP_IN and DM_IN overvoltage
protection response time
2
µs
14
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SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
8.8 Typical Characteristics
717
230
714
225
Standby Queiscent Current (uA)
Non-switching Quiescent Current (uA)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF, COUT_CSN
= 0.1 µF, CBUS = 1 µF, TA = 25 °C.
711
708
705
702
-40C
25C
150C
699
696
220
215
210
205
-40C
25C
125C
150C
200
195
0
4
8
12
VCSN = 8 V
16
20
24
Input Voltage (V)
28
32
36
40
0
4
8
CC1 = Rd
CC1 = OPEN
28
1.2
24
20
16
12
-40C
25C
125C
150C
8
8
12
16
20
24
Input Voltage (V)
28
32
36
28
32
36
40
D002
CC2 = OPEN
UP
DN
1.175
1.15
1.125
1.1
1.075
4
4
16
20
24
Input Voltage (V)
Figure 2. Standby Quiescent Current
1.225
EN Threshold Votlage (V)
Shutdown Queiscent Current (uA)
Figure 1. Non-Switching Quiescent Current
32
0
12
D001
1.05
-50
40
-25
0
25
50
75
Temperature (C)
D003
100
125
150
D004
EN = 0V
Figure 3. Shutdown Quiescent Current
Figure 4. Precision Enable Threshold
3.9
5.1
UP
DN
3.6
5.04
3.45
3.3
5.01
4.98
3.15
4.95
3
4.92
2.85
-60
-40C
25C
125C
150C
5.07
Vcc Voltage (V)
VIN UVLO Voltage (V)
3.75
4.89
-30
0
30
60
90
Temperature (C)
120
Figure 5. VIN UVLO Threshold
150
180
0
4
8
D005
12
16
20
24
Input Voltage (V)
28
32
36
40
D005
Figure 6. VCC vs Input Voltage
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Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF, COUT_CSN
= 0.1 µF, CBUS = 1 µF, TA = 25 °C.
6.2
5.16
VCSN/OUT Voltage (V)
5.14
High-side MOS Current Limit (A)
Vin = 6V
Vin = 13.5V
Vin = 36V
5.12
5.1
5.08
5.06
5.04
-50
-40C
25C
150C
6
5.8
5.6
5.4
5.2
5
4.8
-25
0
25
50
75
Temperature (C)
100
125
150
0
4
8
12
D006
16
20
24
Input Voltage (V)
28
32
36
40
D006
RIMON = 0Ω
Figure 8. High-side Current Limit vs Input Voltage
60
72
55
64
50
On Resistance (m?)
On Resistance (m?)
Figure 7. VCSN/OUT Voltage vs Junction Temperature
80
56
48
40
Vin = 6V
Vin = 13.5V
Vin = 36V
32
24
-50
-25
0
25
50
75
Temperature (C)
100
125
35
Vin = 6V
Vin = 13.5V
Vin = 36V
25
-50
150
-25
0
D008
420
2400
414
2100
408
402
396
390
384
25
50
75
Temperature (C)
100
125
150
D009
Figure 10. Low-side MOSFET on Resistance vs Junction
Temperature
Switching Frequency (kHz)
Switching Frequency (kHz)
40
30
Figure 9. High-side MOSFET on Resistance vs Junction
Temperature
1A
2A
3A
1800
1500
1200
900
600
378
-50
300
-25
0
25
50
75
Temperature (C)
100
125
150
5
10
15
20
25
Input voltage (V)
30
35
40
D011
RT = 8.87kΩ
Figure 11. Switching Frequency vs Junction Temperature
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0
D010
RT = 49.9kΩ
16
45
Figure 12. Switching Frequency vs VIN Voltage
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SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF, COUT_CSN
= 0.1 µF, CBUS = 1 µF, TA = 25 °C.
4.2
4.2
Rlimit = 13k:
Rlimit = 26.1k:
Rlimit = 6.8k:
Rlimit = 13.7k:
3.6
Ext FET Current Limit (A)
Buck Avg Current limit (A)
3.6
3
2.4
1.8
1.2
3
2.4
1.8
1.2
0.6
0.6
0
-50
-25
0
RSNS = 15mΩ
25
50
75
Temperature (C)
100
125
0
-50
150
RSET = 300Ω
0
25
50
75
Temperature (C)
RSNS = 15mΩ
Figure 13. Buck Average Current Limit vs Junction
Temperature
125
150
D013
RSET = 300Ω
13
Vin = 6V
Vin = 13.5V
Vin = 36V
Vin = 6V
Vin = 13.5V
Vin = 36V
12.5
LS_GD Gate Voltage (V)
4.4
4
3.6
3.2
2.8
12
11.5
11
10.5
2.4
10
2
-50
-25
0
25
50
75
Temperature (C)
100
125
9.5
-50
150
-25
0
25
50
75
Temperature (C)
D013
VCSN/OUT = 5.1V
Figure 15. LS_GD Gate Source Current vs Junction
Temperature
100
125
150
D013
RIMON = 0kΩ
Figure 16. LS_GD Gate Voltage vs Junction Temperature
1
1.35
Load Current = 3 A
Load Current = 1.5 A
0.9
Cable Comp Voltage (V)
1.2
Cable Comp Voltage (V)
100
Figure 14. External FET Current Limit vs Junction
Temperature
4.8
LS_GD Gate Source Current (uA)
-25
D012
1.05
0.9
0.75
0.6
0.45
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.3
-50
0
-25
RSNS = 15mΩ
0
25
50
75
Temperature (C)
100
RSET = 300Ω
125
150
D014
RIMON = 13kΩ
Figure 17. Cable Compensation Voltage vs Junction
Temperature
0
0.3
0.6
0.9
RSNS = 15mΩ
1.2 1.5 1.8
Load Current (A)
RSET = 300Ω
2.1
2.4
2.7
3
D014
RIMON = 13kΩ
Figure 18. Cable Compensation Voltage vs Load Current
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Typical Characteristics (continued)
450
7.5
420
7.35
VBUS OVP Threshold (V)
Vbus Discharge Resistance (ohm)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF, COUT_CSN
= 0.1 µF, CBUS = 1 µF, TA = 25 °C.
390
360
330
300
270
7.2
7.05
6.9
6.75
6.6
240
-50
-25
0
25
50
75
Temperature (C)
100
125
6.45
-50
150
4.3
4.3
4.2
4.2
4.1
4
3.9
3.8
3.7
25
50
75
Temperature (C)
100
125
150
D016
4.1
4
3.9
3.8
3.7
3.6
-50
-25
0
25
50
75
Temperature (C)
100
125
3.6
-50
150
800
600
Vconn Switch Limit Current (mA)
700
720
640
560
480
400
-25
0
25
50
75
Temperature (C)
100
125
150
25
50
75
Temperature (C)
100
125
150
D018
500
400
300
200
100
0
-50
-25
0
D019
VCONN = 5V
25
50
75
Temperature (C)
100
125
150
D020
VCONN = 5V
Figure 23. VCONN Current Limiting Switch On Resistance vs
Junction Temperature
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Figure 22. DM_IN Overvoltage Protection Threshold vs
Junction Temperature
880
320
-50
-25
D017
Figure 21. DP_IN Overvoltage Protection Threshold vs
Junction Temperature
Vconn Switch On Resistance (mohm)
0
Figure 20. VBUS Overvoltage Protection Threshold vs
Junction Temperature
DM_IN OVP Threshold (V)
DP_IN OVP Threshold (V)
Figure 19. VBUS Discharge Resistance vs Junction
Temperature
18
-25
D015
Figure 24. VCONN Switch Current Limit vs Junction
Temperature
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Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF, COUT_CSN
= 0.1 µF, CBUS = 1 µF, TA = 25 °C.
400
6.8
Sourcing Current (uA)
360
CC1 OVP Threshold Voltage (V)
UFP 1.5A
UFP 3A
320
280
240
200
160
120
-50
-25
0
25
50
75
Temperature (C)
100
125
6.2
6
5.8
5.6
-25
0
25
50
75
Temperature (C)
D021
100
125
150
D022
Figure 26. CC1 Overvoltage Protection Threshold vs
Junction Temperature
0.705
NTC Temp Shutdown Threshold (%)
0.54
NTC Temp Warning Threshold (%)
6.4
5.4
-50
150
Figure 25. CC Sourcing Current vs Junction Temperature
0.53
0.52
0.51
0.5
0.49
0.48
0.47
-50
6.6
-25
0
25
50
75
Temperature (C)
100
125
150
0.69
0.675
0.66
0.645
0.63
0.615
0.6
-50
-25
0
D025
Figure 27. NTC Temperature Warning Threshold (TPS25831Q1)
Measured Source with 10-cm cable
25
50
75
Temperature (C)
100
125
150
D025
Figure 28. NTC Temperature Shutdown Threshold
(TPS25831-Q1)
Measured on TPS25830-Q1 EVM with 10-cm cable
Figure 29. Bypassing the TPS25830-Q1 Data Switch
Figure 30. Through the TPS25830-Q1 Data Switch
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Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF, COUT_CSN
= 0.1 µF, CBUS = 1 µF, TA = 25 °C.
Figure 31. Data Transmission Characteristics vs Frequency
(TPS25830-Q1)
Figure 32. Off-State Data-Switch Isolation vs Frequency
(TPS25830-Q1)
Figure 33. On-State Cross-Channel Isolation vs Frequency (TPS25830-Q1)
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9 Parameter Measurement Information
OUT
R(L)
C(L)
V(OUT)
tr
90%
tf
10%
Figure 34. VCONN Switch Rise-Fall Test Load Figure
Figure 35. VCONN Switch Rise-Fall Timing
IOS
90%
tr
tf
VLS_GD
I(OUT)
10%
t(IO S)
Figure 36. Short-Circuit Parameters
Figure 37. NFET Gate Drive Rise and Fall Time
0.5m AWG28
0.5m AWG28
10cm AWG18
0.5m AWG28
ICAB LE
0.5m AWG28
0.5m AWG28
Manually Hot-short
PSIL040
18V
27 mF
35V
Voltage
Test Point
TPS2583x-Q1
DC Power Supply
OUT
DP_IN
DM_IN
CC1
CC2
GND
GND
Figure 38. Short-to-Battery System Test Setup
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10 Detailed Description
10.1 Overview
The TPS25830-Q1 and TPS25831-Q1 are full-featured solutions for implementing a compact USB charging port
with support for both Type-C and BC1.2 standards. Both devices contain an efficient 36-V buck regulator power
source capable of providing up to 3.5 A of output current at 5.10 V (nominal). System designers can optimize
efficiency or solution size through careful selection of switching frequency over the range of 300 to 2200 kHz with
sufficient margin to operate above or below the AM radio frequency band. In devices, the buck regulator operates
in forced PWM mode ensuring fixed switching frequency regardless of load current. Spread-spectrum frequency
dithering reduces harmonic peaks of the switching frequency potentially simplifying EMI filter design and easing
compliance.
Current sensing with a precision high-side current sense amplifier enables an accurate, user programmable
overcurrent limit setting; and programmable linear cable compensation to overcome IR losses when powering
remote USB ports.
The TPS25830-Q1 integrates high band-width (800 MHz) USB switches and includes short to VBAT and short to
VBUS protection as well as IEC61000-4-2 electrostatic discharge clamps to protect the host from potentially
damaging overvoltage conditions. The CTRL1 and CTRL2 pins set the operating mode for the TPS25830-Q1
implementing Type-C, CDP and SDP USB port configurations.
The TPS25831-Q1 includes a NTC input and THERM_WARN flag for user programmable thermal protection
using a negative temperature coefficient resistor. The CTRL1 and CTRL2 pins set the operating mode for the
TPS25831-Q1 implementing Type-C, DCP, CDP and SDP USB ports.
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10.2 Functional Block Diagram
R SNS
R SET
BOOT
(28, 29, 30, 31)
(14)
CSN /OUT
(13)
(11)
(1,2,3)
(21)
INT. REG.
BIAS
LS C urren t
Sen se
HS C urren t
Sen se
1V
+
VCC
(25, 26, 27)
±
IN
CSP
PGND
SW
(32)
IMON
Outpu t Vol ta ge R egu la ti on,
Ca bl e Comp en sation a nd
Cu rren t Li mit
R IMON
(12)
Dri ver
ILIMIT
R ILIMIT
RT/ SYNC
(9)
OSC&PLL
OV
Co ntrol L ogi c
PWM
Co mpa rator
Slo pe C omp
+
+
±
EN/ UVL O
(4)
Ena bl e Log ic
CTRL1
(5)
CTRL 2
(6)
Co mpe nsatio n
Ne tw ork
Shu tdow n
Ch arg e Pump
an d Gate Driv ers
AGND
Optional
Softstart
VRE F
(10)
LS_GD
(15)
BUS
(16)
/LD_DET
BUS C ontrol
(23)
Co ntrol a nd
Faul t L ogi c
/ POL
/ FAUL T
(22)
Faul t
con di ti ons
/THER M_WARN
VCC
CC a nd
VCON N
Co ntrol
(20)
CC1
(19)
CC2
(24)
CD P, DC P,
Di vid er 3, 1.2V
/ THER M_ WARN
(TPS25 83 1)
(7)
DP_ OUT
( TPS25 83 0)
(7)
(18)
DP_IN
DM_ OUT
( TPS25 83 0)
(8)
(17)
DM_IN
NTC
( TPS25 83 1)
(8)
VCC
Ther mal
Man ag emen t
NOTE:
x TPS25830: includes DP and DM HS USB Switches
x TPS25831: includes NTC inpu t, / THERM_ WARN flag
THER M_WARN
THER M_WARN
10.3 Feature Description
10.3.1 Buck Regulator
The following operating description of the TPS25830-Q1, TPS25831-Q1 will refer to the Functional Block
Diagram and to the waveforms in Figure 39. TPS2583x-Q1 is a step-down synchronous buck regulator with
integrated high-side (HS) and low-side (LS) switches (synchronous rectifier). The TPS2583x-Q1 supplies a
regulated output voltage by turning on the HS and LS NMOS switches with controlled duty cycle. During highside switch ON time, the SW pin voltage swings up to approximately VIN, and the inductor current iL increase with
linear slope (VIN – VOUT) / L. When the HS switch is turned off by the control logic, the LS switch is turned on
after an anti-shoot-through dead time. Inductor current discharges through the LS switch with a slope of –VOUT /
L. The control parameter of a buck converter is defined as Duty Cycle D = tON / TSW, where tON is the high-side
switch ON time and TSW is the switching period. The regulator control loop maintains a constant output voltage
by adjusting the duty cycle D. In an ideal buck converter, where losses are ignored, D is proportional to the
output voltage and inversely proportional to the input voltage: D = VOUT / VIN.
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Feature Description (continued)
VSW
SW Voltage
D = tON/ TSW
VIN
tON
tOFF
t
0
-VD
Inductor Current
iL
TSW
ILPK
IOUT
'iL
t
0
Figure 39. SW Node and Inductor Current Waveforms in
Continuous Conduction Mode (CCM)
The TPS2583x-Q1 employs fixed frequency peak current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current threshold to control the
ON time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer
external components, makes it easy to design, and provides stable operation with a reasonable combination of
output capacitors. TPS2583x-Q1 operates in FPWM mode for low output voltage ripple, tight output voltage
regulation, and constant switching frequency.
10.3.2 Enable/UVLO and Start-up
The voltage on the EN/UVLO pin controls the ON or OFF operation of TPS2583x-Q1. An EN/UVLO pin voltage
higher than VEN/UVLO-H is required to start the internal regulator and begin monitoring the CCn lines for a valid
Type-C connection. The internal USB monitoring circuitry is on when VIN is within the operation range and the
EN/UVLO threshold is cleared; however, the buck regulator does not begin operation until a valid USB Type-C
detection has been made. This feature ensures the "cold socket" (0 V) USB Type-C VBUS requirement is met.
The EN/UVLO pin is an input and can not be left open or floating. The simplest way to enable the operation of
the TPS2583x-Q1 is to connect the EN to VIN. This allows self-start-up of the TPS2583x-Q1 when VIN is within
the operation range.
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Feature Description (continued)
EN
VEN/UVLO-H
VEN/UVLO-H ± VEN/UVLO-HYS
VEN-VCC-H
VEN-VCC-L
VCC
5V
0
VCSN/OUT
VCSN/OUT
0
Figure 40. Precision Enable Behavior
Many applications will benefit from the employment of an enable divider RENT and RENB (Figure 41) to establish a
precision system UVLO level for the TPS2583x. The system UVLO can be used for sequencing, ensuring reliable
operation, or supply protection, such as a battery discharge level. To ensure the USB port VBUS is within the 5-V
operating range as required for USB compliance (refer to USB.org for the latest USB specifications and
requirements), it is suggested that the RENT and RENB resistors be chosen so that the TPS2583x-Q1 enables
when VIN is approximately 6 V. Considering the drop out voltage of the buck regulator and IR loses in the
system, 6 V provides adequate margin to maintain VBUS within USB specifications. If system requirements such
as a warm crank (start) automotive scenario require operation with VIN < 6 V, the values of RENT and RENB can be
calculated assuming a lower VIN. An external logic signal can also be used to drive EN/UVLO input when a
microcontroller is present and it is desirable to enable or disable the USB port remotely for other reasons.
IN
RENT
EN
RENB
Figure 41. System UVLO by Enable Divider
UVLO configuration using external resistors is governed by the following equations:
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Feature Description (continued)
(1)
(2)
Example:
VIN(ON) = 6 V (user choice)
RENB = 5 kΩ (user choice)
RENT = [(VIN(ON) / VEN/UVLO_H) - 1] × RENB= 19.6 kΩ. Choose standard 20 kΩ.
Therefore VIN(OFF) = 6 V × [1 - (0.09 V / 1.2 V)] = 5.55 V
A typical start-up waveform is shown in Figure 42, indicating typical timings when Rd connected to CC line. The
rise time of DCDC VBUS voltage is about 5 ms.
EN,
5V/Div
VIN
5V/Div
VBUS,
5V/Div
VCC,
5V/Div
40ms/Div
Figure 42. Typical Start-up Behavior, VIN = 13.5 V, CC1 = Rd, RIMON = 12.6 kΩ
For TPS25830-Q1, the pin voltage must meet the requirement below during 150 ms (typical) Rd assert deglitch
time, see Figure 43:
• VBUS < 0.8V (typical), per Type-C requirement;
• VDx_OUT < 2.2V (typical);
• VDx_IN < 1.5V (typical);
After the TPS25830-Q1 Rd assert deglitch time, no additional requirement on these pins. In real application,
LD_DET pin can be used to configure the timing sequence.
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Feature Description (continued)
VIN/EN
Rd assert here
CC1/CC2
Dx_OUT
VBUS
Must < 2.2V
}v[š
Œ
VBUS must < 0.8V
deglitch time
150ms (typ)
DP/DM
Date Switch
ON
OFF
LD_DET
Figure 43. TPS25830-Q1 Pin Voltage Requirement During Rd Assert
10.3.3 Switching Frequency and Synchronization (RT/SYNC)
The switching frequency of the TPS2583x-Q1 can be programmed by the resistor RT from the RT/SYNC pin and
GND pin. To determine the RT resistance, for a given switching frequency, use Equation 3:
RT Resistance (k:)
(3)
70
65
60
55
50
45
40
35
30
25
20
15
10
5
200
400
600
800 1000 1200 1400 1600 1800 2000 2200
Switching Frequency (kHz)
D024
Figure 44. RT Set Resistor vs Switching Frequency
Typical RT resistors value are listed in Table 1.
Table 1. Setting the Switching Frequency with RT
RT (kΩ)
SWITCHING FREQUENCY (kHz)
68.1
300
49.9
400
39.2
500
19.1
1000
12.4
1500
9.31
2000
8.87
2100
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Feature Description (continued)
Table 1. Setting the Switching Frequency with RT (continued)
RT (kΩ)
SWITCHING FREQUENCY (kHz)
8.45
2200
TPS2583x-Q1 switching action can be synchronized to an external clock from 300 kHz to 2.3 MHz. The
RT/SYNC pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can
be synchronized by AC coupling a positive edge into the RT/SYNC pin. The AC coupled peak-to-peak voltage at
the RT/SYNC pin must exceed the SYNC amplitude threshold of 3.5 V (typical) to trip the internal
synchronization pulse detector, and the minimum SYNC clock ON and OFF time must be longer than 100 ns
(typical). When using a low impedance signal source, the frequency setting resistor RT is connected in parallel
with an AC coupling capacitor CCOUP to a termination resistor RTERM (for example, 50 Ω). The two resistors in
series provide the default frequency setting resistance when the signal source is turned off. A 10 pF ceramic
capacitor can be used for CCOUP. Figure 45 show the device synchronized to an external clock.
CCOUP
RT
PLL
Lo-Z
Clock
Source
RTERM
RT/SYNC
PLL
Hi-Z
Clock
Source
RT
RT/SYNC
Figure 45. Synchronize to External Clock
In order to avoid AM radio frequency brand and maintain proper regulation when minimum ON-time or minimum
OFF-time is reached, the TPS2583x-Q1 implement frequency foldback scheme depends on VIN voltage, refer to
Figure 11.
• When 8 V < VIN ≤ 19 V, the switching frequency of TPS2583x-Q1 is determined by RT resistor or external
sync clock.
• When VIN ≤ 8 V, the switching frequency of TPS2583x-Q1 is set to default 420 kHz, regardless of RT resistor
setting or external sync clock.
• When VIN > 19 V, the switching frequency of TPS2583x-Q1 is set to default 420 kHz, regardless of RT
resistor setting or external sync clock
Figure 46, Figure 47 and Figure 48 show the device switching frequency and behavior under different VIN
voltage and RT = 8.87 kΩ.
Figure 49, Figure 50 and Figure 51 show the device switching frequency and behavior under different VIN
voltage and synchronized to an external 2.1 M system clock.
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VIN,
10V/Div
VIN,
10V/Div
SW,
10V/Div
SW,
10V/Div
Inductor Current,
5A/Div
VIN = 7.5 V
1us/Div
L = 2.2 uH
ILOAD = 3 A
Figure 46. Switching Frequency When RT = 8.87 kΩ
Inductor Current,
5A/Div
VIN = 13.5 V
1us/Div
L = 2.2 uH
ILOAD = 3 A
Figure 47. Switching Frequency When RT = 8.87 kΩ
VIN, 5V/Div
VIN,
10V/Div
SW,
10V/Div
Sync, 2V/Div
SW,
5V/Div
Inductor Current,
5A/Div
VIN = 20 V
1us/Div
L = 2.2 uH
ILOAD = 3 A
Figure 48. Switching Frequency When RT = 8.87 kΩ
Inductor Current,
2A/Div
VIN = 7.5 V
1us/Div
L = 2.2 uH
ILOAD = 3 A
Figure 49. Synchronizing to External 2.1-MHz Clock
VIN, 10V/Div
VIN, 5V/Div
Sync, 2V/Div
Sync, 2V/Div
SW,
10V/Div
SW,
10V/Div
Inductor Current,
2A/Div
VIN = 13.5 V
1us/Div
L = 2.2 uH
ILOAD = 3 A
Figure 50. Synchronizing to External 2.1-MHz Clock
Inductor Current,
2A/Div
VIN = 20 V
1us/Div
L = 2.2 uH
ILOAD = 3 A
Figure 51. Synchronizing to External 2.1-MHz Clock
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10.3.4 Spread-Spectrum Operation
In order to reduce EMI, the TPS2583x-Q1 introduce frequency spread spectrum. The spread spectrum is used to
eliminate peak emissions at specific frequencies by spreading emissions across a wider range of frequencies
than a part with fixed frequency operation. In most systems, low frequency conducted emissions from the first
few harmonics of the switching frequency can be easily filtered. A more difficult design criterion is reduction of
emissions at higher harmonics which fall in the FM band. These harmonics often couple to the environment
through electric fields around the switch node. The TPS2583x-Q1 devices use ±6% spread of switching
frequencies with 1/256 swing frequency.
The spread spectrum function is only available when using the TPS2583x-Q1 internal oscillator. If the RT/SYNC
pin is synchronized to an external clock, the spread spectrum function will be turn off.
10.3.5 VCC, VCC_UVLO
The TPS2583x-Q1 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The
nominal voltage for VCC is 5 V. The VCC pin is the output of an LDO and must be properly bypassed. A high
quality ceramic capacitor with a value of 2.2 µF to 4.7 µF, 10 V or higher rated voltage should be placed as close
as possible to VCC and grounded to the PGND ground pin. The VCC output pin should not be loaded with more
than 5 mA, or shorted to ground during operation.
In applications where VCONN support is required, the VCC pin can be over-driven with an external 5-V LDO
capable of sourcing at least 300 mA. In this operating mode the external LDO is the source for the buck low-side
switch gate drive as well as power to the internal VCONN mux.
Note if using external 5-V LDO for VCONN power, the timing sequence below must be required. External VCONN
power can not be enabled before the TPS2583x-Q1 is enabled, external VCONN must be disabled before the
TPS2583x-Q1 is disabled. In real application, customer can tie the EN of external 5-V LDO and EN of
TPS2583x-Q1 together to meet the timing requirement.
IN
EN/UVLO
RT/SYNC
LDO
TPS2583x-Q1
VCC
/FAULT
/LD_DET
PGND
/POL
Figure 52. VCONN Source Using External LDO
10.3.6 Minimum ON-time, Minimum OFF-time
Minimum ON-time, TON_MIN, is the smallest duration of time that the HS switch can be on. TON_MIN is typically 105
ns in the TPS2583x. Minimum OFF-time, TOFF_MIN, is the smallest duration that the HS switch can be off.
TOFF_MIN is typically 80 ns in the TPS2583x-Q1. In CCM (FPWM) operation, TON_MIN and TOFF_MIN limit the
voltage conversion range given a selected switching frequency.
The minimum duty cycle allowed is:
(4)
And the maximum duty cycle allowed is:
(5)
Given fixed TON_MIN and TOFF_MIN, the higher the switching frequency the narrower the range of the allowed duty
cycle.
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10.3.7 Internal Compensation
The TPS2583x-Q1 is internally compensated as shown in Figure 39. The internal compensation is designed such
that the loop response is stable over the specified operating frequency and output voltage range. The TPS2583xQ1 is optimized for transient response over the range 300 kHz ≤ fsw ≤2300 kHz.
10.3.8 Bootstrap Voltage (BOOT)
The TPS2583x-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and
SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the
high-side MOSFET is off and the low-side switch conducts. The recommended value of the BOOT capacitor is
0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is
recommended for stable performance over temperature and voltage.
10.3.9 RSNS, RSET, RILIMIT and RIMON
The programmable current limit threshold and full-scale cable compensation voltage are determined by the
values of the RSNS, RSET, RILIMIT, and RIMON resistors. Refer to Figure 53.
• RSNS is the current sense resistor. The recommended voltage across RSNS under current limit should be
approximately 50 mV as a compromise between accuracy and power dissipation. For example, if current
limiting is desired for IOUT(MAX) ≥ 3.3 A, then RSNS = 0.05 V / 3.3 A = 0.01515 Ω. Choose a standard value of
15 mΩ.
• RSET determines the input current to the transconductance amplifier and current mirror. The amplifier
balances the voltage to be equal to that across RSNS. Choose a RSET value to produce an ISET current
between 75 - 180 µA at the desired IOUT(MAX). Considering 50 mV across RSET, a value of 300 Ω will provide
approximately 166 µA of ISET current to the amplifier and mirror circuit. Care should be taken to limit the ISET
current below 200 µA to avoid saturating the internal amplifier circuit.
• RILIMIT inconjuction with the 0.5 x ISET current produces a voltage on the ILIMIT pin which is proportional to the
load current flowing in RSNS. See Current Limit Setting using RILIMIT for details on setting the current limit.
• RIMON inconjuction with the 0.5 x ISET current produces a voltage on the IMON pin which is proportional to the
load current flowing in RSNS. See Cable Compensation for details on setting the current limit.
(1): VSNS = ILOAD x RSNS
(2): VSNS ~= VSET
(by op amp)
(3): ISET = VSET / RSET = VSNS / RSET
ILOAD
RSNS
+ 50mV -
RSET
CSP
CSN/OUT
RT
Low Offset
Amp
RM
RB
+
IMON
±
IIMON = 0.5 x ISET
ISET
+
RIMON
±
RS = RT
ILIMIT
IILIMIT = 0.5 x ISET
RILIMIT
±
+
1V
Soft
Start
+
+
±
VCOMP
1V
VILIMIT = 1V (current limit by Buck)
VILIMIT = 0.49V (current limit by NFET)
LS_GD
±
+
0.49V
BUS
Figure 53. Current Limit and Cable Compensation Circuit
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10.3.10 Overcurrent and Short Circuit Protection
For maximum versatility, TPS2583x-Q1 includes both a precision, programmable current limit and cycle-by-cycle
current limit to protect the USB port from extreme overload conditions. In most applications the RILIMIT resistor in
conjunction with the selection of RSNS and RSET will determine the overload threshold. The cycle-by-cycle current
limit will serve as a backup means of protection in the event RILMIT is shorted to ground disabling the
programmable current limit function.
10.3.10.1 Current Limit Setting using RILIMIT
Refer to Figure 53. The TPS2583x-Q1 can establish current limit by two methods.
• Using external a single or back-to-back N-Channel MOFETs between CSN/OUT and BUS: A voltage of 0.49
V on the ILIMIT pin initiates current limiting using the external MOSFET by decreasing the LS_GD voltage
causing the FET to operate in the saturation region. To protect the MOSFETs from damage a hiccup timer
limits the duty cycle to prevent thermal runaway. Refer to the Switching Characteristics for MOSFET hiccup
timing.
• Buck average current limit: No MOSFET, CSN/OUT connected to BUS. For TPS25831-Q1, the LS_GD pin
can be left floating. For TPS25830-Q1, the LS_GD pin must be pulled up through 2.2kΩ resistor. In this
configuration a voltage of 1 V across RILIMIT on the ILIMIT pin initiates average current limiting of the buck
regulator.
The two level current limit is described below:
• With external MOSFET Figure 54, Figure 55:
Isolating a fault on the USB port from other loads connected to the CSP output of the TPS2583x-Q1. In
some applications, it may be useful to power additional circuitry (example USB HUB) from the output of
the TPS2583x-Q1 and maintain operation of these circuits in the event of a short circuit downstream of the
BUS pin. To prevent triggering the MOSFET current limit below the programmed ILIMIT threshold,
external circuits should be supplied after the inductor and before the current sense resistor, RSNS.
After RSNS and RSET are determined and the full load ISET current is known, the resistor value RILIMIT can
be determined by:
(6)
In most case, the recommended voltage across RSNS under current limit should be approximately 50 mV
as a compromise between accuracy and power dissipation. While in some application, RILIMIT is the only
resistor that can be changed to achieve different current limit. Typical RILIMIT resistors value are listed in
Table 2 given the condition RSNS= 15 mΩ and RSET= 300 Ω
Table 2. Setting the Current Limit with RILIMIT
Current-Limit Threshold (mA)
•
RILIMIT (kΩ)
With External MOSFET
Buck Average
700
26.1
53.6
1500
12.7
26.1
1700
11.3
22.6
2700
7.15
14.7
3000
6.49
13
3400
5.62
11.5
3800
5.11
10.5
Buck Average Current Limit Figure 56, Figure 57:
CSN/OUT connected directly to BUS. For TPS25831-Q1, LS_GD pin can be floating. For TPS25830-Q1,
LS_GD pin must be pulled up through 2.2kΩ resistor. The TPS2583x-Q1 can operate as a stand-alone
USB charging port. In this configuration, the internal buck regulator operates with average current limiting
as programmed by the ILIMIT pin, potentially producing less heat compared to N-channel MOSFET
current limiting
After RSNS and RSET are determined and the full load ISET current is known, the resistor value RILIMIT can
be determined by:
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(7)
Typical RILIMIT resistors value are listed in Table 2 given the condition RSNS= 15 mΩ and RSET= 300 Ω
CBOOT
CBOOT
To auxiliary
loads
VIN
VIN
BOOT
IN
L
BOOT
IN
RSNS
L
RSNS
SW
SW
RSET
EN/UVLO
To auxiliary
loads
RSET
EN/UVLO
CSP
CSP
RT/SYNC
RT/SYNC
CSN/OUT
CSN/OUT
VCC
VCC
TPS25831-Q1
TPS25830-Q1
LS_GD
FAULT
LS_GD
FAULT
LD_DET
BUS
CC1
CTRL2
CC2
DP_OUT
DP_IN
DM_OUT
DM_IN
IMON
ILIMIT
POL
Type-C Connector
POL
CTRL1
BUS
CTRL1
CC1
CTRL2
CC2
/THERM_WARN
DP_IN
NTC
DM_IN
IMON
AGND PGND
Figure 54. TPS25830-Q1 Current Limit with
External MOSFET
ILIMIT
AGND PGND
Figure 55. TPS25831-Q1 Current Limit with
External MOSFET
CBOOT
CBOOT
VIN
BOOT
IN
L
VIN
RSNS
L
RSNS
SW
RSET
EN/UVLO
RSET
CSP
RT/SYNC
BOOT
IN
SW
EN/UVLO
Type-C Connector
LD_DET
CSP
RT/SYNC
CSN/OUT
CSN/OUT
VCC
VCC
TPS25830-Q1
FAULT
TPS25831-Q1
2.2kohm
LS_GD
LS_GD
FAULT
LD_DET
BUS
CC1
CTRL2
CC2
DP_OUT
DP_IN
DM_OUT
DM_IN
IMON
ILIMIT
AGND PGND
POL
BUS
CTRL1
CC1
CTRL2
CC2
/THERM_WARN
DP_IN
NTC
DM_IN
IMON
Figure 56. TPS25830-Q1 Buck Average Current
Limit
ILIMIT
Type-C Connector
POL
CTRL1
Type-C Connector
LD_DET
AGND PGND
Figure 57. TPS25831-Q1 Buck Average Current
Limit
10.3.10.2 Buck Average Current Limit Design Example
To start the procedure, the ILOAD(MAX), RSNS, RSET, must to be known.
1. Determine ILIMIT, usually chose ILIMIT= ILOAD(MAX) / (1 - 10%).
2. Determine RSNS to achieve 50 mV at current limit. For 3-A Type-C load current, choose ILIMIT = 3.3A. RSNS =
(0.05 V / 3.3 A) = 15 mΩ.
3. Choose RSET = 300 Ω
4. According to Equation 7, RLIMIT = 300 / (0.5 x ( 3.3 X 0.015 + 0.0007)) = 11.95 kΩ.
5. Choose standard 11.8 kΩ.
10.3.10.3 External MOSFET Gate Drivers
The TPS2583x-Q1 has integrated NFET gate drivers, and can support current limit with external NFET. Refer to
Figure 54.
The LS_GD pin of TPS2583x-Q1 can source 3 uA (typical) current to enhance the external MOSFET. A 6.2-V
clamp between LS_GD and CSN/OUT pin limits the gate-to-source voltage. During DCDC start up, the LS_GD
gate drivers begin to source current after VCSN/OUT reach 3 V. If the VCSN/OUT > 7.5 V or VBUS > 7 V under
overvoltage condition, the LS_GD will turn off immediately with 35 uA (typical) sink current.
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If load current above NFET current limit threshold, LS_GD will also turn off the NFET after 2 ms (Typical) and
enter hiccup mode to protect NFET from thermal issue. Refer to Figure 99 for application waveform.
In real application, if VBUS short to VBAT function is needed, 20-V back-to-back NFET is suggested in circuit
design.
10.3.10.4 Cycle-by-Cycle Buck Current Limit
The buck regulator cycle-by-cycle current limit on both the peak and valley of the inductor current. Hiccup mode
will be activated if a fault condition persists to prevent over-heating.
High-side MOSFET overcurrent protection is implemented by the nature of the Peak Current Mode control. The
HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is
compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. Refer to
Functional Block Diagram for more details. The peak current of HS switch is limited by a clamped maximum peak
current threshold IHS_LIMIT which is constant. So the peak current limit of the high-side switch is not affected by
the slope compensation and remains constant over the full duty cycle range.
The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor
current begins to ramp down. The LS switch will not be turned OFF at the end of a switching cycle if its current is
above the LS current limit ILS_LIMIT. The LS switch will be kept ON so that inductor current keeps ramping down,
until the inductor current ramps below the LS current limit ILS_LIMIT. Then the LS switch will be turned OFF and
the HS switch will be turned on after a dead time. This is somewhat different than the more typical peak current
limit, and results in Equation 8 for the maximum load current.
(8)
If VCSN/OUT < 2-V typical due to a short circuit for 128 consecutive cycles, hiccup current protection mode will be
activated. In hiccup mode, the regulator will be shut down and kept off for 118 ms typically, then TPS2583x-Q1
go through a normal re-start with soft start again. If the short-circuit condition remains, hiccup will repeat until the
fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions,
prevents over-heating and potential damage to the device and serves as a backup to the programmable current
limit see the Current Limit Setting using RILIMIT section. Once the output short is removed, the hiccup delay is
passed, the output voltage recovers normally as shown in Figure 96.
10.3.11 Overvoltage, IEC and Short to Battery Protection
The TPS2583x-Q1 integrates OVP and short to battery protection on VBUS, CC1, CC2, DM_IN and DP_IN pins.
These pins can withstand voltage up to 18 V, and can protect upstream processor or Hub data line when
overvoltage or short to battery condition occurs. Refer to Figure 38 for short to battery test setup.
The TPS2583x-Q1 also integrates IEC ESD cell on CC1, CC2, DP_IN and DM_IN pins.
10.3.11.1 VBUS and VCSN/OUT Overvoltage Protection
The TPS2583x-Q1 integrates overvoltage protection on both BUS and CSN/OUT pin, to meet different
application requirement.
BUS pin can withstand up to 18 V, and the OVP threshold is 7-V typical. Once overvoltage is detected on BUS
pin, the LS_GD will turn off immediately, also FAULT asserts after 8-ms deglitch time. Once the excessive
voltage is removed, the LS_GD will turn on again and FAULT deasserts.
CSN/OUT pin can withstand up to 20 V, and the OVP threshold is 7.5-V typical. Once overvoltage is detected on
CSN/OUT pin, the buck converter will stop regulation, also LS_GD will turn off immediately. Once the excessive
voltage is removed, the buck converter will resume and LS_GD turn on again.
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CBOOT
VIN
BOOT
IN
CBOOT
To auxiliary
loads
VIN
L
RSNS
BOOT
L
IN
RSNS
SW
RSET
EN/UVLO
EN/UVLO
CSP
RT/SYNC
RSET
CSP
RT/SYNC
CSN/OUT
CSN/OUT
VCC
VCC
TPS25830-Q1
TPS25830-Q1
LS_GD
LD_DET
2.2kŸ
LS_GD
FAULT
0.22uF
0.22uF
LD_DET
RBUS= 100Ÿ
BUS
CTRL1
CC1
CTRL2
CC2
DP_OUT
DP_IN
DM_OUT
DM_IN
IMON
ILIMIT
Type-C Connector
RBUS= 10Ÿ
POL
AGND PGND
POL
BUS
CTRL1
CC1
CC2
CTRL2
DP_OUT
DP_IN
DM_OUT
DM_IN
IMON
Figure 58. Current Limit With External MOSFET
ILIMIT
Type-C Connector
FAULT
AGND PGND
Figure 59. Buck Average Current Limit
TPS2583x-Q1 is configured in external FET current limit mode as shown in Figure 58. When short to battery
occurs on BUS_Connector, the external MOSFET will be turn off immediately after BUS pin detect overvoltage.
The FAULT signal will assert after 8ms deglitch time, see Figure 104. With Back-to-back FET, the TPS2583x-Q1
can withstand short to battery event even when Vin is off. A 10-Ω 0805 resistor is recommended between BUS
pin and BUS_Connector.
TPS2583x-Q1 is configured in buck average current limit mode as shown in Figure 59. When short to battery
occurs on BUS_Connector, the buck regulator will stop switching after CSN/OUT pin detect overvoltage. The
FAULT signal will also assert after 8-ms deglitch time. A 100-Ω 0805 resistor is recommended between BUS pin
and BUS_Connector in buck average current limit mode.
10.3.11.2 DP_IN and DM_IN Protection
DP_IN and DM_IN protection consists of IEC ESD and overvoltage protection.
The DP_IN and DM_IN pins integrate an IEC ESD cell to provide ESD protection up to ±15 kV air discharge and
±8 kV contact discharge per IEC 61000-4-2 (See the ESD Ratings section for test conditions). The IEC ESD
performance of the TPS2583x-Q1 device depends on the capacitance connected from BUS pin to GND. A 0.22µF capacitor placed close to the BUS pin is recommended.
The ESD stress seen at DP_IN and DM_IN is impacted by many external factors like the parasitic resistance and
inductance between ESD test points and the DP_IN and DM_IN pins. For air discharge, the temperature and
humidity of the environment can cause some difference, so the IEC performance should always be verified in the
end-application circuit.
Overvoltage protection (OVP) is provided for short-to-VBUS or short-to-battery conditions in the vehicle harness,
preventing damage to the upstream USB transceiver or hub. When the voltage on DP_IN or DM_IN exceeds 3.9
V (typical), the TPS2583x-Q1 device immediately turn off DP/DM switch, and responds to block the high-voltage
reverse connection to DP_OUT and DM_OUT. FAULT signal will assert after 8ms deglitch time, see Figure 108.
For DP_IN and DM_IN, when OVP is triggered, the device turns on an internal discharge path with 416-kΩ
resistance to ground. On removal of the overvoltage condition, the pin automatically turns off this discharge path
and returns to normal operation by turning on the previously affected analog switch.
10.3.11.3 CC IEC and OVP Protection
CCx protection consists of IEC ESD and overvoltage protection.
The CC pins integrate an IEC ESD cell to provide ESD protection up to ±15 kV air discharge and ±8 kV contact
discharge per IEC 61000-4-2 (See the ESD Ratings section for test conditions). Additional 0.22-uF capacitor
placed close to the CC pin is recommended in real application.
Overvoltage protection (OVP) is provided for short-to-VBUS or short-to-battery conditions in the vehicle harness.
When the voltage on CC1 or CC2 exceeds 6.1 V (typical), the TPS2583x-Q1 device immediately shut off CC
line. FAULT signal will assert after 8-ms deglitch time, see Figure 106.
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For CC1 and CC2, when OVP is triggered, the device turns on an internal discharge path with 55-kΩ resistance
to ground. On removal of the overvoltage condition, the pin automatically turns off this discharge path and returns
to normal operation.
10.3.12 Cable Compensation
When a load draws current through a long or thin wire, there is an IR drop that reduces the voltage delivered to
the load. Cable droop compensation linearly increases the voltage at the CSN/OUT pin of TPS2583x-Q1 as load
current increases with the objective of maintaining VBUS_CON (the bus voltage at the USB connector) at 5 V,
regardless of load conditions. Most portable devices charge at maximum current when 5 V is present at the USB
connector. Figure 60 provides an example of resistor drops encountered when designing an automotive USB
system with a remote USB connector location.
R(conn1_VBUS)
R(conn2_VBUS) R(pcb2_VBUS) R(USBconn_VBUS)
R(cable_VBUS)
CSP
CSN/OUT
BUS
PGND
Automotive
Connector
BOOT SW
RSET
+
VBUS
-
R(wire)
Automotive
Connector
RSNS
LS_GD
TPS2583x-Q1
+
VBUS_CON
-
USB Connector
R(pcb1_VBUS)
Rdson(NFET)
PCB 2
PCB 1
R(pcb1_GND)
R(conn1_GND)
R(conn2_GND) R(pcb2_GND) R(USBconn_GND)
R(cable_GND)
R(wire) = R(pcb1_VBUS) + R(conn1_VBUS) + R(cable_VBUS) + R(conn2_VBUS) + R(pcb2_VBUS) + R(USBconn_VBUS) +
R(USBconn_GND) + R(pcb2_GND) + R(conn2_GND) + R(cable_GND) + R(conn1_GND) + R(pcb1_GND)
Figure 60. Automotive USB Resistances
The TPS2583x-Q1 detects the load current and increases the voltage at the CSN/OUT pin to compensate the IR
drop in the charging path according to the gain set by the RSNS, RSET, and RIMON resistors as described in RSNS,
RSET, RILIMIT and RIMON.
Output Voltage (V)
The amount of cable droop compensation required can be estimated by the following equation ΔVOUT = (RSNS +
RDSON_NFET + RWIRE) × IBUS. RIMON is then chosen by RIMON = (ΔVOUT × RSET × 2) / (IBUS × RSNS), where ΔVOUT is
the desired cable droop compensation voltage at full load.
5.x
V(DROP)
VOUT with compensation
VBUS with compensation
VBUS without compensation
1
3
2
Output Current (A)
Figure 61. Voltage Drop
Per RSNS, RSET, RILIMIT and RIMON, in most cases, the recommended voltage across RSNS should be 50 mV. In
type-C application, typical RIMON resistors value are listed in Table 3 given the condition full load current = 3 A,
RSNS = 15 mΩ and RSET = 300 Ω.
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Table 3. Setting the Cable Compensation Voltage with RIMON
Cable Compensation Voltage at 3-A Full Load (V)
RIMON (kΩ)
0.3
4.02
0.6
8.06
0.9
12.1
1.2
16.2
1.5
20
Pls be noted that the max cable compensation voltage in TPS2583x-Q1 is 1.5 V.
10.3.12.1 Cable Compensation Design Example
To start the procedure, the RSNS, RDSON_NFET and wire resistance RWIRE, must to be known.
1. Determine RSNS to achieve 50 mV at full current. For 3.3 A (3-A Type-C load current plus at approximately
10% for overcurrent threshold). RSNS = (0.05 V / 3.3 A) = 15 mΩ.
2. RDSON_NFET = 50 mΩ
3. RWIRE = 200 mΩ
4. ΔVOUT = (RSNS + RDSON_NFET + RWIRE) × IBUS = (0.015 + 0.05 + 0.2) × 3 = 0.795 V
5. Choose RSET = 300 Ω
6. RIMON = (ΔVOUT * RSET × 2) / (IBUS × RSNS) = (0.795 × 300 × 2) / (3 × 0.015) = 10.6 kΩ
10.3.13 USB Port Control
The TPS25830-Q1 and TPS25831-Q1 include DP_IN, DM_IN, CC1 and CC2 pins for automatic or host
facilitated USB port power management of either a Type-A or Type-C downstream facing connector. See the
Device Functional Modes section for details on configuring the TPS2583x-Q1.
10.3.14 FAULT Response
The device features an active-low, open-drain fault output. Connect a 100-kΩ pullup resistor from FAULT to VCC
or other suitable I/O voltage. FAULT can be left open or tied to GND when not used.
Table 4 summarizes the conditions that generate a fault and actions taken by the device.
Table 4. Fault and Warning Conditions
EVENT
CONDITION
ACTION
The device regulates current at ISNS either by external NFET
or by the buck regulator control loop.
Overcurrent on OUT
NFET or Buck average current limit
implemented per Current Limit Setting using
RILIMIT.
ICSN/OUT > programmed ISNS.
Overvoltage on BUS
VBUS > VBUS_OV
When current limiting by external NFET, there is NO fault
indicator assertion under minor overload conditions.
When current limiting by buck average current, there is NO
fault indicator assertion under minor overload conditions.
Hard shorts during average buck current limiting may trigger
buck hiccup operation. The FAULT indicator asserts
immediately after NOC cycles in and persists for TOC as
specified in the Cycle-by-Cycle Buck Current Limit section.
The device turns on the BUS discharge path in the event of
an overvoltage conditions, and turn off the LS_GD
immediately. The FAULT indicator asserts and de-asserts
with a 8-ms deglitch.
Overvoltage on the data lines DP_IN or DM_IN > VDx_IN_OV
The device immediately shuts off the USB data switches.
The FAULT indicator asserts and de-asserts with a 8-ms
deglitch.
Overvoltage on CC lines
CC1 or CC2 > VCCx_OV
The device immediately shuts off the CC lines. The FAULT
indicator asserts and de-asserts with a 8-ms deglitch.
Overcurrent on CC lines
when supplying VCONN
ILOAD_CCn > IOS_CCn
The FAULT indicator asserts and de-asserts with a 8-ms
deglitch. The FAULT indicator remains asserted during the
VCONN overload condition and the VCONN path is not
disabled.
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Table 4. Fault and Warning Conditions (continued)
EVENT
CONDITION
ACTION
TPS25831-Q1 External
overtemperature detection
(NTC)
VNTC ≥ VWARN_HIGH
Thermal warning flag THERM_WARN asserts immediately.
Also the type-C advertise current will change to 1.5 A if
operate with 3 A originally. The FAULT flag is not asserted
for this condition, but will assert for conditions stated in this
table.
TPS25831-Q1 External
overtemperature detection
(NTC)
VNTC ≥ VSD_HIGH
The device immediately shuts off the buck regulator, opens
the USB data switches, while simultaneously pulling LS_GD
and BUS low. The THERM_WARN indicator remains
asserted.
10.3.15 USB Specification Overview
Universal Serial Bus specifications provide critical physical and electrical requirements to electronics
manufacturers of USB capable equipment. Adherence to these specifications during product development
coupled with standardized compliance testing assures very high degrees of interoperability amongst USB
products in the market. Since its inception in the mid 1990s, USB has undergone a number of revisions to
enhance utility and extend functionality. For the most up to date standards, please consult the USB Implementers
Forum (USB-IF).
All USB ports are capable of providing a 5-V output making them a convenient power source for operating and
charging portable devices. USB specification documents outline specific power requirements to ensure
interoperability. In general, a USB 2.0 port host port is required to provide up to 500 mA; a USB 3.0 or USB 3.1
port is required to provide up to 900 mA; ports adhering to the USB Battery Charging 1.2 Specification provide up
to 1500 mA; and newer Type-C ports can provide up to 3000 mA. Though USB standards governing power
requirements exist, some manufacturers of popular portable devices created their own proprietary mechanisms
to extend allowed available current beyond the 1500-mA maximum per BC 1.2. While not officially part of the
standards maintained by the USB-IF, these proprietary mechanisms are recognized and implemented by
manufacturers of USB charging ports.
The TPS2583x-Q1 device supports five of the most-common USB-charging schemes found in popular hand-held
media and cellular devices.
• USB Type-C (1.5 A and 3 A advertisement)
• USB Battery Charging Specification BC1.2
• Chinese Telecommunications Industry Standard YD/T 1591-2009
• Divider 3 mode
• 1.2-V mode
The BC1.2 specification includes three different port types:
• Standard downstream port (SDP)
• Charging downstream port (CDP)
• Dedicated charging port (DCP)
BC1.2 defines a charging port as a downstream-facing USB port that provides power for charging portable
equipment. Under this definition, CDP and DCP are defined as charging ports.
Table 5 lists the difference between these port types.
Table 5. USB Operating Modes Table
38
PORT TYPE
SUPPORTS USB2.0 COMMUNICATION
MAXIMUM ALLOWABLE CURRENT
DRAWN BY PORTABLE EQUIPMENT (A)
SDP (USB 2.0)
YES
0.5
SDP (USB 3.0 and 3.1)
YES
0.9
CDP
YES
1.5
DCP
NO
1.5
TYPE-C
YES
3.0
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10.3.16 USB Type C Basics
For a detailed description of the Type-C specifications refer to the USB-IF website to download the latest
information. Understanding the basic concepts of the USB Type-C specification will aid in understanding the
operation of the TPS2583x-Q1 (a DFP device).
USB Type-C removes the need for different plug and receptacle types for host and device functionality. The
Type-C receptacle replaces both Type-A and Type-B receptacle since the Type-C cable is plug-able in either
direction between host and device. A host-to-device logical relationship is maintained via the configuration
channel (CC). Optionally hosts and devices can be either providers or consumers of power when USB Power
Delivery (PD) communication is used to swap roles.
All
•
•
•
USB Type-C ports operate in one of below three data modes:
Host mode: the port can only be host (provider of power)
Device mode: the port can only be device (consumer of power)
Dual-Role mode: the port can be either host or device
Port types:
• DFP (Downstream Facing Port): Host
• UFP (Upstream Facing Port): Device
• DRP (Dual-Role Port): Host or Device
Valid DFP-to-UFP connections:
• Table 6 describes valid DFP-to-UFP connections
• Host to Host or Device to Device have no functions
Table 6. DFP-to-UFP Connections
HOST-MODE PORT
(1)
DEVICE-MODE
PORT
DUAL-ROLE PORT
Host-Mode Port
No Function
Works
Works
Device-Mode Port
Works
No Function
Works
Dual-Role Port
Works
Works
Works (1)
This may be automatic or manually driven.
10.3.16.1 Configuration Channel
The function of the configuration channel is to detect connections and configure the interface across the USB
Type-C cables and connectors.
Functionally the Configuration Channel (CC) is used to serve the following purposes:
• Detect connect to the USB ports
• Resolve cable orientation and twist connections to establish USB data bus routing
• Establish DFP and UFP roles between two connected ports
• Discover and configure power: USB Type-C current modes or USB Power Delivery
• Discovery and configure optional Alternate and Accessory modes
• Enhances flexibility and ease of use
Typical flow of DFP to UFP configuration is shown in Figure 62:
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Figure 62. Flow of DFP to UFP Configuration
10.3.16.2 Detecting a Connection
DFPs and DRPs fulfill the role of detecting a valid connection over USB Type-C. Figure 63 shows a DFP to UFP
connection made with Type C cable. As shown in Figure 63, the detection concept is based on being able to
detect terminations in the product which has been attached. A pull-up and pull-down termination model is used. A
pull-up termination can be replaced by a current source. TPS2583x-Q1 devices use current sources in lieu of RP
as allowed by the Type-C specification.
• In the DFP-UFP connection the DFP monitors both CC pins for a voltage lower than the unterminated
voltage.
• An UFP advertises Rd on both its CC pins (CC1 and CC2).
• A powered cable advertises Ra on only one of CC pins of the plug. Ra is used to inform the source to apply
VCONN.
• An analog audio device advertises Ra on both CC pins of the plug, which identifies it as an analog audio
device. VCONN is not applied on either CC pin in this case.
UFP monitors for
connection
DFP monitors for
connection
Cable
CC
Rp
Rp
Ra
Rds
Ra
Rds
DFP monitors for
connection
UFP monitors for
connection
Figure 63. DFP-UFP Connection
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10.3.16.3 Configuration Channel Pins CC1 and CC2
The TPS2583x-Q1 has two pins, CC1 and CC2 that serve to detect an attachment to the port and resolve cable
orientation. These pins are also used to establish current broadcast to a valid UFP and configure VCONN.
Table 7 lists TPS2583x-Q1 response to various attachments to its port.
Table 7. TPS2583x-Q1 Response
(1)
(2)
(3)
TPS2583x-Q1 RESPONSE (1)
TPS2583x-Q1 TYPE C
PORT
CC1
CC2
BUCK
REGULATOR
LS_GD
VCONN
On CC1 or CC2 (2)
POL
Nothing Attached
OPEN
OPEN
OFF
OFF
NO
Hi-Z
Hi-Z
UFP Connected
Rd
OPEN
ON
ON
NO
Hi-Z
LOW
LD_DET
UFP Connected
OPEN
Rd
ON
ON
NO
LOW
LOW
Powered Cable/No UFP
Connected
OPEN
Ra
OFF
OFF
NO
Hi-Z
Hi-Z
Powered Cable/No UFP
Connected
Ra
OPEN
OFF
OFF
NO
Hi-Z
Hi-Z
Powered Cable/UFP
Connected
Rd
Ra
ON
ON
CC2
Hi-Z
LOW
Powered Cable/UFP
Connected
Ra
Rd
ON
ON
CC1
LOW
LOW
Debug Accessory
Connected (3)
Rd
Rd
OFF
OFF
NO
Hi-Z
Hi-Z
Audio Adapter Accessory
Connected (3)
Ra
Ra
OFF
OFF
NO
Hi-Z
Hi-Z
POL andLD_DET are open drain outputs; pull high with 100 kΩ to VCC when used. Tie to GND or leave open when not used.
To supply VCONN a 5 V external LDO with at least 500mA output current should be connected to the VCC pin.
The TPS2583x-Q1 don't support debug mode or audio mode.
10.3.16.4 Current Capability Advertisement and VCONN Overload Protection
The TPS2583x-Q1 supports all three Type-C current advertisements as defined by the USB Type C standard.
Current broadcast to a connected UFP is controlled by the CTRL1 and CTRL2 pins. For each broadcast level the
device protects itself from a UFP that draws current in excess of the port’s USB Type-C Current advertisement
by setting the current limit as shown in Table 8.
Table 8. USB Type-C Current Advertisement
DEVICE
'830-Q1
'831-Q1
CC CAPABILITY
BROADCAST
MODE
SUPPORT USB 2.0
COMMUNICATION
CTRL1
CTRL2
0
0
RESERVED, DO NOT USE
0
1
RESERVED, DO NOT USE
1
0
SDP
YES: DP_IN to
DP_OUT and DM_IN to
DM_OUT
3A
CDP
YES: DP_IN to
DP_OUT and DM_IN to
DM_OUT
1.5 A
1
1
0
0
0
1
3A
DCP auto
NOT SUPPORT
1
0
1.5 A
SDP
Stub Connection Only
1
1
3A
CDP
Stub Connection Only
CURRENT LIMIT
(typ)
BY RSNS, RSET,
RILIMIT
RESERVED, DO NOT USE
BY RSNS, RSET,
RILIMIT
Under overload conditions, a precision current-limit circuit limits the VCONN output current. When a VCONN
overload condition is present, the TPS2583x-Q1 maintains a constant output current, with the output voltage
determined by (iOS_CCn x RLOAD). VCONN functionality is supported only with an external 5-V supply connected to
VCC. Failure to connect an external supply may cause TPS2583x-Q1 Vcc reset. The device turns off when the
junction temperature exceeds the thermal shutdown threshold, TSD and remains off until the junction temperature
cools approximately 20°C and then restarts. The TPS2583x-Q1 current limit profile is shown in Figure 64.
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VCC
Slope = -rDS-ON
VCONN
0V
0A
ICCn
IOS_CCn
Figure 64. VCONN Current Limit Profile
10.3.16.5 Plug Polarity Detection
Reversible Type-C plug orientation is reported by the POL pin when a UFP is connected. However when no UFP
is attached, POL remains de-asserted irrespective of cable plug orientation. Table 9 describes the POL state
based on which device CC pin detects VRD from an attached UFP pull-down.
Table 9. Plug Polarity Detection
42
CC1
CC2
Rd
Open
Hi-Z
UFP connected
Open
Rd
Asserted (pulled low)
UFP connected with reverse plug orientation
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POL
STATE
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Figure 65 shows an example implementation that uses the POL terminal to control the SEL terminal on the
HD3SS3212. The HD3SS3212 provides switching on the differential channels between Port B and Port C to Port
A depending on cable orientation.
USB Host
LDO
3.3V
5.05 ~ 6V (cable compensated)
IN
OUT
GND
12V
RSNS
BOOT S W
IN
RSE T
CSP
CSN /
OUT
E N/UVL O
RT/S YNC
V CC
TPS25830-Q1
LS _GD
BUS
/FAULT_IN
/FAULT
CC1
/E N
/LD_DET
DM
DM_OUT
DP
DP_OUT
DM_IN
DP_IN
Type -C Con nector
P GND
IL IM IT
IM ON
AGND
CTRL1
CTRL2
CC2
/P OL
USB 3.0 MUX
S STX p
S STX n
S SRX p
S SRX n
OE n
S EL
B0+
B0-
V CC
A0+
C0+
C0-
A0A1+
B1+
B1-
A1-
C1+
C1-
S SRX p2
S SRX n2
S SRX p1
S SRX n1
S STX p2
S STX n2
S STX p1
S STX n1
GND
Figure 65. Example Implementation
10.3.17 Device Power Pins (IN, CSN/OUT, and PGND)
The IN pins are the input power path to the TPS2583x-Q1 devices. The internal LDO and buck regulator high
side switch are supplied from the IN pins. The CSN/OUT pin connects to the negative terminal of the current
sense amplifier and the internal voltage feedback network. This pin must be connected to the output LC filter for
proper operation. PGND is the power ground return. For optimum performance, ensure the IN pin is properly
bypassed to PGND with adequate bulk and high-frequency bypass capacitance located as close to these pins as
possible.
10.3.18 Thermal Shutdown
The device has an internal overtemperature shutdown threshold, TSD to protect the device from damage and
overall safety of the system. When device temperature exceeds TSD, the LD_GD pin is pulled low, and the buck
regulator stops switching. The device attempts to power-up when die temperature decreases by approximately
20°C.
10.3.19
Power Wake
Legacy Type-A ports source 5 V on VBUS regardless of a load connection or not. In contrast, Type-C ports are
"cold," 0 V, until a UFP connection has been detected with the CC lines. This fundamental change in VBUS
operation enables a Type-C port to save power when no load is connected. The TPS2583x-Q1 devices monitor
the CC lines for a UFP connection and enable the internal buck regulator to source VBUS after a UFP is
detected. As a result idle port power consumption is reduced compared to Type-A port systems where the buck
regulator operates continuously to supply VBUS, even when no load is connected.
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10.3.20 Thermal Sensing with NTC (TPS25831-Q1)
The NTC input pin allows for user programmable thermal protection. See the Electrical Characteristics for NTC
pin thresholds. The NTC input pin threshold is ratiometric with VCC. The external resistor divider setting VNTC
must be connected to the TPS25831-Q1 VCC pin to achieve accurate results, see Figure 66 and Figure 67. When
VNTC = 0.5 × VCC (approximately 2.5-V typically), the TPS25831-Q1 performs two actions:
1. If operating with 3-A Type-C advertisement, the CC1 and CC2 pin automatically reduces advertisement to
the 1.5-A level.
2. The THERM_WARN flag is asserted to provide an indication of the over-temperature condition. FAULT is
NOT asserted at this time.
TPS25831-Q1
/THERM_WARN
/THERM_WARN
VCC
VCC
RSER
RPARA
RNTC
NTC
CC override
(3A -> 1.5A)
RB
Vth9 §
VCC
2
Turn off Buck
regulator
Vth9 § 0.65 x VCC
Figure 66. NTC Input Pin
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Ambient Temp
TNTC_TSD
ûTSD
TNTC_WARN
ûTWARN
25C
time
CCx adv. current
330uA
180uA
80uA
ûtWN2SD
ûtSD2WN
time
Therm_Warn
High
Low
time
Buck Regulator
ON
OFF
time
Figure 67. TPS25831-Q1 Behavior When Trigger NTC Threshold
If the overtemprature condition persists causing VNTC = VCC × 0.65 (3.25-V typical), the TPS25831-Q1 turns off
the buck regulator and pulls the LS_GD pin low. The THERM_WARN flag remains asserted; however, the
FAULT pin is NOT asserted for this condition.
Tuning the VNTC theshold levels of VWARN_HIGH and VSD_HIGH is achieved by adding RSER, RPARA, or both RSER and
RPARA in conjunction with RNTC. Figure 68 is an example illustrating how to set the THERM_WARN threshold
between 75°C and 90°C with a ΔT between THERM_WARN assertion and device shutdown of 17°C to 28°C.
Consult the chosen NTC manufacturer's specification for the value of β. It may take some iteration to establish
the desired warning and shutdown thresholds.
Below is NTC spec and resistor value used in Figure 68 example.
•
•
•
•
R0 = 470 kΩ. β = 4750. RNTC=R0 × exp β × (1/T-1/T0)
RPARA = 100 kΩ.
RSER = 5 kΩ.
RB = RNTC(at T_THERM_WARN) = 32 kΩ
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5
4.5
NTC pin voltage
4
VNTC (V)
3.5
VNTC w/top ser (V)
3
VNTC w/top || (V)
2.5
VNTC w para + ser
(V)
2
1.5
Vth WARN
1
Vth S/D
0.5
0
0
50
100
150
Temperature (°C)
Example
Figure 68. VNTC Threshold Examples
The NTC resistor should be placed near the hottest point on the PCB. In most cases, this will be close to the SW
node of the TPS25831-Q1, near the buck inductor, RSNS sense resistor and external MOSFETs (if used).
Buried layer NTC signal Routing
Figure 69. NTC Placement Example
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10.4 Device Functional Modes
10.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the TPS2583x. When VEN is below 1.2 V (typical), the
device is in shutdown mode. The TPS2583x-Q1 also employs VIN and VCC undervoltage lock out protection. If
VIN or VCC voltage is below their respective UVLO level, the regulator will be turned off.
10.4.2 Standby Mode
If the EN pin is pulled above the EN threshold, and there is no active connection on the CC lines, TPS2583x-Q1
remains in a low-power state with the buck converter off until a valid UFP (sink) is detected with a valid RD on
either CC1 or CC2. This mode ensures the Type-C 0 V VBUS requirement is met and saves system power when
no device is connected.
10.4.3 Active Mode
The TPS2583x-Q1 is in Active Mode when VEN is above the precision enable threshold, VIN and VCC are above
their respective UVLO levels and a valid detection has been made on the CC lines. The simplest way to enable
the TPS2583x-Q1 is to connect the EN pin to VIN pin. This allows self startup when the input voltage is in the
operating range: 3.8 V to 36 V and a UFP detection is made. Refer to VCC, VCC_UVLO and Enable/UVLO and
Start-up for details on setting these operating levels.
In Active Mode, the TPS2583x-Q1 buck regulator operates with forced pulse width modulation (FPWM), also
referred to as forced continuous conduction mode (FCCM). This ensures the buck regulator switching frequency
remains constant under all load conditions. FPWM operation provides low output voltage ripple, tight output
voltage regulation, and constant switching frequency. Built-in spread-spectrum modulation aids in distributing
spectral energy across a narrow band around the switching frequency programmed by the RT/SYNC pin. Under
light load conditions the inductor current is allowed to go negative. A negative current limit of IL_NEG is imposed to
prevent damage to the regulator's low side FET. During operation the TPS2583x-Q1 will synchronize to any valid
clock signal on the RT/SYNC input.
10.4.4 Device Truth Table (TT)
The device truth table (Table 10) lists all valid combinations for the two control pins (CTRL1 and CTRL2). The
TPS2583x-Q1 devices monitor the CTRL inputs and transitions to whichever charging mode it is commanded.
Table 10. Truth Table
DEVICE
TPS25830
-Q1
TPS25831
-Q1
CTR
L1
CTR
L2
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
CURRENT
LIMIT
SETTING
USB MODES
BUCK
REGULAT
OR
LS_GD
LD_DET
(OUTPUT)
POL
FAULT
(OUTPUT) (OUTPUT)
NTC
(ANALOG
INPUT)
RESERVED, DO NOT USE
RESERVED, DO NOT USE
See Current
Limit Setting
using RILIMIT
Type-C (1.5A) +
SDP Mode
Type-C (3A) +
CDP Mode
functional, see Table 7
functional,
see
Table 4
n/a
n/a
RESERVED, DO NOT USE
Type-C (3A) +
DCP Auto Mode
Current
Limit Setting
using RILIMIT
Type-C (1.5A) +
SDP Mode
functional
functional, see Table 7
Type-C (3A) +
CDP Mode
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functional,
see
Table 4
functional
functional
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10.4.5 USB Port Operating Modes
10.4.5.1 USB Type-C Mode
The TPS2583x-Q1 is a Type-C controller that supports all Type-C functions in a downstream facing port. It is
also used to manage current advertisement and protection to a connected UFP and active cable. When VIN
exceeds the undervoltage lockout threshold, the device samples the EN pin. A high level on this pin enables the
device and normal operation begins. Having successfully completed its start-up sequence, the device now
actively monitors its CC1 and CC2 pins for attachment to a UFP. When a UFP is detected on either the CC1 or
CC2 pin the buck regulator turn-ons after the required de-bounce time is met. If connected, the LS_GD pin
sources current into the external MOSFET allowing current to flow from CSN/OUT to BUS. If Ra is detected on
the other CC pin (not connected to UFP), VCONN is applied to allow current to flow from VCC to the CC pin
connected to Ra. For a complete listing of various device operational modes refer to Table 7.
The TPS2583x-Q1 always starts in Type-C mode, then transitions to DCP, CDP, or SDP as determined by the
CTRL1 and CTRL2 pins and signaling by the connected portable device on the DP_IN and DM_IN pins.
10.4.5.2 Standard Downstream Port (SDP) Mode — USB 2.0, USB 3.0, and USB 3.1
A SDP is a traditional USB port that follows USB 2.0, USB 3.0 or USB 3.1 protocol. A USB 2.0 SDP supplies a
minimum of 500 mA per port and supports USB 2.0 communications. A USB 3.x SDP supplies a minimum of 900
mA per port and supports USB 3.0 or USB 3.1 communications. For both types, the host controller must be
active to allow charging.
10.4.5.3 Charging Downstream Port (CDP) Mode
A CDP is a USB port that follows USB BC1.2 and supplies a minimum of 1.5 A per port. A CDP provides power
and meets the USB 2.0 requirements for device enumeration. USB-2.0 communication is supported, and the host
controller must be active to allow charging. The difference between CDP and SDP is the host-charge
handshaking logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device and
allows for additional current draw by the client device.
The CDP handshaking process occurs in two steps. During step one, the portable equipment outputs a nominal
0.6-V output on the DP line and reads the voltage input on the DM line. The portable device detects the
connection to an SDP if the voltage is less than the nominal data-detect voltage of 0.3 V. The portable device
detects the connection to a CDP if the DM voltage is greater than the nominal data detect voltage of 0.3 V and
optionally less than 0.8 V.
The second step is necessary for portable equipment to determine whether the equipment is connected to a CDP
or a DCP. The portable device outputs a nominal 0.6-V output on the DM line and reads the voltage input on the
DP line. The portable device concludes the equipment is connected to a CDP if the data line being read remains
less than the nominal data detects voltage of 0.3 V. The portable device concludes it is connected to a DCP if
the data line being read is greater than the nominal data detect voltage of 0.3 V.
10.4.5.4 Dedicated Charging Port (DCP) Mode (TPS25831-Q1 only)
A DCP only provides power and does not support data connection to an upstream port. As shown in the following
sections, a DCP is identified by the electrical characteristics of the data lines. The TPS25831-Q1 only emulates
one state, DCP-auto state. In the DCP-auto state, the device charge-detection state machine is activated to
selectively implement charging schemes involved with the shorted, divider3 and 1.2-V modes. The shorted DCP
mode complies with BC1.2 and Chinese Telecommunications Industry Standard YD/T 1591-2009, whereas the
divider3 and 1.2-V modes are employed to charge devices that do not comply with the BC1.2 DCP standard.
10.4.5.4.1 DCP BC1.2 and YD/T 1591-2009
Both standards specify that the D+ and D– data lines must be connected together with a maximum series
impedance of 200 Ω, as shown in Figure 70.
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D–
200 Ω
(m a x.)
D+
GND
USB Connector
VBUS
5V
Figure 70. DCP Supporting BC1.2 and YD/T 1591-2009
10.4.5.4.2 DCP Divider-Charging Scheme
The device supports divider3, as shown in Figure 71. In the Divider3 charging scheme the device applies 2.7 V
and 2.7 V to D+ and D– data lines.
VBUS
USB Connector
5V
D–
2.7 V
2.7 V
D+
GND
Figure 71. Divider 3 Mode
10.4.5.4.3 DCP 1.2-V Charging Scheme
The DCP 1.2-V charging scheme is used by some hand-held devices to enable fast charging at 2 A. The
TPS25831-Q1 device supports this scheme in DCP-auto state before the device enters BC1.2 shorted mode. To
simulate this charging scheme, the D+ and D– lines are shorted and pulled up to 1.2 V for a fixed duration. Then
the device moves to DCP shorted mode as defined in the BC1.2 specification and as shown in Figure 72.
200 Ω (m a x.)
D–
D+
1.2 V
GND
USB Connector
VBUS
5V
Figure 72. 1.2-V Mode
10.4.5.5 DCP Auto Mode (TPS25831-Q1 only)
The TPS25831-Q1 device integrates an auto-detect state machine that supports all DCP charging schemes. The
auto-detect state machine starts in the Divider3 scheme. If a BC1.2 or YD/T 1591-2009 compliant device is
attached, the TPS25831-Q1 device briefly transitions to the 1.2-V mode before entering BC1.2 DCP mode. The
auto-detect state machine stays in the 1.2 V or DCP mode until the connected device releases the data line, in
which case the auto-detect state machine goes back to the Divider3 scheme. When a Divider3-compliant device
is attached, the TPS25831-Q1 device stays in the Divider3 state.
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5V
S1
S2
S3
2.7 V
2.7 V
S4
DM_IN
D–
DP_IN
D+
GND
GND
USB Connector
VBUS
1.2 V
Divider 3 Mode
S1, S2: ON
S3, S4: OFF
Shorted Mode
S4 ON
S1, S2, S3: OFF
1.2-V Mode
S1, S2: OFF
S3, S4: ON
Figure 73. DCP Auto Mode
10.4.6 High-Bandwidth Data-Line Switches (TPS25830-Q1 only)
The TPS25830-Q1 device passes the DP and DM data lines through the device to enable monitoring and
handshaking while supporting the charging operation. A wide-bandwidth signal switch allows data to pass
through the device without corrupting signal integrity. The data-line switches are turned on in any of the CDP,
SDP modes. The EN/UVLO input must be at logic high and UFP must be entered for the data line switches to be
enabled.
•
•
•
•
•
•
50
NOTE
While in CDP mode, the data switches are ON, even during CDP handshaking.
The data line switches are OFF if EN/UVLO is low.
The data line switches are OFF during External FET current limit conditions.
The data line switches are not turned off during VCONN current-limit conditions.
The data line switches are OFF if UFP mode is not entered.
The data switches are only for a USB-2.0 differential pair. In the case of a USB-3.0 or
3.1 host, the super-speed differential pairs must be routed directly to the USB
connector without passing through the TPS25830-Q1 device.
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11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The TPS2583x-Q1 is a step down DC-to-DC regulator and USB charge port controller. It is typically used in
automotive systems to convert a DC voltage from the vehicle battery to 5-V DC with a maximum output current of
3.5 A. The following design procedure can be used to select components for the TPS2583x-Q1.
11.2 Typical Application
The TPS2583x-Q1 only requires a few external components to convert from a wide voltage range supply to a 5-V
output for powering USB devices. Figure 74 shows a basic schematic.
CBOOT
CSNS
0.1 F
0.1 F
VIN
6 V to 18 V
CIN(HF)
+ CIN(BULK) CIN
10 F
0.1 F
RENT
20 k
RENB
5k
IN (1, 2, 3)
BOOT (32)
SW (28, 29, 30, 31)
EN/UVLO (4)
L
RSNS
10 H
RSET
CSP (14)
CCSP
0.015
5*22 F
300
CSN/OUT (13)
0.22 F 0.22 F 0.22 F
2.2 F
CVCC(HF)
CC1 (20)
RPU
CTRL1 (5)
CTRL2 (6)
RPU
100 k
100 k
RPU
RPU
100 k
100 k
RPU
FAULT (24)
LD_DET (23)
POL (22)
NTC
100
BUS (15)
0.1 F
RPU
100 k
VCC (21)
CCSN/OUT
0.1 F
Type-C Connector
CVCC
LS_GD (10)
THERM_WARN (7)
100 k
CC2 (19)
DM_IN (17)
DP_IN (18)
RT/SYNC (9)
IMON (11)
RIMON
ILIMIT (12)
12.7 k
RILIMIT
11.8 k
AGND (16)
NTC (8)
PGND (25, 26, 27)
CBUS
1 F
RRT
49.9 k
Figure 74. Application Circuit
The integrated buck regulator of TPS2583x-Q1 is internally compensated and optimized for a reasonable
selection of external inductance and capacitance. The external components have to fulfill the needs of the
application, but also the stability criteria of the device's control loop. Table 12 can be used to simplify the output
filter component selection.
11.2.1 Design Requirements
To begin the design process, a few parameters must be known:
• Cable compesation: Total resistance including cable resistance, contact resistance of connectors, TPS2583xQ1 current sense resistor and external NFET rDS(on) (if used). Refer to Figure 60 for examples of resistances
in an automotive application.
• The maximum continuous output current for the charging port. The minimum current-limit setting of
TPS2583x-Q1 device must be higher than this current.
For this example, use the parameters listed in Table 11 as the input parameters.
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Typical Application (continued)
Table 11. Design Example Parameters
PARAMETER
VALUE
Input Voltage, VIN
13.5-V typical, range from 6 V to 18 V
Output Voltage, VOUT
5.1 V
Maximum Output Current IOUT(MAX)
3.0 A
Transient Response 0.3 A to 3 A
5%
Output Voltage Ripple
50 mV
Input Voltage Ripple
400 mV
Switching Frequency fSW
400 kHz
Cable Resistance for Cable Compensation
300 mΩ
Current Limit by Buck Average
3.3 A
Table 12. L and COUT Typical Values
VOUT WITHOUT
CABLE
COMPENSATION
fSW
CIN + CHF
L
CURRENT
LIMIT
CCSP
CCSN/OUT
CBUS
400 kHz
5.10 V
1 x 10 µF + 1 x 100 nF
10 µH
Buck Avg
5 x 22 µF
100 nF
1 to 4.7 µF
400 kHz
5.10 V
1 x 10 µF + 1 x 100 nF
10 µH
Ext. NFET
5 x 22 µF
100 nF
1 to 4.7 µF
2100 kHz
5.10 V
1 x 10 µF + 1 x 100 nF
2.2 µH
Buck Avg
2 x 22 µF
100 nF
1 to 4.7 µF
1. Inductance value is calculated based on VIN = 18 V.
2. All the COUT values are after derating.
11.2.2 Detailed Design Procedure
11.2.2.1
Output Voltage
The output voltage of TPS2583x-Q1 is internally fixed at 5.10 V. Cable compensation can be used to increase
the voltage on the CSN/OUT pin linearly with increasing load current. Refer to the Cable Compensation section
for more details on output voltage variation versus load current. If cable compensation is not desired, use a 0 Ω
RIMON resistor.
11.2.2.2
Switching Frequency
The recommended switching frequency of the TPS2583x-Q1 is in the range of 300 to 400 kHz for best efficiency.
Choose RRT = 49.9 kΩ for 400 kHz operation. To choose a different switching frequency, refer to Table 1.
11.2.2.3
Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current and the rated current. The
inductance is based on the desired peak-to-peak ripple current ΔiL. Since the ripple current increases with the
input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use
Equation 10 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the
amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of
KIND should be 20% to 40%. During an instantaneous short or overcurrent operation event, the RMS and peak
inductor current can be high. The inductor current rating should be higher than the current limit of the device.
'iL
LMIN
52
VOUT u VIN _ MAX
VOUT
VIN _ MAX u L u fSW
VIN _ MAX
VOUT
IOUT u KIND
(9)
VOUT
u
VIN _ MAX u fSW
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In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low
of an inductance can generate too large of an inductor current ripple such that overcurrent protection at the full
load could be falsely triggered. Larger inductor current ripple also implies larger output voltage ripple with same
output capacitors. With peak current mode control, it is not recommended to have too small of an inductor
current ripple. A larger peak current ripple improves the comparator signal to noise ratio.
For this design example, choose KIND = 0.3, the minimum inductor value is calculated to be 8.7 µH. Choose the
nearest standard 10-μH ferrite inductor with a capability of 4-A RMS current and 6-A saturation current.
11.2.2.4 Output Capacitor Selection
The value of the output capacitor, and its ESR, determine the output voltage ripple and load transient
performance. The output capacitor bank is usually limited by the load transient requirements, rather than the
output voltage ripple. Equation 11 can be used to estimate a lower bound on the total output capacitance, and an
upper bound on the ESR, required to meet a specified load transient.
º
ª
'IOUT
K2
COUT t
˜«1 D ˜ 1 K
˜ 2 D»
12
fSW ˜ 'VOUT ˜ K «¬
»¼
ESR d
D
2 K ˜ 'VOUT
ª
2 ˜ 'IOUT «1 K
«¬
K2
12
§
1 ·º
¸¸»
˜ ¨¨1
© (1 D) ¹»¼
VOUT
VIN
where
•
•
•
ΔVOUT = output voltage transient
ΔIOUT = output current transient
K = Ripple factor from Inductor Selection
(11)
Once the output capacitor and ESR have been calculated, Equation 12 can be used to check the peak-to-peak
output voltage ripple; Vr.
Vr # 'IL ˜ ESR 2
1
8 ˜ fSW ˜ COUT
2
(12)
The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple
requirements.
For this example we require a ΔVOUT of ≤ 250 mV for an output current step of ΔIOUT = 2.7 A. Equation 11 gives
a minimum value of 86 µF and a maximum ESR of 0.08 Ω. Assuming a 20% tolerance and a 10% bias de-rating,
we arrive at a minimum capacitance of 110 µF. This can be achieved with a bank of 5 × 22-µF, 10-V, ceramic
capacitors in the 1210 case size. More output capacitance can be used to improve the load transient response.
Ceramic capacitors can easily meet the minimum ESR requirements. In some cases an aluminum electrolytic
capacitor can be placed in parallel with the ceramics to help build up the required value of capacitance.
In practice the output capacitor has the most influence on the transient response and loop phase margin. Load
transient testing and Bode plots are the best way to validate any given design and should always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help to reduce high frequency noise. Small case size ceramic capacitors in the range of
1 nF to 100 nF can be very helpful in reducing voltage spikes on the output caused by inductor and board
parasitics.
The maximum value of total output capacitance should be limited to about 10 times the design value, or 1000 µF,
whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the
regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of startup at full load and loop stability must be performed.
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11.2.2.5
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Input Capacitor Selection
The TPS2583x-Q1 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor,
depending on the application. A high-quality ceramic capacitor type X5R or X7R with sufficient voltage ratings
are recommended. To compensate the derating of ceramic capacitors, a voltage rating of twice the maximum
input voltage is recommended. The bulk capacitance selection depends upon a number of factors: long leads
from the automotive battery to the IN pin of TPS2583x-Q1, cold or warm engine crank requirements, etc. The
bulk capacitor is used to dampen voltage spike due to the lead inductance of the cable or the trace. For this
design, one 10 μF, 50 V, X7R ceramic capacitors are used. A 0.1 μF for high-frequency filtering and place it as
close as possible to the device pins. Consider adding additional bulk capacitance for operation through low VIN
warm-crank profiles is required by the vehicle OEM.
11.2.2.6
Bootstrap Capacitor Selection
Every TPS2583x-Q1 design requires a bootstrap capacitor (CBOOT). The recommended capacitor is 0.1 μF and
rated 10 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap
capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.
11.2.2.7 VCC Capacitor Selection
The VCC pin is the output of an internal LDO for TPS2583x. The LDO supplies gate charge to the LS buck
switch and is the supply to the digital state-machine and analog USB circuitry. To insure stability of the device,
place a minimum of 2.2 μF, 10 V, X7R capacitor from this pin to ground. In addition a 0.1-μF high frequency
decoupling capacitor is highly recommended.
11.2.2.8 Enable and Undervoltage Lockout Set-Point
The system enable and undervoltage lockout (UVLO) is adjusted using the external voltage divider network of
RENT and RENB. The EN/UVLO has two thresholds, one for power up when the input voltage is rising and one for
power down or brown outs when the input voltage is falling. The following equations can be used to determine
the VIN(ON) and VIN(OFF) levels.
(13)
(14)
VIN(ON) = 6 V (user choice)
RENB = 5 kΩ (user choice)
RENT = [(VIN(ON) / VEN/UVLO_H) - 1] × RENB
RENT = [(6 V / 1.2 V) - 1] × 5 kΩ = 20 kΩ. Choose standard 20 kΩ.
Therefore VIN(OFF) = 6 V × [1 - (0.09 V / 1.2 V)] = 5.55 V
11.2.2.9 Current Limit Set-Point
The TPS2583x-Q1 can provide an accurate current limit to protect the USB port from overload based upon the
values of RSNS, RSET and RILIMIT. The design process is the same regardless of whether buck average current
limiting or external NFET current limiting is chosen. The only difference is the current limit threshold voltage on
the ILIMIT pin.
• RSNS is the current sense resistor. The recommended voltage across the RSNS undercurrent limit should be
approximately 50 mV as a compromise between accuracy and power dissipation. For example, if current
limiting is desired for IOUT(MAX) ≥ 3.3 A, then RSNS = 0.05 V / 3.3 A = 0.01515 Ω. Choose a standard value of
15 mΩ.
• RSET determines the input current to the transconductance amplifier and current mirror. The amplifier
balances the voltage to be equal to that across RSNS. Choose a RSET value to produce an ISET current
between 75 - 180 µA at the desired IOUT(MAX). Considering 50 mV across RSET, a value of 300 Ω will provide
approximately 166 µA of ISET current to the amplifier and mirror circuit. Care should be taken to limit the ISET
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•
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current below 200 µA to avoid saturating the internal amplifier circuit.
Buck average current limiting occurs when VILIMIT = 1 V. RILIMIT is calculated as 1 V x 300 Ω / [ 0.5 x (3.3 A x
15 mΩ + 0.7 mV) ] = 11.95 kΩ. A standard 11.8 kΩ value is chosen.
11.2.2.10 Cable Compensation Set-Point
From Table 11 the total cable resistance to be accounted for is 300 mΩ.
1. From Current Limit Set-Point RSNS and RSET have been determined as 15 mΩ and 300 Ω, respectively.
2. RWIRE = 300 mΩ
3. ΔVOUT = (RSNS + RWIRE) × IBUS = (0.015 + 0.3) × 3 = 1.0395 V
4. RIMON = (ΔVOUT × RSET × 2) / (IBUS × RSNS) = (1.0395 × 300 × 2) / (3.3 × 0.015) = 12.6 kΩ. A standard value
of 12.7 kΩ is selected.
11.2.2.11 LD_DET, POL, and FAULT Resistor Selection
The LD_DET, POL, and FAULT pins are open-drain output flags. They can be connected to the TPS2583x-Q1
VCC pin with 100-kΩ resistors, or connected to another suitable I/O voltage supply if actively monitored by a
USB HUB or MCU. They can be left floating if unused.
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11.2.3 Application Curves
100
100
95
90
90
80
Efficiency (%)
Efficiency (%)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF, COUT_CSN
= 0.1 µF, CBUS = 1 µF, TA = 25 °C.
85
80
75
70
60
0.1
1
OUT Current (A)
VOUT = 5.1 V
60
50
40
VIN = 6V
VIN = 13.5V
VIN = 18V
VIN = 36V
65
70
VIN = 8.5V
VIN = 13.5V
VIN = 18V
30
20
0.1
4
1
OUT Current (A)
A001
fSW = 400 kHz
VOUT = 5.1 V
100
100
95
90
90
80
85
80
75
70
60
0.1
1
OUT Current (A)
RSENS = 15 mΩ
70
60
50
VIN = 8.5V
VIN = 13.5V
VIN = 18V
30
20
0.1
4
fSW = 400 kHz
RSENS = 15 mΩ
4
A004
fSW = 2100 kHz
L = 2.2uH
Figure 78. Efficiency With Sense Resistor
0.4
0.1
VIN = 6V
VIN = 13.5V
VIN = 18V
Load = 1A
Load = 2A
Load = 3A
0.08
Line Regulation (%)
0.3
Load Regulation (%)
1
OUT Current (A)
A003
Figure 77. Efficiency With Sense Resistor
0.2
0.1
0
-0.1
0.06
0.04
0.02
0
-0.02
-0.2
-0.04
0
0.5
VOUT = 5.1 V
1
1.5
2
OUT Current (A)
fSW = 400 kHz
Figure 79. Load Regulation
56
L = 2.2uH
40
VIN = 6V
VIN = 13.5V
VIN = 18V
VIN = 36V
65
A002
fSW = 2100 kHz
Figure 76. Buck Only Efficiency
Efficiency (%)
Efficiency (%)
Figure 75. Buck Only Efficiency
4
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2.5
3
6
9
12
15
A005
VOUT = 5.1 V
18
21
24
VIN Voltage (V)
27
30
33
36
A006
fSW = 400 kHz
Figure 80. Line Regulation
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TPS25830-Q1 TPS25831-Q1
TPS25830-Q1, TPS25831-Q1
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SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF, COUT_CSN
= 0.1 µF, CBUS = 1 µF, TA = 25 °C.
VBUS,
200mV/Div
VBUS,
200mV/Div
Load Current,
2A/Div
Load Current,
2A/Div
200us/Div
ILOAD = 0 A to 3.5 A
200us/Div
RIMON = 0 Ω
Figure 81. Load Transient Without Cable Compensation
ILOAD = 0.75 A to 2.25 A
RIMON = 0 Ω
Figure 82. Load Transient Without Cable Compensation
VBUS,
500mV/Div
VBUS,
500mV/Div
Load Current,
2A/Div
Load Current,
2A/Div
2ms/Div
2ms/Div
ILOAD = 0 A to 3.5 A
RIMON = 13 kΩ
Figure 83. Load Transient With Cable Compensation
ILOAD = 0.75 A to 2.25 A
RIMON = 13 kΩ
Figure 84. Load Transient With Cable Compensation
6
SW,
5V/Div
VBUS Voltage (V)
5.5
5
4.5
4
VBUS,
10mV/Div (AC coupled)
Load = 0A
Load = 1A
Load = 2A
Load = 3A
Load = 3.5A
3.5
3
4
4.5
5
5.5
6
Input Voltage (V)
6.5
7
Figure 85. Dropout Characteristic
7.5
A007
2us/Div
RIMON = 13 kΩ
Figure 86. 3.5-A Output Ripple
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Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF, COUT_CSN
= 0.1 µF, CBUS = 1 µF, TA = 25 °C.
SW,
5V/Div
SW,
5V/Div
VBUS,
10mV/Div (AC coupled)
VBUS,
10mV/Div (AC coupled)
2us/Div
2us/Div
RIMON = 13 kΩ
RIMON = 13 kΩ
Figure 87. 100-mA Output Ripple
Figure 88. No Load Output Ripple
EN,
5V/Div
EN,
5V/Div
VIN
5V/Div
VIN
5V/Div
VBUS,
5V/Div
VBUS,
5V/Div
VCC,
5V/Div
VCC,
5V/Div
10ms/Div
40ms/Div
VIN = 0 V to 13.5 V
CC1 = Rd
ILOAD = 3 A
VIN = 13.5 V to 0 V
Figure 89. Startup Relate to VIN
CC1 = Rd
ILOAD = 3 A
Figure 90. Shutdown Relate to VIN
EN, 5V/Div
EN,
5V/Div
VIN
5V/Div
VIN, 5V/Div
VBUS, 2V/Div
VBUS,
2V/Div
VCC, 2V/Div
VCC,
5V/Div
40ms/Div
EN = 0 V to 5 V
CC1 = Rd
Figure 91. Startup Relate to EN
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ILOAD = 3 A
40ms/Div
EN = 5 V to 0 V
CC1 = Rd
ILOAD = 3 A
Figure 92. Shutdown Relate to EN
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Product Folder Links: TPS25830-Q1 TPS25831-Q1
TPS25830-Q1, TPS25831-Q1
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SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF, COUT_CSN
= 0.1 µF, CBUS = 1 µF, TA = 25 °C.
VIN, 10V/Div
VIN, 10V/Div
VBUS, 2V/Div
Rd assert
Rd desert
VBUS, 2V/Div
CC1, 2V/Div
CC1, 2V/Div
CC2, 2V/Div
CC2, 2V/Div
40ms/Div
CC1 = Open to Rd
CC2 = Open
ILOAD = 3 A
20ms/Div
CC1 = Rd to Open
Figure 93. Rd Assert
CC2 = Open
ILOAD = 3 A
Figure 94. Rd Desert
EN, 10V/Div
EN, 10V/Div
FAULT, 2V/Div
Short removed
FAULT, 2V/Div
VBUS, 2V/Div
VBUS, 2V/Div
Load Current,
5A/Div
100ms/Div
EN to High
VBUS = GND
Load Current, 5A/Div
RLIMIT = 13 kΩ
Figure 95. Enable Into Short Without External FET
40ms/Div
RLIMIT = 13 kΩ
Figure 96. Short Circuit Recovery Without External FET
EN, 10V/Div
EN, 10V/Div
FAULT, 2V/Div
FAULT, 2V/Div
VBUS, 1V/Div
1Ÿ load removed
Load Current, 2A/Div
VBUS, 1V/Div
Load Current, 2A/Div
EN to High
100ms/Div
VBUS = GND
100ms/Div
RLIMIT = 13 kΩ
Figure 97. Enable Into 1-Ω Load Without External FET
RLIMIT = 13 kΩ
Figure 98. 1-Ω Load Recovery Without External FET
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Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF, COUT_CSN
= 0.1 µF, CBUS = 1 µF, TA = 25 °C.
EN, 10V/Div
EN, 10V/Div
FAULT, 2V/Div
Short removed
FAULT, 2V/Div
VBUS, 2V/Div
VBUS, 2V/Div
Load Current, 2A/Div
Load Current, 2A/Div
100ms/Div
EN to High
VBUS = GND
100ms/Div
RLIMIT = 6.8 kΩ
RLIMIT = 6.8 kΩ
Figure 99. Enable Into Short With External FET
EN, 10V/Div
Figure 100. Short Circuit Recovery With External FET
EN, 10V/Div
FAULT, 2V/Div
FAULT, 2V/Div
VBUS, 2V/Div
VBUS hot short to
GND
VBUS, 2V/Div
VBUS hot short to
GND
Load Current, 2A/Div
Load Current, 5A/Div
1ms/Div
2ms/Div
RLIMIT = 13 kΩ
Figure 101. VBUS Hot Short to GND Without External FET
RLIMIT = 6.8 kΩ
Figure 102. VBUS Hot Short to GND With External FET
FAULT, 5V/Div
FAULT, 2V/Div
CC2, 2V/Div
VBUS, 2V/Div
VBUS short to 18V BAT
CC2 hot short to GND
VBUS, 5V/Div
CC2 Current,
200mA/Div
2ms/Div
2ms/Div
CC1 = Rd
CC2 = Ra
Figure 103. CC2 Hot Short to GND
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CC1 = Rd
CC2 = OPEN
NO LOAD
Figure 104. VBUS Short to BAT With External FET
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Product Folder Links: TPS25830-Q1 TPS25831-Q1
TPS25830-Q1, TPS25831-Q1
www.ti.com
SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF, COUT_CSN
= 0.1 µF, CBUS = 1 µF, TA = 25 °C.
FAULT, 2V/Div
FAULT, 2V/Div
VBUS, 5V/Div
CC short to 18V BAT
CC2, 5V/Div
20ms/Div
CC1 = Rd
CC2 = OPEN
NO LOAD
2ms/Div
CC1 = Rd
Figure 105. VBUS Short to BAT Recovery With External
FET
CC2 = OPEN
NO LOAD
Figure 106. CC Short to BAT
FAULT, 2V/Div
FAULT, 2V/Div
CC2, 5V/Div
DP short to 18V BAT
DP, 5V/Div
2ms/Div
2ms/Div
CC1 = Rd
CC2 = OPEN
NO LOAD
CC1 = Rd
Figure 107. CC Short to BAT Recovery
FAULT, 2V/Div
CC2 = OPEN
NO LOAD
Figure 108. DP Short to BAT
VNTC, 2V/Div
VNTC > VWARN_HIGH
VBUS, 5V/Div
THERM_WARN, 5V/Div
DP, 5V/Div
CC1, 2V/Div
SW, 10V/Div
20ms/Div
CC1 = Rd
CC2 = OPEN
NO LOAD
Figure 109. DP Short to BAT Recovery
100ms/Div
VNTC = 0 V to 3 V
CC1 = Rd
CC2 = OPEN
Figure 110. Thermal Sensing With NTC Behavior 1
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Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF, COUT_CSN
= 0.1 µF, CBUS = 1 µF, TA = 25 °C.
VNTC, 2V/Div
VNTC > VSD_HIGH
THERM_WARN, 5V/Div
CC1, 2V/Div
SW, 10V/Div
100ms/Div
VNTC = 0 V to 4 V
CC1 = Rd
CC2 = OPEN
Figure 111. Thermal Sensing With NTC Behavior 2
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TPS25830-Q1, TPS25831-Q1
www.ti.com
SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
12 Power Supply Recommendations
The TPS2583x-Q1 is designed to operate from an input voltage supply range between 6 V and 36 V. This input
supply should be able to withstand the maximum input current and maintain a stable voltage. The resistance of
the input supply rail should be low enough that an input current transient does not cause a high enough drop at
the TPS2583x-Q1 supply voltage that can cause a false UVLO fault triggering and system reset. If the input
supply is located more than a few inches from the TPS2583x, additional bulk capacitance may be required in
addition to the ceramic input capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF
electrolytic capacitor is a typical choice.
13 Layout
13.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. Input capacitor: The input bypass capacitor CIN must be placed as close as possible to the IN and PGND
pins. Grounding for both the input and output capacitors should consist of localized top side planes that
connect to the PGND pin and PAD.
2. VCC bypass capacitor: Place bypass capacitors for VCC close to the VCC pin and ground the bypass
capacitor to device ground.
3. Use a ground plane in one of the middle layers as noise shielding and heat dissipation path.
4. Connect the thermal pad to the ground plane. The QFN package has a thermal pad (PAD) connection that
must be soldered down to the PCB ground plane. This pad acts as a heat-sink connection. The integrity of
this solder connection has a direct bearing on the total effective RθJA of the application.
5. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
6. Provide enough PCB area for proper heat sinking. As stated in the section, enough copper area must be
used to ensure a low RθJA, commensurate with the maximum load current and ambient temperature. Make
the top and bottom PCB layers with two-ounce copper; and no less than one ounce. Use an array of heatsinking vias to connect the thermal pad (PAD) to the ground plane on the bottom PCB layer. If the PCB
design uses multiple copper layers (recommended), thermal vias can also be connected to the inner layer
heat-spreading ground planes.
7. The SW pin connecting to the inductor should be as short as possible, and just wide enough to carry the load
current without excessive heating. Short, thick traces or copper pours (shapes) should be used for high
current conduction path to minimize parasitic resistance. The output capacitors should be placed close to the
VOUT end of the inductor and closely grounded to PGND pin and exposed PAD.
8. Sense and Set Resistors: The RSNS and RSET resistors connect to the current sense amplifier inputs at the
CSP and CSN/OUT pins. For best current limit and cable compensation accuracy; short, parallel traces give
the best performance. If it is not possible to place RSNS and RSET near the CSP and CSN/OUT pins, it is
recommended that the traces from sense resistor be routed in parallel and of similar lengths. A small filter
capacitor in parallel with RSNS and a small filter capacitor from CSN/OUT to AGND help decouple noise.
9. RILIMIT and RIMON resistors should be placed as close as possible to the ILIMIT and IMON pins and
connected to AGND. If needed, these components can be placed on the bottom side of the PCB with signals
routed through small vias.
10. Trace routing of DP_IN, DM_IN, DP_OUT, and DM_OUT: Route these traces as micro-strips with nominal
differential impedance of 90 Ω. Minimize the use of vias in the high-speed data lines. Keep the reference
GND plane devoid from cuts or splits above the differential pairs to prevent impedance discontinuities.
11. Keep the CC lines close to the same length. Do not create stubs or test points on the CC lines.
12. POL, LD_DET, FAULT and THERM_WARN (TPS25831-Q1) are open-drain outputs. They can be
connected to the VCC pin via pull-up resistors. Suggested resistor value is 100 kΩ.
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13.2 Ground Plane and Thermal Considerations
It is recommended to use one of the middle layers as a solid ground plane. Ground plane provides shielding for
sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. The PGND pins
should be connected to the ground plane using vias right next to the bypass capacitors. PGND pin is connected
to the source of the internal LS switch. The PGND net contains noise at switching frequency and may bounce
due to load variations. PGND trace, as well as VIN and SW traces, should be constrained to one side of the
ground plane. The other side of the ground plane contains much less noise and should be used for sensitive
routes. AGND and PGND should be connected under the QFN package PAD.
It is recommended to provide adequate device heat sinking by utilizing the PAD of the IC as the primary thermal
path. Use a minimum 2 row, 2 column "+" array of 12 mil thermal vias to connect the PAD to the system ground
plane heat sink. The vias should be evenly distributed under the PAD. Use as much copper as possible, for
system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the
copper thickness for the four layers, starting from the top of, 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with
enough copper thickness provide low current conduction impedance, proper shielding and lower thermal
resistance.
The thermal characteristics of the TPS2583x-Q1 are specified using the parameter θJA, which characterize the
junction temperature of silicon to the ambient temperature in a specific system. Although the value of θJA is
dependent on many variables, it still can be used to approximate the operating junction temperature of the
device. To obtain an estimate of the device junction temperature, one may use the following relationship:
TJ = PD x θJA + TA
(15)
where
TJ = Junction temperature in °C
PD = VIN x IIN x (1 - Efficiency) - 1.1 x IOUT2 x DCR in Watt
DCR = Inductor DC parasitic resistance in Ω
θJA = Junction to ambient thermal resistance of the device in °C/W
TA = Ambient temperature in °C
θJA is highly related to PCB size and layout, as well as environmental factors such as heat sinking and air flow.
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SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
13.3 Layout Example
INDUCTOR
PGND
PGND
VIN
31
30
27
28
26
25
A2
24
FAULT
2
23
LD_DET
POL
21
VCC
CTRL1
5
20
CC1
CTRL2
6
19
CC2
DP_OUT
7
18
DP_IN
DM_OUT
8
17
DM_IN
14
COUT
PGND
CFILT
CFILT
CFILT
PGND
A3
16
15
USB
AGND
13
BUS
12
CSP
IMON
11
CSN/OUT
10
ILIM
9
RT
22
4
LS_GD
3
EN
A4
COUT
PGND
29
CVCC
IN
32
1
CVCC
A1
SW
BT
CHF
COUT
COUT
CIN
RSET
RSNS
PGND
VBUS
PGND
INNER GND PLANE
Top Trace/Plane
Inner GND Plane
Top
VIA to Signal Layer
VIA to GND Planes
VIA to Strap
Inner GND Plane
Signal Layers
Power and GND
Figure 112. Layout
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SLVSDP6D – JUNE 2018 – REVISED SEPTEMBER 2019
www.ti.com
14 Device and Documentation Support
14.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 13. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS25830-Q1
Click here
Click here
Click here
Click here
Click here
TPS25831-Q1
Click here
Click here
Click here
Click here
Click here
14.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
14.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
14.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
14.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
14.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS25830QWRHBRQ1
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
T25830
TPS25830QWRHBTQ1
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
T25830
TPS25831QWRHBRQ1
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
T25831
TPS25831QWRHBTQ1
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
T25831
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS25830QWRHBRQ1
VQFN
RHB
32
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
5.25
5.25
1.1
8.0
12.0
Q2
TPS25830QWRHBTQ1
VQFN
RHB
32
250
180.0
12.4
5.25
5.25
1.1
8.0
12.0
Q2
TPS25831QWRHBRQ1
VQFN
RHB
32
3000
330.0
12.4
5.25
5.25
1.1
8.0
12.0
Q2
TPS25831QWRHBTQ1
VQFN
RHB
32
250
180.0
12.4
5.25
5.25
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS25830QWRHBRQ1
VQFN
RHB
32
3000
370.0
355.0
55.0
TPS25830QWRHBTQ1
VQFN
RHB
32
250
195.0
200.0
45.0
TPS25831QWRHBRQ1
VQFN
RHB
32
3000
370.0
355.0
55.0
TPS25831QWRHBTQ1
VQFN
RHB
32
250
195.0
200.0
45.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
5 x 5, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
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PACKAGE OUTLINE
RHB0032R
VQFN - 1 mm max height
SCALE 2.500
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
0.5
0.3
0.3
0.2
PIN 1 INDEX AREA
DETAIL
5.1
4.9
OPTIONAL TERMINAL
TYPICAL
0.1 MIN
(0.05)
SECTION A-A
A-A 20.000
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
3.7
0.1
8X (0.2)
2X 3.5
A2
9
16
(0.2) TYP
A3
28X 0.5
8
17
2X
3.5
33
A
8X (0.375)
A SYMM
EXPOSED
THERMAL PAD
SEE TERMINAL
DETAIL
1
24
A4
A1
PIN 1 ID
(OPTIONAL)
32
SYMM
25
0.5
32X
0.3
32X
0.3
0.2
0.1
0.05
C A B
4223771/A 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHB0032R
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.7)
(R0.05)
TYP
32X (0.6)
SYMM
8X (0.575)
25
32
8X (0.2)
A4
A1
32X (0.25)
1
24
4X
(0.97)
( 0.2) TYP
VIA
33
SYMM
(2.225)
TYP
4X
(1.26)
(4.8)
28X (0.5)
8
17
A2
A3
9
4X
(0.97)
4X (1.26)
16
(2.225) TYP
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223771/A 06/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHB0032R
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.26 TYP)
9X ( 1.06)
8X (0.575)
32X (0.6)
32
25
8X (0.2)
32X (0.25)
33
1
24
(1.26)
TYP
(R0.05) TYP
SYMM
(4.8)
(2.225)
TYP
28X (0.5)
8
17
METAL
TYP
9
16
SYMM
(2.225) TYP
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33
74% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:18X
4223771/A 06/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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