Texas Instruments | PCA9544A Low Voltage 4-Channel I2C and SMBus Multiplexer With Interrupt Logic (Rev. F) | Datasheet | Texas Instruments PCA9544A Low Voltage 4-Channel I2C and SMBus Multiplexer With Interrupt Logic (Rev. F) Datasheet

Texas Instruments PCA9544A Low Voltage 4-Channel I2C and SMBus Multiplexer With Interrupt Logic (Rev. F) Datasheet
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PCA9544A
SCPS146F – OCTOBER 2005 – REVISED AUGUST 2019
PCA9544A Low Voltage 4-Channel I2C and SMBus Multiplexer With Interrupt Logic
1 Features
3 Description
•
•
•
•
•
The PCA9544A is a 4-channel, bidirectional
translating multiplexer controlled via the I2C bus. The
SCL/SDA upstream pair fans out to four downstream
pairs, or channels. One SCL/SDA pair can be
selected at a time, and this is determined by the
contents of the programmable control register. Four
interrupt inputs (INT3–INT0), one for each of the
downstream pairs, are provided. One interrupt output
(INT) acts as an AND of the four interrupt inputs.
1
•
•
•
•
•
•
•
•
•
•
•
•
1-of-4 Bidirectional translating switches
I2C Bus and SMBus compatible
Four active-low interrupt inputs
Active-low interrupt output
Three address pins, allowing up to eight devices
on the I2C Bus
Channel selection via I2C Bus
Power up with all switch channels deselected
Low RON switches
Allows voltage-level translation between 1.8-V,
2.5-V, 3.3-V, and 5-V Buses
No glitch on power up
Supports hot insertion
Low standby current
Operating power-supply voltage range of
2.3 V to 5.5 V
5.5-V Tolerant inputs
0 to 400-kHz Clock frequency
Latch-up performance exceeds 100 mA Per JESD
78
ESD Protection exceeds JESD 22
– 2000-V Human-body model (A114-A)
– 200-V Machine model (A115-A)
– 1000-V Charged-device model (C101)
2 Applications
•
•
•
•
Servers
Routers (Telecom Switching Equipment)
Factory Automation
Products With I2C Slave Address Conflicts (For
Example, Multiple, Identical Temp Sensors)
A power-on reset function puts the registers in their
default state and initializes the I2C state machine,
with no channel selected.
The pass gates of the switches are constructed such
that the VCC pin can be used to limit the maximum
high voltage, which will be passed by the PCA9544A.
This allows the use of different bus voltages on each
pair, so that 1.8-V, 2.5-V, or 3.3-V parts can
communicate with 5-V parts, without any additional
protection. External pull-up resistors pull the bus up
to the desired voltage level for each channel. All I/O
pins are 5-V tolerant.
Device Information(1)
PART NUMBER
PCA9544A
PACKAGE
BODY SIZE (NOM)
TVSOP (DGV) (20)
5.00 mm x 4.40 mm
SOIC (DW) (20)
12.8 mm x 7.50 mm
TSSOP (PW) (20)
6.50 mm × 4.40 mm
VQFN (RGY) (20)
4.50 mm x 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
Channel 0
I2C or SMBus
Master
SDA
SCL
INT
VCC
SD0
SC0
INT0
SD1
SC1
INT1
(e.g. µProcessor)
PCA9544A
A0
A1
A2
GND
SD2
SC2
INT2
SD3
SC3
INT3
Slaves A0, A1...AN
Channel 1
Slaves B0, B1...BN
Channel 2
Slaves B0, B1...BN
Channel 3
Slaves B0, B1...BN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCA9544A
SCPS146F – OCTOBER 2005 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
6
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Interface Timing Requirements...........................
Switching Characteristics ..........................................
Interrupt Timing Requirements .................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 10
8.5 Programming .......................................................... 10
8.6 Register Map........................................................... 12
9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application .................................................. 15
10 Power Supply Recommendations ..................... 18
10.1 Power-On Reset Errata......................................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
Changes from Revision E (June 2014) to Revision F
Page
•
Changed text From: "The PCA9544A is a quad bidirectional translating switch" To: "The PCA9544A is a 4-channel,
bidirectional translating multiplexer" in the Description .......................................................................................................... 1
•
Changed the Device Information table ................................................................................................................................... 1
•
Deleted the RGW, GQN, and ZQN packages from the Pin Configuration and Functions section......................................... 3
•
Moved Tstg to the Absolute Maximum Ratings ....................................................................................................................... 4
•
Changed the Handling Ratings table to ESD Ratings table ................................................................................................... 4
•
Added the Thermal Information table ..................................................................................................................................... 4
•
Changed the first paragraph of the Overview section ............................................................................................................ 8
•
Changed text From: "bidirectional translating switch" To: "bidirectional translating multiplexer" ......................................... 10
•
Changed text from: "One or several SCn/SDn downstream pairs or channels, are selected" To: "Only one SCn/SDn
downstream pair, or channel, can be selected" in the Control Register Definition section.................................................. 13
•
Deleted sentence: "If multiple switches will be enabled.." from the second paragraph of the Application Information
section .................................................................................................................................................................................. 15
Changes from Revision D (February 2008) to Revision E
•
2
Page
Added Power-On Reset Errata section. .............................................................................................................................. 18
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SCPS146F – OCTOBER 2005 – REVISED AUGUST 2019
5 Pin Configuration and Functions
DGV, DW, or PW Package
TVSOP, SOIC, TSSOP (20 Pins)
Top View
2
19
SDA
A2
3
18
SCL
INT0
4
17
INT
SD0
5
16
SC3
SC0
6
15
SD3
INT1
7
14
INT3
SD1
8
13
SC2
9
12
SD2
GND
10
11
INT2
A1
2
19
SDA
A2
3
18
SCL
INT0
4
17
INT
SD0
5
16
SC3
Th ermal
Pad
SC0
6
15
SD3
INT1
7
14
INT3
SD1
8
13
SC2
SC1
9
12
SD2
10
SC1
VCC
A1
20
VCC
GND
No t to scale
11
20
INT2
1
A0
A0
1
RGY Package
VQFN (20 Pins)
Top View
No t to scale
Pin Functions
PIN
(1)
FUNCTION
NO.
NAME
1
A0
Address input 0. Connect directly to VCC or ground.
2
A1
Address input 1. Connect directly to VCC or ground.
3
A2
Address input 2. Connect directly to VCC or ground.
4
INT0
Active-low interrupt input 0. Connect to VDPU0 (1) through a pull-up resistor.
5
SD0
Serial data 0. Connect to VDPU0 (1) through a pull-up resistor.
6
SC0
Serial clock 0. Connect to VDPU0 (1) through a pull-up resistor.
7
INT1
Active-low interrupt input 1. Connect to VDPU1 (1) through a pull-up resistor.
8
SD1
Serial data 1. Connect to VDPU1 (1) through a pull-up resistor.
9
SC1
Serial clock 1. Connect to VDPU1 (1) through a pull-up resistor.
10
GND
Ground
11
INT2
Active-low interrupt input 2. Connect to VDPU2 (1) through a pull-up resistor.
12
SD2
Serial data 2. Connect to VDPU2 (1) through a pull-up resistor.
13
SC2
Serial clock 2. Connect to VDPU2 (1) through a pull-up resistor.
14
INT3
Active-low interrupt input 3. Connect to VDPU3 (1) through a pull-up resistor.
15
SD3
Serial data 3. Connect to VDPU3 (1) through a pull-up resistor.
16
SC3
Serial clock 3. Connect to VDPU3 (1) through a pull-up resistor.
17
INT
Active-low interrupt output. Connect to VDPUM (1) through a pull-up resistor.
18
SCL
Serial clock line. Connect to VDPUM (1) through a pull-up resistor.
19
SDA
Serial data line. Connect to VDPUM (1) through a pull-up resistor.
20
VCC
Supply power
VDPUX is the pull-up reference voltage for the associated data line. VDPUM is the master I2C reference voltage while VDPU0-VDPU3 are the
slave channel reference voltages.
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SCPS146F – OCTOBER 2005 – REVISED AUGUST 2019
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
7
VI
Input voltage range (2)
–0.5
7
II
Input current
IO
Output current
UNIT
V
V
±20
mA
±25
mA
Continuous current through VCC
±100
mA
Continuous current through GND
±100
mA
400
mW
Ptot
Total power dissipation
TA
Operating free-air temperature range
–40
85
°C
Tstg
Storage temperature range
–60
150
°C
(1)
(2)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
MIN
V(ESD)
(1)
(2)
Electrostatic discharge
MAX
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions (1)
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
(1)
MIN
MAX
2.3
5.5
SCL, SDA
0.7 × VCC
6
A2–A0, INT3–INT0
0.7 × VCC
VCC + 0.5
SCL, SDA
–0.5
0.3 × VCC
A2–A0, INT3–INT0
–0.5
0.3 × VCC
–40
85
UNIT
V
V
V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs.
6.4 Thermal Information
PCA9544A
THERMAL METRIC (1)
DGV
DW
PW
RGY
20 PINS
20 PINS
20 PINS
20 PINS
37
UNIT
RθJA
Junction-to-ambient thermal resistance
92
58
96.5
RθJC(top)
Junction-to-case (top) thermal resistance
43.9
41.9
36.2
°C/W
RθJB
Junction-to-board thermal resistance
64.5
40.3
48.2
°C/W
ψJT
Junction-to-top characterization parameter
4.2
18.1
3.6
°C/W
ψJB
Junction-to-board characterization parameter
63.6
40
47.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VPOR
Power-on reset voltage
TEST CONDITIONS
(2)
No load,
VI = VCC or GND
VCC
MIN TYP (1)
MAX
VPOR
1.7
2.1
5V
3.6
4.5 V to 5.5 V
Vpass
Switch output voltage
VSWin = VCC,
ISWout = –100 μA
2.6
3.3 V
3 V to 3.6 V
IOH
INT
VO = VCC
1.6
SCL, SDA
IOL
VOL = 0.6 V
INT
2.8
2.3 V to 5.5 V
VOL = 0.4 V
2
10
3
7
6
10
3
7
SCL, SDA
A2–A0
VI = VCC or GND
ICC
±1
fSCL = 100 kHz
VI = VCC or GND,
VI = GND,
IO = 0
IO = 0
Standby mode
High inputs
INT3–INT0
Supply-current
change
SCL, SDA
A2–A0
Ci
INT3–INT0
Cio(OFF)
(3)
RON
(1)
(2)
(3)
μA
±1
Low inputs
ΔICC
mA
±1
2.3 V to 5.5 V
INT3–INT0
Operating mode
μA
±1
SC3–SC0, SD3–SD0
II
V
1.5
1.1
2.3 V to 5.5 V
VOL = 0.4 V
V
4.5
1.9
2.5 V
2.3 V to 2.7 V
UNIT
SCL, SDA
SC3–SC0, SD3–SD0
Switch-on resistance
VI = VCC,
IO = 0
5.5 V
3
12
3.6 V
3
11
2.7 V
3
10
5.5 V
0.3
1
3.6 V
0.1
1
2.7 V
0.1
1
5.5 V
0.3
1
3.6 V
0.1
1
2.7 V
0.1
1
8
15
8
15
8
15
8
15
4.5
6
4.5
6
15
19
6
8
One INT3–INT0 input at 0.6 V,
Other inputs at VCC or GND
One INT3–INT0 input at VCC – 0.6 V,
Other inputs at VCC or GND
SCL or SDA input at 0.6 V,
Other inputs at VCC or GND
2.3 V to 5.5 V
μA
SCL or SDA inputs at VCC – 0.6 V,
Other inputs at VCC or GND
VI = VCC or GND
2.3 V to 5.5 V
VI = VCC or GND,
Switch OFF
VO = 0.4 V,
IO = 15 mA
VO = 0.4 V,
IO = 10 mA
μA
2.3 V to 5.5 V
4.5 V to 5.5 V
4
9
16
3 V to 3.6 V
5
11
20
2.3 V to 2.7 V
7
16
45
pF
pF
Ω
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC), TA = 25°C.
The power-on reset circuit resets the I2C bus logic with VCC < VPOR. VCC must be lowered to 0.2 V to reset the device.
Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
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6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
STANDARD-MODE
I2C BUS
MIN
MAX
100
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
2
tscl
I C clock low time
tsp
I2C spike time
tsds
I2C serial-data setup time
FAST-MODE
I2C BUS
MAX
0
400
0.6
4.7
100
(1)
(1)
0
μs
50
250
ns
ns
tsdh
I C serial-data hold time
ticr
I2C input rise time
1000 20 + 0.1Cb
(2)
300
ns
ticf
I2C input fall time
300 20 + 0.1Cb
(2)
300
ns
tocf
I2C output fall time (10-pF to 400-pF bus)
300 20 + 0.1Cb
(2)
300
ns
2
0
kHz
μs
1.3
50
2
UNIT
MIN
μs
tbuf
I C bus free time between stop and start
4.7
1.3
μs
tsts
I2C start or repeated start condition setup
4.7
0.6
μs
tsth
I2C start or repeated start condition hold
4
0.6
μs
2
tsps
I C stop condition setup
tvdL(Data)
Valid-data time (high to low) (3)
SCL low to SDA output low valid
tvdH(Data)
Valid-data time (low to high) (3)
SCL low to SDA output high valid
tvd(ack)
Valid-data time of ACK condition
ACK signal from SCL low
to SDA output low
2
Cb
(1)
(2)
(3)
4
I C bus capacitive load
0.6
μs
1
1
μs
0.6
0.6
μs
1
1
μs
400
400
pF
A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL signal), in order
to bridge the undefined region of the falling edge of SCL.
Cb = total bus capacitance of one bus line in pF
Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 1).
6.7 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
(1)
Propagation delay time
RON = 20 Ω, CL = 15 pF
RON = 20 Ω, CL = 50 pF
FROM
(INPUT)
TO
(OUTPUT)
SDA or SCL
SDn or SCn
MIN
MAX
0.3
1
UNIT
ns
tiv
Interrupt valid time (2)
INTn
INT
4
μs
tir
Interrupt reset delay time (2)
INTn
INT
2
μs
(1)
(2)
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
Data taken using a 4.7-kΩ pull-up resistor and 100-pF load (see Figure 2).
6.8 Interrupt Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tPWRL
Low-level pulse duration rejection of INTn inputs (1)
1
μs
tPWRH
(1)
0.5
μs
(1)
6
High-level pulse duration rejection of INTn inputs
Data taken using a 4.7-kΩ pull-up resistor and 100-pF load (see Figure 2).
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7 Parameter Measurement Information
VCC
RL = 1 kW
SDn, SCn
DUT
CL = 50 pF
(See Note A)
I2C-Port Load Configuration
Two Bytes for Complete
Device Programming
Stop
Start
Address
Address
Condition Condition
Bit 7
Bit 6
(P)
(S)
(MSB)
BYTE
Address
Bit 1
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
ACK
(A)
Stop
Condition
(P)
DESCRIPTION
I2C
1
2
address + R/W
Control register data
tscl
tsch
0.7 x VCC
SCL
tvd(ACK)
or tvdL
tvdH
ticr
ticf
tbuf
tsp
0.3 x VCC
tsts
0.7 x VCC
SDA
0.3 x VCC
ticr
ticf
tsth
tsdh
tsps
tsds
Repeat
Start
Condition
Start or Repeat
Start Condition
Stop
Condition
Voltage Waveforms
A.
CL includes probe and jig capacitance.
B.
All
input
pulses
are
supplied
PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns
C.
The outputs are measured one at a time, with one transition per measurement.
by
generators
having
the
following
characteristics:
Figure 1. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms
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Parameter Measurement Information (continued)
VCC
RL = 4.7 kW
DUT
INT
CL = 100 pF
(See Note A)
Interrupt Load Configuration
INTn
(input)
0.5 x VCC
INTn
(input)
0.5 x VCC
tir
tiv
INT
(output)
0.5 x VCC
INT
(output)
Voltage Waveforms (t iv)
0.5 x VCC
Voltage Waveforms (t ir)
A.
CL includes probe and jig capacitance.
B.
All
input
pulses
are
supplied
PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns
by
generators
having
the
following
characteristics:
Figure 2. Interrupt Load Circuit and Voltage Waveforms
8 Detailed Description
8.1 Overview
The PCA9544A is a 4-channel, bidirectional translating I2C multiplexer. The master SCL/SDA signal pair is
directed to one of the four channels of slave devices, SC0/SD0-SC3/SD3. Only one individual downstream
channel can be selected of the four channels at a time. The PCA9544A also supports interrupt signals in order
for the master to detect an interrupt on the INT output pin that can result from any of the slave devices connected
to the INT3-INT0 input pins.
The device can be reset by cycling the power supply, VCC, also known as a power-on reset (POR), which resets
the state machine and allows the PCA9544A to recover should one of the downstream I2C buses get stuck in a
low state. A POR event causes all channels to be deselected.
The connections of the I2C data path are controlled by the same I2C master device that is switched to
communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware
selectable by A0-A2 pins), a single 8-bit control register is written to or read from to determine the selected
channels and state of the interrupts.
The PCA9544A may also be used for voltage translation, allowing the use of different bus voltages on each
SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using
external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel.
8
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8.2 Functional Block Diagram
PCA9544A
SC0
SC1
SC2
SC3
SD0
SD1
6
9
13
16
5
8
12
SD2
SD3
GND
VCC
SCL
SDA
INT0
INT1
INT2
INT3
(1)
15
Switch Control Logic
10
20
Power-on Reset
18
19
1
Input Filter
4
7
11
14
2
I2C Bus Control
Interrupt Logic
3
Output
Filter
17
A0
A1
A2
INT
Pin numbers shown are for DGV, DW, PW, and RGY packages.
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8.3 Feature Description
The PCA9544A is a 4-channel, bidirectional translating multiplexer for I2C buses that supports Standard-Mode
(100 kHz) and Fast-Mode (400 kHz) operation. The PCA9544A features I2C control using a single 8-bit control
register in which the three least significant bits control the enabling and disabling of the 4 switch channels of I2C
data flow. The PCA9544A also supports interrupt signals for each slave channel and this data is held in the four
most significant bits of the control register. Depending on the application, voltage translation of the I2C bus can
also be achieved using the PCA9544A to allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts.
Additionally, in the event that communication on the I2C bus enters a fault state, the PCA9544A can be reset to
resume normal operation by means of a power-on reset which results from cycling power to the device.
8.4 Device Functional Modes
8.4.1 Power-On Reset
When power is applied to VCC, an internal power-on reset holds the PCA9544A in a reset condition until VCC has
reached VPOR. At this point, the reset condition is released, and the PCA9544A registers and I2C state machine
are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must
be lowered below VPOR to reset the device.
Refer to the Power-On Reset Errata section.
8.5 Programming
8.5.1 I2C Interface
The I2C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not
busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 3).
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 3. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the stop condition (P) (see Figure 4).
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 4. Definition of Start and Stop Conditions
10
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Programming (continued)
A device generating a message is a transmitter; a device receiving a message is the receiver. The device that
controls the message is the master, and the devices that are controlled by the master are the slaves (see
Figure 5).
SDA
SCL
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Slave
Receiver
Master
Transmitter
I2C
Multiplexer
Master
Transmitter/
Receiver
Slave
Figure 5. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the
receiver can send an ACK bit.
When a slave receiver is addressed, it must generate an acknowledge (ACK) after the reception of each byte.
Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the
SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 6). Setup and hold times
must be taken into account.
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for ACK
Start
Condition
Figure 6. Acknowledgment on the I2C Bus
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Data is transmitted to the PCA9544A control register using the write mode shown in Figure 7.
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Programming (continued)
Slave Address
SDA
S
1
1
1
0
Control Register
A2 A1 A0
Start Condition
0
A
X
X
X
X
X
B2 B1 B0
R/W ACK From Slave
A
ACK From Slave
P
Stop Condition
Figure 7. Write Control Register
Data is read from the PCA9544A control register using the read mode shown in Figure 8.
Slave Address
SDA
S
1
1
1
0
A2
Control Register
A1
Start Condition
A0
1
A
R/W
INT3 INT2 INT1 INT0
B2
0
ACK From Slave
B1
B0
NA
NACK From Master
P
Stop Condition
Figure 8. Read Control Register
8.6 Register Map
8.6.1 Control Register
8.6.1.1 Device Address
Following a start condition, the bus master must output the address of the slave it is accessing. The address of
the PCA9544A is shown in Figure 9. To conserve power, no internal pull-up resistors are incorporated on the
hardware-selectable address pins, and they must be pulled high or low.
Slave Address
1
1
1
Fixed
0
A2
A1
A0 R/W
Hardware
Selectable
Figure 9. PCA9544A Address
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.
8.6.1.2 Control Register Description
Following the successful acknowledgment of the slave address, the bus master sends a byte to the PCA9544A,
which is stored in the control register. If multiple bytes are received by the PCA9544A, it saves the last byte
received. This register can be written and read via the I2C bus.
12
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Register Map (continued)
Channel-Selection Bits
(Read/Write)
Interrupt Bits
(Read Only)
7
6
5
4
INT3 INT2 INT1 INT0
3
2
1
0
X
B2
B1
B0
Enable Bit
INT0
INT1
INT2
INT3
Figure 10. Control Register
8.6.1.3 Control Register Definition
Only one SCn/SDn downstream pair, or channel, can be selected by the contents of the control register (see
Table 1). This register is written after the PCA9544A has been addressed. The three LSBs of the control byte are
used to determine which channel is to be selected. When a channel is selected, the channel becomes active
after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in a high state
when the channel is made active, so that no false conditions are generated at the time of connection. A stop
condition always must occur right after the acknowledge cycle.
Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status) (1)
(1)
INT3
INT2
INT1
INT0
D3
B2
B1
B0
COMMAND
X
X
X
X
X
0
X
X
No channel selected
X
X
X
X
X
1
0
0
Channel 0 enabled
X
X
X
X
X
1
0
1
Channel 1 enabled
X
X
X
X
X
1
1
0
Channel 2 enabled
X
X
X
X
X
1
1
1
Channel 3 enabled
0
0
0
0
0
0
0
0
No channel selected,
power-up default state
Only one channel may be selected at a time.
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8.6.1.4 Interrupt Handling
The PCA9544A provides four interrupt inputs (one for each channel) and one open-drain interrupt output. When
an interrupt is generated by any device, it is detected by the PCA9544A, and the interrupt output is driven low.
The channel does not need to be active for detection of the interrupt. A bit also is set in the control register (see
Table 2).
Bits 4–7 of the control register correspond to channels 0–3 of the PCA9544A, respectively. Therefore, if an
interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the
control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0
causes bit 4 of the control register to be set on the read. The master then can address the PCA9544A and read
the contents of the control register to determine which channel contains the device generating the interrupt. The
master can reconfigure the PCA9544A to select this channel and locate the device generating the interrupt and
clear it. Once the device responsible for the interrupt clears, the interrupt clears.
It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to
ensure that all devices on a channel are interrogated for an interrupt.
The interrupt inputs can be used as general-purpose inputs if the interrupt function is not required.
If unused, interrupt input(s) must be connected to VCC.
Table 2. Control Register Read (Interrupt) (1)
INT3
X
X
X
0
1
(1)
14
INT2
X
X
0
1
X
INT1
X
INT0
0
D3
B2
B1
B0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
COMMAND
No interrupt on channel 0
Interrupt on channel 0
No interrupt on channel 1
Interrupt on channel 1
No interrupt on channel 2
Interrupt on channel 2
No interrupt on channel 3
Interrupt on channel 3
Several interrupts can be active at the same time. For example, INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0 means that there is no interrupt
on channels 0 and 3, and there is interrupt on channels 1 and 2.
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9 Application and Implementation
9.1 Application Information
Applications of the PCA9544A contain an I2C (or SMBus) master device and up to four I2C slave devices. The
downstream channels are ideally used to resolve I2C slave address conflicts. For example, if four identical digital
temperature sensors are needed in the application, one sensor can be connected at each channel: 0, 1, 2, and 3.
When the temperature at a specific location needs to be read, the appropriate channel can be enabled and all
other channels switched off, the data can be retrieved, and the I2C master can move on and read the next
channel.
In an application where the I2C bus contains many additional slave devices that do not result in I2C slave address
conflicts, these slave devices can be connected to any desired channel to distribute the total bus capacitance
across multiple channels.
9.2 Typical Application
A typical application of the PCA9544A contains anywhere from 1 to 5 separate data pull-up voltages, VDPUX , one
for the master device (VDPUM) and one for each of the selectable slave channels (VDPU0 – VDPU3). In the event
where the master device and all slave devices operate at the same voltage, then the pass voltage, Vpass = VDPUX.
Once the maximum Vpass is known, Vcc can be selected easily using Figure 12. In an application where voltage
translation is necessary, additional design requirements must be considered (See Design Requirements).
Figure 11 shows an application in which the PCA9544A can be used.
VDPUM = 2.3 V to 5.5 V
VCC = 2.3 V to 5.5 V
VDPU0 = 2.3 V to 5.5 V
20
SDA
I2C/SMBus
SCL
Master
VCC
19
SD0
5
SC0
6
4
SDA
18
17
SCL
INT
INT0
Channel 0
VDPU1 = 2.3 V to 5.5 V
SD1
SC1
INT1
8
9
7
VDPU2 = 2.3 V to 5.5 V
PCA9544A
SD2
SC2
Channel 1
12
13
Channel 2
11
INT2
3
A2
2
A1
1
A0
10
GND
SD3
SC3
INT3
VDPU3 = 2.3 V to 5.5 V
15
16
Channel 3
14
Figure 11. Typical Application
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Typical Application (continued)
9.2.1 Design Requirements
The pull-up resistors on the INT3-INT0 terminals in the application schematic are not required in all applications.
If the device generating the interrupt has an open-drain output structure or can be tri-stated, a pull-up resistor is
required. If the device generating the interrupt has a push-pull output structure and cannot be tri-stated, a pull-up
resistor is not required. The interrupt inputs should not be left floating in the application.
The A0 and A1 terminals are hardware selectable to control the slave address of the PCA9544A. These
terminals may be tied directly to GND or VCC in the application.
If multiple slave channels are activated simultaneously in the application, then the total IOL from SCL/SDA to
GND on the master side are the sum of the currents through all pull-up resistors, Rp.
The pass-gate transistors of the PCA9544A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another.
Figure 12 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using
data specified in the Electrical Characteristics section of this data sheet). In order for the PCA9544A to act as a
voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the
main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V
to effectively clamp the downstream bus voltages. As shown in Figure 12, Vpass(max) is 2.7 V when the PCA9544A
supply voltage is 4 V or lower, so the PCA9544A supply voltage could be set to 3.3 V. pull-up resistors then can
be used to bring the bus voltages to their appropriate levels (see Figure 11).
9.2.2 Detailed Design Procedure
Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up
resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a
function of VDPUX, VOL,(max), and IOL:
VDPUX - VOL(max)
Rp(min) =
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL =
400 kHz) and bus capacitance, Cb:
Rp(max) =
tr
0.8473 ´ Cb
(2)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for fast-mode operation. The bus
capacitance can be approximated by adding the capacitance of the PCA9544A, Cio(OFF), the capacitance of
wires/connections/traces, and the capacitance of each individual slave on a given channel. If multiple channels
are activated simultaneously, each of the slaves on all channels contributes to total bus capacitance.
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Typical Application (continued)
9.2.3 PCA9544A Application Curves
25
5
Standard-mode
Fast-mode
4.5
Maximum
20
Typical
3.5
Rp(max) (kOhm)
Vpass (V)
4
3
2.5
2
Minimum
1.5
1
2
2.5
3
3.5
4
4.5
5
10
5
5.5
0
0
VCC (V)
Space
spacespace
15
Space
spacespace
50
100
150
200
250
Cb (pF)
Standard-mode
(fSCL= 100 kHz, tr = 1 µs)
Figure 12. Pass-Gate Voltage (Vpass) vs Supply Voltage
(VCC) at Three Temperature Points
300
350
400
450
D008
Fast-mode
(fSCL= 400 kHz, tr= 300 ns)
Figure 13. Maximum Pull-up resistance (Rp(max)) vs Bus
Capacitance (Cb)
1.8
1.6
Rp(min) (kOhm)
1.4
1.2
1
0.8
0.6
0.4
VDPUX > 2V
VDPUX <= 2
0.2
0
0
0.5
1
1.5
2
2.5
3
3.5
VDPUX (V)
4
4.5
5
5.5
D009
VOL = 0.2*VDPUX, IOL = 2 mA when VDPUX ≤ 2 V
VOL = 0.4 V, IOL = 3 mA when VDPUX > 2 V
Figure 14. Minimum Pull-up Resistance (Rp(min)) vs Pull-up Reference Voltage (VDPUX)
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10 Power Supply Recommendations
The operating power-supply voltage range of the PCA9544A is 2.3 V to 5.5 V applied at the VCC pin. When the
PCA9544A is powered on for the first time or anytime the device needs to be reset by cycling the power supply,
the power-on reset requirements must be followed to ensure the I2C bus logic is initialized properly.
10.1 Power-On Reset Errata
A power-on reset condition can be missed if the VCC ramps are outside specification listed below.
10.1.1 System Impact
If ramp conditions are outside timing allowances above, POR condition can be missed, causing the device to lock
up.
11 Layout
11.1 Layout Guidelines
For PCB layout of the PCA9544A, common PCB layout practices should be followed but additional concerns
related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C
signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and terminals that
are connected to ground should have a low-impedance path to the ground plane in the form of wide polygon
pours and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the
VCC terminal, using a larger capacitor to provide additional power in the event of a short power supply glitch and
a smaller capacitor to filter out high-frequency ripple.
In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same
potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In
an application where voltage translation is required, VDPUM, VDPU0, VDPU1, VDPU2, and VDPU3 may all be on the
same layer of the board with split planes to isolate different voltage potentials.
To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn, SDn and INTn) should be a
short as possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper
weight).
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11.2 Layout Example
LEGEND
Partial Power Plane
Polygonal
Copper Pour
To I2C Master
VIA to Power Plane
VIA to GND Plane (Inner Layer)
VDPUM
By-pass/De-coupling
capacitors
A0
VCC
A1
SDA
A2
SCL
INT0
SD0
SC0
VDPU3
INT
SC3
SD3
INT3
SD1
SC2
SC1
SD2
GND
INT2
GND
VDPU2
To Slave Channel 2
To Slave Channel 1
INT1
VDPU1
VCC
PCA9544A
VDPU0
To Slave Channel 3
To Slave Channel 0
GND
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following packaging information and addendum reflect the most current data available for the designated
devices. This data is subject to change without notice and revision of this document.
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PACKAGE OPTION ADDENDUM
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7-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PCA9544ADGVR
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD544A
PCA9544ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9544A
PCA9544ADWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9544A
PCA9544APW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD544A
PCA9544APWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD544A
PCA9544APWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD544A
PCA9544APWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD544A
PCA9544APWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD544A
PCA9544ARGYR
ACTIVE
VQFN
RGY
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PD544A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
7-Nov-2019
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Nov-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
PCA9544ADGVR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TVSOP
DGV
20
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
PCA9544ADWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
PCA9544APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
PCA9544APWT
TSSOP
PW
20
250
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
PCA9544ARGYR
VQFN
RGY
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Nov-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCA9544ADGVR
TVSOP
DGV
20
2000
367.0
367.0
35.0
PCA9544ADWR
SOIC
DW
20
2000
367.0
367.0
45.0
PCA9544APWR
TSSOP
PW
20
2000
367.0
367.0
38.0
PCA9544APWT
TSSOP
PW
20
250
367.0
367.0
38.0
PCA9544ARGYR
VQFN
RGY
20
3000
367.0
367.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGY 20
VQFN - 1 mm max height
PLASTIC QUAD FGLATPACK - NO LEAD
3.5 x 4.5, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225264/A
www.ti.com
PACKAGE OUTLINE
RGY0020A
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
3.65
3.35
A
B
PIN 1 INDEX AREA
4.65
4.35
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2.05 0.1
2X 1.5
(0.2) TYP
10
11
9
EXPOSED
THERMAL PAD
12
14X 0.5
2X
3.5
21
SYMM
3.05 0.1
2
PIN 1 ID
19
20X
20
1
SYMM
0.30
0.18
0.1
0.05
0.5
20X
0.3
C A B
4225320/A 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
SYMM
1
20
20X (0.6)
2
19
20X (0.24)
(1.275)
(4.3)
21
SYMM
(3.05)
14X (0.5)
(0.775)
9
12
(R0.05) TYP
( 0.2) TYP
VIA
11
10
(0.75) TYP
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225320/A 09/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (0.92)
(R0.05) TYP
20
1
20X (0.6)
2
19
20X (0.24)
4X
(1.33)
21
SYMM
(4.3)
(0.77)
14X (0.5)
(0.56)
9
12
METAL
TYP
11
10
(0.75)
TYP
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 21
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4225320/A 09/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2019, Texas Instruments Incorporated
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