Texas Instruments | SN65C1168E-SEP Dual Differential Drivers and Receivers With ±12-kV ESD Protection | Datasheet | Texas Instruments SN65C1168E-SEP Dual Differential Drivers and Receivers With ±12-kV ESD Protection Datasheet

Texas Instruments SN65C1168E-SEP Dual Differential Drivers and Receivers With ±12-kV ESD Protection Datasheet
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SN65C1168E-SEP
SLLSFC4 – JULY 2019
SN65C1168E-SEP Dual Differential Drivers and Receivers
With ±12-kV ESD Protection
1 Features
•
•
1
•
•
•
•
VID V62/19606
Radiation hardened
– Single event latch-up (SEL) immune to 43
MeV-cm2/mg at 125°C
– ELDRS-free to 30 krad(Si)
– Total ionizing dose (TID) RLAT for every wafer
lot up to 20 krad(Si)
Space Enhanced Plastic
– Controlled baseline
– Gold wire
– NiPdAu lead finish
– One assembly and test site
– One fabrication site
– Available in military (–55°C to 125°C)
temperature range
– Extended product life cycle
– Extended product-change notification
– Product traceability
– Enhanced mold compound for low outgassing
Meet or exceed standards TIA/EIA-422-B and ITU
recommendation V.11
Operate from single 5-V power supply
ESD protection for RS-422 bus pins
– ±12-kV human-body model (HBM)
– ±8-kV IEC 61000-4-2, contact discharge
– ±8-kV IEC 61000-4-2, air-gap discharge
•
•
•
•
•
Low-pulse skew
Receiver input impedance . . . 17 kΩ (typical)
Receiver input sensitivity . . . ±200 mV
Receiver common-mode input voltage range of
–7 V to 7 V
Glitch-free power-up/power-down protection
2 Applications
•
•
•
Support low earth orbit space applications
Satellite communications
AC and servo motor drives
3 Description
The SN65C1168E-SEP consists of dual drivers and
dual receivers with ±12-kV ESD (HBM) and ±8-kV
ESD (IEC61000-4-2 Air-Gap Discharge and Contact
Discharge) for RS-422 bus pins. The device meets
the requirements of TIA/EIA-422-B and ITU
recommendation V.11. Some parameters do not meet
all TIA/EIA-422-B and ITU recommendation V.11
requirements after 20-krad(Si) TID exposure.
The SN65C1168E-SEP drivers have individual activehigh enables.
Device Information(1)
PART NUMBER
SN65C1168EMPWTSEP
SN65C1168EMPWSEP
PACKAGE
BODY SIZE (NOM)
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
SN65C1168E-SEP
4
1DE
1D
1R
2DE
2D
2R
15
14
13
3
2
1
12
9
10
11
5
6
7
1Y
1Z
1A
1B
2Y
2Z
2A
2B
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65C1168E-SEP
SLLSFC4 – JULY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
5
5
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Driver Section Electrical Characteristics ...................
Receiver Section Electrical Characteristics ..............
Driver Section Switching Characteristics ..................
Receiver Section Switching Characteristics..............
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
13
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application .................................................. 15
10 Power Supply Recommendations ..................... 15
11 Device and Documentation Support ................. 16
11.1
11.2
11.3
11.4
11.5
11.6
Parameter Measurement Information .................. 9
Detailed Description ............................................ 12
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
July 2019
*
Initial release.
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5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
1B
1
16
VCC
1A
2
15
ID
1R
3
14
1Y
1DE
4
13
1Z
2R
5
12
2DE
2A
6
11
2Z
2B
7
10
2Y
GND
8
9
2D
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
1A
2
I
RS422 differential input (noninverting) to receiver 1
2A
6
I
RS422 differential input (noninverting) to receiver 2
1B
1
I
RS422 differential input (inverting) to receiver 1
2B
7
I
RS422 differential input (inverting) to receiver 2
1D
15
I
Logic data input to RS422 driver 1
2D
9
I
Logic data input to RS422 driver 2
1DE
4
I
Driver 1 enable (active high)
2DE
12
I
Driver 2 enable (active high)
GND
8
—
Device ground
1R
3
O
Logic data output of RS422 receiver 1
2R
5
O
Logic data output of RS422 receiver 2
VCC
16
—
Power supply
1Y
14
O
RS-422 differential (noninverting) driver output 1
2Y
10
O
RS-422 differential (noninverting) driver output 2
1Z
13
O
RS-422 differential (noninverting) driver output 1
2Z
11
O
RS-422 differential (noninverting) driver output 2
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6 Specifications
6.1 Absolute Maximum Ratings
over recommended operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage (2)
VI
Input voltage
VID
Differential input voltage (3)
VO
Output voltage
IIK
Input clamp current
IOK
Output clamp current
IO
Output current
ICC
Supply current
MIN
MAX
–0.5
7
Driver, DE, RE
–0.5
7
A or B, Receiver
–14
14
Receiver
–14
14
Driver
–0.5
7
Receiver
–0.5
VCC + 0.5
Driver, VI < 0
–20
Driver, VO < 0
–20
Receiver
Driver
Receiver
–20
20
–150
150
–25
25
GND current
TJ
Operating virtual junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
–65
UNIT
V
V
V
V
mA
mA
mA
200
mA
–200
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential input voltage are with respect to the network GND.
Differential input voltage is measured at the noninverting terminal, with respect to the inverting terminal.
6.2 ESD Ratings
VALUE UNIT
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±12000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
IEC 61000-4-2, air-gap discharge
±8000
IEC 61000-4-2, contact discharge
±8000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
MIN
NOM
MAX
4.5
5
5.5
V
Receiver
±7
V
Differential input voltage
Receiver
±7
V
VI
Input voltage
Except A, B
0
5.5
V
VO
Output voltage
Receiver
0
VCC
V
VIH
High-level input voltage
Except A, B
2
VIL
Low-level input voltage
Except A, B
0.8
Receiver
–6
VCC
Supply voltage
VIC
Common-mode input voltage (1)
VID
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
(1)
Driver
UNIT
V
V
mA
–20
Receiver
6
Driver
mA
20
–55
125
°C
Refer to TIA/EIA-422-B for exact conditions.
6.4 Thermal Information
SN65C1168E-SEP
THERMAL METRIC
(1)
PW (TSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
102.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32.3
°C/W
RθJB
Junction-to-board thermal resistance
48.8
°C/W
ψJT
Junction-to-top characterization parameter
1.8
°C/W
ψJB
Junction-to-board characterization parameter
48.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Driver Section Electrical Characteristics
over recommended supply voltage and operating free-air temperature ranges (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input clamp voltage
II = –18 mA
VOH
High-level output voltage
VIH = 2 V, VIL = 0.8 V, IOH = –20 mA
VOL
Low-level output voltage
VIH = 2 V, VIL = 0.8 V, IOL = 20 mA
|VOD1|
Differential output voltage 1
IO = 0 mA
MIN
TYP (1)
2.4
3.5
MAX
UNIT
–1.5
V
V
0.2
2
0.4
V
6
V
|VOD2|
Differential output voltage 2
RL = 100 Ω, see Figure 1
(2)
Δ|VOD|
Change in magnitude of
differential output voltage
RL = 100 Ω, see Figure 1
(2)
–0.4
0.4
V
VOC
Common-mode output voltage
RL = 100 Ω, see Figure 1 (2)
–3
3
V
Δ|VOC|
Change in magnitude of
common-mode output voltage
RL = 100 Ω, see Figure 1
(2)
–0.4
0.4
V
IO(OFF)
Output current with power off
VCC = 0 V
IO(OFF)
Output current with power off (3)
VCC = 0 V
IOZ
High-impedance-state output current
IOZ
High-impedance-state output current (3)
IIH
High-level input current
VI = VCC or VIH
IIL
Low-level input current
VI = GND or VIL
IOS
Short-circuit output current
VO = VCC or GND (4)
ICC
Supply current (total package)
No load,
Enabled
VI = VCC or GND
4
6
VI = 2.4 or 0.5 V (5)
5
9
ICC
Supply current (total package) (3)
No load,
Enabled
VI = VCC or GND
Ci
Input capacitance
(1)
(2)
(3)
(4)
(5)
6
2
3.7
V
VO = 6 V
100
VO = –0.25 V
100
VO = 6 V
3
VO = –0.25 V
3
VO = 2.5 V
20
VO = 5 V
–20
VO = 2.5 V
2
VO = 5 V
–2
1
–30
VI = 2.4 or 0.5 V
μA
mA
μA
mA
μA
–36
μA
–160
mA
17
(5)
16
6
mA
mA
pF
All typical values are at VCC = 5 V and TA = 25°C.
Refer to TIA/EIA-422-B for exact conditions.
25°C only. Post 20-krad(Si) HDR TID using worst case static biasing.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
This parameter is measured per input, while the other inputs are at VCC or GND.
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6.6 Receiver Section Electrical Characteristics
over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage,
differential input
VIT–
Negative-going input threshold voltage,
differential input
Vhys
Input hysteresis (VIT+ – VIT–)
VOH
High-level output voltage
VID = 200 mV, IOH = –6 mA
VOL
Low-level output voltage
VID = –200 mV, IOL = 6 mA
MAX
–0.2 (2)
ICC
Supply current (total package) (4)
No load
V
0.3
–2.5
VIC = –7 V to 7 V, other input at 0 V
No load,
Enabled
0.1
VI = –10 V
Input resistance
Supply current (total package)
4.2
1.5
rI
4
V
mV
VI = 10 V
Other input at 0 V
ICC
3.8
UNIT
V
60
Line input current
(3)
(4)
(5)
TYP (1)
0.2
II
(1)
(2)
MIN
17
V
mA
kΩ
VI = VCC or GND
4
6
VIH = 2.4 V or 0.5 V (3)
5
9
VI = VCC or GND
17
VI = 2.4 or 0.5 V (5)
16
mA
mA
All typical values are at VCC = 5 V and TA = 25°C.
The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for
common-mode input voltage and threshold voltage levels only.
Refer to TIA/EIA-422-B for exact conditions.
25°C only. Post 20-krad(Si) HDR TID using worst case static biasing.
This parameter is measured per input, while the other inputs are at VCC or GND.
6.7 Driver Section Switching Characteristics
over recommended supply voltage and operating free-air temperature ranges (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPHL
Propagation delay time, high- to low-level output
tPLH
Propagation delay time, low- to high-level output
tsk(p)
Pulse skew
tr
Rise time
tf
Fall time
tPZH
Output-enable time to high level
tPZL
Output-enable time to low level
tPHZ
Output-disable time from high level
tPLZ
Output-disable time from low level
fSW
Maximum switching frequency
(1)
MIN
R1 = R2 = 50 Ω, R3 = 500 Ω,
C1 = C2 = C3 = 40 pF, S1 is open,
see Figure 2
TYP (1)
MAX
8
16
ns
UNIT
8
16
ns
1.5
4
ns
5
8
ns
5
8
ns
R1 = R2 = 50 Ω, R3 = 500 Ω,
C1 = C2 = C3 = 40 pF, S1 is closed,
see Figure 4
10
19
ns
10
19
ns
R1 = R2 = 50 Ω, R3 = 500 Ω,
C1 = C2 = C3 = 40 pF, S1 is closed,
see Figure 4
7
16
ns
7
16
ns
R1 = R2 = 50 Ω, R3 = 500 Ω,
C1 = C2 = C3 = 40 pF, S1 is open,
see Figure 3
R1 = R2 = 50 Ω, R3 = 500 Ω,
C1 = C2 = C3 = 40 pF, S1 is open,
see Figure 3
20
MHz
All typical values are at VCC = 5 V and TA = 25°C.
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6.8 Receiver Section Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN TYP (2) MAX
UNIT
tPLH
Propagation delay time, low- to high-level output
See Figure 5
9
15
27
ns
tPHL
Propagation delay time, high- to low-level output
See Figure 5
9
15
27
ns
tTLH
Transition time, low- to high-level output
4
9
ns
tPHL
Transition time, high- to low-level output
4
9
ns
(1)
(2)
8
VIC = 0 V, see Figure 5
Measured per input while the other inputs are at VCC or GND.
All typical values are at VCC = 5 V and TA = 25°C.
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7 Parameter Measurement Information
RL
2
VOD2
RL
2
VOC
Figure 1. Driver Test Circuit, VOD and VOC
3V
Input
(see Note B)
VOH
R3
50%
1.3 V
Y
1.5 V
C1
S1
t sk(p)
R2
C3
0V
t PHL
R1
C2
1.3 V
t PLH
Y
Input
1.3 V
50%
1.3 V
VOL
t sk(p)
VOH
Z
50%
1.3 V
Z
See Note A
t PHL
50%
1.3 V
VOL
t PLH
TEST CIRCUIT
VOLTAGE WAVEFORMS
A.
C1, C2, and C3 include probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf
≤ 6 ns.
Figure 2. Driver Test Circuit and Voltage Waveforms
C2
Input
R1
0V
R3
VOD
1.5 V
C1
S1
R2
C3
3V
Input
(see Note B)
Y
Differential
Output
90%
90%
10%
10%
Z
tr
See Note A
tf
VOLTAGE WAVEFORMS
TEST CIRCUIT
A.
C1, C2, and C3 include probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf
≤ 6 ns.
Figure 3. Driver Test Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
3V
Input DE
Y
C2
0V
or
3V
1.3 V
R1
R3
C1
S1
C3
Pulse
Generator
1.5 V
Output
0V
t PZL
1.5 V
VOL + 0.3 V
0.8 V
R2
VOL
t PHZ
Z
DE
See Note A
50Ω
1.3 V
t PLZ
t PZH
VOH
VOH - 0.3 V
Output
2V
1.5 V
See Note B
TEST CIRCUIT
VOLTAGE WAVEFORMS
A.
C1, C2, and C3 include probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf
≤ 6 ns.
Figure 4. Driver Test Circuit and Voltage Waveforms
VCC
S1
2.5 V
0V
-2.5 V
B Input
A Input = 0 V
(see Note B)
t PLH
t PHL
RL
A Input
Device
Under
Test
B Input
Output
CL = 50 pF
(see Note A)
10%
90%
50%
90%
50%
t TLH
TEST CIRCUIT
VOH
10%
VOL
t THL
VOLTAGE WAVEFORMS
A.
C1, C2, and C3 include probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf
≤ 6 ns.
Figure 5. Receiver Test Circuit and Voltage Waveforms
10
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Parameter Measurement Information (continued)
3V
RE Input
(see Note B)
VCC
S1
1.3 V
1.3 V
0V
t PLZ
t PZL
VCC
Output
VOL + 0.5 V
RE Input
VID = -2.5 V
or 2.5 V
RL
Device
Under
Test
t PHZ
50%
VOL
t PZH
VOH
CL = 50 pF
(see Note A)
VOH – 0.5 V
Output
50%
GND
t PZL, t PLZ Measurement: S1 to V CC
t PZH, t PHZ Measurement: S1 to GND
VOLTAGE WAVEFORMS
TEST CIRCUIT
A.
C1, C2, and C3 include probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf
≤ 6 ns.
Figure 6. Receiver Test Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN65C1168E-SEP consist of dual drivers and dual receivers powered from a single 5-V supply. This device
meets the requirements of TIA/EIA-422-B and ITU recommendation V.11.
8.2 Functional Block Diagram
SN65C1168E-SEP
4
1DE
1D
1R
2DE
2D
2R
15
14
13
3
2
1
12
9
10
11
5
6
7
1Y
1Z
1A
1B
2Y
2Z
2A
2B
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8.3 Feature Description
8.3.1 Active High Driver Output Enables
SN65C1168E-SEP drivers can be configured individually by 1DE and 2DE logic inputs. Both drivers are set at
high-impedance when disabled.
12
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8.4 Device Functional Modes
Table 1 and Table 2 lists the functional modes of SN65C1168E-SEP.
Table 1. Each Driver (1)
(1)
OUTPUTS
INPUT
D
ENABLE
DE
Y
Z
H
H
H
L
L
H
L
H
X
L
Z
Z
H = High level, L = Low level, X = Irrelevant, Z = High impedance
(off)
Table 2. Each Receiver (1)
(1)
DIFFERENTIAL INPUTS
A–B
OUTPUT
R
VID ≥ 0.2 V
H
–0.2 V < VID < 0.2 V
?
VID ≤ –0.2 V
L
Open
H
H = High level, L = Low level, ? = Indeterminate
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Figure 7 shows a typical RS-422 application. One transmitter is able to broadcast to multiple receiving nodes
connected together over a shared differential bus. Twisted-pair cabling with a controlled differential impedance is
used, and a termination resistance is placed at the farthest receive end of the cable in order to match the
transmission line impedance and minimize signal reflections.
EQUIVALENT OF DRIVER ENABLE INPUT
VCC
EQUIVALENT OF A OR B INPUT
VCC
17 kΩ
NOM
Input
1.7 kΩ
NOM
Input
288 kΩ
NOM
1.7 kΩ
NOM
VCC (A)
or
GND (B)
GND
GND
Figure 7. Schematic of Inputs
14
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Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: SN65C1168E-SEP
SN65C1168E-SEP
www.ti.com
SLLSFC4 – JULY 2019
Application Information (continued)
TYPICAL OF EACH DRIVER OUTPUT
TYPICAL OF EACH RECEIVER OUTPUT
VCC
VCC
Output
Output
GND
GND
Figure 8. Schematic of Outputs
9.2 Typical Application
Figure 9. Typical RS-422 Application
9.2.1 Design Requirements
A
•
•
•
typical RS-422 implementation using SN65C116xE requires the following:
5-V power source.
Connector that ensures the correct polarity for port pins.
Cabling that supports the desired operating rate and transmission distance.
9.2.2 Detailed Design Procedure
Place the device close to bus connector to keep traces (stub) short to prevent adding reflections to the bus line.
If desired, add external fail-safe biasing to ensure ±200 mV on the A-B port when the driver circuit is disabled.
10 Power Supply Recommendations
Use a 5-V power supply for VCC place 0.1-μF bypass capacitors close to the power supply pins to reduce errors
coupling in from noisy or high impedance power supplies.
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Product Folder Links: SN65C1168E-SEP
15
SN65C1168E-SEP
SLLSFC4 – JULY 2019
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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Product Folder Links: SN65C1168E-SEP
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN65C1168EMPWSEP
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
1168SEP
SN65C1168EMPWTSEP
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
1168SEP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN65C1168EMPWTSEP
Package Package Pins
Type Drawing
TSSOP
PW
16
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65C1168EMPWTSEP
TSSOP
PW
16
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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