Texas Instruments | TLIN2029-Q1 Fault Protected Local Interconnect Network (LIN) Transceiver with Dominant State Timeout (Rev. C) | Datasheet | Texas Instruments TLIN2029-Q1 Fault Protected Local Interconnect Network (LIN) Transceiver with Dominant State Timeout (Rev. C) Datasheet

Texas Instruments TLIN2029-Q1 Fault Protected Local Interconnect Network (LIN) Transceiver with Dominant State Timeout (Rev. C) Datasheet
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TLIN2029-Q1
SLLSEY6C – OCTOBER 2017 – REVISED JULY 2019
TLIN2029-Q1 Fault Protected Local Interconnect Network (LIN) Transceiver with Dominant
State Timeout
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications
– Device Temperature: –40°C to 125°C Ambient
– Device HBM Certification Level: ±8 kV
– Device CDM Certification Level: ±1.5 kV
Compliant to LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A
and ISO/DIS 17987–4.2
Conforms to SAEJ2602 Recommended Practice
for LIN
Supports 24 V Applications
LIN Transmit Data Rate up to 20 kbps.
Wide Operating Ranges
– 4 V to 48 V Supply Voltage
– ±58 V LIN Bus Fault Protection
Sleep Mode: Ultra-Low Current Consumption
Allows Wake-Up Event From:
– LIN Bus
– Local Wake up through EN
Power Up and Down Glitch Free Operation
Protection Features:
– Under Voltage Protection on VSUP
– TXD Dominant Time Out Protection (DTO)
– Thermal Shutdown Protection
– Unpowered Node or Ground Disconnection
Failsafe at System Level.
Available in SOIC (8) Package and Leadless
VSON (8) Package with Improved Automated
Optical Inspection (AOI) Capability
Body Electronics and Lighting
Infotainment and Cluster
Hybrid Electric Vehicles and Power Train Systems
Passive Safety
Appliances
3 Description
The TLIN2029-Q1 is a Local Interconnect Network
(LIN) physical layer transceiver with integrated wakeup and protection features, compliant to LIN 2.0, LIN
2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4.2
standards. LIN is a single wire bidirectional bus
typically used for low speed in-vehicle networks using
data rates up to 20 kbps. The TLIN2029-Q1 is
designed to support 24 V applications with wider
operating voltage and additional bus-fault protection.
The LIN receiver supports data rates up to 100 kbps
for in-line programming. The TLIN2029-Q1 converts
the LIN protocol data stream on the TXD input into a
LIN bus signal using a current-limited wave-shaping
driver which reduces electromagnetic emissions
(EME). The receiver converts the data stream to logic
level signals that are sent to the microprocessor
through the open-drain RXD pin. Ultra-low current
consumption is possible using the sleep mode which
allows wake-up via LIN bus or pin. The integrated
resistor, ESD and fault protection allows designers to
save board space in their applications.
Device Information(1)
PART NUMBER
TLIN2029-Q1
PACKAGE
BODY SIZE (NOM)
SOIC (D) (8)
4.90 mm x 3.91 mm
VSON (DRB) (8)
3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematics, Master Mode
VBAT
Simplified Schematics, Slave Mode
VSUP
VBAT
VSUP
VREG
VREG
VSUP
VDD
VDD
VSUP
VDD
EN
2
NC
NC
8
3
VSUP
Master Node
Pullup
VSUP
VDD
MCU w/o
pullup
VDD I/O
EN
6
LIN
2
NC
NC
8
3
MCU w/o
pullup
LIN Bus
VDD I/O
MCU
1
200 pF
RXD
TXD
7
I/O
1 kŸ
MCU
GND
VDD
7
I/O
LIN Controller
or
SCI/UART
VDD
6
LIN Controller
or
SCI/UART
4
5
1
GND
LIN Bus
200 pF
RXD
TXD
LIN
4
5
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLIN2029-Q1
SLLSEY6C – OCTOBER 2017 – REVISED JULY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
5
7
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
ESD Ratings - IEC ....................................................
Thermal Information ..................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 22
9
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application ................................................. 24
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February 2018) to Revision C
Page
•
Changed the SOIC package Body Size From: 4.90 mm x 6.00 mm To: 4.90 mm x 3.91 mm in the Device
Information ............................................................................................................................................................................. 1
•
Changed the 220 pF capacitor To: 200 pF in the Simplified Schematics, Master Mode ....................................................... 1
•
Changed the 220 pF capacitor To: 200 pF in the Simplified Schematics, Slave Mode ......................................................... 1
•
Changed VLOGIC absolute maximum rating MAX from 5.5 V to 6 V........................................................................................ 4
•
Changed the 220 pF capacitor To: 200 pF in Figure 23 ...................................................................................................... 24
•
Changed the title of Figure 24 To: Recessive to Dominant Propagation ............................................................................. 25
•
Changed the title of Figure 25 To: Dominant to Recessive Propagation ............................................................................. 25
•
Changed text From: "For slave applications a 220 pF capacitor" To: "For slave applications a 200 pF capacitor" For
Pin 6 (LIN) in the Layout Guidelines..................................................................................................................................... 26
Changes from Revision A (December 2017) to Revision B
Page
•
Changed From: "Complaint to LIN 2.0..." To: "Compliant to LIN 2.0..." in the Features and Description.............................. 1
•
Changed From: "complaint to LIN 2.0..." To: "compliant to LIN 2.0..." in the Overview section .......................................... 18
Changes from Original (October 2017) to Revision A
•
2
Page
Changed the device status from Advance Information to Production Data............................................................................ 1
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SLLSEY6C – OCTOBER 2017 – REVISED JULY 2019
5 Pin Configuration and Functions
D Package
8-Pin (SOIC)
Top View
DRB Package
8-Pin (VSON)
Top View
RXD
1
8
NC
EN
2
7
VSUP
NC
3
6
LIN
TXD
4
5
GND
RXD
1
8
NC
EN
2
7
VSUP
NC
3
6
LIN
TXD
4
5
GND
Thermal
Pad
Not to scale
Not to scale
Pin Functions
PIN
Name
No.
Type
DESCRIPTION
RXD
1
DO
RXD output (open-drain) interface reporting state of LIN bus voltage
EN
2
DI
Enable input - High put the device in normal operation mode and low put the device in sleep mode
NC
3
–
Not connected
TXD
4
DI
TXD input interface to control state of LIN output - Internal pulled to ground
GND
5
GND
LIN
6
HV I/O
VSUP
7
HV Supply
NC
8
Thermal Pad
–
GND
Ground
LIN bus single-wire transmitter and receiver
Device supply voltage (connected to battery in series with external reverse blocking diode)
Not connected
Ground and should be soldered (DRB package only)
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Symbol
Parameter
MIN
MAX
–0.3
60
V
LIN bus input voltage (ISO/DIS 17987 Param 82)
–58
58
V
Logic pin voltage (RXD, TXD, EN)
–0.3
6
V
TA
Ambient temperature range
–40
125
°C
TJ
Junction temperature range
–55
150
°C
VSUP
Supply voltage range (ISO/DIS 17987 Param 10)
VLIN
VLOGIC
(1)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
Human body model (HBM) TXD, RXD, EN Pins, per AEC Q100002 (1)
±4000
Human body model (HBM) LIN and VSUP Pin, per AEC Q100002 (2)
±8000
Charged device model (CDM),
per AEC Q100-011
±1500
All terminals
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
LIN bus a stressed with respect to GND.
6.3 ESD Ratings - IEC
ESD and Surge Protection Ratings
V(ESD)
Electrostatic discharge
(1)
Powered ESD Performance, per
SAEJ2962-1 (2)
V(ESD)
VALUE
UNIT
IEC 61000-4-2 contact discharge
±8000
V
contact discharge
±8000
air-gap discharge
±25000
Pulse 1
ISO 7637-2 and IEC 62215-3 transients according to IBEE Pulse 2
LIN EMC test specifications (3) (LIN and VSUP)
Pulse 3a
Pulse 3b
(1)
(2)
(3)
V
–100
V
75
V
–150
V
100
V
IEC 61000-4-2 is a system level ESD test. Results given here are specific to the IBEE LIN EMC Test specification conditions. Different
system level configurations may lead to different results
SAEJ2962-1 Testing performed at 3rd party US3 approved EMC test facility, test report available upon request
ISO 7637 is a system level transient test. Different systme level configurations may lead to diffrent results
6.4 Thermal Information
THERMAL METRIC
(1)
TLIN2029D
TLIN2029DRB
D (SOIC)
DRB (VSON)
8-PINS
8-PINS
UNIT
RΘJA
Junction-to-ambient thermal resistance
115.5
48.5
°C/W
RΘJC(top)
Junction-to-case (top) thermal resistance
58.7
55.5
°C/W
RΘJB
Junction-to-board thermal resistance
58.9
22.2
°C/W
ΨJT
Junction-to-top characterization parameter
14.1
1.2
°C/W
ΨJB
Junction-to-board characterization parameter
58.2
22.2
°C/W
RΘJC(bot)
Junction-to-case (bottom) thermal resistance
4.8
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER - DEFINITION
MIN
NOM
MAX
UNIT
VSUP
Supply voltage
4
48
V
VLIN
LIN Bus input voltage
0
48
V
VLOGIC
Logic Pin Voltage (RXD, TXD, EN)
0
5.25
TSD
Thermal shutdown temperature
TSD(HYS)
Thermal shutdown hysteresis
V
165
°C
15
°C
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply
VSUP
VSUP
Operational supply voltage (ISO/DIS
17987 Param 10, 53)
Nominal supply voltage (ISO/DIS 17987
Param 10, 53)
Under voltage VSUP threshold
UVHYS
Delta hysteresis voltage for VSUP under
voltage threshold
ISUP
Supply current
Supply current
4
48
V
Normal and Standby Modes: ramp VSUP
while LIN signal is a 10 kHZ square
wave with 50 % duty cycle and 36V
swing. See Figure 1 and Figure 2
4
48
V
Sleep Mode
4
48
V
2.9
3.85
V
Min is falling edge and Max is rising
edge
UVSUP
ISUP
Device is operational beyond the LIN
defined nominal supply voltage range
See Figure 1 and Figure 2
0.2
Normal Mode: EN = high, bus dominant:
total bus load where RLIN > 500 Ω and
CLIN < 10 nF (See Figure 7)
1.2
5
mA
Standby Mode: EN = low, bus dominant:
total bus load where RLIN > 500 Ω and
CLIN < 10 nF (See Figure 7)
1
2.1
mA
Normal Mode: EN = high, bus recessive:
LIN = VSUP,
400
700
µA
Standby Mode: EN = low, bus recessive:
LIN = VSUP,
20
35
µA
Sleep Mode: 4.0 V < VSUP ≤ 27 V, LIN
= VSUP, EN = 0 V, TXD and RXD
floating
9
15
µA
30
µA
Sleep Mode: 27 V < VSUP ≤ 48 V, LIN =
VSUP, EN = 0 V, TXD and RXD floating
TSD
Thermal shutdown
TSD(HYS)
Thermal shutdown hysteresis
V
℃
165
℃
15
RXD OUTPUT PIN (OPEN DRAIN)
VOL
Output low voltage
Based upon external pull-up to VCC
IOL
Low level output current, open drain
LIN = 0 V, RXD = 0.4 V
1.5
0.6
IILG
Leakage current, high-level
LIN = VSUP, RXD = 5 V
–5
V
mA
0
5
µA
0.8
V
TXD INPUT PIN
VIL
Low level input voltage
VIH
High level input voltage
IILG
Low level input leakage current
RTXD
Interal pull-down resitor value
–0.3
2
TXD = low
5.5
V
–5
0
5
µA
125
350
800
kΩ
LIN PIN
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
HIGH level output voltage
VOL
LOW level output voltage
MIN
LIN recessive, TXD = high, IO = 0 mA,
VSUP = 7 V to 48 V
0.85
LIN recessive, TXD = high, IO = 0 mA,
VSUP = 4 V ≤ VSUP < 7 V
3
TYP
MAX
UNIT
VSUP
V
LIN dominant, TXD = low, VSUP = 7 V to
48 V
0.2
VSUP
LIN dominant, TXD = low, VSUP = 4 V ≤
VSUP < 7 V
1.2
V
58
V
200
mA
VSUP_NON_OP
VSUP where impact of recessive LIN
bus < 5% (ISO/DIS 17987 Param 11,
54/56)
TXD& RXD open LIN = 4 V to 58 V
IBUS_LIM
Limiting current (ISO/DIS 17987 Param
12, 57)
TXD = 0 V, VLIN = 36 V, RMEAS = 440 Ω,
VSUP = 36 V, VBUSdom < 4.518 V
See Figure 6
40
IBUS_PAS_dom
Receiver leakage current, dominant
(ISO/DIS 17987 Param 13, 58)
LIN = 0 V, VSUP = 24 V Driver
off/recessive Figure 7
–1
IBUS_PAS_rec1
Receiver leakage current, recessive
(ISO/DIS 17987 Param 14, 59)
LIN > VSUP, 4 V ≤ VSUP ≤ 45 V Driver
off; Figure 8
IBUS_PAS_rec2
Receiver leakage current, recessive
(ISO/DIS 17987 Param 14, 59)
LIN = VSUP, Driver off; Figure 8
IBUS_NO_GND
Leakage current, loss of ground
(ISO/DIS 17987 Param 15, 60)
IBUS_NO_GND
Leakage current, loss of ground
(ISO/DIS 17987 Param 15, 60)
IBUS_NO_BAT
Leakage current, loss of supply (ISO/DIS
LIN = 48 V, VSUP = GND; Figure 10
17987 Param 16, 61)
VBUSdom
Low level input voltage (ISO/DIS 17987
Param 17, 62)
LIN dominant (including LIN dominant for
wake up) See Figure 4, Figure 3
VBUSrec
High level input voltage (ISO/DIS 17987
Param 18, 63)
Lin recessive See Figure 4, Figure 3
VBUS_CNT
Receiver center threshold (ISO/DIS
17987 Param 19, 64)
VBUS_CNT = (VIL + VIH)/2 See
Figure 4, Figure 3
VHYS
Hysteresis voltage (ISO/DIS 17987
Param 20, 65)
VHYS = (VIL - VIH) See Figure 4, Figure 3
–0.3
90
mA
20
µA
–5
5
µA
GND = VSUP, VSUP = 27 V, LIN = 0
V; Figure 9
–1
1
mA
GND = VSUP, VSUP ≥ 36 V, LIN = 0
V; Figure 9
–1.5
1.5
mA
5
µA
0.4
0.6
0.475
VSUP
VSUP
0.5
0.525
VSUP
0.175
VSUP
VSERIAL_DIODE Serial diode LIN term pull-up path
By design and characterization
0.4
0.7
1
V
RSLAVE
Internal pull-up resistor to VSUP
Normal and standby modes
20
45
60
kΩ
IRSLEEP
Pull-up current source to VSUP
Sleep mode, VSUP = 27 V, LIN = GND
–2
–20
µA
CLINPIN
Capacitance of the LIN pin
45
pF
0.8
V
EN INPUT PIN
VIL
Low level input voltage
VIH
High level input voltage
VIT
Hysteresis voltage
By design and characterization
IILG
Low level input current
EN = low
REN
Internal pull-down resistor
6
–0.3
2
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5.5
V
50
500
mV
–5
0
5
µA
125
350
800
kΩ
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6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
D112V
Duty Cycle 1 (ISO/DIS 17987 Param
27) (1)
THREC(MAX) = 0.744 x VSUP, THDOM(MAX)
= 0.581 x VSUP, VSUP = 7 V to 18 V, tBIT
= 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x
tBIT) (See Figure 11, Figure 12)
0.396
D112V
Duty Cycle 1
THREC(MAX) = 0.625 x VSUP, THDOM(MAX)
= 0.581 x VSUP, VSUP = 4 V to 7 V, tBIT =
50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x
tBIT) (See Figure 11, Figure 12)
0.396
D212V
Duty Cycle 2 (ISO/DIS 17987 Param 28)
THREC(MAX) = 0.422 x VSUP, THDOM(MIN)
= 0.284 x VSUP, VSUP = 4.6 V to 18 V,
tBIT = 50 µs (20 kbps), D2 =
tBUS_rec(MAX)/(2 x tBIT) (See Figure 11,
Figure 12)
D312V
Duty Cycle 3 (ISO/DIS 17987 Param 29)
THREC(MAX) = 0.778 x VSUP, THDOM(MAX)
= 0.616 x VSUP, VSUP = 7 V to 18 V, tBIT
= 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2
x tBIT) (See Figure 11, Figure 12)
0.417
D312V
Duty Cycle
THREC(MAX) = 0.645 x VSUP, THDOM(MAX)
= 0.616 x VSUP, VSUP = 4 V to 7 V, tBIT =
96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x
tBIT) (See Figure 11, Figure 12)
0.417
D412V
Duty Cycle 4 (ISO/DIS 17987 Param 30)
THREC(MIN) = 0.389 x VSUP, THDOM(MIN) =
0.251 x VSUP, VSUP = 4.6 V to 18 V, tBIT
= 96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2
x tBIT) (See Figure 11, Figure 12)
D124V
Duty Cycle 1 (ISO/DIS 17987 Param
72) (1)
THREC(MAX) = 0.710 x VSUP, THDOM(MAX)
= 0.544 x VSUP, VSUP = 15 V to 36 V, tBIT
= 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x
tBIT) (See Figure 11, Figure 12)
Duty Cycle 2 (ISO/DIS 17987 Param 73)
THREC(MAX) = 0.446 x VSUP, THDOM(MIN)
= 0.302 x VSUP, VSUP = 15.6 V to 36 V,
tBIT = 50 µs (20 kbps), D2 =
tBUS_rec(MAX)/(2 x tBIT) (See Figure 11,
Figure 12)
Duty Cycle 3 (ISO/DIS 17987 Param 74)
THREC(MAX) = 0.744 x VSUP, THDOM(MAX)
= 0.581 x VSUP, VSUP = 7 V to 36 V, tBIT
= 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2
x tBIT) (See Figure 11, Figure 12)
0.386
D324V
Duty Cycle
THREC(MAX) = 0.645 x VSUP, THDOM(MAX)
= 0.581 x VSUP, VSUP = 4 V to 7 V, tBIT =
96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x
tBIT) (See Figure 11, Figure 12)
0.386
D424V
Duty Cycle 4 (ISO/DIS 17987 Param 75)
THREC(MIN) = 0.442 x VSUP, THDOM(MIN) =
0.284 x VSUP, VSUP = 4.6 V to 36 V, tBIT
= 96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2
x tBIT) (See Figure 11, Figure 12)
D224V
D324V
(1)
TYP
MAX
UNIT
0.581
0.59
0.33
0.642
0.591
Duty cycles: LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω. Duty cycles 3 and 4 are
defined for 10.4-kbps operation. The TLIN1029 also meets these lower data rate requirements, while it is capable of the higher speed
20-kbps operation as specified by duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle
definitions, for details see the SAEJ2602 specification
6.8 Timing Requirements
SYMBOL
DESCRIPTION
TEST CONDITIONS
MIN
trx_pdr, trx_pdf
Receiver rising propagation delay time
(ISO/DIS 17987 Param 31, 76)
RRXD = 2.4 kΩ, CRXD = 20 pF
(See Figure 13 and Figure 14 )
trs_sym
Symmetry of receiver propagation delay
time Receiver rising propagation delay
time
Rising edge with respect to falling edge,
(trx_sym = trx_pdf – trx_pdr), RRXD = 2.4
kΩ, CRXD = 20 pF (See Figure 13
and Figure 14 )
–2
NOM
MAX
6
µs
2
µs
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Timing Requirements (continued)
SYMBOL
DESCRIPTION
TEST CONDITIONS
tLINBUS
LIN wakeup time (Minimum dominant
time on LIN bus for wakeup)
See Figure 17, Figure 20, and Figure 21)
tCLEAR
Time to clear false wakeup prevention
logic if LIN bus had a bus stuck
dominant fault (recessive time on LIN
bus to clear bust stuck dominant fault)
See Figure 21
tDST
Dominant state time out
MIN
NOM
MAX
UNIT
25
65
150
µs
8
25
50
µs
20
45
80
ms
15
µs
tMODE_CHANGE Mode change delay time
Time to change from standby mode to
normal mode or normal mode to sleep
mode through EN pin: See Figure 15
and Figure 22
tNOMINT
Normal mode initialization time
Time for normal mode to initialize and
data on RXD pin to be valid
See Figure 15
35
µs
tPWR
Power up time
Upon power up time it takes for valid
data on RXD
1.5
ms
8
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6.9 Typical Characteristics
7 Parameter Measurement Information
1
NC
RXD
5V
2
VSUP
EN
3
NC
LIN
4
TXD
GND
8
7
Power Supply
Resolution: 10mV/1mA
Accuracy: 0.2%
VPS
6
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
Jitter: < 25 ns
5
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
Figure 1. Test System: Operating Voltage Range with RX and TX Access: Parameters 9, 10
Trigger Point
Delta t = + 5 µs
(tBIT = 50 µs)
RX
2 x tBIT = 100 µs (20 kBaud)
Figure 2. RX Response: Operating Voltage Range
Period T = 1/f
LIN Bus Input
Amplitude
(signal range)
Frequency: f = 20 Hz
Symmetry: 50%
Figure 3. LIN Bus Input Signal
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Parameter Measurement Information (continued)
1
RXD
5V
2
3
NC
VSUP
EN
NC
LIN
4
TXD
GND
8
Power Supply
Resolution: 10mV/1mA
Accuracy: 0.2%
VPS
7
6
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
Jitter: < 25 ns
5
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
Figure 4. LIN Receiver Test with RX access Param 17, 18, 19, 20
1
RXD
5V
NC
2
EN
VSUP
3
NC
LIN
4
TXD
GND
8
Power Supply 1
Resolution: 10mV/1mA
Accuracy: 0.2%
7
6
5
VPS1
D
RBUS
Power Supply 2
Resolution: 10mV/1mA
Accuracy: 0.2%
VPS2
Measurement Tools
O-scope:
DMM
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Figure 5. VSUP_NON_OP Param 1154/56
10
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Parameter Measurement Information (continued)
1
NC
RXD
5V
2
VSUP
EN
3
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
T = 10 ms
Jitter: < 25 ns
NC
LIN
4
TXD
GND
8
Power Supply
Resolution: 10mV/1mA
Accuracy: 0.2%
VPS
7
6
RMEAS
5
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
Figure 6. Test Circuit for IBUS_LIM at Dominant State (Driver on) Param 12
1
RXD
2
EN
3
NC
4
TXD
NC
VSUP
LIN
GND
8
7
6
Power Supply
Resolution: 10mV/1mA
Accuracy: 0.2%
VPS
RMEAS = 499 Ÿ
5
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
Figure 7. Test Circuit for IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V, Param 13
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Parameter Measurement Information (continued)
1
8
NC
RXD
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
V
PS1
2
7
VSUP
EN
1 kŸ
6
3
NC
LIN
4
TXD
GND
Power Supply 2
Resolution: 10mV/1mA
VPS2 Accuracy: 0.2%
VPS2 2 V/s ramp
[8 V Æ 36 V]
5
V Drop across resistor
< 20 mV
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
Figure 8. Test Circuit for IBUS_PAS_rec Param 14
1
5V
RXD
NC
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
V
8
PS1
2
3
4
EN
NC
TXD
VSUP
LIN
GND
7
6
1 kŸ
Power Supply 2
Resolution: 10mV/1mA
VPS2 Accuracy: 0.2%
VPS2 2 V/s ramp
[0 V Æ 36 V]
5
V Drop across resistor
< 1V
Measurement Tools
O-scope:
DMM
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Figure 9. Test Circuit for IBUS_NO_GND Loss of GND
12
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Parameter Measurement Information (continued)
1
5V
NC
RXD
2
VSUP
EN
3
4
NC
LIN
TXD
GND
8
7
6
Power Supply 2
Resolution: 10mV/ 1mA
VPS Accuracy: 0.2%
10 kŸ
VPS 2 V/s ramp
[0 V Æ 36 V]
5
V Drop across resistor
< 1V
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
Figure 10. Test Circuit for IBUS_NO_BAT Loss of Battery
1
RXD
NC
8
5V
2
3
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
Jitter: < 25 ns
EN
VSUP
NC
LIN
TXD
GND
4
Power Supply 1
Resolution: 10mV/1mA
Accuracy: 0.2%
V
7
PS1
6
5
RMEAS
Power Supply 2
Resolution: 10mV/1mA
VPS2 Accuracy: 0.2%
Measurement Tools
O-scope:
DMM
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Figure 11. Test Circuit Slope Control and Duty Cycle Param 27, 28, 29, 30, 72, 73, 74, 75
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Parameter Measurement Information (continued)
tBIT
tBIT
RECESSIVE
D = 0.5
TXD (Input)
DOMINANT
THREC(MAX)
D112: 0.744 * VSUP
D312: 0.778 * VSUP
D124: 0.710 * VSUP
D324: 0.744 * VSUP
THDOM(MAX)
D112: 0.581 * VSUP
D312: 0.616 * VSUP
D124: 0.554 * VSUP
D324: 0.581 * VSUP
D212: 0.422 * VSUP
D412: 0.389 * VSUP
D224: 0.446 * VSUP
D424: 0.442 * VSUP
D212: 0.284 * VSUP
D412: 0.251 * VSUP
D224: 0.302 * VSUP
D424: 0.284 * VSUP
LIN Bus
Signal
THREC(MIN)
THDOM(MIN)
tBUS_DOM(MAX)
Thresholds
RX Node 1
VSUP
Thresholds
RX Node 2
tBUS_REC(MAX)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
D = tBUS_REC(MIN)/(2 x tBIT)
tBUS_DOM(MIN)
tBUS_REC(MIN)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
D = tBUS_REC(MIN)/(2 x tBIT)
Figure 12. Definition of Bus Timing Parameters
14
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Parameter Measurement Information (continued)
VCC
2.4 kŸ
1
RXD
NC
8
Power Supply
Resolution: 10mV/1mA
Accuracy: 0.2%
VPS
5V
2
20 pF
EN
VSUP
3
NC
LIN
4
TXD
GND
7
6
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
Jitter: < 25 ns
5
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
Figure 13. Propagation Delay Test Circuit; Param 31, 32
THREC(MAX)
LIN Bus
Signal
Thresholds
RX Node 1
THDOM(MAX)
VSUP
THREC(MIN)
Thresholds
RX Node 2
THDOM(MIN)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
trx_pdr(1)
trx_pdf(1)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
trx_pdr(2)
trx_pdf(2)
Copyright © 2017, Texas Instruments Incorporated
Figure 14. Propagation Delay
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Parameter Measurement Information (continued)
Wake Event
tMODE_CHANGE
EN
tMODE_CHANGE
Normal
Transition
Sleep
Standby
Transition
Mirrors Bus
Indetermin
ate Ignore
Floating
Wake Request
RXD = Low
Indeterminate Ignore
MODE
RXD
tNOMINT
Normal
Mirrors
Bus
Figure 15. Mode Transitions
EN
TXD
Weak Internal Pulldown
Weak Internal Pulldown
VSUP
LIN
RXD
Floating
MODE
Sleep
Normal
Figure 16. Wakeup Through EN
16
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Parameter Measurement Information (continued)
0.6 x VSUP
LIN
0.6 x VSUP
VSUP
0.4 x VSUP
0.4 x VSUP
t < tLINBUS
TXD
tLINBUS
Weak Internal Pulldown
EN
RXD
Floating
MODE
Sleep
Standby
Normal
Figure 17. Wakeup through LIN
RRXD
RXD
NC
CRXD
VSUP
100 nF
EN
RLIN
NC
TXD
LIN
CLIN
GND
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Figure 18. Test Circuit for AC Characteristics
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8 Detailed Description
8.1 Overview
The TLIN2029-Q1 is a Local Interconnect Network (LIN) physical layer transceiver, compliant to LIN 2.0, LIN 2.1,
LIN 2.2, LIN 2.2A and ISO/DIS 17987–4.2 standards, with integrated wake-up and protection features. The LIN
bus is a single wire bidirectional bus typically used for low speed in-vehicle networks using data rates from 2.4
kbps to 20 kbps. The TLIN2029-Q1LIN receiver works up to 100 kbps supporting in-line programming. The LIN
protocol data stream on the TXD input is converted by the TLIN2029-Q1 into a LIN bus signal using a currentlimited wave-shaping driver as outlined by the LIN physical layer specification. The receiver converts the data
stream to logic level signals that are sent to the microprocessor through the open-drain RXD pin. The LIN bus
has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In the recessive
state, the LIN bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode. No external pull-up
components are required for slave applications. Master applications require an external pull-up resistor (1 kΩ)
plus a series diode per the LIN specification. The TLIN2029-Q1 provides many protection features such as
immunity to ESD and high bus standoff voltage. The device also provides two methods to wake up: EN pin and
from the LIN bus.
8.2 Functional Block Diagram
VSUP/2
RXD
Comp
Filter
EN
45 kQ
Wake Up
State & Control
350 kQ
NC
Fault Detection
& Protection
Dominant State
Timeout
TXD
DR/
Slope
CTL
350 kQ
8.3 Feature Description
8.3.1 LIN (Local Interconnect Network) Bus
This high voltage input/output pin is a single wire LIN bus transmitter and receiver. The LIN pin can survive
transient voltages up to 60 V. Reverse currents from the LIN to supply (VSUP) are minimized with blocking diodes,
even in the event of a ground shift or loss of supply (VSUP).
18
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Feature Description (continued)
8.3.1.1 LIN Transmitter Characteristics
The transmitter has thresholds and AC parameters according to the LIN specification. The transmitter is a low
side transistor with internal current limitation and thermal shutdown. During a thermal shut-down condition, the
transmitter is disabled to protect the device. There is an internal pull-up resistor with a serial diode structure to
VSUP, so no external pull-up components are required for the LIN slave mode applications. An external pull-up
resistor and series diode to VSUP must be added when the device is used for a master node application.
8.3.1.2 LIN Receiver Characteristics
The receiver’s characteristic thresholds are proportional to the device supply pin in accordance to the LIN
specification.
The receiver is capable of receiving higher data rates (> 100 kbps) than supported by LIN or SAEJ2602
specifications. This allows the TLIN2029-Q1 to be used for high speed downloads at the end-of-line production or
other applications. The actual data rate achievable depends on system time constants (bus capacitance and
pullup resistance) and driver characteristics used in the system.
8.3.1.2.1 Termination
There is an internal pull-up resistor with a serial diode structure to VSUP, so no external pull-up components are
required for the LIN slave mode applications. An external pull-up resistor (1 kΩ) and a series diode to VSUP must
be added when the device is used for master node applications as per the LIN specification.
Figure 19 shows a Master Node configuration and how the voltage levels are defined
Simplified Transceiver
RXD
VLIN_Bus
VSUP
VSUP/2
Voltage drop across the
diodes in the pullup path
VSUP
VBattery
VSUP
Receiver
VLIN_Recessive
Filter
1 NŸ
45 NŸ
LIN
LIN
Bus
TXD
350 NŸ
GND
Transmitter
with slope control
VLIN_Dominant
t
Copyright © 2017, Texas Instruments Incorporated
Figure 19. Master Node Configuration with Voltage Levels
8.3.2 TXD (Transmit Input and Output)
TXD is the interface to the MCU’s LIN protocol controller or SCI and UART that is used to control the state of the
LIN output. When TXD is low the LIN output is dominant (near ground). When TXD is high the LIN output is
recessive (near VBattery). See Figure 19. The TXD input structure is compatible with microcontrollers with 3.3 V
and 5 V I/O. TXD has an internal pull-down resistor. The LIN bus is protected from being stuck dominant through
a system failure driving TXD low through the dominant state timer-out timer.
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Feature Description (continued)
8.3.3 RXD (Receive Output)
RXD is the interface to the MCU’s LIN protocol controller or SCI and UART, which reports the state of the LIN
bus voltage. LIN recessive (near VBattery) is represented by a high level on the RXD and LIN dominant (near
ground) is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage.
This allows the device to be used with 3.3 V and 5 V I/O microcontrollers. If the microcontroller’s RXD pin does
not have an integrated pullup, an external pullup resistor to the microcontroller I/O supply voltage is required. In
standby mode the RXD pin is driven low to indicate a wake up request from the LIN bus.
8.3.4 VSUP (Supply Voltage)
VSUP is the power supply pin. VSUP is connected to the battery through an external reverse-blocking diode
(Figure 19). If there is a loss of power at the ECU level, the device has extremely low leakage from the LIN pin,
which does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered
(ignition supplied) while the rest of the network remains powered (battery supplied).
8.3.5 GND (Ground)
GND is the device ground connection. The device can operate with a ground shift as long as the ground shift
does not reduce the VSUP below the minimum operating voltage. If there is a loss of ground at the ECU level, the
device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN
systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains
powered (battery supplied).
8.3.6 EN (Enable Input)
EN controls the operational modes of the device. When EN is high the device is in normal operating mode
allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low the device is put into sleep
mode and there are no transmission paths available. The device can enter normal mode only after wake up. EN
has an internal pull-down resistor to ensure the device remains in low power mode even if EN floats.
8.3.7 Protection Features
The TLIN2029-Q1 has several protection features that will now be described.
8.3.8 TXD Dominant Time Out (DTO)
During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application
failure, the LIN bus is protected by the dominant state timeout timer. This timer is triggered by a falling edge on
the TXD pin. If the low signal remains on TXD for longer than tDST, the transmitter is disabled, thus allowing the
LIN bus to return to recessive state and communication to resume on the bus. The protection is cleared and the
tDST timer is reset by a rising edge on TXD. The TXD pin has an internal pull-down to ensure the device fails to a
known state if TXD is disconnected. During this fault, the transceiver remains in normal mode (assuming no
change of stated request on EN), the transmitter is disabled, the RXD pin reflects the LIN bus and the LIN bus
pull-up termination remains on.
8.3.9 Bus Stuck Dominant System Fault: False Wake Up Lockout
The TLIN2029-Q1 contains logic to detect bus stuck dominant system faults and prevents the device from
waking up falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus.
If the bus is dominant, the wake up logic is locked out until a valid recessive on the bus “clears” the bus stuck
dominant, preventing excessive current use. Figure 20 and Figure 21 show the behavior of this protection.
20
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Feature Description (continued)
EN
LIN Bus
< tLINBUS
tLINBUS
< tLINBUS
Figure 20. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wakeup
EN
LIN Bus
tLINBUS
tLINBUS
tLINBUS
tCLEAR
< tCLEAR
Figure 21. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wakeup
8.3.10 Thermal Shutdown
The LIN transmitter is protected by limiting the current; however, if the junction temperature of the device
exceeds the thermal shutdown threshold, the device puts the LIN transmitter into the recessive state. Once the
over temperature fault condition has been removed and the junction temperature has cooled beyond the
hysteresis temperature, the transmitter is re-enabled, assuming the device remained in the normal operation
mode. During this fault, the transceiver remains in normal mode (assuming no change of state request on EN),
the transmitter is in recessive state, the RXD pin reflects the LIN bus and LIN bus pullup termination remains on.
8.3.11 Under Voltage on VSUP
The TLIN2029-Q1 contains a power on reset circuit to avoid false bus messages during under voltage conditions
when VSUP is less than UVSUP.
8.3.12 Unpowered Device and LIN Bus
In automotive applications some LIN nodes in a system can be unpowered (ignition supplied) while others in the
network remains powered by the battery. The TLIN2029-Q1 has extremely low unpowered leakage current from
the bus so an unpowered node does not affect the network or load it down.
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8.4 Device Functional Modes
The TLIN2029-Q1 has three functional modes of operation: normal, sleep, and standby. The next sections will
describe these modes as well as how the device moves between the different modes. Figure 22 graphically
shows the relationship while Table 1 shows the state of pins.
Table 1. Operating Modes
MODE
EN
RXD
LIN BUS
TERMINATION
TRANSMITTER
Sleep
Low
Floating
Weak Current Pullup
Off
Standby
Low
Low
45 kΩ (typical)
Off
Wake up event detected,
waiting on MCU to set EN
Normal
High
LIN Bus
Data
45 kΩ (typical)
On
LIN transmission up to 20 kbps
COMMENT
Unpowered System
VSUP < VSUP_UNDER
VSUP < VSUP_UNDER
VSUP > VSUP_UNDER
EN = High
VSUP > VSUP_UNDER
EN = Low
VSUP < VSUP_UNDER
VSUP < VSUP_UNDER
Standby Mode
Driver: Off
RXD: Low
Termination: 45 kŸ
Normal Mode
Driver: On
RXD: LIN Bus Data
Termination: 45 kŸ
EN = High
LIN Bus Wake up
Sleep Mode
Driver: Off
RXD: Floating
Termination: Weak pullup
EN = Low
EN = High
Copyright © 2017, Texas Instruments Incorporated
Figure 22. Operating State Diagram
8.4.1 Normal Mode
If the EN pin is high at power up the device will power up in normal mode and if low will power up in standby
mode. The EN pin controls the mode of the device. In normal operational mode the receiver and transmitter are
active and the LIN transmission up to the LIN specified maximum of 20 kbps is supported. The receiver detects
the data stream on the LIN bus and outputs it on RXD for the LIN controller. A recessive signal on the LIN bus is
a logic high and a dominant signal on the LIN bus is a logic low. The driver transmits input data from TXD to the
LIN bus. Normal mode is entered as EN transitions high while theTLIN2029-Q1 is in sleep or standby mode for >
tMODE_CHANGE plus tNOMINT.
22
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8.4.2 Sleep Mode
Sleep Mode is the power saving mode for the TLIN2029-Q1. Sleep mode is only entered when the EN pin is low
and from normal mode. Even with extremely low current consumption in this mode, the TLIN2029-Q1 can still
wake up from LIN bus through a wake up signal or if EN is set high for > tMODE_CHANGE. The LIN bus is filtered to
prevent false wake up events. The wake up events must be active for the respective time periods (tLINBUS).
The sleep mode is entered by setting EN low for longer than tMODE_CHANGE.
While the device is in sleep mode, the following conditions exist.
• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if
LIN is short circuited to ground). However, the weak current pull-up is active to prevent false wake up events
in case an external connection to the LIN bus is lost.
• The normal receiver is disabled.
• EN input and LIN wake up receiver are active.
8.4.3 Standby Mode
This mode is entered whenever a wake up event occurs through LIN bus while the device is in sleep mode. The
LIN bus slave termination circuit is turned on when standby mode is entered. Standby mode is signaled through
a low level on RXD. See Standby Mode Application Note for more application information.
When EN is set high for longer than tMODE_CHANGE while the device is in standby mode the device returns to
normal mode and the normal transmission paths from TXD to LIN bus and LIN bus to RXD are enabled.
8.4.4 Wake Up Events
There are two ways to wake up from sleep mode:
• Remote wake up initiated by the falling edge of a recessive (high) to dominant (low) state transition on LIN
bus where the dominant state is be held for tLINBUS filter time. After this tLINBUS filter time has been met and a
rising edge on the LIN bus going from dominant state to recessive state initiates a remote wake up event,
eliminating false wake ups from disturbances on the LIN bus or if the bus is shorted to ground.
• Local wake up through EN being set high for longer than tMODE_CHANGE.
8.4.4.1 Wake Up Request (RXD)
When the TLIN2029-Q1 encounters a wake up event from the LIN bus, RXD goes low and the device transitions
to standby mode until EN is reasserted high and the device enters normal mode. Once the device enters normal
mode, the RXD pin is releases the wake up request signal and the RXD pin then reflects the receiver output from
the LIN bus.
8.4.4.2 Mode Transitions
When the TLIN2029-Q1 is transitioning from normal to sleep or standby modes the device needs the time
tMODE_CHANGE to allow the change to fully propagate from the EN pin through the device into the new state. When
transitioning from sleep or standby to normal mode the device needs tMODE_CHANGE plus tNOMINT.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLIN2029-Q1 can be used as both a slave device and a master device in a LIN network. The device comes
with the ability to support both remote wake up request and local wake up request.
9.2 Typical Application
The device integrates a 45 kΩ pull-up resistor and series diode for slave applications. For master applications an
external 1 kΩ pull-up resistor with series blocking diode can be used. Figure 23 shows the device being used in
both master and slave applications.
VSUP
MASTER
NODE
VREG
VSUP
VDD
VSUP
VBAT
I/O
VDD
EN
2
NC
NC
8
3
7
Master Node
Pullup (3)
MCU w/o
pullup(2)
VDD I/O
1 kŸ
MCU
TLIN2029-Q1
LIN Controller
Or
SCU/UART(1)
LIN
1
200 pF
RXD
TXD
GND
6
LIN Bus
VDD
4
5
VSUP
SLAVE
NODE
VREG
VSUP
VDD
VDD
VSUP
VDD
I/O
EN
2
NC
NC
8
3
7
MCU w/o
pullup(2)
VDD I/O
MCU
TLIN2029-Q1
LIN Controller
Or
SCU/UART(1)
GND
6
LIN
1
200 pF
RXD
TXD
4
5
(1)
If RXD on MCU on LIN slave has internal pullup; no external pullup resistor is needed.
(2)
If RXD on MCU or LIN slave does not have an internal pullup requires external pullup resistor.
(3)
Master node applications require and external 1 kΩ pullup resistor and serial diode.
(4)
Decoupling capacitor values are system dependent but usually have 100 nF, 1 µF and ≥ 10 µF.
Figure 23. Typical LIN Bus
24
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Typical Application (continued)
9.2.1 Design Requirements
The RXD output structure is an open-drain output stage. This allows the TLIN2029-Q1 to be used with 3.3- V and
5-V I/O processor. If the RXD pin of the processor does not have an integrated pull-up, an external pull-up
resistor to the processor I/O supply voltage is required. The select external pull-up resistor value should be
between 1 kΩ to 10 kΩ. The VSUP pin of the device should be decoupled with a 100-nF capacitor as close to the
supply pin of the device as possible. The system should include 1 µF and ≥ 10 µF decoupling capacitors on VSUP
as per each application requirements.
9.2.2 Detailed Design Procedures
9.2.2.1 Normal Mode Application Note
When using the TLIN2029-Q1 in systems which are monitoring the RXD pin for a wake up request, special care
should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition period
between states as the receivers are switched. The application software should not look for an edge on the RXD
pin indicating a wake up request until tMODE_CHANGE. This is shown in Figure 15
9.2.2.2 Standby Mode Application Note
If the TLIN2029-Q1 detects an under voltage on VSUP the RXD pin transitions low and would signal to the
software that the TLIN2029-Q1 is in standby mode and should be returned to sleep mode for the lowest power
state.
9.2.2.2.1 TXD Dominant State Timeout Application Note
The maximum dominant TXD time allowed by the TXD dominant state time out limits the minimum possible data
rate of the device. The LIN protocol has different constraints for master and slave applications thus there are
different maximum consecutive dominant bits for each application case and thus different minimum data rates.
9.2.3 Application Curves
and show the propagation delay from the TXD pin to the LIN pin for both dominant to recessive and recessive to
dominant stated under lightly loaded conditions.
Figure 24. Recessive to Dominant Propagation
Figure 25. Dominant to Recessive Propagation
10 Power Supply Recommendations
The TLIN2029-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from 4 V to
45 V. A 100 nF decoupling capacitor should be placed as close to the VSUP pin of the device as possible.
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11 Layout
In order for your PCB design to be successful, start with design of the protection and filtering circuitry. Because
ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high frequency
layout techniques must be applied during PCB design. Placement at the connector also prevents these noisy
events from propagating further into the PCB and system.
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
Pin 1(RXD): The pin is an open drain output and requires and external pull-up resistor in the range of 1 kΩ
and 10 kΩ to function properly. If the microprocessor paired with the transceiver does not have an integrated
pull-up, an external resistor should be placed between RXD and the regulated voltage supply for the
microprocessor.
Pin 2 (EN): EN is an input pin that is used to place the device in a low power sleep mode. If this feature is not
used the pin should be pulled high to the regulated voltage supply of the microprocessor through a series
resistor, values between 1 kΩ and 10 kΩ. Additionally, a series resistor may be placed on the pin to limit
current on the digital lines in the case of an over voltage fault.
Pin 3 (NC): Not Connected.
Pin 4 (TXD): The TXD pin is the transmit input signal to the device from the microcontroller. A series resistor
can be placed to limit the input current to the device in the case of an over-voltage on this pin. A capacitor to
ground can be placed close to the input pin of the device to filter noise.
Pin 5 (GND): This is the ground connection for the device. This pin should be tied to the ground plane
through a short trace with the use of two vias to limit total return inductance.
Pin 6 (LIN): This pin connects to the LIN bus. For slave applications a 200 pF capacitor to ground is
implemented. For maser applications and additional series resistor and blocking diode should be placed
between the LIN pin and the VSUP pin. See Figure 23.
Pin 7 (VSUP): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed as close
to the device as possible.
Pin 8 (NC): Not Connected.
NOTE
All ground and power connections should be made as short as possible and use at least
two vias to minimize the total loop inductance.
26
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11.2 Layout Example
VDD
R1
RXD
1 RXD
U1
NC
8
VDD
2 EN
VSUP 7
C3
D2
R2
R3
EN
VSUP
LIN 6
D1
LIN
J1
C3
3 NC
R8
GND
Only needed for
the Master node
GND
GND
R6
C1
TXD
5 TXD
GND 5
GND
GND
Figure 26. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
LIN Standards:
• ISO/DIS 17987-1.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and
use case definition
• ISO/DIS 17987-4.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer
(EPL) specification 12V/24V
• SAEJ2602-1: LIN Network for Vehicle Applications
• LIN Specifications LIN 2.0, LIN 2.1, LIN 2.2 and LIN 2.2A
EMC requirements:
• SAEJ2962-1: Communication Transceivers Qualification Requirements - LIN
• ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge
• ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband
radiated electromagnetic energy - Part 4: Harness excitation methods
• ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1:
Definitions and general considerations
• ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical
transient transmission by capacitive and inductive coupling via lines other than supply lines
• IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz Part 4: Direct RF power injection method
• IEC 61000-4-2
• IEC 61967-4
• CISPR25
Conformance Test requirements:
• ISO/DIS 17987-7.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer
(EPL) conformance test specification
• SAEJ2602-2: LIN Network for Vehicle Applications Conformance Test
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
28
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12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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32
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PACKAGE OUTLINE
DRB0008F
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.05)
SECTION A-A
SECTION A-A
SCALE 30.000
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
EXPOSED
THERMAL PAD
1.6 0.05
(0.2) TYP
4
5
A
A
2X
1.95
2.4 0.05
8
1
6X 0.65
8X
PIN 1 ID
(OPTIONAL)
8X
0.5
0.3
0.35
0.25
0.1
0.05
C A B
C
4222121/C 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRB0008F
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.55)
( 0.2) VIA
TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222121/C 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRB0008F
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
8X (0.6)
METAL
TYP
1
8
8X (0.3)
(0.635)
SYMM
(1.07)
6X (0.65)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4222121/C 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLIN2029DQ1
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
TL029
TLIN2029DRBRQ1
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
TL029
TLIN2029DRBTQ1
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
TL029
TLIN2029DRQ1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
TL029
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jul-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLIN2029DRBRQ1
Package Package Pins
Type Drawing
SON
DRB
8
TLIN2029DRBTQ1
SON
DRB
TLIN2029DRQ1
SOIC
D
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
8
250
180.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jul-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLIN2029DRBRQ1
SON
DRB
8
3000
370.0
355.0
55.0
TLIN2029DRBTQ1
SON
DRB
8
250
220.0
205.0
50.0
TLIN2029DRQ1
SOIC
D
8
2500
366.0
364.0
50.0
Pack Materials-Page 2
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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