Texas Instruments | TUSB8043A Four-port USB 3.2 x1 Gen1 Hub | Datasheet | Texas Instruments TUSB8043A Four-port USB 3.2 x1 Gen1 Hub Datasheet

Texas Instruments TUSB8043A Four-port USB 3.2 x1 Gen1 Hub Datasheet
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TUSB8043A
SLLSF94 – JUNE 2019
TUSB8043A Four-port USB 3.2 x1 Gen1 Hub
1 Features
•
•
1
•
•
•
•
•
•
•
•
•
•
•
Four port USB 3.2 x1 Gen1 (5 Gbps) hub
USB 2.0 hub features
– Multi transaction translator (MTT) hub: four
transaction translators
– Two asynchronous endpoint buffers per
transaction translator
Supports battery charging:
– Supports D+/D- divider charging port (ACP1,
ACP2, and ACP3) when the upstream port is
unconnected or not configured
– Supports automatic mode for transition
between DCP or ACP modes when the
upstream port is unconnected
– Supports galaxy charging
– CDP mode (upstream port connected)
– DCP mode (upstream port unconnected)
– DCP mode complies with chinese
telecommunications industry standard YD/T
1591-2009
Supports Operation as a USB 3.2 x1 Gen1 or
USB 2.0 Compound Device
Per port or ganged power switching and overcurrent notification inputs
Supports four external downstream ports plus
internal USB 2.0-only port for USB HID to I2C
functionality
Internal downstream port for I2C control through
USB HID supports high-speed, full-speed
operation. Its speed matches that of the upstream
port.
Supports vendor requests to read and write I2C
and EEPROM read at 100 k and 400 k (Default)
I2C master supports clock stretching
OTP ROM, Serial EEPROM or I2C/SMBus slave
interface for custom configurations:
– VID and PID
– Port customizations
– Manufacturer and product strings (not by OTP
ROM)
– Serial number (not by OTP ROM)
Application Feature selection using pin selection
or EEPROM or I2C/SMBus slave interface
Provides 128-Bit Universally Unique Identifier
(UUID)
Supports on-board and in-system EEPROM
programming Via the USB 2.0 upstream port
•
•
•
Single clock input, 24-MHz crystal or oscillator
Downstream ports configurable to USB2.0 only
64-Pin QFN package (RGC)
2 Applications
Computer systems, docking stations, monitors,
set-top boxes
3 Description
The TUSB8043A is a four-port USB 3.2 x1 Gen1 (5
Gbps) hub. It provides simultaneous SuperSpeed
USB and high-speed/full-speed connections on the
upstream port and provides SuperSpeed USB, highspeed, full-speed, or low-speed connections on the
downstream ports. When the upstream port is
connected to an electrical environment that only
supports
high-speed
or
full-speed/low-speed
connections, SuperSpeed USB connectivity is
disabled on the downstream ports.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TUSB8043A
VQFN (64)
9.00 mm × 9.00 mm
TUSB8043AI
VQFN (64)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Diagram
USB 3.1 System Implementation
USB 3.x Host Controller
USB 2.0
Device
USB 2.0
HID to I2C
TUSB8043A
USB 3.x Hub
USB 1.1
Device
USB 2.0
Device
USB 2.0 Hub
USB 2.0
Device
USB 3.x
Device
USB 3.x
Device
USB 3.x
Device
USB 1.1
Device
USB 1.x Connection
USB 2.0 Connection
USB 2.0/3.x Device
USB 2.0 Device
USB 3.x Connection
USB 3.x Device
USB 1.x Device
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB8043A
SLLSF94 – JUNE 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
8
8.5 Register Maps ......................................................... 25
1
1
1
2
3
4
9
9
9.1 Application Information............................................ 40
9.2 Typical Application .................................................. 40
10 Power Supply Recommendations ..................... 49
10.1 TUSB8043A Power Supply ................................... 49
10.2 Downstream Port Power ....................................... 49
10.3 Ground .................................................................. 49
Absolute Maximum Ratings ...................................... 9
ESD Ratings.............................................................. 9
Recommended Operating Conditions....................... 9
Thermal Information .................................................. 9
Electrical Characteristics......................................... 10
Timing Requirements .............................................. 12
11 Layout................................................................... 50
11.1 Layout Guidelines ................................................. 50
11.2 Layout Examples................................................... 51
12 Device and Documentation Support ................. 53
12.1
12.2
12.3
12.4
12.5
Detailed Description ............................................ 14
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Application and Implementation ........................ 40
14
14
15
22
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
53
53
53
53
53
13 Mechanical, Packaging, and Orderable
Information ........................................................... 53
4 Revision History
2
DATE
REVISION
NOTES
June 2019
*
Preliminary release.
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5 Description (continued)
When the upstream port is connected to an electrical environment that only supports full-speed/low-speed
connections, SuperSpeed USB and high-speed connectivity are disabled on the downstream ports.
The TUSB8043A supports per port or ganged power switching and over-current protection, and supports battery
charging applications.
An individually port power controlled hub switches power on or off to each downstream port as requested by the
USB host. Also when an individually port power controlled hub senses an over-current event, only power to the
affected downstream port is switched off.
A ganged hub switches on power to all its downstream ports when power is required to be on for any port. The
power to the downstream ports is not switched off unless all ports are in a state that allows power to be removed.
Also when a ganged hub senses an over-current event, power to all downstream ports is switched off.
The TUSB8043A downstream ports provide support for battery charging applications by providing Battery
Charging Downstream Port (CDP) handshaking support. It also supports a Dedicated Charging Port (DCP) mode
when the upstream port is not connected. The DCP mode supports USB devices which support with the USB
Battery Charging, Galaxy Charging, and Chinese Telecommunications Industry Standard YD/T 1591-2009. In
addition when upstream port is unconnected, the TUSB8043A supports the divider charging port modes (ACPx
modes) and an automatic transition through all modes, starting with ACP3 and ending in DCP.
The TUSB8043A provides pin strap configuration for some features including battery charging support, and also
provides customization though OTP ROM, I2C EEPROM, or via an I2C/SMBus slave interface for PID, VID, and
custom port and phy configurations. Custom string support is also available when using an I2C EEPROM or the
I2C/SMBus slave interface.
The TUSB8043A supports programming of an attached EEPROM through its internal USB HID to I2C interface.
The device is available in a 64-pin RGC package and is offered in a commercial version (TUSB8043A) for
operation over the temperature range of 0°C to 70°C, and in an industrial version (TUSB8043AI) for operation
over the temperature range of –40°C to 85°C.
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6 Pin Configuration and Functions
USB_R1
VDD33
XI
XO
NC
USB_SSRXM_UP
USB_SSRXP_UP
VDD
USB_SSTXM_UP
USB_SSTXP_UP
USB_DM_UP
USB_DP_UP
VDD33
VDD
GRSTz
TEST
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RGC Package
64 Pin (VQFN)
(Top View)
USB_DP_DN1
1
48
USB_VBUS
USB_DM_DN1
2
47
OVERCUR2z
USB_SSTXP_DN1
3
46
OVERCUR1z
USB_SSTXM_DN1
4
45
AUTOENz/HS_SUSPEND
VDD
5
44
OVERCUR3z
USB_SSRXP_DN1
6
43
OVERCUR4z
USB_SSRXM_DN1
7
42
GANGED/SMBA2/HS_UP
VDD
8
41
PWRCTL_POL
USB_DP_DN2
9
40
FULLPWRMGMTz/SMBA1/SS_UP
USB_DM_DN2
10
39
SMBUSz/SS_SUSPEND
USB_SSTXP_DN2
11
38
SCL/SMBCLK
USB_SSTXM_DN2
12
37
SDA/SMBDAT
VDD
13
36
PWRCTL1/BATEN1
USB_SSRXP_DN2
14
35
PWRCTL2/BATEN2
USB_SSRXM_DN2
15
34
VDD33
VDD33
16
33
PWRCTL3/BATEN3
Thermal
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
USB_DP_DN3
USB_DM_DN3
USB_SSTXP_DN3
USB_SSTXM_DN3
VDD
USB_SSRXP_DN3
USB_SSRXM_DN3
USB_DP_DN4
USB_DM_DN4
USB_SSTXP_DN4
USB_SSTXM_DN4
VDD
USB_SSRXP_DN4
USB_SSRXM_DN4
VDD
PWRCTL4/BATEN4
Pad
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
Clock and Reset Signals
GRSTz
50
I, PU
Global power reset. This reset brings all of the TUSB8043A internal registers to their default
states. When GRSTz is asserted, the device is completely nonfunctional.
XI
62
I
Crystal input. This pin is the crystal input for the internal oscillator. The input may alternately
be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback
resistor is required between XI and XO.
4
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
61
O
Crystal output. This pin is the crystal output for the internal oscillator. If XI is driven by an
external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback
resistor is required between XI and XO.
USB_SSTXP_UP
55
O
USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_UP
56
O
USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_UP
58
I
USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_UP
59
I
USB SuperSpeed receiver differential pair (negative)
USB_DP_UP
53
I/O
USB High-speed differential transceiver (positive)
USB_DM_UP
54
I/O
USB High-speed differential transceiver (negative)
USB_R1
64
USB_VBUS
48
XO
USB Upstream Signals
I
Precision resistor reference. A 9.53-kΩ ±1% resistor should be connected between USB_R1
and GND.
I
USB upstream port power monitor. The VBUS detection requires a voltage divider. The signal
USB_VBUS must be connected to VBUS through a 90.9-KΩ ±1% resistor, and to ground
through a 10-kΩ ±1% resistor from the signal to ground.
USB Downstream Signals
USB_SSTXP_DN1
3
O
USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN1
4
O
USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN1
6
I
USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN1
7
I
USB SuperSpeed receiver differential pair (negative)
USB_DP_DN1
1
I/O
USB High-speed differential transceiver (positive)
USB_DM_DN1
2
I/O
USB High-speed differential transceiver (negative)
USB Port 1 Power On Control for Downstream Power/Battery Charging Enable. The pin is
used for control of the downstream power switch for Port 1. This pin be left unconnected if
power management is not implemented.
PWRCTL1/BATEN1
36
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value
I/O, PD of the battery charging support for Port 1 as indicated in the Battery Charging Support
register:
0 = Battery charging not supported
1 = Battery charging supported
USB Port 1 Over-Current Detection. This pin is typically connected to the over current output
of the downstream port power switch for Port 1.
0 = An over current event has occurred
OVERCUR1z
46
I, PU
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins
must be connected to the over current output of the power switch or circuit which detects the
over current conditions. For the case when another OVERCURz pin is used, this pin can be
left unconnected.
USB_SSTXP_DN2
11
O
USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN2
12
O
USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN2
14
I
USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN2
15
I
USB SuperSpeed receiver differential pair (negative)
USB_DP_DN2
9
I/O
USB High-speed differential transceiver (positive)
USB_DM_DN2
10
I/O
USB High-speed differential transceiver (negative)
USB Port 2 Power On Control for Downstream Power/Battery Charging Enable. The pin is
used for control of the downstream power switch for Port 2. This pin be left unconnected if
power management is not implemented.
PWRCTL2/BATEN2
35
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value
I/O, PD of the battery charging support for Port 2 as indicated in the Battery Charging Support
register:
0 = Battery charging not supported
1 = Battery charging supported
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
USB Port 2 Over-Current Detection. This pin is typically connected to the over current output
of the downstream port power switch for Port 2.
0 = An over current event has occurred
OVERCUR2z
47
I, PU
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins
must be connected to the over current output of the power switch or circuit which detects the
over current conditions. For the case when another OVERCURz pin is used, this pin can be
left unconnected.
USB_SSTXP_DN3
19
O
USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN3
20
O
USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN3
22
I
USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN3
23
I
USB SuperSpeed receiver differential pair (negative)
USB_DP_DN3
17
I/O
USB High-speed differential transceiver (positive)
USB_DM_DN3
18
I/O
USB High-speed differential transceiver (negative)
USB Port 3 Power On Control for Downstream Power/Battery Charging Enable. The pin is
used for control of the downstream power switch for Port 3. This pin be left unconnected if
power management is not implemented.
PWRCTL3/BATEN3
33
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value
I/O, PD of the battery charging support for Port 3 as indicated in the Battery Charging Support
register:
0 = Battery charging not supported
1 = Battery charging supported
USB Port 3 Over-Current Detection. This pin is typically connected to the over current output
of the downstream port power switch for Port 3.
0 = An over current event has occurred
OVERCUR3z
44
I, PU
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins
must be connected to the over current output of the power switch or circuit which detects the
over current conditions. For the case when another OVERCURz pin is used, this pin can be
left unconnected.
USB_SSTXP_DN4
26
O
USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN4
27
O
USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN4
29
I
USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN4
30
I
USB SuperSpeed receiver differential pair (negative)
USB_DP_DN4
24
I/O
USB High-speed differential transceiver (positive)
USB_DM_DN4
25
I/O
USB High-speed differential transceiver (negative)
USB Port 4 Power On Control for Downstream Power/Battery Charging Enable. The pin is
used for control of the downstream power switch for Port 4. This pin be left unconnected if
power management is not implemented.
PWRCTL4/BATEN4
32
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value
I/O, PD of the battery charging support for Port 4 as indicated in the Battery Charging Support
register:
0 = Battery charging not supported
1 = Battery charging supported
USB Port 4 Over-Current Detection. This pin is typically connected to the over current output
of the downstream port power switch for Port 4.
0 = An over current event has occurred
OVERCUR4z
43
I, PU
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins
must be connected to the over current output of the power switch or circuit which detects the
over current conditions. For the case when another OVERCURz pin is used, this pin can be
left unconnected.
I2C/SMBUS I2C Signals
6
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
I2C clock/SMBus clock. Function of pin depends on the setting of the SMBUSz input.
SCL/SMBCLK
38
I/O, PD
When SMBUSz = 1, this pin acts as the serial clock interface for an I2C EEPROM.
When SMBUSz = 0, this pin acts as the serial clock interface for an SMBus host.
Can be left unconnected if external interface not implemented.
I2C data/SMBus data. Function of pin depends on the setting of the SMBUSz input.
SDA/SMBDAT
37
I/O, PD
When SMBUSz = 1, this pin acts as the serial data interface for an I2C EEPROM.
When SMBUSz = 0, this pin acts as the serial data interface for an SMBus host.
Can be left unconnected if external interface not implemented.
I2C/SMBus mode select/SuperSpeed USB Suspend Status. The value of the pin is sampled
at the de-assertion of reset set I2C or SMBus mode as follows:
1 = I2C Mode Selected
SMBUSz/SS_SUSPEND
39
I/O, PU
0 = SMBus Mode Selected
Can be left unconnected if external interface not implemented.
After reset, this signal indicates the SuperSpeed USB Suspend status of the upstream port if
enabled through the stsOutputEn bit in the Additional Feature Configuration register. When
enabled, a value of 1 indicates the connection is suspended.
Test and Miscellaneous Signals
Full power management enable/SMBus address bit 1/SuperSpeed USB Connection Status
Upstream port.
The value of the pin is sampled at the de-assertion of reset to set the power switch control
follows:
0 = Power switching and over current inputs supported
1 = Power switching and over current inputs not supported
Full power management is the ability to control power to the downstream ports of the
TUSB8043A using PWRCTL[4:1]/BATEN[4:1].
FULLPWRMGMTz/FULL
AUTOz/SMBA1/SS_UP
40
I/O, PD
If BATENx = 1 on any port, full power management must be enabled so the value of the
terminal is sampled at the de-assertion to initialize the value of the FULLAUTOz bit.
When AUTOENz = 0 and FULLAUTOz = 0: all ACP modes are supported.
When AUTOENz = 0 and FULLAUTOz = 1:only highest current ACP mode is used in auto
mode.
When SMBus mode is enabled, this pin sets the value of the SMBus slave address bit 1.
Can be left unconnected if full power management and SMBus are not implemented.
After reset, this signal indicates the SuperSpeed USB connection status of the upstream port
if enabled through the stsOutputEn bit in the Additional Feature Configuration register. When
enabled a value of 1 indicates the upstream port is connected to a SuperSpeed USB capable
port.
Note: Power switching must be supported for battery charging applications.
Power Control Polarity.
PWRCTL_POL
41
The value of the pin is sampled at the de-assertion of reset to set the polarity of
I/O, PU PWRCTL[4:1].
0 = PWRCTL polarity is active low
1 = PWRCTL polarity is active high
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
Ganged operation enable/SMBus Address bit 2/HS Connection Status Upstream Port.
The value of the pin is sampled at the de-assertion of reset to set the power switch and over
current detection mode as follows:
0 = Individual power control supported when power switching is enabled
1 = Power control gangs supported when power switching is enabled
GANGED/SMBA2/HS_U
P
42
I/O, PD When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus slave
address bit 2.
After reset, this signal indicates the High-speed USB connection status of the upstream port if
enabled through the stsOutputEn bit in Additional Feature Configuration register. When
enabled, a value of 1 indicates the upstream port is connected to a High-speed USB capable
port.
Note: Individual power control must be enabled for battery charging applications.
Automatic Charge Mode Enable/HS Suspend Status.
The value of the pin is sampled at the de-assertion of reset to determine if automatic mode is
enabled as follows:
AUTOENz/HS_SUSPEN
D
45
I/O, PU
0 = Automatic Mode is enabled on ports that are enabled for battery charging when the
hub is unconnected. Please note that CDP is not supported on Port 1 when operating in
Automatic mode.
1 = Automatic Mode is disabled
This value is also used to set the autoEnz bit in the Battery Charging Support Register.
After reset, this signal indicates the High-speed USB Suspend status of the upstream port if
enabled through the stsOutputEn bit in Additional Feature Configuration register. When
enabled, a value of 1 indicates the connection is suspended.
TEST
This pin is reserved for factory test. For normal operation, this pin requires an external pull
down resistor to ground on PCB. Recommend 10k or stronger resistor.
49
I
VDD
5, 8,
13, 21,
28, 31,
51, 57
PWR
1.1-V power rail
VDD33
16, 34,
52, 63
PWR
3.3-V power rail
PWR
Ground. Thermal pad must be connected to ground.
Power and Ground Signals
VSS (Thermal Pad)
NC
8
60
—
No connect, leave floating
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply Voltage
Range
Voltager Range
Tstg
(1)
MIN
MAX
VDD Supply voltage range
-0.3
1.4
UNIT
V
VDD33 Supply voltage range
-0.3
3.8
V
USB_SSRXP_UP, USB_SSRXN_UP, SSRXP_DN[4:1],
USB_RXN_DP[4:1] and USB_VBUS terminals
-0.3
1,4
V
XI terminal
-0.3
2.45
V
All other terminals
-0.3
3.8
V
Storage temperature
-65
150
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
1.1V Supply voltage
0.99
1.1
1.26
V
VDD33
3.3V Supply voltage
3.0
3.3
3.6
V
0
1.155
V
USB_VBU
Voltage at USB_VBUS terminal.
S
TA
TUSB8043A Ambient temperature
0
70
°C
TA
TUSB8043AI Ambient temperature
-40
85
°C
TJ
Junction temperature
-40
105
°C
7.4 Thermal Information
TUSB8043A
THERMAL METRIC (1)
RGC
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
26
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
11.5
°C/W
RθJB
Junction-to-board thermal resistance
5.3
°C/W
ΨJT
Junction-to-top characterization parameter
0.2
°C/W
ΨJB
Junction-to-board characterization parameter
5.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low Power Modes
IDD_PWRO
VDD current after Power On (after reset)
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
18
mA
VDD33 current after Power On (after
reset)
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
2
mA
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
23
mA
VDD33 current when upstream port is
disconnected
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
2
mA
VDD current in Suspend
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
23
mA
VDD33 current in Suspend
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
2
mA
VDD current during SMbus programming.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
290
mA
VDD33 current during SMbus
programming
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
75
mA
VDD current upstream port connected to
IDD_3H_1S USB 3.0 Host, downstream port(s)
S_0HS_U12 connected to 1 SS device, and 0 HS
device. Links in U1/U2.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
220
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 1 SS device, and 0 HS
device. Links in U1/U2.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_3H_1S USB 3.0 Host, downstream port(s)
connected to 1 SS device, and 0 HS
S_0HS_U0
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
330
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 1 SS device, and 0 HS
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_3H_2S USB 3.0 Host, downstream port(s)
S_0HS_U12 connected to 2 SS devices, and 0 HS
device. Links in U1/U2
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
301
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 2 SS devices, and 0 HS
device. Links in U1/U2
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_3H_2S USB 3.0 Host, downstream port(s)
connected to 2 SS devices, and 0 HS
S_0HS_U0
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
460
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 2 SS devices, and 0 HS
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_3H_3S USB 3.0 Host, downstream port(s)
S_0HS_U12 connected to 3 SS devices, and 0 HS
device. Links in U1/U2
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
372
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 3 SS devices, and 0 HS
device. Links in U1/U2
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
N
IDD33_PW
RON
IDD_UPDIS VDD current when upstream port is
disconnected
C
IDD33_UP
DISC
IDD_SUSP
END
IDD33_SUS
PEND
Active Power Modes (US State / DS State)
IDD_SMBU
S
IDD33_SM
BUS
IDD33_3H_
1SS_0HS_
U12
IDD33_3H_
1SS_0HS_
U0
IDD33_3H_
2SS_0HS_
U12
IDD33_3H_
2SS_0HS_
U0
IDD33_3H_
3SS_0HS_
U12
10
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Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD current upstream port connected to
IDD_3H_3S USB 3.0 Host, downstream port(s)
connected to 3 SS devices, and 0 HS
S_0HS_U0
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
560
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 3 SS devices, and 0 HS
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_3H_4S USB 3.0 Host, downstream port(s)
S_0HS_U12 connected to 4 SS devices, and 0 HS
device. Links in U1/U2
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
467
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 4 SS devices, and 0 HS
device. Links in U1/U2
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_3H_4S USB 3.0 Host, downstream port(s)
connected to 4 SS devices, and 0 HS
S_0HS_U0
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
672
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 4 SS devices, and 0 HS
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_3H_1S USB 3.0 Host, downstream port(s)
connected to 1 SS device, and 1 HS
S_1HS_U0
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
372
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 1 SS devices, and 1 HS
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
84
mA
VDD current upstream port connected to
IDD_3H_1S USB 3.0 Host, downstream port(s)
connected to 2 SS device, and 2 HS
S_2HS_U0
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
480
mA
VDD33 current upstream port connected
to USB 3.0 Host, downstream port(s)
connected to 2 SS devices, and 2 HS
device. Links in U0.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
95
mA
VDD current upstream port connected to
IDD_2H_0S USB 2.0 Host, downstream port(s)
connected to 0 SS device, and 1 HS
S_1HS
device.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD33 current upstream port connected
IDD33_2H_ to USB 2.0 Host, downstream port(s)
connected to 0 SS devices, and 1 HS
0SS_1HS
device.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
45
mA
VDD current upstream port connected to
IDD_2H_0S USB 2.0 Host, downstream port(s)
connected to 0 SS device, and 4 HS
S_4HS
device.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
74
mA
VDD33 current upstream port connected
IDD33_2H_ to USB 2.0 Host, downstream port(s)
connected to 0 SS devices, and 4 HS
0SS_4HS
device.
VDD = 1.1V; VDD33 = 3.3V; TA = 25 °C;
76
mA
IDD33_3H_
3SS_0HS_
U0
IDD33_3H_
4SS_0HS_
U12
IDD33_3H_
4SS_0HS_
U0
IDD33_3H_
1SS_1HS_
U0
IDD33_3H_
1SS_2HS_
U0
3.3V I/O
VIH
(1)
High-level input voltage (1)
2
3.6
V
Applies to external inputs and bi-directional buffers
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Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
(1)
TYP
MAX
UNIT
VIL
Low-level input voltage
0
0.8
V
VI
Input voltage
0
3.6
V
VO
Output voltage (2)
0
3.6
V
tt
Input transition time (tRISE and tFALL)
25
ns
1.3 x
VDD33
V
(3)
VHYS
Input hysteresis
VOH
High-level output voltage
IOH = -4 mA
VOL
Low-level output voltage
IOH = 4 mA
IOZP
High-impedance output current with
internal pullup or pulldown resistor. (4)
VI = 0 to VDD33;
II
Input current (5)
VI = 0 to VDD33;
RPD
Internal pull-down resistance
13.5
19
RPU
Internal pull-up resistance
14.5
19
25
kΩ
(2)
(3)
(4)
(5)
2.4
V
-250
-15
0.4
V
250
µA
15
µA
27.5
kΩ
Applies to external outputs and bi-directional buffers
Applies to GRSTZ
Applies to pins with internal pullups/pulldowns.
Applies to external input buffers
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
Power-on timings. Refer to Figure 1
(1) (2)
td1
VDD stable before VDD33 stable.
td2
VDD and VDD33 before de-assertion of GRSTz.
tsu_io
Setup for MISC inputs.
thd_io
Hold for MISC inputs.
tVDD33_RAM
P
tVDD_RAMP
(1)
(2)
(3)
12
(3)
(3)
0
ms
3
ms
0.1
µs
0.1
µs
VDD33 supply ramp requirement.
0.2
100
ms
VDD supply ramp requirement.
0.2
100
ms
As long as GRSTz is de-asserted after both supplies are stable, there is no power-on relationship between VDD33 and VDD. If GRSTz is
only connected to a capacitor to GND, then VDD must be stable minimum of 10 µs before VDD33.
An active reset is required if the VDD33 supply is stable before VDD supply. This active reset shall meet the 3 ms power-up delay
counting from both power supplies stable to de-assertion of GRSTz.
MISC pins sampled at de-assertion of GRSTz: BATEN[4:1], AUTOENz, FULLPWRMGMTz, GANGED, SMBUSz, and PWRCTL_POL.
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ttd2
GRSTz
VDD33
td1
VDD
tSU_IO
tHD_IO
MISC_IO
Figure 1. Power-Up Timing Requirements
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8 Detailed Description
8.1 Overview
The TUSB8043A is a four-port USB 3.2 x1 Gen1 compliant hub. It provides simultaneous SuperSpeed USB and
high-speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed,
or low-speed connections on the downstream ports. When the upstream port is connected to an electrical
environment that only supports high-speed or full-speed/low-speed connections, SuperSpeed USB connectivity is
disabled on the downstream ports. When the upstream port is connected to an electrical environment that only
supports full-speed/low-speed connections, SuperSpeed USB and high-speed connectivity are disabled on the
downstream ports.
8.2 Functional Block Diagram
Power
Distribution
VBUS
Detect
USB 2.0 Hub
XI
SuperSpeed Hub
Oscilator
USB_SSTXM_DN4
USB_SSTXP_DN4
USB_SSRXM_DN4
USB_SSRXP_DN4
USB_SSTXM_DN3
USB_SSTXP_DN3
USB_SSRXM_DN3
USB_SSRXP_DN3
USB_SSTXM_DN2
USB_SSTXP_DN2
USB_SSRXM_DN2
USB_SSRXP_DN2
USB_SSTXM_DN1
USB_SSTXP_DN1
USB DM DN4
_ _
USB_DP_DN4
USB_ DM_ DN3
USB_DP_DN3
USB_DP_DN2
USB_DM_DN2
USB_DP_DN1
USB_DM_DN1
Clock
and
Reset
Distribution
USB_SSRXM_DN1
USB_SSRXP_DN1
XO
GRSTz
USB_SSTXM_UP
USB_SSTXP_UP
USB_SSRXM_UP
USB_SSRXP_UP
VDD
VSS
USB_VBUS
USB_DM_UP
USB_DP_UP
USB_R1
VDD33
TEST
HID
to
I2C
GANGED/SMBA2/HS_UP
FULLPWRMGMTz/SMBA1/SS_UP
PWRCTL_POL
SMBUSz/SS_SUSPEND
AUTOENz/HS_SUSPEND
SCL/SMBCLK
SDA/SMBDAT
OVERCUR1z
PWRCTL1/BATEN1
OVERCUR2z
PWRCTL2/BATEN2
GPIO
I2C
SMBUS
Control
Registers
OTP
ROM
OVERCUR3z
PWRCTL3/BATEN3
OVERCUR4z
PWRCTL4/BATEN4
14
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8.3 Feature Description
8.3.1 Battery Charging Features
The TUSB8043A provides support for USB Battery Charging (BC1.2) and custom charging. Battery charging
support may be enabled on a per port basis through the REG_6h(batEn[3:0]) or the BATEN[4:1] pins.
USB Battery charging support includes both Charging Downstream Port (CDP) and Dedicated Charging Port
(DCP) modes. The DCP mode is compliant with the Chinese Telecommunications Industry Standard YD/T 15912009. CDP is enabled when the upstream port has detected valid VBUS, configured, and host sets port power.
When the upstream port is not connected and battery charging support is enabled, the TUSB8043A enables
DCP mode once all other battery modes such as ACPx have failed or are disabled.
In addition to USB Battery charging (BC1.2), the TUSB8043A supports custom charging indications: Divider
Charging (ACP3, ACP2, ACP1 modes), and Galaxy compatible charging. These custom charging modes are
only supported when upstream port is unconnected and AUTOMODE is enabled. AUTOMODE can be enabled
either thru AUTOENz pin or from Reg_0Ah bit 1 (autoModeEnz) . When in AUTOMODE and upstream port is
disconnected, the port automatically transitions from ACP mode to the DCP mode depending on the portable
device connected. The divided mode places a fixed DC voltage on the ports DP and DM signals which allows
some devices to identify the capabilities of the charger. The default divider mode indicates support for up to 10W
(ACP3). The divider mode can be configured to report a lower-current setting (up to 5 W) through REG_0Ah
(HiCurAcpModeEn).
When the upstream port is not connected and battery charging support is enabled for a port, the TUSB8043A
drives the port power enable active. If AUTOMODE is disabled, then DCP mode is used. If AUTOMODE is
enabled and fully automatic mode is disabled (FullAutoEn bit is cleared (Reg_25h Bit 0) or FULLAUTOz pin = 0),
then TUSB8043A starts with highest enabled divider current mode (ACPx). The TUSB8043A remains in highest
current mode as long as a pull-up is not detected on DP pin. If an pull-up is detected on DP pin, then
TUSB8043A drives the port power enable inactive and switch to Galaxy mode, if enabled, or to DCP mode if
Galaxy mode is disabled. The TUSB8043A again drives the port power enable active. The TUSB8043A remains
in Galaxy mode as long as no pull-up is detected on DP pin. If an pull-up is detected on DP pin, then
TUSB8043A drives the port power enable inactive and transition to DCP mode. The TUSB8043A again drives
the port power enable active. In DCP mode, the TUSB8043A looks for a pull-up detected on DP pin or RxVdat. If
a pull-up or RxVdat is detected on DP, the TUSB8043A remains in DCP mode. If no pull-up or RxVdat is
detected on DP pin after 2 seconds, the TUSB8043A drives the port power enable inactive and transition back to
ACPx mode. This sequence repeats until upstream port is connected.
When Automatic mode is enabled and full automatic mode is enabled (FullAutoEn Reg_25h bit 0 is set or
FULLAUTOz pin = 1), TUSB8043A performs same sequence described in previous paragraph with the addition
of attempting all supported ACPx modes before sequencing to Galaxy Mode (if enabled) or DCP mode.
The supported battery charging modes when TUSB8043A configured for SMBus or external EEPROM is detailed
in Battery Charging Modes with SMBus/EEPROM Table.
The supported battery charging modes when TUSB8043A configured for I2C but without an external EEPROM is
determined by the sampled state of the pins. These modes are detailed in Battery Charging Modes without
EEPROM Table.
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Feature Description (continued)
batEn[n] Reg_06h Bits 3:0
Upstream VBUS
HiCurAcpMode En Reg_0Ah Bit 4
autoModeEnz Reg_0Ah Bit 1
FullAutoEn Reg_25h Bit 0
Galaxy_Enz Reg_25h Bit 1
Table 1. TUSB8043A Battery Charging Modes with SMBus or I2C EEPROM
Battery Charging Mode Port x
(x = n + 1)
0
Don’t Care
Don't Care
Don’t Care
Don't Care
Don't Care
No Charging support
1
> 4V
Don't Care
Don't Care
Don't Care
Don't Care
CDP
1
< 4V
Don't Care
1
Don't Care
Don't Care
DCP
1
< 4V
Don't Care
0
1
1
AUTOMODE enabled. Sequences through all ACPx modes and DCP
Alternate ACP3, ACP2, ACP1, DCP
1
<4V
0
0
0
1
AUTOMODE enabled. Sequences between ACP2 and DCP.
Alternate ACP2, DCP
1
< 4V
1
0
0
1
AUTOMODE enabled. Sequences between ACP3 and DCP.
Alternate ACP3, DCP
1
< 4V
Don't Care
0
1
0
AUTOMODE enabled with Galaxy compatible charging support.
Alternate ACP3, ACP2, ACP1, Galaxy, DCP
1
< 4V
0
0
0
0
AUTOMODE enabled with Galaxy compatible charging support.
Alternate ACP2, Galaxy, DCP
1
< 4V
1
0
0
0
AUTOMODE enabled with Galaxy compatible charging support.
Alternate ACP3, Galaxy, DCP
16
BATEN[3:0] pins
Upstream VBUS
AUTOENz pin
FULLAUTOz pin
Table 2. TUSB8043A Battery Charging Modes without EEPROM
Battery Charging Mode Port x
(x = n + 1)
0
Don’t Care
Don’t Care
Don't Care
No Charging support
1
> 4V
Don't Care
Don't Care
CDP
1
< 4V
1
0
DCP
1
< 4V
0
0
AUTOMODE enabled with Galaxy compatible charging support. Sequences
through all ACPx modes.
Alternate ACP3, ACP2, ACP1, Galaxy, DCP.
1
< 4V
0
1
AUTOMODE enabled with Galaxy compatible charging support.
Alternate ACP3, Galaxy, DCP
1
< 4V
1
1
AUTOMODE enabled. Sequences through all ACPx modes.
Alternate ACP3, ACP2, ACP1, DCP.
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8.3.2
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USB Power Management
The TUSB8043A can be configured for power switched applications using either per-port (Full power managed)
or ganged power-enable controls and over-current status inputs. When battery charge is enabled, the
TUSB8043A always functions in full power managed.
Power switch support is enabled by REG_5h (fullPwrMgmtz) and the per-port or ganged mode is configured by
REG_5h(ganged).
The TUSB8043A supports both active high and active low power-enable controls. The PWRCTL[4:1] polarity is
configured by REG_Ah(pwrctlPol). The power control polarity can also be selected by the PWRCTL_POL pin.
8.3.3 I2C Programming Support Using Internal HID to I2C Interface
The TUSB8043A I2C programming mode is supported using class-specific requests through the HID interface.
The HID embedded port is numbered 1 greater than the highest numbered exposed port. The internal HID to I2C
function of the TUSB8043A does not have an interrupt OUT endpoint. The TUSB8043A supports GET REPORT
(Input) through the HID interrupt and control endpoints. The GET REPORT (Feature) and SET REPORT (Output)
occurs through the control endpoint.
Table 3. HID Requests I2C Programming Support
COMMAND
bmRequestType
bRequest
wValue
wIndex
wLength
DATA
Setup field Offset
Offset = 0
Offset = 1
Offset = 2
Offset = 4
Offset = 6
N/A
0000H
Report Length
Report
0000H
Report Length
Report
GET REPORT
A1H
01H
0100H – input
0300H - feature
SET REPORT
21H
09H
0200H – output
Other HID class specific requests are optional and not supported (SET IDLE, SET PROTOCOL, GET IDLE, GET
PROTOCOL) . Also report IDs are not required since all requests are not interleaved.
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8.3.3.1 SET REPORT (Output)
Report length includes overhead bytes (1 byte of opcode, 1 byte of device address and 2 bytes of data length)
and must match the number of bytes sent in the data stage or the request is stalled.
• 1-byte opcode
– 8'b0000xy01 read I2C
– 8'b0000xy10 write I2C with stop
– 8'b0000xy11 write I2C without stop (use to set sub-address prior to read)
– Bit 2 (y) when set forces 100 kHz I2C.
– Bit 3 (x) when set disables EP1. When EP1 is disabled, EP1 will always NAK and EP0 should be used for
Get Report.
• 1-byte I2C slave (7-bit) address
• 2-byte I2C transaction data length
• "length" bytes of Data for a write, but none for a read.
Set Report status stage reports only the status of the receipt and validity of the request, not the status of the I2C
transaction. As long as the fields construct a valid request, the status stage is Acked by a null packet. Otherwise,
it is STALLed. For example, if the report_length does not match the amount of data sent before the status stage
or the wLength does not match the number of bytes of data sent in the data stage, the status stage is STALLed.
Software shall ensure properly formatted commands and data responses. The sum of the start address and
wLength shall be less than the total size of the address range of the target device in a properly formatted
command. Hardware shall wrap any data addresses above FFFFh and shall discard any data transmitted greater
than wLength and return STALL. A STALL is returned if opcode is 00h.
The I2C master that performs the I2C reads and writes initiated through USB HID interface supports clock
stretching. It operates at 400 kHz by default, but can be configured for 100 kHz through eFuse or register or by
opcode.
If the TUSB8043A is suspended (L2) by the USB host, the USB HID interface must enter suspend, but the I2C
master shall remain active while attempting to complete an active I2C write request. An active I2C read request
may be aborted if the TUSB8043A enters USB suspend state. Per the USB specification, the USB host should
not suspend the HID interface while an I2C read or write is still in progress. The USB HID interface shall refuse
requests to enter USB 2.0 sleep mode (L1) while an I2C read or write is in progress.
8.3.3.2 GET REPORT (Feature)
This HID Report is return a 2-byte constant (0x82FF) which can be used to identify compatible HID devices even
if the customer changes the VID/PID.
8.3.3.3 GET REPORT (Input)
A report length of one reports the status byte only. To receive a report with data, the report length must be the
length of the data, plus one byte for status and two bytes for the length field.
• 1-byte Status
– 0 Success
– 1 Fail — timeout (35 ms)
– 2 Fail — Address nak
– 3 Fail — data nak
• 2-byte length
• "length" bytes of Data for a read, but not for a write.
A Get Report (input) request is required for both read and write. The interrupt and control endpoint will NAK until
the I2C transaction is complete, so that it can report length, data for a read, and final status.
18
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8.3.4 One Time Programmable (OTP) Configuration
The TUSB8043A allows device configuration through one time programmable non-volatile memory (OTP). The
programming of the OTP is supported using vendor-defined USB device requests. For details using the OTP
features please contact your TI representative.
Table 4 provides a list features which may be configured using the OTP.
Table 4. OTP Configurable Features
CONFIGURATION REGISTER
OFFSET
BIT FIELD
DESCRIPTION
REG_01h
[7:0]
Vendor ID LSB
REG_02h
[7:0]
Vendor ID MSB
REG_03h
[7:0]
Product ID LSB
REG_04h
[7:0]
Product ID MSB
REG_07h
[0]
Port removable configuration for downstream ports 1. OTP
configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 =
removable.
REG_07h
[1]
Port removable configuration for downstream ports 2. OTP
configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 =
removable.
REG_07h
[2]
Port removable configuration for downstream ports 3. OTP
configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 =
removable.
REG_07h
[3]
Port removable configuration for downstream ports 4. OTP
configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 =
removable.
REG_08h
[3:0]
REG_0Ah
[1]
Battery Charger Automatic Mode enable.
REG_0Ah
[4]
High-current divider mode enable.
REG_0Bh
[0]
USB 2.0 port polarity configuration for upstream port.
REG_0Bh
[1]
USB 2.0 port polarity configuration for downstream ports 1.
REG_0Bh
[2]
USB 2.0 port polarity configuration for downstream ports 2.
REG_0Bh
[3]
USB 2.0 port polarity configuration for downstream ports 3.
REG_0Bh
[4]
USB 2.0 port polarity configuration for downstream ports 4.
REG_25h
[4:0]
Device Configuration Register 3
REG_26h
[3:0]
USB2.0 Only Port Register
REG_F0h
[3:1]
USB BC power switch power off duration during automode.
Port used Configured register.
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8.3.5 Clock Generation
The TUSB8043A accepts a crystal input to drive an internal oscillator or an external clock source. If a clock is
provided to XI instead of a crystal, XO is left open. Otherwise, if a crystal is used, the connection needs to follow
the guidelines below. Since XI and XO are coupled to other leads and supplies on the PCB, it is important to
keep them as short as possible and away from any switching leads. It is also recommended to minimize the
capacitance between XI and XO. This can be accomplished by shielding C1 and C2 with the clean ground lines.
R1
1M
Y1
XI
24 MHz
CLOCK
XO
CL1
CL2
Figure 2. TUSB8043A Clock
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8.3.6 Crystal Requirements
The crystal must be fundamental mode with load capacitance of 12 pF - 24 pF and frequency stability rating of
±100 PPM or better. To ensure proper startup oscillation condition, a maximum crystal equivalent series
resistance (ESR) of 50 Ω is recommended. A parallel load capacitor should be used if a crystal source is used.
The exact load capacitance value used depends on the crystal vendor. Refer to application note Selection and
Specification for Crystals for Texas Instruments USB2.0 devices (SLLA122) for details on how to determine the
load capacitance value.
8.3.7 Input Clock Requirements
When using an external clock source such as an oscillator, the reference clock should have a ±100 PPM or
better frequency stability and have less than 50-ps absolute peak to peak jitter or less than 25-ps peak to peak
jitter after applying the USB 3.2 Gen1 jitter transfer function. XI should be tied to the 1.8-V clock source and XO
should be left floating.
8.3.8 Power-Up and Reset
The TUSB8043A does not have specific power sequencing requirements with respect to the core power (VDD)
or I/O and analog power (VDD33) as long as GRSTz is held in an asserted state while supplies ramp. The core
power (VDD) or I/O power (VDD33) may be powered up for an indefinite period of time while the other is not
powered up if all of these constraints are met:
• All maximum ratings and recommended operating conditions are observed.
• All warnings about exposure to maximum rated and recommended conditions are observed, particularly
junction temperature. These apply to power transitions as well as normal operation.
• Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of the
device.
• Bus contention while VDD33 is powered down may violate the absolute maximum ratings.
A supply bus is powered up when the voltage is within the recommended operating range. It is powered down
when it is below that range, either stable or in transition.
A minimum reset duration of 3 ms is required. This is defined as the time when the power supplies are in the
recommended operating range to the de-assertion of GRSTz. This can be generated using programmable-delay
supervisory device or using an RC circuit. When a RC circuit is used, the external capacitor size chosen must be
large enough to meet the 3ms minimum duration requirement. The R of the RC circuit is the internal RPU.
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8.4 Device Functional Modes
8.4.1 External Configuration Interface
The TUSB8043A supports a serial interface for configuration register access. The device may be configured by
an attached I2C EEPROM or accessed as a slave by an external SMBus master. The external interface is
enabled when both the SCL/SMBCLK and SDA/SMBDAT pins are pulled up to 3.3 V at the de-assertion of reset.
The mode, I2C master or SMBus slave, is determined by the state of SMBUSz/SS_SUSPEND pin at reset. With
the integrated USB HID to I2C master, the I2C interface can also be used to program an external EEPROM or
perform updates of an external MCU's firmware.
8.4.2 I2C EEPROM Operation
The TUSB8043A supports a single-master, standard mode (100 KHz) or fast mode (400KHz) connection to a
dedicated I2C EEPROM when the I2C interface mode is enabled. In I2C mode, the TUSB8043A reads the
contents of the EEPROM at bus address 1010000b using 7-bit addressing starting at address 0. The
TUSB8043A reads the entire EEPROM contents using a single burst read transaction. The burst read transaction
ends when the address reaches FFh.
If the value of the EEPROM contents at address byte 00h equals 55h, the TUSB8043A loads the configuration
registers according to the EEPROM map. If the first byte is not 55h, the TUSB8043A exits the I2C mode and
continues execution with the default values in the configuration registers. The hub is not connect on the upstream
port until the configuration is completed.
NOTE
The bytes located above offset Ah are optional. The requirement for data in those
addresses is dependent on the options configured in the Device Configuration, and Device
Configuration 2 registers.
The minimum size I2C EEPROM required is 2Kbit.
For details on I2C operation refer to the UM10204 I2C-bus Specification and User Manual.
8.4.3 Port Configuration
The TUSB8043A port configurations can be selected by registers or efuse. The Port Used Configuration register
(USED[3:0]) define how many ports can possibly be reported by the hub. The device removable configuration
register (RMBL[3:0]) define if the ports that USB 3.2 are reported as used have permanently connected devices
or not. The USB 2.0 Only Port register (USB2_ONLY[3:0]) define whether or not a used port is reported as part
of the USB 2.0 hub or both the USB2.0 and SS hubs. The USB2_ONLY field enables the USB2.0 port even if the
corresponding USED bit is low. The internal HID port will always be the highest number USB2.0 port. Table 5
shows examples of the possible combinations.
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Device Functional Modes (continued)
Table 5. TUSB8043A Downstream Port Configuration Examples
USED[3:0]
RMBL[3:0]
USB2_ONLY
[3:0]
Reported Port Configuration
Physical to Logical Port mapping
Physical1 => Logical Port1 for USB 3.2 and USB2.0.
1111
1111
0000
4 Port USB 3.2 Hub
5 Port USB2.0 Hub
Port 5 is permanently attached HID
Physical2 => Logical Port2 for USB 3.2 and USB2.0.
Physical3 => Logical Port3 for USB 3.2 and USB2.0.
Physical4 => Logical Port4 for USB 3.2 and USB2.0.
Physical5 => Logical Port5 for USB2.0.
Physical1 Not used.
1110
1111
0000
3 Port USB 3.2 Hub
4 Port USB2.0 Hub
Port 4 is permanently attached HID
Physical2 => Logical Port1 for USB 3.2 and USB2.0.
Physical3 => Logical Port2 for USB 3.2 and USB2.0.
Physical4 => Logical Port3 for USB 3.2 and USB2.0.
Physical5 => Logical Port4 for USB 2.0.
Physical1 Not used.
1100
0111
0000
2 Port USB 3.2 Hub
3 Port USB2.0 hub with permanently attached
device on Port 2
Port 3 is a permanently attached HID
Physical2 Not used.
Physical3 => Logical Port1 for USB 3.2 and USB2.0.
Physical4 => Logical Port2 for USB 3.2 and USB2.0.
Physical5 => Logical Port3 for USB2.0.
Physical1 => Logical Port1 for USB 3.2 and USB2.0.
0011
1111
0010
1 Port USB 3.2 Hub
3 Port USB 2.0 Hub
Port 3 is a permanently attached HID
Physical2 => Logical Port2 for USB2.0.
Physical3 Not Used.
Physical4 Not used.
Physical5 => Logical Port3 for USB2.0.
Physical1 Not used.
1000
1111
0010
1 Port USB 3.2 Hub
3 Port USB 2.0 Hub
Port 3 is a permanently attached HID
Physical2 => Logical Port2 for USB2.0.
Physical3 Not used
Physical4 => Logical Port1 for USB 3.2 and USB2.0.
Physical5 => Logical Port3 for USB2.0.
Physical1 => Logical Port1 for USB 3.2 and USB2.0.
1111
1111
1110
1 Port USB 3.2 Hub
5 Port USB 2.0 Hub
Port 5 is a permanently attached HID
Physical2 => Logical Port2 for USB2.0.
Physical3 => Logical Port3 for USB2.0.
Physical4 => Logical Port4 for USB2.0.
Physical5 => Logical Port5 for USB2.0.
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8.4.4 SMBus Slave Operation
When the SMBus interface mode is enabled, the TUSB8043A supports read block and write block protocols as a
slave-only SMBus device.
The TUSB8043A slave address is 1000 1xyz, where:
• x is the state of GANGED/SMBA2/HS_UP pin at reset,
• y is the state of FULLPWRMGMTz/SMBA1/SS_UP pin at reset, and
• z is the read/write bit; 1 = read access, 0 = write access.
For details on SMBus requirements, refer to the System Management Bus Specification.
NOTE
If the TUSB8043A is addressed by a host using an unsupported protocol it does not
respond. The TUSB8043A waits indefinitely for configuration by the SMBus host and
doesnot connect on the upstream port until the SMBus host indicates configuration is
complete by clearing the CFG_ACTIVE bit.
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8.5 Register Maps
8.5.1 Configuration Registers
The internal configuration registers are accessed on byte boundaries. The configuration register values are
loaded with defaults but can be over-written when the TUSB8043A is in I2C or SMBus mode. Refer to Table 4 for
registers configurable from OTP.
Table 6. TUSB8043A Register Map
BYTE
ADDRESS
CONTENTS
EEPROM CONFIGURABLE
00h
ROM Signature Register
Yes
01h
Vendor ID LSB
Yes
02h
Vendor ID MSB
Yes
03h
Product ID LSB
Yes
04h
Product ID MSB
Yes
05h
Device Configuration Register
Yes
06h
Battery Charging Support Register
Yes
07h
Device Removable Configuration Register
Yes
08h
Port Used Configuration Register
Yes
09h
Reserved. Must default to 00h.
Yes
0Ah
Device Configuration Register 2
Yes
0Bh
USB 2.0 Port Polarity Control Register
Yes
0Ch-0Fh
Reserved
No
10h-1Fh
UUID Byte [15:0]
No
20h-21h
LangID Byte [1:0]
Yes
22h
Serial Number Length
Yes
23h
Manufacturer String Length
Yes
24h
Product String Length
Yes
25h
Device Configuration Register 3
Yes
26h
USB 2.0 Only Port Register
Yes
27h-2Eh
Reserved
Yes
2Fh
Reserved
No
30h-4Fh
Serial Number String Byte [31:0]
Yes
50h-8Fh
Manufacturer String Byte [63:0]
Yes
90h-CFh
Product String Byte [63:0]
Yes
D0h-D4h
Reserved
Yes, but do not change default.
D5h-D7h
Reserved
No
D8h-DCh
Reserved
Yes, but do not change default.
DDh-EFh
Reserved
No
F0h
Additional Features Configuration Register
Yes
F1h-F7h
Reserved
No
F8h
SMBus Device Status and Command Register
No
F9h - FFh
Reserved
No
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8.5.2 ROM Signature Register
Figure 3. Register Offset 0h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Table 7. Bit Descriptions – ROM Signature Register
Bit
7:0
Field
romSignature
Type
Description
RW
ROM Signature Register. This register is used by the TUSB8043A in
I2C mode to validate the attached EEPROM has been programmed.
The first byte of the EEPROM is compared to the mask 55h and if not
a match, the TUSB8043A aborts the EEPROM load and executes with
the register defaults.
8.5.3 Vendor ID LSB Register
Figure 4. Register Offset 1h
Bit No.
Reset State
7
0
6
1
5
0
4
1
3
0
2
0
1
0
0
1
Table 8. Bit Descriptions – Vendor ID LSB Register
Bit
7:0
Field
vendorIdLsb
Type
Description
RO/RW
Vendor ID LSB. Least significant byte of the unique vendor ID
assigned by the USB-IF; the default value of this register is 51h
representing the LSB of the TI Vendor ID 0451h. The value may be
over-written to indicate a customer Vendor ID.
Value used for this field is the non-zero value written by
EEPROM/SMBus to both PID and VID. If a zero value is written by
EEPROM/SMbus to both PID and VID, then value used for this field is
the non-zero value from OTP. If a zero value is written by OTP, then
value used for this field is 51h.
8.5.4 Vendor ID MSB Register
Figure 5. Register Offset 2h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
1
1
0
0
0
Table 9. Bit Descriptions – Vendor ID MSB Register
Bit
7:0
26
Field
vendorIdMsb
Type
Description
RO/RW
Vendor ID MSB. Most significant byte of the unique vendor ID
assigned by the USB-IF; the default value of this register is 04h
representing the MSB of the TI Vendor ID 0451h. The value may be
over-written to indicate a customer Vendor ID.
Value used for this field is the non-zero value written by
EEPROM/SMBus to both PID and VID. If a zero value is written by
EEPROM/SMbus to both PID and VID, then value used for this field is
the non-zero value from OTP. If a zero value is written by OTP, then
value used for this field is 04h.
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8.5.5 Product ID LSB Register
Figure 6. Register Offset 3h
Bit No.
Reset State
7
0
6
1
5
0
4
0
3
0
2
0
1
0
0
0
Table 10. Bit Descriptions – Product ID LSB Register
Bit
7:0
Field
productIdLsb
Type
Description
RO/RW
Product ID LSB. Least significant byte of the product ID assigned by
Texas Instruments and reported in the SuperSpeed Device descriptor.
the default value of this register is 40h representing the LSB of the
SuperSpeed product ID assigned by Texas Instruments The value
reported in the USB 2.0 Device descriptor is the value of this register
bit wise XORed with 00000010b. The value may be over-written to
indicate a customer product ID.
Value used for this field is the non-zero value written by
EEPROM/SMBus to both PID and VID. If a zero value is written by
EEPROM/SMbus to both PID and VID, then value used for this field is
the non-zero value from OTP. If a zero value is written by OTP, then
value used for this field is 40h .
8.5.6 Product ID MSB Register
Figure 7. Register Offset 4h
Bit No.
Reset State
7
1
6
0
5
0
4
0
3
0
2
0
1
1
0
1
Table 11. Bit Descriptions – Product ID MSB Register
Bit
7:0
Field
productIdMsb
Type
Description
RO/RW
Product ID MSB. Most significant byte of the product ID assigned by
Texas Instruments; the default value of this register is 83h representing
the MSB of the product ID assigned by Texas Instruments. The value
may be over-written to indicate a customer product ID.
Value used for this field is the non-zero value written by
EEPROM/SMBus to both PID and VID. If a zero value is written by
EEPROM/SMbus to both PID and VID, then value used for this field is
the non-zero value from OTP. If a zero value is written by OTP, then
value used for this field is 83h.
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8.5.7 Device Configuration Register
Figure 8. Register Offset 5h
Bit No.
Reset State
7
0
6
0
5
0
4
1
3
X
2
X
1
0
0
0
Table 12. Bit Descriptions – Device Configuration Register
Bit
7
6
customStrings
customSernum
Type
Description
RW
Custom strings enable. This bit controls the ability to write to the
Manufacturer String Length, Manufacturer String, Product String
Length, Product String, and Language ID registers
0 = The Manufacturer String Length, Manufacturer String, Product
String Length, Product String, and Language ID registers are read only
1 = The Manufacturer String Length, Manufacturer String, Product
String Length, Product String, and Language ID registers may be
loaded by EEPROM or written by SMBus
The default value of this bit is 0.
RW
Custom serial number enable. This bit controls the ability to write to the
serial number registers.
0 = The Serial Number String Length and Serial Number String
registers are read only
1 = Serial Number String Length and Serial Number String registers
may be loaded by EEPROM or written by SMBus
The default value of this bit is 0.
5
u1u2Disable
RW
U1 U2 Disable. This bit controls the U1/U2 support.
0 = U1/U2 support is enabled
1 = U1/U2 support is disabled, the TUSB8043A will not initiate or
accept any U1 or U2 requests on any port, upstream or downstream,
unless it receives or sends a Force_LinkPM_Accept LMP. After
receiving or sending an FLPMA LMP, it continues to enable U1 and U2
according to USB 3.2 protocol until it gets a power-on reset or is
disconnected on its upstream port.
When the TUSB8043A is in I2C mode, the TUSB8043A loads this bit
from the contents of the EEPROM.
When the TUSB8043A is in SMBUS mode, the value may be overwritten by an SMBus host.
4
RSVD
RO
Reserved. This bit is reserved and returns 1 when read.
RW
Ganged. This bit is loaded at the de-assertion of reset with the value of
the GANGED/SMBA2/HS_UP pin.
0 = When fullPwrMgmtz = 0, each port is individually power switched
and enabled by the PWRCTL[4:1]/BATEN[4:1] pins
1 = When fullPwrMgmtz = 0, the power switch control for all ports is
ganged and enabled by the PWRCTL[4:1]/BATEN1 pin
When the TUSB8043A is in I2C mode, the TUSB8043A loads this bit
from the contents of the EEPROM.
When the TUSB8043A is in SMBUS mode, the value may be overwritten by an SMBus host.
RW
Full Power Management. This bit is loaded at the de-assertion of reset
with the value of the FULLPWRMGMTz/SMBA1/SS_UP pin.
0 = Port power switching status reporting is enabled
1 = Port power switching status reporting is disabled
When the TUSB8043A is in I2C mode, the TUSB8043A loads this bit
from the contents of the EEPROM.
When the TUSB8043A is in SMBUS mode, the value may be overwritten by an SMBus host.
3
2
28
Field
ganged
fullPwrMgmtz
1
u1u2TimerOvr
RW
U1 U2 Timer Override. When this field is set, the TUSB8043A
overrides the downstream ports U1/U2 timeout values set by USB 3.2
Host software. If software sets value in the range of 1h - FFh, the
TUSB8043A uses the value of FFh. If software sets value to 0, then
TUSB8043A uses value of 0. REG_09h [6] must be set to enable this
feature.
0
RSVD
RO
Reserved. This field is reserved and returns 0 when read.
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8.5.8 Battery Charging Support Register
Figure 9. Register Offset 6h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
X
2
X
1
X
0
X
Table 13. Bit Descriptions – Battery Charging Support Register
Bit
Field
Type
Description
7:4
RSVD
RO
Reserved. Read only, returns 0 when read.
RW
Battery Charger Support. The bits in this field indicate whether the
downstream port implements the charging port features.
0 = The port is not enabled for battery charging support features
1 = The port is enabled for battery charging support features
Each bit corresponds directly to a downstream port, i.e. batEn0
corresponds to downstream port 1, and batEN1 corresponds to
downstream port 2.
The default value for these bits are loaded at the de-assertion of reset
with the value of PWRCTL/BATEN[3:0].
When in I2C/SMBus mode the bits in this field may be over-written by
EEPROM contents or by an SMBus host.
3:0
batEn[3:0]
8.5.9 Device Removable Configuration Register
Figure 10. Register Offset 7h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
X
2
X
1
X
0
X
Table 14. Bit Descriptions – Device Removable Configuration Register
Bit
7
6:4
3:0
Field
Type
Description
customRmbl
RW
Custom Removable. This bit controls selection of port removable bits,
port used bits, and USB2_ONLY bits.
0 = rmbl[3:0], used[3:0], and USB2_ONLY[3:0] are read only and the
values are loaded from the OTP ROM
1 = rmbl[3:0], used[3:0], and USB2_ONLY[3:0] are read/write and can
be loaded by EEPROM or written by SMBus
This bit may be written simultaneously with rmbl[3:0].
RSVD
RO
Reserved. Read only, returns 0 when read.
RO/RW
Removable. The bits in this field indicate whether a device attached to
downstream ports 4 through 1 are removable or permanently attached.
0 = The device attached to the port is not removable
1 = The device attached to the port is removable
Each bit corresponds directly to a downstream port n + 1, i.e. rmbl0
corresponds to downstream port 1, rmbl1 corresponds to downstream
port 2, etc.
This field is read only unless the customRmbl bit is set to 1. Otherwise
the value of this filed reflects the inverted values of the OTP ROM
non_rmb[3:0] field.
rmbl[3:0]
8.5.10 Port Used Configuration Register
Figure 11. Register Offset 8h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
1
2
1
1
1
0
1
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Table 15. Bit Descriptions – Port Used Configuration Register
Bit
Field
Type
Description
7:4
RSVD
RO
Reserved. Read only.
RO/RW
Used. The bits in this field indicate whether a port is enabled.
0 = The port is not used or disabled
1 = The port is used or enabled
Each bit corresponds directly to a downstream port, i.e. used0
corresponds to downstream port 1, used1 corresponds to downstream
port 2, etc. This field is read only unless the customRmbl bit is set to 1.
When the corresponding USB2_ONLY bit is set, the USB2 port is used
and enabled regardless of the bit programmed into this field.
3:0
30
used[3:0]
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8.5.11 Device Configuration Register 2
Figure 12. Register Offset Ah
Bit No.
Reset State
7
0
6
0
5
X
4
0
3
0
2
0
1
0
0
0
Table 16. Bit Descriptions – Device Configuration Register 2
Bit
7
6
5
4
3:2
Field
Type
Description
Reserved
RO
Reserved. Read-only, returns 0 when read.
RW
Custom Battery Charging Feature Enable. This bit controls the ability
to write to the battery charging feature configuration controls.
0 = The HiCurAcpModeEn is read only and the values are loaded from
the OTP ROM.
1 = The HiCurAcpModeEn bit is read/write and can be loaded by
EEPROM or written by SMBus.
This bit may be written simultaneously with HiCurAcpModeEn.
RW
Power enable polarity. This bit is loaded at the de-assertion of reset
with the value of the PWRCTL_POL pin.
0 = PWRCTL polarity is active low
1 = PWRCTL polarity is active high
When the TUSB8043A is in I2C mode, the TUSB8043A loads this bit
from the contents of the EEPROM.
When the TUSB8043A is in SMBUS mode, the value may be overwritten by an SMBus host.
HiCurAcpModeEn
RO/RW
High-current ACP mode enable. This bit enables the high-current tablet
charging mode when the automatic battery charging mode is enabled
for downstream ports.
0 = High current divider mode disabled . High current is ACP2(default)
1 = High current divider mode enabled. High current mode is ACP3
This bit is read only unless the customBCfeatures bit is set to 1. If
customBCfeatures is 0, the value of this bit reflects the value of the
OTP ROM HiCurAcpModeEn bit.
Reserved
RW
Reserved. These registers are unused and returns whatever value was
written.
customBCfeatures
pwrctlPol
1
autoModeEnz
RW
Automatic Mode Enable. This bit is loaded at the de-assertion of reset
with the value of the AUTOENz/HS_SUSPEND pin.
The automatic mode only applies to downstream ports with battery
charging enabled when the upstream port is not connected. Under
these conditions:
0 = Automatic mode battery charging features are enabled.
1 = Automatic mode is disabled; only Battery Charging DCP and CDP
mode is supported.
NOTE: When the upstream port is connected, Battery Charging CDP
mode is supported on all ports that are enabled for battery charging
support regardless of the value of this bit.
0
RSVD
RO
Reserved. Read only, returns 0 when read.
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8.5.12 USB 2.0 Port Polarity Control Register
Figure 13. Register Offset Bh
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Table 17. Bit Descriptions – USB 2.0 Port Polarity Control Register
Bit
7
6:5
4
3
2
1
0
32
Field
Type
Description
customPolarity
RW
Custom USB 2.0 Polarity. This bit controls the ability to write the
p[4:0]_usb2pol bits.
0 = The p[4:0]_usb2pol bits are read only and the values are loaded
from the OTP ROM.
1 = The p[4:0]_usb2pol bits are read/write and can be loaded by
EEPROM or written by SMBus.
This bit may be written simultaneously with the p[4:0]_usb2pol bits
RSVD
RO
Reserved. Read only, returns 0 when read.
RO/RW
Downstream Port 4 DM/DP Polarity. This controls the polarity of the
port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin
out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If
customPolarity is 0 the value of this bit reflects the value of the OTP
ROM p4_usb2pol bit.
RO/RW
Downstream Port 3 DM/DP Polarity. This controls the polarity of the
port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin
out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If
customPolarity is 0 the value of this bit reflects the value of the OTP
ROM p3_usb2pol bit.
RO/RW
Downstream Port 2 DM/DP Polarity. This controls the polarity of the
port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin
out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If
customPolarity is 0 the value of this bit reflects the value of the OTP
ROM p2_usb2pol bit.
RORW
Downstream Port 1 DM/DP Polarity. This controls the polarity of the
port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin
out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If
customPolarity is 0 the value of this bit reflects the value of the OTP
ROM p1_usb2pol bit.
RO/RW
Upstream Port DM/DP Polarity. This controls the polarity of the port.
0 = USB 2.0 port polarity is as documented by the pin out
1 = USB 2.0 port polarity is swapped from that documented in the pin
out, i.e. DM becomes DP, and DP becomes DM.
This bit is read only unless the customPolarity bit is set to 1. If
customPolarity is 0 the value of this bit reflects the value of the OTP
ROM p0_usb2pol bit.
p4_usb2pol
p3_usb2pol
p2_usb2pol
p1_usb2pol
p0_usb2pol
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8.5.13 UUID Registers
Figure 14. Register Offset 10h-1Fh
Bit No.
Reset State
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
X
Table 18. Bit Descriptions – UUID Byte N Register
Bit
Field
Type
Description
7:0
uuidByte[n]
RO
UUID byte N. The UUID returned in the Container ID descriptor. The
value of this register is provided by the device and is meets the UUID
requirements of Internet Engineering Task Force (IETF) RFC 4122 A
UUID URN Namespace.
8.5.14 Language ID LSB Register
Figure 15. Register Offset 20h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
1
2
0
1
0
0
1
Table 19. Bit Descriptions – Language ID LSB Register
Bit
7:0
Field
langIdLsb
Type
Description
RO/RW
Language ID least significant byte. This register contains the value
returned in the LSB of the LANGID code in string index 0. The
TUSB8043A only supports one language ID. The default value of this
register is 09h representing the LSB of the LangID 0409h indicating
English United States.
When customStrings is 1, this field may be over-written by the contents
of an attached EEPROM or by an SMBus host.
8.5.15 Language ID MSB Register
Figure 16. Register Offset 21h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Table 20. Bit Descriptions – Language ID MSB Register
Bit
7:0
Field
langIdMsb
Type
Description
RO/RW
Language ID most significant byte. This register contains the value
returned in the MSB of the LANGID code in string index 0. The
TUSB8043A only supports one language ID. The default value of this
register is 04h representing the MSB of the LangID 0409h indicating
English United States.
When customStrings is 1, this field may be over-written by the contents
of an attached EEPROM or by an SMBus host.
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8.5.16 Serial Number String Length Register
Figure 17. Register Offset 22h
Bit No.
Reset State
7
0
6
0
5
0
4
1
3
1
2
0
1
0
0
0
Table 21. Bit Descriptions – Serial Number String Length Register
Bit
Field
Type
Description
7:6
RSVD
RO
Reserved. Read only, returns 0 when read.
RO/RW
Serial number string length. The string length in bytes for the serial
number string. The default value is 18h indicating that a 24 byte serial
number string is supported. The maximum string length is 32 bytes.
When customSernum is 1, this field may be over-written by the
contents of an attached EEPROM or by an SMBus host.
When the field is non-zero, a serial number string of
serNumbStringLen bytes is returned at string index 1 from the data
contained in the Serial Number String registers.
5:0
serNumStringLen
8.5.17 Manufacturer String Length Register
Figure 18. Register Offset 23h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Table 22. Bit Descriptions – Manufacturer String Length Register
Bit
Field
Type
Description
7
RSVD
RO
Reserved. Read only, returns 0 when read.
RO/RW
Manufacturer string length. The string length in bytes for the
manufacturer string. The default value is 0, indicating that a
manufacturer string is not provided. The maximum string length is 64
bytes.
When customStrings is 1, this field may be over-written by the contents
of an attached EEPROM or by an SMBus host.
When the field is non-zero, a manufacturer string of mfgStringLen
bytes is returned at string index 3 from the data contained in the
Manufacturer String registers.
6:0
mfgStringLen
8.5.18 Product String Length Register
Figure 19. Register Offset 24h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Table 23. Bit Descriptions – Product String Length Register
Bit
Field
Type
Description
7
RSVD
RO
Reserved. Read only, returns 0 when read.
RO/RW
Product string length. The string length in bytes for the product string.
The default value is 0, indicating that a product string is not provided.
The maximum string length is 64 bytes.
When customStrings is 1, this field may be over-written by the contents
of an attached EEPROM or by an SMBus host.
When the field is non-zero, a product string of prodStringLen bytes is
returned at string index 3 from the data contained in the Product String
registers.
6:0
34
prodStringLen
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8.5.19 Device Configuration Register 3
Figure 20. Register Offset 25h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Table 24. Bit Descriptions – Device Configuration Register 3
Bit
Field
Type
Description
7:6
RSVD
RO
Reserved. Read only, returns 0 when read.
bcdUSB30
RW
This field when set forces SS hub to report bcdUSB = 3.0 instead of
3.2.
5
4
USB2.0_only
RW
USB 2.0 hub reports as 2.0 only. This bit disables the USB 2.0 hub
from reporting 5Gbps support in the wSpeedsSupported field of the
USB SS BOS SS device capability descriptor. This bit also disables
the USB3.0 hub.
This bit is read/write but the read value returned is the Boolean OR of
this bit and the corresponding eFuse bit. If either bit is set, this feature
is enabled.
3
USB2_DFP_UNCONF
RW
This field when set enables USB 2.0-defined Unconfigured state on
DFPs.
R/W
I2C 100kHz. This bit controls the clock rate of the I2C master for both
USB to I2C requests . The EEPROM reads occurs at 400K unless
eFuse is used to set the rate to 100k.
This bit is read/write but the read value returned is the Boolean OR of
this bit and the corresponding eFuse bit. If either bit is set, this feature
is enabled.
R/W
Disable Galaxy compatible modes. When this field is high, Galaxy
charging compatible mode does not included in AUTOMODE charger
sequence.
This bit is read/write but the read value returned is the Boolean OR of
this bit and the corresponding eFuse bit. If either bit is set, this feature
is disabled.
R/W
Enable all divider battery charging modes. When automode is enabled
and this bit is set, any DS port enabled for battery charging attempts
all divider battery charging modes before DCP, starting with the
highest current option.
The bit is writable, but the value read back is the Boolean OR of this
bit and the corresponding eFuse control.
If either bit is set, eFuse or this register, this feature is enabled.
2
1
0
I2C_100k
Galaxy_Enz
FullAutoEn
8.5.20 USB 2.0 Only Port Register
Figure 21. Register Offset 26h
Bit No.
Reset State
7
0
6
0
5
0
4
1
3
0
2
0
1
0
0
0
Table 25. Bit Descriptions – USB 2.0 Only Port Register
Bit
Field
Type
Description
7:4
RSVD
RO
Reserved. Read only.
RO/RW
USB 2.0 Only Ports. The bits in this field primarily indicate whether a
port is enabled only for USB 2.0 operation. This field is read-only
unless customRmbl bit is set. Also, these bits overrides the
corresponding USED bit.
A value of 0 indicates the hub port is enabled for both USB 3.2 and
USB 2.0.
A value of 1 indicates the hub port is enabled only for USB 2.0
operation.
3:0
USB2_ONLY[3:0]
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8.5.21 Serial Number String Registers
Figure 22. Register Offset 30h-4Fh
Bit No.
Reset State
7
X
6
X
5
x
4
x
3
x
2
x
1
x
0
x
Table 26. Bit Descriptions – Serial Number Registers
36
Bit
Field
Type
Description
7:0
serialNumber[n]
RO/RW
Serial Number byte N. The serial number returned in the Serial
Number string descriptor at string index 1. The default value of these
registers is assigned by TI. When customSernum is 1, these registers
may be over-written by EEPROM contents or by an SMBus host.
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8.5.22 Manufacturer String Registers
Figure 23. Register Offset 50h-8Fh
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Table 27. Bit Descriptions – Manufacturer String Registers
Bit
7:0
Field
mfgStringByte[n]
Type
Description
RW
Manufacturer string byte N. These registers provide the string values
returned for string index 3 when mfgStringLen is greater than 0. The
number of bytes returned in the string is equal to mfgStringLen.
The programmed data should be in UNICODE UTF-16LE encodings
as defined by The Unicode Standard, Worldwide Character Encoding,
Version 5.0.
8.5.23 Product String Registers
Figure 24. Register Offset 90h-CFh
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Table 28. Bit Descriptions – Product String Byte N Register
Bit
7:0
Field
prodStringByte[n]
Type
Description
RO/RW
Product string byte N. These registers provide the string values
returned for string index 2 when prodStringLen is greater than 0. The
number of bytes returned in the string is equal to prodStringLen.
The programmed data should be in UNICODE UTF-16LE encodings
as defined by The Unicode Standard, Worldwide Character Encoding,
Version 5.0.
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8.5.24 Additional Feature Configuration Register
Figure 25. Register Offset F0h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Table 29. Bit Descriptions – Additional Feature Configuration Register
Bit
Field
Type
Description
7:5
Reserved
RW
Reserved. This field defaults to 3'b000 and must not be changed.
RW
Status output enable. This field when set enables of the Status output
signals, HS_UP, HS_SUSPEND, SS_UP, SS_SUSPEND.
0 = STS outputs are disabled.
1 = STS outputs are enabled.
This bit may be loaded by EEPROM or over-written by a SMBUS host.
4
stsOutputEn
3:1
pwronTime
RW
Power On Delay Time. When the efuse_pwronTime field is all 0s, this
field sets the delay time from the removal disable of PWRCTL to the
enable of PWRCTL when transitioning battery charging modes. For
example, when disabling the power on a transition from ACP to DCP
Mode. The nominal timing is defined as follows:
TPWRON_EN = (pwronTime x 1) x 200 ms
(1)
This field may be over-written by EEPROM contents or by an SMBus
host.
0
38
usb3spreadDis
RW
USB3 Spread Spectrum Disable. This bit allows firmware to disable the
spread spectrum function of the USB3 phy PLL.
0 = Spread spectrum function is enabled
1= Spread spectrum function is disabled
This bit may be loaded by EEPROM or over-written by a SMBUS host.
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8.5.25 SMBus Device Status and Command Register
Figure 26. Register Offset F8h
Bit No.
Reset State
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Table 30. Bit Descriptions – SMBus Device Status and Command Register
Bit
Field
Type
Description
7:2
RSVD
RO
Reserved. Read only, returns 0 when read.
RSU
SMBus interface reset. This bit loads the registers back to their GRSTz
values. Note, that since this bit can only be set when in SMBus mode
the cfgActive bit is also reset to 1. When software sets this bit it must
reconfigure the registers as necessary.
This bit is set by writing a 1 and is cleared by hardware on completion
of the reset. A write of 0 has no effect.
RCU
Configuration active. This bit indicates that configuration of the
TUSB8043A is currently active. The bit is set by hardware when the
device enters the I2C or SMBus mode. The TUSB8043A shall not
connect on the upstream port while this bit is 1.
When in I2C mode, the bit is cleared by hardware when the
TUSB8043A exits the I2C mode.
When in the SMBus mode, this bit must be cleared by the SMBus host
in order to exit the configuration mode and allow the upstream port to
connect.
The bit is cleared by a writing 1. A write of 0 has no effect.
1
0
smbusRst
cfgActive
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TUSB8043A is a four-port USB 3.2 x1 Gen1 compliant hub. It provides simultaneous SuperSpeed USB and
high-speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed,
or low speed connections on the downstream port. The TUSB8043A can be used in any application that needs
additional USB compliant ports. For example, a specific notebook may only have two downstream USB ports. By
using the TUSB8043A, the notebook can increase the downstream port count to five.
9.2 Typical Application
9.2.1 Discrete USB Hub Product
A common application for the TUSB8043A is as a self powered standalone USB hub product. The product is
powered by an external 5V DC Power adapter. In this application, using a USB cable TUSB8043A upstream port
is plugged into a USB Host controller. The downstream ports of the TUSB8043A are exposed to users for
connecting USB hard drives, cameras, flash drives, and so forth.
USB
Type B
Connector
DC
PWR
US Port
TUSB8043A
USB
PWR
SWITCH
USB
PWR
SWITCH
DS Port 1
USB Type A
Connector
DS Port 2
DS Port 3
DS Port 4
USB Type A
Connector
USB Type A
Connector
USB Type A
Connector
Figure 27. Discrete USB Hub Product
40
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Typical Application (continued)
9.2.1.1 Design Requirements
Table 31. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VDD Supply
1.1 V
VDD33 Supply
3.3 V
Upstream Port USB Support (SS, HS, FS)
SS, HS, FS
Downstream Port 1 USB Support (SS, HS, FS, LS)
SS, HS, FS, LS
Downstream Port 2 USB Support (SS, HS, FS, LS)
SS, HS, FS, LS
Downstream Port 3 USB Support (SS, HS, FS, LS)
SS, HS, FS, LS
Downstream Port 4 USB Support (SS, HS, FS, LS)
SS, HS, FS, LS
Number of Removable external exposed Downstream Ports
4
Number of Non-Removable external exposed Downstream Ports
0
Full Power Management of Downstream Ports
Yes. (FULLPWRMGMTZ = 0)
Individual Control of Downstream Port Power Switch
Yes. (GANGED = 0)
Power Switch Enable Polarity
Active High. (PWRCTL_POL = 1)
Battery Charge Support for Downstream Port 1
Yes
Battery Charge Support for Downstream Port 2
Yes
Battery Charge Support for Downstream Port 3
Yes
Battery Charge Support for Downstream Port 4
Yes
I2C EEPROM Support
No
24MHz Clock Source
Crystal
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Upstream Port Implementation
The upstream of the TUSB8043A is connected to a USB3 Type B connector. This particular example has
GANGED pin and FULLPWRMGMTZ pin pulled low which results in individual power support each downstream
port. The VBUS signal from the USB3 Type B connector is feed through a voltage divider. The purpose of the
voltage divider is to make sure the level meets USB_VBUS input requirements
R1
90.9K
0402
1%
C1
10uF
R2
10K 1%
0402
1%
U1A
J1
48
VBUS
DM
DP
GND
SSTXN
SSTXP
GND
SSRXN
SSRXP
SHIELD0
SHIELD1
1
2
3
4
5
6
7
8
9
10
11
USB3_TYPEB_CONNECTOR
VBUS
USB_DM_UP
USB_DP_UP
CAP_UP_TXM
CAP_UP_TXP
C2
0.1uF 0201
USB_SSTXM_UP
C3
0.1uF 0201
USB_SSTXP_UP
USB_SSRXM_UP
USB_SSRXP_UP
54
53
56
55
59
58
USB_VBUS
USB_DM_UP
USB_DP_UP
GANGED/SMBA2/HS_UP
FULLPWRMGMTZ/SMBA1/SS_UP
USB_SSTXM_UP
USB_SSTXP_UP
USB_SSRXM_UP
USB_SSRXP_UP
42
40
R3
4.7K
0402
5%
R4
4.7K
0402
5%
TUSB8043A
C4
0.1uF
C5
0.001uF
R5
1M
0402
5%
Figure 28. Upstream Port Implementation
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9.2.1.2.2 Downstream Port 1 Implementation
The downstream port 1 of the TUSB8043A is connected to a USB3 Type A connector. With BATEN1 pin pulled
up, Battery Charge support is enabled for Port 1. If Battery Charge support is not needed, then pull-up resistor on
BATEN1 should be uninstalled.
BOARD_3P3V
FB1
R6
4.7K
0402
5%
POPULATE
FOR BC SUPPORT
DN1_VBUS
DN1_VBUS
VBUS_DS1
220 at 100MHZ
C6
0.1uF
J2
U1B
USB_DM_DN1
USB_DP_DN1
USB_SSRXM_DN1
USB_SSRXP_DN1
USB_SSTXM_DN1
USB_SSTXP_DN1
PWRCTL1/BATEN1
OVERCUR1
2
1
USB_DM_DN1
USB_DP_DN1
7
6
USB_SSRXM_DN1
USB_SSRXP_DN1
4
3
USB_SSTXM_DN1
C7
0.1uF 0201
C8
CAP_DN_TXM1
CAP_DN_TXP1
USB_SSTXP_DN1
36
0.1uF 0201
PWRCTRL1_BATEN1
46
1
2
3
4
5
6
7
8
9
10
11
VBUS
DM
DP
GND
SSRXN
SSRXP
GND
SSTXN
SSTXP
SHIELD0
SHIELD1
USB3_TYPEA_CONNECTOR
OVERCUR1Z
R7
1M
0402
5%
TUSB8043A
C9
0.001uF
C10
0.1uF
Figure 29. Downstream Port 1 Implementation
9.2.1.2.3 Downstream Port 2 Implementation
The downstream port 2 of the TUSB8043A is connected to a USB3 Type A connector. With BATEN2 pin pulled
up, Battery Charge support is enabled for Port 2. If Battery Charge support is not needed, then pull-up resistor on
BATEN2 should be uninstalled. For ferrite bead used on the VBUS connection, a lower resistance is
recommended due to noticeable IR drop during high current charging modes. The isolation between the Type-A
connectors shield ground and signal ground pins is not required. Some applications may have better ESD/EMI
performance when the grounds are shorted together.
BOARD_3P3V
FB2
POPULATE
FOR BC SUPPORT
R8
4.7K
0402
5%
DN2_VBUS
DN2_VBUS
VBUS_DS2
220 at 100MHZ
C11
0.1uF
J3
U1C
USB_DM_DN2
USB_DP_DN2
USB_SSRXM_DN2
USB_SSRXP_DN2
USB_SSTXM_DN2
USB_SSTXP_DN2
PWRCTL2/BATEN2
OVERCUR2
10
9
USB_DM_DN2
USB_DP_DN2
15
14
USB_SSRXM_DN2
USB_SSRXP_DN2
12
11
USB_SSTXM_DN2
USB_SSTXP_DN2
35
C13
C12
0.1uF 0201
0.1uF 0201
CAP_DN2_TXM
CAP_DN2_TXP
PWRCTRL2_BATEN2
47
OVERCUR2Z
TUSB8043A
R9
1M
0402
5%
C15
0.001uF
1
2
3
4
5
6
7
8
9
10
11
VBUS
DM
DP
GND
SSRXN
SSRXP
GND
SSTXN
SSTXP
SHIELD0
SHIELD1
USB3_TYPEA_CONNECTOR
C14
0.1uF
Figure 30. Downstream Port 2 Implementation
42
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9.2.1.2.4 Downstream Port 3 Implementation
The downstream port3 of the TUSB8043A is connected to a USB3 Type A connector. With BATEN3 pin pulled
up, Battery Charge support is enabled for Port 3. If Battery Charge support is not needed, then pull-up resistor on
BATEN3 should be uninstalled. For ferrite bead used on the VBUS connection, a lower resistance is
recommended due to noticeable IR drop during high current charging modes. The isolation between the Type-A
connectors shield ground and signal ground pins is not required. Some applications may have better ESD/EMI
performance when the grounds are shorted together.
BOARD_3P3V
FB3
POPULATE
FOR BC SUPPORT
R10
4.7K
0402
5%
VBUS_DS3
DN3_VBUS
220 at 100MHZ
C16
0.1uF
J4
U1D
USB_DM_DN3
USB_DP_DN3
USB_SSRXM_DN3
USB_SSRXP_DN3
USB_SSTXM_DN3
USB_SSTXP_DN3
PWRCTL3/BATEN3
OVERCUR3
18
17
USB_DM_DN3
USB_DP_DN3
23
22
USB_SSRXM_DN3
USB_SSRXP_DN3
20
19
USB_SSTXM_DN3
USB_SSTXP_DN3
C18
33
C17
0.1uF 0201
0.1uF 0201
CAP_DN3_TXM
CAP_DN3_TXP
PWRCTRL3_BATEN3
44
R11
1M
0402
5%
OVERCUR3Z
TUSB8043A
C19
0.001uF
1
2
3
4
5
6
7
8
9
10
11
VBUS
DM
DP
GND
SSRXN
SSRXP
GND
SSTXN
SSTXP
SHIELD0
SHIELD1
USB3_TYPEA_CONNECTOR
C20
0.1uF
Figure 31. Downstream Port 3 Implementation
9.2.1.2.5 Downstream Port 4 Implementation
The downstream port 4 of the TUSB8043A is connected to a USB3 Type A connector. With BATEN4 pin pulled
up, Battery Charge support is enabled for Port 4. If Battery Charge support is not needed, then pull-up resistor on
BATEN4 should be uninstalled. For ferrite bead used on the VBUS connection, a lower resistance is
recommended due to noticeable IR drop during high current charging modes. The isolation between the Type-A
connectors shield ground and signal ground pins is not required. Some applications may have better ESD/EMI
performance when the grounds are shorted together.
BOARD_3P3V
FB4
POPULATE
FOR BC SUPPORT
R12
4.7K
0402
5%
VBUS_DS4
DN4_VBUS
220 at 100MHZ
C21
0.1uF
J5
U1E
USB_DM_DN4
USB_DP_DN4
USB_SSRXM_DN4
USB_SSRXP_DN4
USB_SSTXM_DN4
USB_SSTXP_DN4
PWRCTL4/BATEN4
OVERCUR4
25
24
USB_DM_DN4
USB_DP_DN4
30
29
USB_SSRXM_DN4
USB_SSRXP_DN4
27
26
USB_SSTXM_DN4
USB_SSTXP_DN4
32
C23
C22
0.1uF 0201
0.1uF 0201
CAP_DN4_TXM
CAP_DN4_TXP
PWRCTRL4_BATEN4
43
OVERCUR4Z
TUSB8043A
R13
1M
0402
5%
C25
0.001uF
1
2
3
4
5
6
7
8
9
10
11
VBUS
DM
DP
GND
SSRXN
SSRXP
GND
SSTXN
SSTXP
SHIELD0
SHIELD1
USB3_TYPEA_CONNECTOR
C24
0.1uF
Figure 32. Downstream Port 4 Implementation
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9.2.1.2.6 VBUS Power Switch Implementation
This particular example uses the Texas Instruments TPS2561 Dual Channel Precision Adjustable CurrentLimited power switch. For details on this power switch or other power switches available from Texas Instruments,
refer to the Texas Instruments website.
BOARD_3P3V
BOARD_3P3V
BOARD_5V
R19
10K
0402
5%
C42
0.1uF
U2
2
3
PWRCTRL1_BATEN1
PWRCTRL2_BATEN2
R20
10K
0402
5%
PWRCTRL1_BATEN1
PWRCTRL2_BATEN2
4
5
1
11
IN
IN
OUT1
FAULT1Z
EN1
OUT2
EN2
FAULT2Z
GND
PAD
ILIM
9
DN1_VBUS
DN1_VBUS
10
8
OVERCUR1Z
DN2_VBUS
DN2_VBUS
6
7
OVERCUR2Z
ILIM1
C43
C45
0.1uF
TPS2561
+
R21
25.5K
0402
5%
0.1uF
C44
150uF
+
C46
150uF
Limiting DS Port VBUS current to 2.2A per port.
BOARD_3P3V
BOARD_3P3V
BOARD_5V
R22
10K
0402
5%
C47
0.1uF
R23
10K
0402
5%
U3
2
3
4
PWRCTRL3_BATEN3
5
PWRCTRL4_BATEN4
1
11
IN
IN
OUT1
FAULT1Z
EN1
OUT2
EN2
FAULT2Z
GND
PAD
TPS2561
ILIM
9
DN3_VBUS
DN3_VBUS
10
8
OVERCUR3Z
DN4_VBUS
DN4_VBUS
6
7
OVERCUR4Z
ILIM2
C48
0.1uF
R24
25.5K
0402
5%
C50
+
C49
150uF
0.1uF
+
C51
150uF
Limiting DS Port VBUS current to 2.2A per port.
Figure 33. VBUS Power Switch Implementation
9.2.1.2.7 Clock, Reset, and Misc
The PWRCTL_POL is left unconnected which results in active high power enable (PWRCTL1, PWRCTL2,
PWRCTL3, and PWRCTL4) for a USB VBUS power switch. SMBUSz pin is also left unconnected which selects
I2C mode. Both PWRCTL_POL and SMBUSz pins have internal pull-ups. The 1 µF capacitor on the GRSTN pin
can only be used if the VDD11 supply is stable before the VDD33 supply. The depending on the supply ramp of
the two supplies the capacitor size may have to be adjusted.
44
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U1F
C39
50
1uF
GRSTN
SCL/SMBCLK
SDA/SMBDAT
SMBUSZ/SS_SUSPEND
62
R14
XI
AUTOENZ/HS_SUSPEND
PWRCTL_POL
1M
61
XO
Y1
TEST
USB_R1
38
37
39
45
41
49
64
TUSB8043A
24MHz
C40
C41
18pF
18pF
R15
9.53K
0402
1%
R16
4.7K
R18
4.7K
0402
5%
Figure 34. Clock, Reset, and Misc
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9.2.1.2.8 TUSB8043A Power Implementation
BOARD_1P1V
VDD11
C26
C27
C28
C29
C30
C31
C32
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C33
10uF
220 at 100MHZ
NC
VDD33
VDD33
VDD33
VDD33
16
34
52
63
VDD33
BOARD_3P3V
FB6
65
60
TPAD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U1G
5
13
21
28
31
51
57
8
FB5
C34
C35
C36
C37
0.1uF
0.1uF
0.1uF
0.1uF
C38
10uF
220 at 100MHZ
TUSB8043A
Figure 35. TUSB8043A Power Implementation
46
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9.2.1.3 Application Curves
Figure 36. Upstream Port
Figure 37. Downstream Port 1
Figure 38. Downstream Port 2
Figure 39. Downstream Port 3
Figure 40. Downstream Port 4
Figure 41. High-Speed Upstream Port
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48
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Figure 42. High-Speed Downstream Port 1
Figure 43. High-Speed Downstream Port 2
Figure 44. High-Speed Downstream Port 3
Figure 45. High-Speed Downstream Port 4
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10 Power Supply Recommendations
10.1 TUSB8043A Power Supply
VDD should be implemented as a single power plane, as should VDD33.
• The VDD pins of the TUSB8043A supply 1.1 V (nominal) power to the core of the TUSB8043A. This power rail
can be isolated from all other power rails by a ferrite bead to reduce noise.
• The DC resistance of the ferrite bead on the core power rail can affect the voltage provided to the device due
to the high current draw on the power rail. The output of the core voltage regulator may need to be adjusted
to account for this or a ferrite bead with low DC resistance (less than 0.05 Ω) can be selected.
• The VDD33 pins of the TUSB8043A supply 3.3 V power rail to the I/O of the TUSB8043A. This power rail can
be isolated from all other power rails by a ferrite bead to reduce noise.
• All power rails require a 10 µF capacitor or 1 µF capacitors for stability and noise immunity. These bulk
capacitors can be placed anywhere on the power rail. The smaller decoupling capacitors should be placed as
close to the TUSB8043A power pins as possible with an optimal grouping of two of differing values per pin.
10.2 Downstream Port Power
•
•
•
The downstream port power, VBUS, must be supplied by a source capable of supplying 5V and up to 900 mA
per port. Downstream port power switches can be controlled by the TUSB8043A signals. It is also possible to
leave the downstream port power always enabled.
A large bulk low-ESR capacitor of 22 µF or larger is required on each downstream port’s VBUS to limit in-rush
current.
The ferrite beads on the VBUS pins of the downstream USB port connections are recommended for both
ESD and EMI reasons. A 0.1µF capacitor on the USB connector side of the ferrite provides a low impedance
path to ground for fast rise time ESD current that might have coupled onto the VBUS trace from the cable.
10.3 Ground
It is recommended that only one board ground plane be used in the design. This provides the best image plane
for signal traces running above the plane. The thermal pad of the TUSB8043A and any of the voltage regulators
should be connected to this plane with vias. An earth or chassis ground is implemented only near the USB port
connectors on a different plane for EMI and ESD purposes.
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11 Layout
11.1 Layout Guidelines
11.1.1 Placement
1. 9.53K +/-1% resistor connected to pin USB_R1 should be placed as close as possible to the TUSB8043A.
2. A 0.1 µF should be placed as close as possible on each VDD and VDD33 power pin.
3. The 100 nF capacitors on the SSTXP and SSTXM nets should be placed close to the USB connector (Type
A, Type B, and so forth).
4. The ESD and EMI protection devices (if used) should also be placed as close as possible to the USB
connector.
5. If a crystal is used, it must be placed as close as possible to the TUSB8043A XI and XO pins.
6. Place voltage regulators as far away as possible from the TUSB8043A, the crystal, and the differential pairs.
7. In general, the large bulk capacitors associated with each power rail should be placed as close as possible to
the voltage regulators.
11.1.2 Package Specific
1. The TUSB8043A package has a 0.5-mm pin pitch.
2. The TUSB8043A package has a 6.0-mm x 6.0-mm thermal pad. This thermal pad must be connected to
ground through a system of vias.
3. All vias under device, except for those connected to thermal pad, should be solder masked to avoid any
potential issues with thermal pad layouts.
11.1.3 Differential Pairs
This section describes the layout recommendations for all the TUSB8043A differential pairs: USB_DP_XX,
USB_DM_XX, USB_SSTXP_XX, USB_SSTXM_XX, USB_SSRXP_XX, and USB_SSRXM_XX.
1. Must be designed with a differential impedance of 90 Ω ±10%.
2. In order to minimize cross talk, it is recommended to keep high speed signals away from each other. Each
pair should be separated by at least 5 times the signal trace width. Separating with ground as depicted in the
layout example also helps minimize cross talk.
3. Route all differential pairs on the same layer adjacent to a solid ground plane.
4. Do not route differential pairs over any plane split.
5. Adding test points causes impedance discontinuity; and therefore, negative impacts signal performance. If
test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes stub on the differential pair.
6. Avoid 90 degree turns in trace. The use of bends in differential traces should be kept to a minimum. When
bends are used, the number of left and right bends should be as equal as possible and the angle of the bend
should be ≥ 135 degrees. This minimizes any length mismatch causes by the bends and therefore minimize
the impact bends have on EMI.
7. Minimize the trace lengths of the differential pair traces. The maximum recommended trace length for SS
differential pair signals and USB 2.0 differential pair signals is eight inches. Longer trace lengths require very
careful routing to assure proper signal integrity.
8. Match the etch lengths of the differential pair traces (i.e. DP and DM or SSRXP and SSRXM or SSTXP and
SSTXM). There should be less than 5 mils difference between a SS differential pair signal and its
complement. The USB 2.0 differential pairs should not exceed 50 mils relative trace length difference.
9. The etch lengths of the differential pair groups do not need to match (i.e. the length of the SSRX pair to that
of the SSTX pair), but all trace lengths should be minimized.
10. Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure
that the same via type and placement are used for both signals in a pair. Any vias used should be placed as
close as possible to the TUSB8043A device.
11. To ease routing, the polarity of the SS differential pairs can be swapped. This means that SSTXP can be
routed to SSTXM or SSRXM can be routed to SSRXP.
50
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Layout Guidelines (continued)
12. To ease routing of the USB2 DP and DM pair, the polarity of these pins can be swapped. If this is done, the
appropriate Px_usb2pol register, where x = 0, 1, 2, 3, or 4, must be set.
13. Do not place power fuses across the differential pair traces.
11.2 Layout Examples
11.2.1 Upstream Port
Figure 46. Example Routing of Upstream Port
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Layout Examples (continued)
11.2.2 Downstream Port
Figure 47. Example Routing of Downstream Port
The remaining three downstream ports routing can be similar to the example provided.
52
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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31-Jul-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TUSB8043AIRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TUSB8043A
TUSB8043AIRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TUSB8043A
TUSB8043ARGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
TUSB8043A
TUSB8043ARGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
TUSB8043A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jul-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TUSB8043AIRGCR
VQFN
RGC
64
TUSB8043AIRGCT
VQFN
RGC
TUSB8043ARGCR
VQFN
RGC
TUSB8043ARGCT
VQFN
RGC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TUSB8043AIRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
TUSB8043AIRGCT
VQFN
RGC
64
250
210.0
185.0
35.0
TUSB8043ARGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
TUSB8043ARGCT
VQFN
RGC
64
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGC 64
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9 x 9, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
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PACKAGE OUTLINE
RGC0064G
VQFN - 1 mm max height
SCALE 1.500
PLASTIC QUAD FLATPACK - NO LEAD
9.1
8.9
A
B
PIN 1 INDEX AREA
9.1
8.9
(0.1) TYP
LEADFRAME PROFILE
OPTION
SCALE 8.000
1 MAX
C
SEATING PLANE
0.05
0.00
0.08
2X 7.5
17
60X 0.5
(0.2) TYP
6 0.05
32
16
33
SEE DETAIL
2X
7.5
EXPOSED
THERMAL PAD
1
PIN 1 ID
(OPTIONAL)
48
64
49
64X
0.5
0.3
64X
0.30
0.18
0.1
0.05
C A
B
4222053/B 06/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGC0064G
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 6)
SYMM
49
64
64X (0.6)
1
48
64X (0.24)
8X (1.01)
60X (0.5)
18X (1.16)
(8.8)
SYMM
(0.58)
TYP
( 0.2) TYP
VIA
(0.58) TYP
16
33
32
8X (1.01)
17
18X (1.16)
(R0.05)
ALL PAD CORNERS
(8.8)
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL SIDES
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222053/B 06/2015
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RGC0064G
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
25X ( 0.96)
64
64X (0.6)
(1.16) TYP
49
1
(R0.05) TYP
48
64X (0.24)
60X (0.5)
(1.16)
TYP
SYMM
(8.8)
(R0.05) TYP
16
METAL
TYP
17
SYMM
33
32
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
64% PRINTED SOLDER COVERAGE BY AREA
SCALE:12X
4222053/B 06/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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