Texas Instruments | TS3USB3000 DPDT USB 2.0 High-Speed and Mobile High-Definition Link (MHL) 6.1-GHz Switch (Rev. F) | Datasheet | Texas Instruments TS3USB3000 DPDT USB 2.0 High-Speed and Mobile High-Definition Link (MHL) 6.1-GHz Switch (Rev. F) Datasheet

Texas Instruments TS3USB3000 DPDT USB 2.0 High-Speed and Mobile High-Definition Link (MHL) 6.1-GHz Switch (Rev. F) Datasheet
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TS3USB3000
SCDS337F – DECEMBER 2012 – REVISED JUNE 2019
TS3USB3000 DPDT USB 2.0 High-Speed and Mobile High-Definition Link (MHL)
6.1-GHz Switch
1 Features
3 Description
•
•
The TS3USB3000 device is a double-pole, double
throw (DPDT) multiplexer that includes a high-speed
Mobile High-Definition Link (MHL) switch and an USB
2.0 High-Speed (480 Mbps) switch in the same
package. These configurations allow the system
designer to use a common USB or Micro-USB
connector for both MHL video signals and USB data.
1
•
•
•
•
•
VCC Range 2.3 V to 4.8 V
Mobile Hi-Definition Link (MHL) Switch:
– Bandwidth (–3 dB): 6.1 GHz
– RON (Typical): 5.7 Ω
– CON (Typical): 1.6 pF
USB Switch:
– Bandwidth (–3 dB): 6.1 GHz
– RON (Typical): 4.6 Ω
– CON (Typical): 1.4 pF
Current Consumption: 30 µA (Typical)
Special Features:
– IOFF Protection Prevents Current Leakage in
Powered-Down State (VCC and VBUS = 0 V)
– 1.8-V Compatible Control Inputs (SEL, OE)
– Overvoltage Tolerance (OVT) on all I/O Pins
up to 5.5 V Without External Components
– Overvoltage Protection When 9-V Short to
D+/-Pin
ESD Performance:
– 3.5-kV Human Body Model (A114B, Class II)
– 1-kV Charged-Device Model (C101)
10-Pin UQFN Package
(1.5-mm × 2-mm, 0.5-mm Pitch)
The TS3USB3000 has a VCC range of 2.3 V to 4.8 V
and supports overvoltage tolerance (OVT) feature,
which allows the I/O pins to withstand overvoltage
conditions (up to 5.5 V). The power-off protection
feature forces all I/O pins to be in high-impedance
mode when power is not present, allowing full
isolation of the signal lines under such condition
without excessive leakage current. The select pins of
TS3USB3000 are compatible with 1.8-V control
voltage, allowing them to be directly interfaced with
the General-Purpose I/O (GPIO) from a mobile
processor.
The TS3USB3000 comes with a small 10-pin UQFN
package with only 1.5 mm × 2 mm in size, which
makes it a perfect candidate to be used in mobile
applications.
Device Information
PART NUMBER
TS3USB3000
BODY SIZE (NOM)
1.50 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
PACKAGE
UQFN (10)
(1)
Smartphones, Tablets, Mobile
Portable Instrumentation
Digital Still Cameras
Functional Block Diagram
TS3USB3000
USB+
D+
MHL+
USB DMHL -
SEL
Control
Logic
OE
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS3USB3000
SCDS337F – DECEMBER 2012 – REVISED JUNE 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5
5
5
6
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dynamic Characteristics ...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application .................................................. 14
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
13.1 Package Option Addendum .................................. 21
4 Revision History
Changes from Revision E (July 2018) to Revision F
•
Page
Removed the duplicate Tape and Reel Information ............................................................................................................. 20
Changes from Revision D (November 2017) to Revision E
Page
•
Changed Feature From: Overvoltage Protection When 9-V Short to D-Pin To: Overvoltage Protection When 9-V
Short to D+/-Pin ...................................................................................................................................................................... 1
•
Changed From: VD-, D– DC voltage To: VD+/–, D+/- DC voltage in the Absolute Maximum Ratings ..................................... 5
•
Changed Note (4) From: This rating only applies to the D– pin with respect to GND. To: This rating only applies to
the D+/– pins with respect to GND in the Absolute Maximum Ratings ................................................................................. 5
•
Changed D- To: D+/- in Overvoltage Protection When 9-V Short to D+/– Pin ................................................................... 11
•
Changed D- To: D+/- in Pin Leakage ................................................................................................................................... 13
Changes from Revision C (January 2017) to Revision D
•
Changed the Package Option Addendum Device Marking column ..................................................................................... 20
Changes from Revision B (October 2015) to Revision C
•
2
Page
Extended the IC recommended VCC operating range to VCC = 2.3 to 4.8 V in the Features, Description, Absolute
Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics, Dynamic Characteristics and
Timing Requirements sections ............................................................................................................................................... 6
Changes from Revision A (April 2013) to Revision B
•
Page
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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Changes from Original (December 2012) to Revision A
•
Page
Updated TI data sheet – no specific changes. ...................................................................................................................... 1
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SCDS337F – DECEMBER 2012 – REVISED JUNE 2019
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5 Pin Configuration and Functions
10
VCC
RSE Package
10-Pin UQFN
Top View
1
9
SEL
USB±
2
8
D+
MHL+
3
7
D±
MHL±
4
6
OE
GND
5
USB+
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
USB+
I/O
USB data (Differential +)
2
USB–
I/O
USB data (Differential –)
3
MHL+
I/O
MHL data (Differential +)
4
MHL–
I/O
MHL data (Differential –)
5
GND
—
Ground
6
OE
I
7
D–
I/O
Data switch output (Differential –)
8
D+
I/O
Data switch output (Differential +)
9
SEL
I
10
VCC
—
4
Output enable (Active low)
Switch select (logic Low = D+/D– to USB+/USB– Logic High = D+/D– to MHL+/MHL–)
Supply voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2)
Supply voltage (3)
VCC
(3)
MIN
MAX
UNIT
–0.3
5.5
V
VI/O
Input-output DC voltage
–0.3
5.5
V
VD+/–
D+/- DC voltage (4)
–0.3
9
V
VI
Digital input voltage (SEL, OE)
–0.3
5.5
V
IK
Input-output port diode current
VI/O < 0
–50
IIK
Digital logic input clamp current (3)
VI < 0
–50
ICC
Continuous current through VCC
IGND
Continuous current through GND
–100
Tstg
Storage temperature
–65
(1)
(2)
(3)
(4)
mA
mA
100
mA
mA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to ground, unless otherwise specified.
This rating only applies to the D+/– pins with respect to GND. VCC must be powered within the recommended operating conditions of
2.3 V to 4.8 V and the OE pin must be logic high for this rating to be applicable. Any condition where VCC is unpowered or the OE pin is
not high must reference the rest of the Absolute Maximum Ratings Table.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VCC
VI/O
(USB)
VI/O
(MHL)
MIN
MAX
Supply voltage
2.3
4.8
UNIT
V
Analog voltage
0
3.6
V
VI
Digital input voltage (SEL, OE)
0
VCC
V
TRAMP (VCC)
Power supply ramp time requirement (VCC)
100
1000
μs/V
TA
Operating free-air temperature
–40
85
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6.4 Thermal Information
TS3USB3000
THERMAL METRIC
(1)
RSE (UQFN)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
(1)
191.6
°C/W
Junction-to-case (top) thermal resistance
94.3
°C/W
Junction-to-board thermal resistance
117.5
°C/W
7.4
°C/W
117.4
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TA = –40°C to +85°C, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
MHL SWITCH
VCC = 2.7 V
VI/O = 1.65 V, ION = –8 mA
5.7
9
VCC = 2.3 V
VI/O = 1.65 V, ION = –8 mA
5.7
9.5
ΔRON
ON-state resistance
match between + and – VCC = 2.3 V
paths
VI/O = 1.65 V, ION = –8 mA
0.1
Ω
RON
ON-state resistance
flatness
VCC = 2.3 V
VI/O = 1.65 V to 3.45 V, ION = –8 mA
1
Ω
(FLAT)
IOZ
OFF leakage current
VCC = 4.8 V
Switch OFF, VMHL± = 1.65 V to 3.45 V,
VD± = 0 V
IOFF
Power-off leakage
current
VCC = 0 V
Switch ON or OFF, VMHL± = 1.65 V to 3.45 V,
VD± = NC
VCC = 4.8 V
RON
ION
ON-state resistance
Ω
–2
2
µA
–10
10
µA
Switch ON, VMHL± = 1.65 V to 3.45 V,
VD± = NC
–2
2
VCC = 2.3 V
Switch ON, VMHL± = 1.65 V to 3.45 V,
VD± = NC
–125
125
ON leakage current
µA
USB SWITCH
ON-state resistance
VCC = 2.3 V
VI/O = 0.4 V, ION = –8 mA
4.6
ΔRON
ON-state resistance
match between + and – VCC = 2.3 V
paths
VI/O = 0.4 V, ION = –8 mA
0.1
Ω
RON
ON-state resistance
flatness
VCC = 2.3 V
VI/O = 0 V to 0.4 V, ION = –8 mA
1
Ω
(FLAT)
IOZ
OFF leakage current
VCC = 4.8 V
Switch OFF, VUSB± = 0 V to 3.6 V, VD± = 0 V
IOFF
Power-off leakage
current
VCC = 0 V
Switch ON or OFF, VUSB± = 0 V to 3.6 V,
VD± = NC
VCC = 4.8 V
VCC = 2.3 V
ION
ON leakage current
7.5
Ω
RON
–2
2
µA
–10
10
µA
Switch ON, VUSB± = 0 V to 3.6 V,
VD± = NC
–2
2
Switch ON, VUSB± = 0 V to 3.6 V,
VD± = NC
–125
125
µA
DIGITAL CONTROL INPUTS (SEL, OE)
VIH
Input logic high
VCC = 2.3 V to 4.8 V
VIL
Input logic low
VCC = 2.3 V to 4.8 V
IIN
Input leakage current
VCC = 4.8 V, VI/O = 0 V to 3.6 V, VIN = 0 to 4.8 V
6
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1.3
–10
V
0.6
V
10
μA
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6.6 Dynamic Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CON(MHL)
MHL path ON capacitance
VCC = 3.3 V, VI/O = 0 or 3.3 V,
f = 240 MHz
Switch ON
1.6
2
pF
CON(USB)
USB path ON capacitance
VCC = 3.3 V, VI/O = 0 or 3.3 V,
f = 240 MHz
Switch ON
1.4
2
pF
COFF(MHL)
MHL path OFF capacitance
VCC = 3.3 V, VI/O = 0 or 3.3 V
f = 240 MHz
Switch OFF
1.4
2
pF
COFF(USB)
USB path OFF capacitance
VCC = 3.3 V, VI/O = 0 or 3.3 V
f = 240 MHz
Switch OFF
1.6
2
pF
CI
Digital input capacitance
VCC = 3.3 V, VI = 0 or 2 V
OISO
OFF Isolation
VCC = 2.3 V to 4.8 V, RL = 50 Ω,
f = 240 MHz
XTALK
Crosstalk
BW(MHL)
BW(USB)
2.2
pF
Switch OFF
–34
dB
VCC = 2.3 V to 4.8 V, RL = 50 Ω,
f = 240 MHz
Switch ON
–37
dB
MHL path –3-dB bandwidth
VCC = 2.3 V to 4.8 V, RL = 50 Ω,
f = 240 MHz
Switch ON
6.1
GHz
USB path –3-dB bandwidth
VCC = 2.3 V to 4.8 V, RL = 50 Ω,
Switch ON
6.1
GHz
SUPPLY
VCC
Power supply voltage
2.3
ICC
Positive supply current
VCC = 4.8 V, VIN = VCC or GND, VI/O = 0 V,
Switch ON or OFF
Icc, HZ
Power supply current in high-Z
mode
VCC = 4.8 V, VIN = VCC or GND, VI/O = 0 V,
Switch ON or OFF, OE = H
4.8
V
30
50
µA
5
10
µA
NOM
MAX
6.7 Timing Requirements
MIN
tpd
Propagation delay
100
tswitch
Switching time (SEL to output)
tZH, ZL
MHL enable time (OE to output)
(MHL)
tHZ, LZ
600
RL = 50 Ω,
CL = 5 pF,
VCC = 2.3 V to 4.8 V
MHL disable time (OE to output)
(MHL)
tZH, ZL
USB enable time (OE to output)
(USB)
tHZ, LZ
ps
See Figure 1
VI/O = 3.3 V or 0 V
UNIT
ns
100
µs
200
ns
100
µs
200
ns
20
ps
VI/O = 0.8 V or 0 V
USB disable time (OE to output)
(USB)
tSK(P)
Skew of opposite transitions of same output
USB+/3V
D+/-
MHL+/-
1.8 V
CL
RL
VSEL
50 %
50 %
0V
SEL
CL
RL
tSWITCH
3V
VMHL/USB
VSEL
tSWITCH
50 %
50 %
0V
(1) All input pulses are suppleid by generators having the following characteristics: 355 ” 10 MHz, ZO = 50
tf < 5 ns
, tr < 5 ns,
(2) CL includes probe and jig capacitance.
Figure 1. Timing Diagram
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6.0
6.0
5.5
5.5
5.0
5.0
4.5
4.5
Ron (Ÿ)
Ron (Ÿ)
6.8 Typical Characteristics
4.0
3.5
3.5
3.0
3.0
2.5
2.5
2.0
2.0
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
Vin (V)
8
4.0
4.0
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
Vin (V)
C002
4.0
C002
Figure 2. ON-Resistance vs VI for MHL Switch
Figure 3. ON-Resistance vs VI for USB Switch
Figure 4. Differential S21 vs Frequency for MHL Switch
Figure 5. Differential S21 vs Frequency for USB Switch
Figure 6. Off Isolation vs Frequency for MHL Path
Figure 7. Off Isolation vs Frequency for USB Path
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Typical Characteristics (continued)
Figure 8. Cross Talk vs Frequency for MHL Path
Figure 9. Cross Talk vs Frequency for USB Path
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7 Parameter Measurement Information
VDD
VOUT1
VON
VOUT2
+
Channel ON
SEL
ION
VSEL
+
RON = (VON – VI/O1) / ION or (VON –
VI/O2) / ION
VSEL = H or L
GND
Figure 10. ON-State Resistance (RON)
VDD
VOUT1
VOUT2
+
A
SEL
Channel OFF
+
VSEL
IOZ
VIN
VSEL = H or L
+
GND
Figure 11. OFF Leakage Current (IOZ)
VDD
Network Analyzer
VOUT+
RS
VS
VOUT-
RS
Channel ON
VS
VSEL = H or L
RS=RL=50Ω
GND
RL
RL
Figure 12. Bandwidth (BW)
10
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8 Detailed Description
8.1 Overview
The TS3USB3000 device is a 2-channel SPDT switch specially designed for the switching of high-speed MHL
and USB 2.0 and 3.0 signals in handset and consumer applications, such as cell phones, digital cameras, and
notebooks with hubs or controllers with limited USB I/Os. The wide bandwidth (6.1 GHz) of this switch allows
signals to pass with minimum edge and phase distortion. The device multiplexes differential outputs from a USB
host device to one of two corresponding outputs or from one USB connector to two processors or controllers.
The switch is bidirectional and offers little or no attenuation of the high-speed signals at the outputs. The device
also has a low power mode that reduces the power consumption to 5 μA for portable applications with a battery
or limited power budget.
The device is designed for low bit-to-bit skew and high channel-to-channel noise isolation, and is compatible with
various standards, such as high-speed USB 2.0 (480 Mbps).
The TS3USB3000 device integrates ESD protection cells on all pins, is available in a tiny UQFN package
(1.5 mm × 2 mm) and is characterized over the free-air temperature range from –40°C to +85°C.
8.2 Functional Block Diagram
TS3USB3000
USB+
D+
MHL+
USB DMHL -
SEL
Control
Logic
OE
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8.3 Feature Description
8.3.1 Low Power Mode
The TS3USB3000 has a low power mode that reduces the power consumption to 5 μA while the device is not in
use. To put the device in low power mode and disable the switch, the bus-switch enable pin OE must be
supplied with a logic High signal.
8.3.2 Overvoltage Protection When 9-V Short to D+/– Pin
This section describes how to protect the TS3USB3000 and the surrounding system when the D+/– pin is
exposed to voltages greater than 5 V and less than 9 V. Voltages higher than 9 V damages the device.
In charging applications it is possible for the USB plug to be inserted in such a way that the VBUS pin shorts to
the D+/– pin of the connector. If there are peripherals on the D+/– pin that cannot tolerate conditions up to 9 V
they can be damaged or destroyed. The TS3USB3000 can be used to protect the system from excess voltage if
the correct precautions are taken.
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Feature Description (continued)
In Figure 13, the system has an application processor (AP) that cannot survive 9 V on the USB data lines. The
following procedure protects the system and the TS3USB3000. As stated in the Absolute Maximum Ratings table
footnotes, the 9 V rating is only applicable while the VCC is powered within the voltage range of the
recommended operating conditions and the OE pin is high.
1. After a charger is connected to the USB port, the AP detects that a DCP is attached.
2. The AP pulls the OE pin high to disable the switches.
3. The AP communicates to the Charger that it can negotiate for a faster charging mode with VBUS at 9 V.
4. The TS3USB3000 is now in a low-power state with the switches disabled and can protect the AP.
5V
9V
Phone/Tablet
Battery
Charger
IC
3.3 V
Potential short
in connector
VCC
VBUS
MHL-
D-
D-
USBMHL+
D+
D+
GND
USB+
Application
Processor
SEL
OE
GND
TS3USB3000
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Figure 13. Potential VBUS to D+/– Short Example
12
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Feature Description (continued)
8.3.3 Pin Leakage
When the voltage on the D+/– pins rises above VCC +1 V a leakage path in the device starts conducting as
shown in Figure 14. The amount of leakage depends on the VCC voltage and the pin voltage. This leakage is
governed by Equation 1:
V -V
Pin Leakage = D CC
12000
(1)
Leakage Path
VCC
USBDMHLUSB+
D+
MHL+
SEL
OE
GND
Figure 14. Potential Leakage Path D+/– to VCC
8.4 Device Functional Modes
8.4.1 High Impedance Mode
The TS3USB3000 has a high impedance mode that places all the signal paths in a Hi-Z state while the device is
not in use. To put the device in high impedance mode and disable the switch, the bus-switch enable pin OE must
be supplied with a logic High signal as shown in Table 1.
Table 1. Function Table
SEL
OE
SWITCH STATUS
X
High
Both USB and MHL switches in High-Z
Low
Low
D+/D– to USB+/USB–
High
Low
D+/D– to MHL+/MHL–
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
There are many USB applications in which the USB hubs or controllers have a limited number of USB I/Os or
need to route signals from a single USB connector. The TS3USB3000 solution can effectively expand the limited
USB I/Os by switching between multiple USB buses to interface them to a single USB hub or controller or route
signals from on connector to two different locations.
9.2 Typical Application
Figure 15 represents a typical application of the TS3USB3000 USB/MHL switch. The TS3USB3000 is used to
switch signals between the USB path, which goes to the baseband or application processor, or the MHL path,
which goes to the HDMI to MHL bridge. The TS3USB3000 has internal 6-MΩ pulldown resistors on SEL and OE.
The pulldown on SEL ensure the USB channel is selected by default. The pulldown on OE enables the switch
when power is applied. The TS5A3157 is a separate SPDT switch that is used to switch between MHL’s CBUS
and the USB ID line that is needed for USB OTG (USB On-The-Go) application.
V BAT
To
Battery
Charger
VCC
TS3USB3000
USB_ D+
USB+
VBUS
D+
USB_ D-
Baseband or
Application
Processor
USBD+
DDID
GND
SEL
GPO 1
MHL+
MHL +
MHL-
MHL -
HDMI to
MHL Bridge
CBUS
OE
HDMI
GND
GPO 2
MicroUSB
Connector
ID _USB
COM
TS5A3157
Copyright © 2017, Texas Instruments Incorporated
Figure 15. Typical TS3USB3000 Application
9.2.1 Design Requirements
Design requirements of the MHL and USB 1.0,1.1, and 2.0 standards must be followed. The TS3USB3000 has
internal 6-MΩ pulldown resistors on SEL and OE, so no external resistors are required on the logic pins. The
internal pulldown resistor on SEL ensures the USB channel is selected by default. The internal pulldown resistor
on OE enables the switch when power is applied to VCC.
9.2.2 Detailed Design Procedure
The TS3USB3000 can be properly operated without any external components. However, TI recommends that
unused pins must be connected to ground through a 50-Ω resistor to prevent signal reflections back into the
device.
14
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Typical Application (continued)
9.2.3 Application Curves
Figure 16. Eye Pattern: 0.7 Gbps With No Device
The TS3USB3000 contributes only 8.4 ps of peak-to-peak jitter
for 0.7-Gbps data rate
Figure 17. Time Interval Error Histogram: 0.7 Gbps With
No Device
The TS3USB3000 contributes only 8.4 ps of peak-to-peak jitter
for 0.7-Gbps data rate
Figure 18. Eye Pattern: 0.7 Gbps for MHL Switch
Figure 19. Time Interval Error Histogram: 0.7 Gbps for
MHL Switch
Figure 20. Eye Pattern: 2.2 Gbps With No Device
Figure 21. Time Interval Error Histogram: 2.2 Gbps With
No Device
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Typical Application (continued)
The TS3USB3000 contributes only 3.8 ps of peak-to-peak jitter
for 2.2-Gbps data rate
Figure 22. Eye Pattern: 2.2 Gbps for MHL Switch
Figure 23. Time Interval Error Histogram: 2.2 Gbps for
MHL Switch
Figure 24. Eye Pattern: 3 Gbps With No Device
Figure 25. Time Interval Error Histogram: 3 Gbps With No
Device
The TS3USB3000 contributes only 5.8 ps of peak-to-peak jitter
for 3-Gbps data rate
Figure 26. Eye Pattern: 3 Gbps for MHL Switch
16
The TS3USB3000 contributes only 3.8 ps of peak-to-peak jitter
for 2.2-Gbps data rate
The TS3USB3000 contributes only 5.8 ps of peak-to-peak jitter
for 3-Gbps data rate
Figure 27. Time Interval Error Histogram: 3 Gbps for MHL
Switch
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Typical Application (continued)
Figure 28. Eye Pattern: 4.5 Gbps With No Device
The TS3USB3000 contributes only 7.6 ps of peak-to-peak jitter
for 4.5-Gbps data rate
Figure 29. Time Interval Error Histogram: 4.5 Gbps With
No Device
The TS3USB3000 contributes only 7.6 ps of peak-to-peak jitter
for 4.5-Gbps data rate
Figure 30. Eye Pattern: 4.5 Gbps for MHL Switch
Figure 31. Time Interval Error Histogram: 4.5 Gbps for
MHL Switch
Figure 32. 480-Mbps USB 2.0 Eye Pattern With No Device
Figure 33. 480-Mbps USB 2.0 Eye Pattern for USB Switch
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10 Power Supply Recommendations
Power to the device is supplied through the VCC pin and must follow the USB 1.0, 1.1, and 2.0 standards. TI
recommends placing a bypass capacitor as close to the supply pin VCC as possible to help smooth out lower
frequency noise to provide better load regulation across the frequency spectrum.
11 Layout
11.1 Layout Guidelines
Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the D±
traces.
The high-speed D± must match and be no more than 4 inches long; otherwise, the eye diagram performance
may be degraded. A high-speed USB connection is made through a shielded, twisted pair cable with a differential
characteristic impedance. In layout, the impedance of D+ and D– traces must match the cable characteristic
differential impedance for optimal performance.
Route the high-speed USB signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points on twisted pair
lines; through-hole pins are not recommended.
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices or ICs that use or duplicate clock signals.
Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then
the stub must be less than 200 mm.
Route all high-speed USB signal traces over continuous GND planes, with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
Due to high frequencies associated with the USB, a printed circuit board with at least four layers is
recommended; two signal layers separated by a ground and power layer as shown in Figure 34.
Signal 1
GND Plane
Power Plane
Signal 2
Figure 34. Four-Layer Board Stack-Up
The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer must
be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power
plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the
number of signal vias reduces EMI by reducing inductance at high frequencies.
18
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11.2 Layout Example
LEGEND
VIA to Power Plane
Polygonal Copper Pour
VIA to GND Plane
Bypass Capacitor
V+
To Microcontroller
10
1 USB+
VCC
SEL 9
USB port
2 USB–
D+ 8
3 MHL+
D– 7
To USB connector
MHL port
4 MHL–
OE 6
GND
5
To Microcontroller
Figure 35. Package Layout Diagram
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• USB 2.0 Board Design and Layout Guidelines
• High-Speed Layout Guidelines Application Report
• High-Speed Interface Layout Guidelines
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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13.1 Package Option Addendum
13.1.1 Packaging Information
Orderable Device
(1)
(2)
(3)
(4)
(5)
(6)
Status
(1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan
(2)
Lead/Ball
Finish (3)
MSL Peak Temp
(4)
Op Temp (°C)
Device Marking (5) (6)
TS3USB3000MRSER
ACTIVE
UQFN
RSE
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
DRJ, DR0, DRR
TS3USB3000RSER
ACTIVE
UQFN
RSE
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
DSJ, DSO, DSR
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jun-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TS3USB3000MRSER
UQFN
RSE
10
3000
180.0
9.5
2.2
1.8
0.75
4.0
8.0
Q3
TS3USB3000RSER
UQFN
RSE
10
3000
180.0
9.5
1.7
2.2
0.75
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jun-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TS3USB3000MRSER
UQFN
RSE
10
3000
189.0
185.0
36.0
TS3USB3000RSER
UQFN
RSE
10
3000
189.0
185.0
36.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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