Texas Instruments | TIOS101, TIOS101x Digital Sensor Output Drivers with Integrated Surge Protection (Rev. B) | Datasheet | Texas Instruments TIOS101, TIOS101x Digital Sensor Output Drivers with Integrated Surge Protection (Rev. B) Datasheet

Texas Instruments TIOS101, TIOS101x Digital Sensor Output Drivers with Integrated Surge Protection (Rev. B) Datasheet
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TIOS101, TIOS1013, TIOS1015
SLLSEV6B – JULY 2017 – REVISED JUNE 2019
TIOS101, TIOS101x Digital Sensor Output Drivers with Integrated Surge Protection
1 Features
2 Applications
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1
•
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7-V to 36-V Supply Voltage
PNP, NPN or Push-Pull Configurable Output
Low Residual Voltage of 1.75 V at 250 mA
50-mA to 350-mA Configurable Current Limit
Tolerant to ±65-V Transients < 100 µs
Reverse Polarity Protection of up to 60 V on VCC,
OUT and GND
Integrated EMC Protection on VCC and OUT
– ±16 kV IEC 61000-4-2 ESD Contact Discharge
– ±4 kV IEC 61000-4-4 Electrical Fast Transient
– ±1.2 kV/500 Ω IEC 61000-4-5 Surge
Fast Demagnetization of Inductive Loads
up to 1.5 H
Large Capacitive Load Driving Capability
< 2.2-mA Quiescent Supply Current
Integrated LDO Options for up to 20 mA Current
– TIOS101: No LDO
– TIOS1013: 3.3-V LDO
– TIOS1015: 5-V LDO
Overtemperature Warning and Thermal Protection
Fault Indicator
Extended Ambient Temperature: -40°C to 125°C
2.5 mm x 3 mm 10-pin VSON Package
Proximity Switches
Capacitive and Inductive Sensors
Digital Outputs
3 Description
The TIOS101(x) devices are configurable as highside, low-side or push-pull drivers. These devices are
capable of withstanding up to 1.2 kV (500 Ω) of IEC
61000-4-5 surge and feature integrated reverse
polarity protection.
A simple pin-programmable interface allows easy
interfacing to the controller circuits. The output
current limit can be configured using an external
resistor.
Fault reporting and internal protection functions are
provided for under voltage, over circuit current and
over temperature.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TIOS101
TIOS1013
VSON (10)
2.50 mm x 3.00 mm
TIOS1015
(1) For all available devices, see the orderable addendum at the
end of the data sheet.
Typical Application Diagram
TIO S101(x)
VCC_OUT
VCC
VOL TA GE
REGULATOR
0.1 µF
100 V
1 µF
10 V
IN
Sen sor
Front-End
EN
CONTROL
LOG IC
10 kŸ
OUT
DIA GNOSTICS
and
CONTROL
NFA UL T
CUR_OK
TMP_OK
PWR_OK
GND
ILIM_ADJ
R SET
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TIOS101, TIOS1013, TIOS1015
SLLSEV6B – JULY 2017 – REVISED JUNE 2019
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagrams ....................................... 9
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 15
9
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application ................................................. 17
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 22
12 Device and Documentation Support ................. 23
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
13 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
Changes from Revision A (August 2018) to Revision B
Page
•
Added device numbers TIOS1013 and TIOS1015 to the data sheet .................................................................................... 1
•
Changed all TIOS101-3 To: TIOS1013 and TIOS101-5 To: TIOS1015 ................................................................................ 1
•
Changed Feature From: Reverse Polarity Protection of up to 55 V on VCC To: Reverse Polarity Protection of up to
60 V on VCC .......................................................................................................................................................................... 1
•
Changed the Supply voltage values From: MIN = –55 V, MAX = 50 V To: MIN = –60 V, MAX = 60 V in the Absolute
Maximum Ratings ................................................................................................................................................................... 4
•
Changed the Voltage difference Max value From: 55 V To: 60 V in the Absolute Maximum Ratings................................... 4
•
Changed |55 V| To: |60 V| in the Leakage current Test Conditions in the Electrical Characteristics .................................... 6
•
Changed text From: "not exceed 55 V DC at any time." To: "not exceed 60 V DC at any time." in the Reverse
Polarity Protection section .................................................................................................................................................... 13
Changes from Original (July 2017) to Revision A
•
2
Page
Changed the Thermal Information table values ..................................................................................................................... 5
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5 Pin Configuration and Functions
DMW Package
10-Pin (VSON)
Top View
VCC_IN/OUT
1
10
NFAULT
2
9
VCC
NC
3
8
OUT
IN
4
7
GND
EN
5
6
ILIM_ADJ
Thermal
Pad
NC
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
OUT
8
O
VCC
9
POWER
Supply voltage (24 V nominal)
GND
7
POWER
Device ground
EN
5
I
Driver enable input signal from the local controller. Logic low sets the OUT output at Hi-Z. Weak internal pulldown.
IN
4
I
Transmit data input from the local controller. No effect if EN is low. Logic high sets low-side switch. Logic low
sets high-side switch. Weak internal pull-up.
VCC_IN/OUT
1
POWER
ILIM_ADJ
6
I
NFAULT
2
OPEN-DRAIN
3, 10
—
No internal connection.
—
—
Connect to GND plane for optimal thermal and electrical performance
NC
Thermal Pad
Switch output
3.3-V or 5-V linear regulator output; external 3.3-V or 5-V logic supply input for option without LDO.
Input for current limit adjustment. Connect resistor RSET between ILIM_ADJ and GND.
Fault indicator output signal to the microcontroller. A low level indicates either an over- current, an
undervoltage in supply or an overtemperature condition. Connect this pin via pull-up resistor to VCC_IN/OUT.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
Supply voltage
MIN
MAX
UNIT
Steady state voltage for VCC and OUT
–60
60
V
Transient pulse width < 100 µs for VCC and OUT
–65
65
V
60
V
V
Voltage difference
|V(VCC) – V(OUT)|
Logic supply voltage (TIOS101)
VCC_IN
–0.3
6
Input logic voltage
IN, EN, ILIM_ADJ
–0.3
6
V
Output current
NFAULT
–5
5
mA
-55
170
°C
Storage temperature, Tstg
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with reference to the GND pin, unless otherwise specified.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC
All pins
JS-001 (1)
V(ESD)
Electrostatic discharge
Contact discharge, per IEC 61000-4-2
Surge protection with 500 Ω, per IEC 61000-4-5;
1.2/50 μs (2)
(1)
(2)
(3)
±4000
(2) (3)
Electrical fast transient, per IEC 61000-4-4 (2)
UNIT
±16000
Pins VCC, OUT
and GND
V
±4000
±1200
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Minimum 100-nF capacitor is required between VCC and GND. Minimum 1-µF capacitor is required between VCC_IN/OUT and GND.
Passing level is ±4500 V if the device is powered and EN=IN=HIGH.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
V(VCC)
Supply voltage
3.3 V configuration
V(VCC_IN)
Logic level input voltage (TIOS101 only)
RSET
External resistor for OUT current limit
1/tBIT
Signaling rate (push-pull mode)
I(VCC_OUT)
LDO output current (TIOS1013 and TIOS1015 only)
TA
Operating ambient temperature
TJ
Junction temperature
4
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5 V configuration
NOM
MAX
UNIT
7
24
36
V
3
3.3
3.6
V
4.5
5
5.5
V
100
kΩ
250
kbps
20
mA
125
°C
150
°C
0
–40
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6.4 Thermal Information
TIOS101(x)
THERMAL METRIC (1)
UNIT
DMW (10 Pins)
RθJA
Junction-to-ambient thermal resistance
68.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
60.1
°C/W
RθJB
Junction-to-board thermal resistance
40.6
°C/W
ψJT
Junction-to-top characterization parameter
13.4
°C/W
ψJB
Junction-to-board characterization parameter
40.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
25.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EN = LOW, no load
1.5
2.2
mA
EN = HIGH, no load
2
2.7
mA
0.8
V
POWER SUPPLIES (VCC)
I(VCC)
Quiescent supply current
LOGIC-LEVEL INPUTS (EN, IN)
VIL
Input logic low voltage
VIH
Input logic high voltage
RPD
Pull-down (EN) resistance
100
kΩ
RPU
Pull-up (IN) resistance
200
kΩ
2
V
CONTROL OUTPUT (NFAULT)
VOL
Output logic low voltage
IO = 4 mA
IOZ
Output high impedance leakage
Output in Hi-Z, VO = 0 V or VCC_IN/OUT
0.5
V
1
µA
I = 250 mA
1.75
V
I = 200 mA
1.5
V
I = 100 mA
1.1
V
I = 250 mA
1.75
V
I = 200 mA
1.5
V
I = 100 mA
1.1
V
–1
DRIVER OUTPUT (OUT)
High-side driver residual voltage
VDS(ON)
Low-side driver residual voltage
IP
OUT pull-up/down current
IO(LIM)
Driver output current limit
EN = LOW, IN = LOW, pull-down current
40
50
80
µA
EN = LOW, IN = HIGH, pull-up current
40
50
80
µA
RSET = 100 kΩ
35
50
70
mA
RSET = 0 kΩ
300
350
400
mA
RSET = OPEN (1)
300
350
400
mA
PROTECTION CIRCUITS
VCC falling; NFAULT = Hi-Z
6
V
VCC rising; NFAULT = LOW
6.5
V
V(UVLO)
VCC under voltage lockout
V(UVLO,HYS
VCC under voltage hysteresis
Rising to falling threshold
VCC_IN under voltage lockout
(No LDO option)
VCC_IN falling; NFAULT = Hi-Z
2.4
V
VCC_IN rising; NFAULT = LOW
2.5
V
Rising to falling threshold
100
mV
100
mV
)
V(UVLO_IN)
V(UVLO,HYS
)
VCC_IN under voltage hysteresis
(No LDO option)
T(WRN)
Thermal warning
T(SDN)
Thermal shutdown
T(HYS)
Thermal hysteresis for shutdown
(1)
125
Die temperature TJ
150
°C
160
°C
10
°C
Current fault indication will be active. Current fault auto recovery will be de-activated.
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Leakage current in reverse
polarity
IREV
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(OUT) < V(VCC) or
V(OUT) > V(VCC)
up to |36 V|
50
µA
V(OUT) < V(OUT) or
V(OUT) > V(VCC)
up to |60 V|
80
µA
550
µA
10
µA
EN = HIGH, IN = LOW; V(OUT to VCC) = 3 V
EN = HIGH, IN = HIGH; V(OUT to GND) = -3 V
LINEAR REGULATOR (LDO)
V(VCC_OUT)
Voltage regulator output
TIOS1015
4.75
5
5.25
V
TIOS1013
3.13
3.3
3.46
V
TIOS1015
1.9
V
TIOS1013
2.3
V
mV/V
V(DROP)
Voltage regulator drop-out voltage
ICC = 20 mA load current
(V(VCC) – V(VCC_OUT))
REG
Line regulation
(dV(VCC_OUT)/dV(VCC)
I(VCC_OUT) = 1 mA
1.7
LREG
Load regulation
(dV(VCC_OUT)/V(VCC_OUT))
V(VCC) = 24 V, I(VCC_OUT) = 100 µA to 20 mA
1%
PSSR
Power Supply Rejection Ratio
100 kHz, I(VCC_OUT) = 20 mA
40
dB
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Driver propagation delay
tP(skew)
Driver propagation delay skew. |tPLH tPHL|
tPZH, tPZL
Driver enable delay
tPHZ, tPLZ
Driver disable delay
tr, tf
Driver output rise, fall time
|tr – tf|
Difference in rise and fall time
tSC
Current fault blanking time
tpSC
Current fault indication delay
tSCEN
Current fault driver re-enable wait time
t(UVLO)
OUT re-enable delay after UVLO
(1)
6
MIN
See Figure 5
See Figure 6
See Figure 7
RL = 2 kΩ
CL = 5 nF
R(SET) = 0 Ω
TYP
MAX
UNIT
600
800
ns
100
ns
4
µs
4
µs
150
ns
50
175
200
260
(1)
15
V(UVLO) rising threshold crossing
time to OUT enable time
10
30
ns
µs
µs
ms
50
ms
OUT output remains Hi-Z for this time
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6.7 Typical Characteristics
3
1.8
1.6
2.5
Residual Voltage (V)
Supply Current (mA)
1.4
2
1.5
1
1.2
1
0.8
0.6
0.4
-40qC
25qC
125qC
0.5
EN = High
EN = Low
0.2
0
0
0
5
10
No load
15
20
25
Supply Voltage (V)
30
35
40
0
IN = OPEN
100
150
Load Current (mA)
200
250
D002
25°C
Figure 1. Supply Current vs Supply Voltage
Figure 2. Residual Voltage vs Load Current: High Side
1.6
400
1.4
350
1.2
300
1
250
IO(LIM) (mA)
Residual Voltage (V)
50
D001
0.8
0.6
0.4
Low Side
High Side
200
150
100
-40qC
25qC
125qC
0.2
50
0
0
0
50
100
150
Load Current (mA)
200
250
0
20
D003
Figure 3. Residual Voltage vs Load Current: Low Side
40
60
RSET (k:)
80
100
D004
Figure 4. Current Limit vs RSET
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7 Parameter Measurement Information
VCC
RL
IN
OUT
RL
CL
EN
Figure 5. Test Circuit for Driver Switching
VOH
VOH
80%
80%
50%
IN
tPHL
OUT
tPHL
OUT
VOH
50%
20%
20%
OUT
VOL
VOL
VOL
tr
tf
Figure 6. Waveforms for Driver Output Switching Measurements
IN = Low
IN = High
50%
50%
EN
EN
tPLZ
tPLZ
tPZH
tPHZ
VVCC/2
VOH
50%
20%
OUT
VOL
80%
50%
OUT
VVCC/2
Figure 7. Waveforms for Driver Enable or Disable Time Measurements
8
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8 Detailed Description
8.1 Overview
Figure 8 shows that the device driver output (OUT) can be used in a push-pull, high-side, or low-side
configuration using the enable (EN) and transmit data (IN) input pins. OUT can drive resistive, large capacitive or
large inductive loads.
TIOS101 and TIOS101x devices have integrated IEC 61000-4-4/5 EFT and surge protection. In addition,
tolerance to ±65-V transients enables flexibility to choose from a wider range of TVS diodes if an application
requires higher levels of protection. These integrated robustness features will simplify the system-level design by
reducing the external protection circuitry.
These devices implement protection features for over-current, over-voltage and over-temperature conditions. The
devices also provide a current-limit setting of the driver output current using an external resistor.
The TIOS101x devices derive the low voltage supply from the typical 24 V industrial supply via an internal linear
regulator to provide power to the local controller and sensor circuitry.
8.2 Functional Block Diagrams
VCC
VCC_IN
Control
Logic
IN
EN
OUT
Diagnostics
& Control
NFAULT
CUR_OK
TMP_OK
PWR_OK
GND
ILIM_ADJ
Figure 8. Block Diagram, TIOS101
Voltage
Regulator
VCC_OUT
Control
Logic
IN
EN
VCC
OUT
Diagnostics
& Control
NFAULT
CUR_OK
TMP_OK
PWR_OK
GND
ILIM_ADJ
Figure 9. Block Diagram, TIOS101x
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8.3 Feature Description
8.3.1 Current Limit Configuration
The output current can be configured with an internal resistor on ILIM_ADJ pin. The maximum settable current
limit is 300 mA. This maximum setting specifies a minimum of 300 mA over temperature and voltage.
Output disable due to current fault and current fault auto recovery features can be disabled by floating ILIM_ADJ
pin. However, the current fault indication is still active in this configuration. This feature is useful when driving
large capacitances.
Table 1. Current Limitation
ILIM_ADJ Pin Condition
OUT Current Limit
NFAULT Indication During
Fault
Output Disable and Auto
Recovery
RSET resistor to GND
Variable
Yes
Yes
Connected to GND
300 mA
Yes
Yes
OPEN
300 mA
Yes
No
8.3.2 Current Fault Detection, Indication and Auto Recovery
If the output current at OUT exceeds the internally set current limit IO(LIM) for a duration longer than tSC, the
NFAULT pin is driven logic low to indicate a fault condition. The output is turned off, but the LDO continues to
function. The output periodically retries to check if the output is still in the over current condition. In this mode,
the output is switched on for tSC in tSCEN intervals. Current fault auto recovery mode can be disabled by setting
ILIM_ADJ = OPEN. See Table 3.Toggling EN will clear NFAULT.
8.3.3 Thermal Warning, Thermal Shutdown
If the die temperature exceeds T(WRN), the NFAULT flag is held low indicating a potential over temperature
problem. When the TJ exceeds T(SDN), The output is disabled but the LDO remains operational. As soon as the
temperature drops below the temperature threshold (and after T(HYS)), the internal circuit re-enables the driver,
subject to the state of the EN and IN pins.
10
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8.3.4 Fault Reporting (NFAULT)
NFAULT is driven low if either a current fault condition is detected, die temperature has exceeded T(WRN) or
supply has dropped below the UVLO threshold. NFAULT returns to high-impedance as soon as all three fault
conditions clear.
EN
*
EN
Current
Fault
T >TWRN
CUR_OK = Z
TMP_OK = L
Driver= EN/EN*
LDO= ON
CUR_OK = L
Driver = OFF
LDO= ON
t= tSCEN
T < (TSD + THYS)
Out at IO(LIM) and T < TWRN
OUT NOT at IO(LIM)
T < TWRN & EN*
&
OUT at IO(LIM)
T<
RN
TW
RN
TW
for t > tsc
T > TWRN
CUR_OK = Z
Driver = ON
LDO = ON
T>
Thermal
Warning
T > TSD
Normal
Operation
EN*
CUR_OK=Z
Driver = OFF
LDO = ON
OUT at IO(LIM)
Output at Hi-Z
Current
Fault Recovery
Thermal
Shutdown
CUR_OK = L
CUR_OK = Z
TMP_OK = L
Driver = OFF
LDO = ON
Driver = ON for tsc
LDO= ON
NFAULT = [CUR_OK && PWR_OK && TMP_OK]
Figure 10. Device State Diagram
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8.3.5 Device Function Tables
Table 2. Driver Function
EN
IN
OUT
COMMENT
L / Open
X
Hi-Z
H
L
H
OUT is sourcing current (high-side drive)
H
H / Open
L
OUT is sinking current (low-side drive)
Device is in ready-to-receive state
Table 3. Current Limit Indicator Function (t > tSC)
EN
H
IN
H / Open
H
L
L / Open
X
OUT CURRENT
NFAULT
| I(OUT) | > IO(LIM)
L
OUT current exceeds the set limit for over tSC
COMMENT
| I(OUT) | < IO(LIM)
Z
Normal operation
| I(OUT) | > IO(LIM)
L
OUT current exceeds the set limit for over tSC
| I(OUT) | < IO(LIM)
Z
Normal operation
X
Z
Driver is disabled, current limit indicator is inactive
8.3.6 The Integrated Voltage Regulator (LDO)
The TIOS1013 and TIOS1015 each have an integrated linear voltage regulator (LDO) which can supply power to
external components. The voltage regulator is specified for VCC voltages in the range of 7 V to 36 V with respect
to GND. The LDO is capable of delivering up to 20 mA. The LDO output is current limited to 35-mA to limit the
inrush current onto VCC_OUT decoupling capacitors during initial power up.
The LDO is designed to be stable with standard ceramic capacitors with values of 1 μF or larger at the output.
X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature.
Maximum ESR should be less than 1 Ω. With tolerance and dc bias effects, the minimum capacitance to ensure
stability is 1 μF.
12
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8.3.7 Reverse Polarity Protection
Reverse polarity protection circuitry protects the devices against accidental reverse polarity connections to the
VCC, OUT and GND pins. The maximum voltage between any of the pins may not exceed 60 V DC at any time.
Figure 11 and Figure 12 shows all the possible connection combinations.
VCC
VCC
DC
OUT
TIOS101(x)
OUT
DC
TIOS101(x)
RL
GND
RL
GND
Correct
Configuration
Reverse Polarity Prot ected
Fault Conditions
VCC
VCC
DC
OUT
TIOS101(x)
RL
GND
OUT
DC
TIOS101(x)
GND
RL
Reverse Polarity Prot ected
Reverse Polarity Prot ected
Fault Conditions
Fault Conditions
VCC
TIOS101(x)
VCC
DC
OUT
RL
GND
OUT
DC
TIOS101(x)
GND
RL
Reverse Polarity Prot ected
Reverse Polarity Prot ected
Fault Conditions
Fault Conditions
Figure 11. High-Side Driver Configuration
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VCC
VCC
DC
OUT
TIOS101(x)
DC
OUT
TIOS101(x)
RL
RL
GND
GND
Reverse Polarity Prot ected
Fault Conditions
Correct
Configuration
VCC
VCC
DC
OUT
TIOS101(x)
DC
OUT
TIOS101(x)
RL
RL
GND
GND
Reverse Polarity Prot ected
Fault Conditions
Reverse Polarity Prot ected
Fault Conditions
VCC
VCC
TIOS101(x)
DC
OUT
TIOS101(x)
DC
OUT
RL
RL
GND
Reverse Polarity Prot ected
Fault Conditions
GND
Reverse Polarity Prot ected
Fault Conditions
Figure 12. Low-Side Driver Configuration
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8.3.8 Integrated Surge Protection and Transient Waveform Tolerance
The VCC and OUT pins of the device are capable of withstanding up to 1.2 kV of 1.2/50 – 8/20 μs IEC 61000-4-5
surge with a source impedance of 500 Ω. The surge testing should be performed with a minimum 100 nF supply
decoupling capacitor between VCC and GND, and 1 µF between VCC_IN/OUT and GND.
External TVS diodes may be required for higher transient protection levels. The system designer should ensure
that the maximum clamping voltage of the external diodes should be < 65 V at the desired current level. The
device is capable of withstanding up to ±65-V transient pulses < 100 µs.
Combination
Wave
Generator
R
Protection
Equipment
Auxiliary
Equipment
EUT
VCC
OUT
Decoupling
Network
>100nF
GND
1.2/50 - 80/20 µs CWG
R = 500 Ω
Figure 13. Surge Test Setup
8.3.9 Power Up Sequence
VCC_IN and VCC domains can be powered up in any sequence. In the event of VCC is powered and VCC_IN is
not, the OUT pin remains in high impedance.
8.3.10 Undervoltage Lock-Out (UVLO)
The device enters UVLO if the VCC voltage falls below V(UVLO). (For the device without the integrated LDO, the
device monitors VCC_IN in addition to VCC. UVLO happens if either supply falls below the threshold.)
As soon as the supply falls below V(UVLO), NFAULT is pulled low, the LDO is turned off and the OUT output is
disabled (Hi-Z). Receiver performance is not specified in this mode.
When the supply rises above V(UVLO), NFAULT returns to Hi-Z (given no other fault conditions present) and the
LDO will be enabled immediately. The OUT output will be turned on after T(UVLO) delay.
8.4 Device Functional Modes
These devices can operate in three different modes.
8.4.1 NPN Configuration (N-Switch Mode)
Set IN pin high (or open) and use EN pin as control for realizing the function of an N-switch (low-side
configuration) on OUT.
8.4.2 PNP Configuration (P-Switch Mode)
Set IN pin low and use EN pin as control for realizing the function of a P-switch (high-side configuration) on OUT.
8.4.3 Push-Pull Mode
Set EN pin high and toggle IN as control for realizing the function of a push-pull output on OUT. Table 4, Table 5
and Table 6 summarize the pin configurations to accomplish the functional modes.
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Table 4. NPN Mode
EN
IN
OUT
L / Open
H / Open
Hi-Z
H
H / Open
N-Switch
Table 5. PNP Mode
EN
IN
L / Open
L
OUT
Hi-Z
H
L
P-Switch
Table 6. Push-Pull Mode
16
EN
IN
L / Open
X
Hi-Z
H
H / Open
N-Switch
H
L
P-Switch
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OUT
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
TIOS101 and TIOS101x are robust 24-V digital drivers for industrial sensors.
9.2 Typical Application
TIO S101(x)
VCC_OUT
VCC
VOL TA GE
REGULATOR
0.1 µF
100 V
1 µF
10 V
10 kŸ
Sen sor
Front-End
CONTROL
LOG IC
IN
EN
OUT
DIA GNOSTICS
and
CONTROL
NFA UL T
CUR_OK
TMP_OK
PWR_OK
GND
ILIM_ADJ
R SET
Figure 14. Typical Application Schematic
9.2.1 Design Requirements
Table 7 shows recommended components for a typical system design.
Table 7. Design Parameters
PARAMETERS
VALUE
Input voltage range (VCC)
24 V, 30 V (max)
Output current (OUT)
200 mA
Output voltage (VCC_OUT), Pick TIOS1015
5V
Maximum LDO output current (IVCC(OUT))
5 mA
Pull-up resistors for NFAULT
10 kΩ
VCC decoupling capacitor
0.1 µF / 100 V
LDO output capacitor
1 µF / 10 V
ILIM_ADJ resistor (RSET)
10 kΩ
Maximum Ambient Temperature, TA
105°C
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9.2.2 Detailed Design Procedure
9.2.2.1 Maximum Junction Temperature Check
For a 200 mA current limit:
• The maximum driver output current limit, IO(LIM) = 250 mA (allowed for current limit tolerance).
• The maximum voltage drop across the high-side switch is given with VDS(ON) = 1.75 V.
This causes a power consumption of:
2&12 = 8&5(10) T +1(.+/) = 1.758 T 250 I# = 437.5 I9
(1)
For a 5 mA LDO current output,
2&.&1 = k8.+ F 88%%_176 o x +8%%_176 = :30 F 5;V x 5 mA = 125 mW
(2)
Total power dissipation,
2& = 2&12 + 2&.&1 = 437.5 I9 + 125 I9 = 562.5 I9
(3)
Multiply this value with the Junction-to-ambient thermal resistance of θJA = 68.1°C/W (taken from the Thermal
Information table) to receive the difference between junction temperature, TJ, and ambient temperature, TA:
¿6 = 6, F 6# = 2& x E,# = 562.5 I9 T 68.1°%/9 = 38.3°%
(4)
Add this value to the maximum ambient temperature of TA = 105°C to receive the final junction temperature:
6, FI=T = 6#FI=T + ¿6 = 105°% + 38.3°% = 143.3°%
(5)
As long as TJ-max is below the recommended maximum value of 150°C, no thermal shutdown will occur.
However, thermal warning may occur as the junction temperature is greater than TWRN.
Note that the modeling of the complete system may be necessary to predict junction temperature in smaller
PCBs and/or enclosures without air flow.
9.2.2.2 Driving Capacitive Loads
These devices are capable of driving capacitive loads on the OUT output. Assuming a pure capacitive load
without series/parallel resistance, the maximum capacitance that can be charged without triggering current fault
can be calculated as:
CLOAD
[IO LIM x t SC ]
V VCC
(6)
Higher capacitive loads can be driven if a series resistor is connected between the OUT and the load. Capacitive
loads can be connected to VCC and GND.
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9.2.2.3 Driving Inductive Loads
The TIOS101(x) family is capable of magnetizing and demagnetizing inductive loads up to 1.5 H. These devices
contain internal circuitry that enables fast demagnetization when configured as either P-switch or N-switch mode.
In P-switch configuration, the load inductor L is magnetized when the OUT pin is driven high. When the PNP is
turned off, there is a significant amount of negative inductive kick back at the OUT pin. This voltage is clamped
internally at about -75 V.
Similarly in N-switch configuration, the load inductor L is magnetized when the OUT pin is driven low. When the
NPN is turned off, there is a significant amount of positive inductive kick back at the OUT pin. This voltage is
clamped internally at about 75 V.
The equivalent protection circuits are shown in Figure 15 and Figure 16. The minimum value of the resistive load
R can be calculated as:
R
V VCC
IO( LIM )
(7)
spacer
VCC
VCC
R
OUT
OUT
L
L
R
TIO S101(x)
TIO S101(x)
Figure 15. PNP Mode
Figure 16. NPN Mode
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3 V/div
8 V/div
10 V/div
2 V/div
10 V/div
9.2.3 Application Curves
Time 10 ms/div
Time 1 Ps/div
125 kHz
Figure 18. OUT Power Up Delay, Low Side Mode
4 V/div
3 V/div
10 V/div
300 mA/div
10 V/div
800 mV/div
Figure 17. OUT in Push-Pull Mode
Time 50 Ps/div
Time 10 ms/div
Figure 20. OUT In Current Fault, Low Side Mode
4 V/div
4 V/div
300 mA/div
300 mA/div
6 V/div
6 V/div
Figure 19. OUT Power Up Delay, High Side Mode
Time 10 ms/div
Time 50 Ps/div
Figure 21. OUT In Current Fault, High Side Mode
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Figure 22. OUT In Current Fault Auto Recovery,
Low Side Mode
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3 V/div
4 V/div
40 V/div
300 mA/div
2 V/div
6 V/div
www.ti.com
Time 10 ms/div
Time 10 ms/div
1.5-H
Induct
or
Figure 23. OUT In Current Fault Auto Recovery,
High Side Mode
With =
100 Ω
RSET =
OPEN
3 V/div
40 V/div
2 V/div
Figure 24. OUT Driving, Low Side Mode
Time 10 ms/div
1.5-H Inductor
With = 100 Ω
RSET = OPEN
Figure 25. OUT Driving, High Side Mode
10 Power Supply Recommendations
The TIOS101 and TIOS101x are designed to operate from a 24-V nominal supply at VCC, which can vary by
+12 V and -17 V from the nominal value to remain within the device's recommended supply voltage range of 7 V
to 36 V. This supply should be buffered with at least a 100-nF/100-V capacitor.
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11 Layout
11.1 Layout Guidelines
•
Use of a 4-layer board is recommended for good heat conduction. Use layer 1 (top layer) for control signals,
layer 2 as GND, layer 3 for the 24-V supply plane (VCC), and layer 4 for the regulated output supply
(VCC_IN/OUT).
Connect the thermal pad to GND with maximum amount of thermal vias for best thermal performance.
Use entire planes for VCC, VCC_IN/OUT and GND to assure minimum inductance.
The VCC terminal must be decoupled to ground with a low-ESR ceramic decoupling capacitor with a
minimum value of 100 nF. The capacitor must have a voltage rating of 50 V minimum (100 V depending on
max sensor supply fault rating) and an X5R or X7R dielectric.
• The optimum placement of the capacitor is closest to the VCC and GND terminals to reduce supply drops
during large supply current loads. See Figure 26 for a PCB layout example.
Connect all open-drain control outputs via 10 kΩ pull-up resistors to the VCC_IN/OUT plane to provide a
defined voltage potential to the system controller inputs when the outputs are high-impedance.
Connect the RSET resistor between ILIM_ADJ and GND.
Decouple the regulated output voltage at VCC_IN/OUT to ground with a low-ESR, 1 μF, ceramic decoupling
capacitor. The capacitor should have a voltage rating of 10 V minimum and an X5R or X7R dielectric.
•
•
•
•
•
•
•
11.2 Layout Example
VIA to Layer 2: Power Ground Plane (VCC)
VIA to Layer 3: 24V Supply Plane (GND)
VIA to Layer 4: Regulated Supply Plane (VCC_IN/OUT)
1uF/10V
VC
100nF/
50V
T
U
/O
N
_I
C
NFAULT
NC
VCC
VCC
NC
OUT
GND
EN
ILIM_ADJ
OUT
IN
Exposed Thermal
Pad Area
RSET
GND
Use Multiple Vias for
VCC and GND
Figure 26. Layout Example
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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30-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TIOS1013DMWR
ACTIVE
VSON
DMW
10
1500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TS1013
TIOS1013DMWT
ACTIVE
VSON
DMW
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TS1013
TIOS1015DMWR
ACTIVE
VSON
DMW
10
1500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TS1015
TIOS1015DMWT
ACTIVE
VSON
DMW
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TS1015
TIOS101DMWR
ACTIVE
VSON
DMW
10
1500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TS101
TIOS101DMWT
ACTIVE
VSON
DMW
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TS101
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-May-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TIOS1013DMWR
VSON
DMW
10
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1500
178.0
13.5
2.75
3.35
1.05
8.0
12.0
Q2
TIOS1013DMWT
VSON
DMW
10
250
178.0
13.5
2.75
3.35
1.05
8.0
12.0
Q2
TIOS1015DMWR
VSON
DMW
10
1500
178.0
13.5
2.75
3.35
1.05
8.0
12.0
Q2
TIOS1015DMWT
VSON
DMW
10
250
178.0
13.5
2.75
3.35
1.05
8.0
12.0
Q2
TIOS101DMWR
VSON
DMW
10
1500
178.0
13.5
2.75
3.35
1.05
8.0
12.0
Q2
TIOS101DMWT
VSON
DMW
10
250
178.0
13.5
2.75
3.35
1.05
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-May-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TIOS1013DMWR
VSON
DMW
10
1500
189.0
185.0
36.0
TIOS1013DMWT
VSON
DMW
10
250
189.0
185.0
36.0
TIOS1015DMWR
VSON
DMW
10
1500
189.0
185.0
36.0
TIOS1015DMWT
VSON
DMW
10
250
189.0
185.0
36.0
TIOS101DMWR
VSON
DMW
10
1500
189.0
185.0
36.0
TIOS101DMWT
VSON
DMW
10
250
189.0
185.0
36.0
Pack Materials-Page 2
PACKAGE OUTLINE
DMW0010A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
2.6
2.4
C
1 MAX
SEATING PLANE
0.08 C
1.65 0.1
(0.2) TYP
0.05
0.00
SYMM
EXPOSED
THERMAL PAD
5
2X
2
6
SYMM
11
1.95 0.1
1
10
8X 0.5
PIN 1 ID
(OPTIONAL)
0.475
10X
0.275
10X
0.29
0.19
0.1
0.05
C A B
C
4223225/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DMW0010A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
10X (0.575)
(0.575)
1
10
10X (0.24)
(0.725)
11
SYMM
(1.95)
8X (0.5)
(R0.05) TYP
5
6
( 0.2) VIA
TYP
SYMM
(2.825)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223225/A 08/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DMW0010A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.575)
1
SYMM
METAL
TYP
11
10
10X (0.24)
(0.535)
SYMM
8X (0.5)
(0.87)
(R0.05) TYP
5
6
2X (1.5)
(2.825)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11
81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4223225/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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