Texas Instruments | DS90LV028AQ-Q1 Automotive LVDS Dual Differential Line Receiver (Rev. H) | Datasheet | Texas Instruments DS90LV028AQ-Q1 Automotive LVDS Dual Differential Line Receiver (Rev. H) Datasheet

Texas Instruments DS90LV028AQ-Q1 Automotive LVDS Dual Differential Line Receiver (Rev. H) Datasheet
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DS90LV028AQ-Q1
SNLS299H – MAY 2008 – REVISED MAY 2019
DS90LV028AQ-Q1 Automotive LVDS Dual Differential Line Receiver
1 Features
3 Description
•
The DS90LV028AQ is a dual CMOS differential line
receiver designed for applications requiring ultra low
power dissipation, low noise and high data rates. The
device is designed to support data rates in excess of
400 Mbps (200 MHz) utilizing Low Voltage Differential
Signaling (LVDS) technology.
1
•
•
•
•
•
•
•
•
•
•
•
AECQ-100 Qualified for Automotive Applications
– Temperature Grade 1: -40°C to +125°C TA
>400 Mbps (200 MHz) Switching Rates
50 ps Differential Skew (Typical)
0.1 ns Channel-to-Channel Skew (Typical)
2.5 ns Maximum Propagation Delay
3.3V Power Supply Design
Flow-Through Pinout
Power Down High Impedance on LVDS Inputs
Low Power design (18 mW at 3.3 V static)
LVDS Inputs Accept LVDS/CML/LVPECL Signals
Conforms to ANSI/TIA/EIA-644 Standard
Available in SOIC Package
The DS90LV028AQ accepts low voltage (350 mV
typical) differential input signals and translates them
to 3V CMOS output levels. The DS90LV028AQ has a
flow-through design for easy PCB layout.
The DS90LV028AQ and companion LVDS line driver
DS90LV027AQ provide a new alternative to high
power PECL/ECL devices for high speed point-topoint interface applications.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
DS90LV028AQ
LVDS-to-LVCMOS Translation
Infotainment and Cluster
Automotive Head Unit
PACKAGE
BODY SIZE (NOM)
SOIC (D 8)
4.90 mm x 3.91 mm
WSON (DQF 8)(2)
2.00 mm x 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Product Preview
Functional Diagram
RIN1-
R
ROUT1
R
ROUT2
RIN1+
RIN2-
RIN2+
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
DS90LV028AQ-Q1
SNLS299H – MAY 2008 – REVISED MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Performance Curves.....................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Functional Block Diagram ......................................... 9
8.2 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................. 12
11 Device and Documentation Support ................. 13
11.1
11.2
11.3
11.4
11.5
Device Support ....................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
12 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (November 2018) to Revision H
Page
•
Deleted the Thermal Pad from the DQF package .................................................................................................................. 3
•
Changed VCC 0.3 To: VCC + 0.3 in the Absolute Maximum Ratings table.............................................................................. 4
•
Added NOTE: "These parameters are specified by design." ................................................................................................. 5
Changes from Revision F (August 2018) to Revision G
Page
•
Changed the Pin image views ............................................................................................................................................... 3
•
Changed the Pin Descriptions format .................................................................................................................................... 3
Changes from Revision E (April 2013) to Revision F
Page
•
Added Applications list, Device Information table, ESD Ratings table, Device Functional Modes, Application and
Implementation section, Layout section, Device and Documentation Support section.......................................................... 1
•
Added the DQF package to the data sheet ........................................................................................................................... 3
Changes from Revision D (April 2013) to Revision E
•
2
Page
Changed layout of National Data Sheet to TI format ............................................................................................................. 7
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5 Pin Configuration and Functions
D Package
SOIC 8 Pin
Top View
DQF Package
WSON 8 Pin
Top View
RIN1-
1
8
VCC
RIN1+
2
7
ROUT1
RIN2+
3
6
ROUT2
RIN2-
5
4
RIN1-
1
8
VCC
RIN1+
2
7
ROUT1
RIN2+
3
6
ROUT2
RIN2-
4
5
GND
GND
(1)
DQF - Product Preview
Pin Descriptions
Pin Number
Name
1
RIN1-
4
RIN2-
2
RIN1+
3
RIN2+
6
ROUT2
7
ROUT1
Description
Inverting receiver input pin
Non-inverting receiver input pin
Receiver output pin
8
VCC
Power supply pin, +3.3V +/- 0.3V
5
GND
Ground pin
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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
MIN
MAX
UNIT
Supply Voltage (VCC)
−0.3
4
V
Input Voltage (RIN+, RIN−)
−0.3
3.9
V
VCC + 0.3
V
260
°C
135
°C
150
°C
−0.3
Output Voltage (ROUT)
Lead Temperature Range Soldering
(4 sec.)
Maximum Junction Temperature
−65
Storage temperature, Tstg
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±8000
Charged-device model (CDM), per JEDEC specification JESD22-C101
or ANSI/ESDA/JEDEC JS-002 (2)
±1250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. .
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Supply Voltage (VCC)
Min
Typ
Max
Units
3
3.3
3.6
V
3
V
+125
°C
Receiver Input Voltage
GND
Operating Free Air Temperature (TA)
−40
25
6.4 Thermal Information
DS90LV028AQ
THERMAL METRIC (1)
D (SOIC)
DQF (WSON)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
103.0
104
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
41.0
n/a
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
Symbol
Parameter
Conditions
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
RIN+,
RIN−
VCC = 3.6 V or 0 V
VIN = 0V
Input Current
VOH
Output High Voltage
IOH = −0.4 mA, VID = +200 mV
VOL
Output Low Voltage
IOL = 2 mA, VID = −200 mV
VIN = +3.6V
VCC = 0 V
Output Short Circuit Current
VOUT = 0 V
VCL
Input Clamp Voltage
ICL = −18 mA
ICC
No Load Supply Current
Inputs Open
Typ
Max
Units
+100
mV
mV
−10
±1
+10
μA
−10
±1
+10
μA
+20
μA
-20
2.7
ROUT
(3)
IOS
Min
−100
IIN
(2)
(3)
Pin
VCM = +1.2 V, 0 V, 3 V
VIN = +2.8V
(1)
(1) (2)
3.1
V
0.3
0.5
V
−15
−50
−100
mA
−1.5
−0.8
9
mA
VCC
5.4
V
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified (such as VID).
All typicals are given for: VCC = +3.3V and TA = +25°C.
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted
at a time, do not exceed maximum junction temperature specification.
6.6 Switching Characteristics (1)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (2) (3) (4)
Min
Typ
Max
Units
tPHLD
Symbol
Differential Propagation Delay High to Low
Parameter
CL = 15 pF
Conditions
1
1.6
2.5
ns
tPLHD
Differential Propagation Delay Low to High
VID = 200 mV
1
1.7
2.5
ns
tSKD1
Differential Pulse Skew |tPHLD − tPLHD|
0
50
650
ps
tSKD2
Differential Channel-to-Channel Skew-same device
0
0.1
0.5
ns
(5)
(Figure 15 and Figure 16)
(6)
tSKD3
Differential Part to Part Skew
(7)
tSKD4
Differential Part to Part Skew
(8)
tTLH
Rise Time
325
800
ps
tTHL
Fall Time
225
800
ps
fMAX
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Maximum Operating Frequency
(9)
0
1
ns
0
1.5
ns
250
MHz
These parameters are specified by design. The min/max limits are not tested in production and are based on statistical analysis of the
device performance over PVT (process, voltage, temperature) ranges.
All typicals are given for: VCC = +3.3V and TA = +25°C.
CL includes probe and jig capacitance.
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0% to 100%) ≤ 3 ns for RIN.
tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of
the same channel.
tSKD2 is the differential channel-to-channel skew of any event on the same device. This specification applies to devices having multiple
receivers within the integrated circuit.
tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
at the same VCC and within 5°C of each other within the operating temperature range.
tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over the recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min|
differential propagation delay.
fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria:
60%/40% duty cycle, VOL (max 0.4V), VOH (min 2.7V), load = 15 pF (stray plus probes).
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6.7 Typical Performance Curves
Figure 1. Output High Voltage vs Power Supply Voltage
Figure 2. Output Low Voltage vs Power Supply Voltage
Figure 3. Output Short Circuit Current vs Power Supply
Voltage
Figure 4. Differential Transition Voltage vs Power Supply
Voltage
Figure 5. Power Supply Current vs Frequency
Figure 6. Differential Propagation Delay vs Power Supply
Voltage
6
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Typical Performance Curves (continued)
Figure 7. Differential Propagation Delay vs Differential Input
Voltage
Figure 8. Differential Propagation Delay vs Common-Mode
Voltage
Figure 9. Transition Time vs Power Supply Voltage
Figure 10. Differential Skew vs Power Supply Voltage
Figure 11. Differential Propagation Delay vs Load
Figure 12. Differential Propagation Delay vs Load
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Typical Performance Curves (continued)
Figure 13. Transition Time vs Load
Figure 14. Transition Time vs Load
7 Parameter Measurement Information
Figure 15. Receiver Propagation Delay and Transition Time Test Circuit
Figure 16. Receiver Propagation Delay and Transition Time Waveforms
8
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8 Detailed Description
8.1 Functional Block Diagram
RIN1-
R
ROUT1
R
ROUT2
RIN1+
RIN2-
RIN2+
8.2 Device Functional Modes
Table 1. Truth Table
(1)
INPUTS
OUTPUT
[RIN+] − [RIN−]
ROUT
VID ≥ 0.1V
H
VID ≤ −0.1V
L
−0.1V ≤ VID ≤ 0.1V
? (1)
? indicates state is indeterminate
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
General application guidelines and hints for LVDS drivers and receivers may be found in the following application
notes: LVDS Owner's Manual at www.ti.com.
LVDS drivers and receivers are intended to be primarily used in a simple point-to-point configuration as is shown
in Figure 17. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The
receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a
parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of
100Ω. A termination resistor of 100Ω should be used, and is located as close to the receiver input pins as
possible. The termination resistor converts the driver output (current mode) into a voltage that is detected by the
receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream
connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits,
and total termination loading must be taken into account.
The DS90LV028AQ differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V
common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V.
The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting
may be the result of a ground potential difference between the driver's ground reference and the receiver's
ground reference, the common-mode effects of coupled noise, or a combination of the two. The AC parameters
of both receiver input pins are optimized for a recommended operating input voltage range of 0V to +2.4V
(measured from each pin to ground). The device will operate for receiver input voltages up to VCC, but exceeding
VCC will turn on the ESD protection circuitry which will clamp the bus voltages.
9.2 Typical Application
Figure 17. Balanced System Point-to-Point Application
9.2.1 Detailed Design Procedure
9.2.1.1 Power Decoupling Recommendations
Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)
0.1 μF and 0.01 μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the
device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple
vias should be used to connect the decoupling capacitors to the power planes. A 10 μF (35 V) or greater solid
tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply
and ground.
9.2.1.2 Termination
Use a termination resistor which best matches the differential impedance or your transmission line. The resistor
should be between 90 Ω and 130 Ω. Remember that the current mode outputs need the termination resistor to
generate the differential voltage. LVDS will not work correctly without resistor termination. Typically, connecting a
single resistor across the pair at the receiver end will suffice.
10
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Typical Application (continued)
Surface mount 1% - 2% resistors are the best. PCB stubs, component lead, and the distance from the
termination to the receiver inputs should be minimized. The distance between the termination resistor and the
receiver should be < 10 mm (12 mm MAX).
9.2.1.3 Input Failsafe Biasing
External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe
under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor
and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors
should be in the 5 kΩ to 15 kΩ range to minimize loading and waveform distortion to the driver. The commonmode bias point ideally should be set to approximately 1.2 V (less than 1.75 V) to be compatible with the internal
circuitry. Please refer to application note AN-1194, “Failsafe Biasing of LVDS Interfaces” (SNLA051)for more
information.
9.2.1.4 Probing LVDS Transmission Lines
Always use high impedance (> 100 kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
9.2.1.5 Cables and Connectors, General Comments
When choosing cable and connectors for LVDS it is important to remember:
Use controlled impedance media. The cables and connectors you use should have a matched differential
impedance of about 100Ω. They should not introduce major impedance discontinuities.
Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for
noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and
also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by
the receiver.
For cable distances < 0.5 M, most cables can be made to work effectively. For distances 0.5 M ≤ d ≤ 10 M, CAT
3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive.
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10 Layout
10.1 Layout Guidelines
10.1.1 Differential Traces
Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable)
and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave
the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as
common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than
traces 3mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise
induced on the differential lines is much more likely to appear as common-mode which is rejected by the
receiver.
Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI
will result! (Note that the velocity of propagation, v = c/E r where c (the speed of light) = 0.2997 mm/ps or 0.0118
in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match
differential impedance and provide isolation for the differential lines. Minimize the number of vias and other
discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode
rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid
discontinuities in differential impedance. Minor violations at connection points are allowable.
10.1.2 PC Board Considerations
Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to
put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
12
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11 Device and Documentation Support
11.1 Device Support
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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20-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS90LV028AQDQFRQ1
PREVIEW
WSON
DQF
8
3000
TBD
Call TI
Call TI
DS90LV028AQDQFTQ1
PREVIEW
WSON
DQF
8
250
TBD
Call TI
Call TI
DS90LV028AQMA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
90LV0
28AQM
DS90LV028AQMAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
90LV0
28AQM
PDS90LV028AQDQFTQ1
ACTIVE
WSON
DQF
8
250
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
20-Sep-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DS90LV028AQMAX/NOP
B
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
5.4
2.0
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90LV028AQMAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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