Texas Instruments | TPS65987DDJ USB Type-C and USB PD Controller with Integrated Power Switches | Datasheet | Texas Instruments TPS65987DDJ USB Type-C and USB PD Controller with Integrated Power Switches Datasheet

Texas Instruments TPS65987DDJ USB Type-C and USB PD Controller with Integrated Power Switches Datasheet
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TPS65987DDJ
SLVSF34 – MAY 2019
TPS65987DDJ USB Type-C and USB PD Controller with Integrated Power Switches
1 Features
•
1
•
•
•
•
•
USB Power Delivery (PD) controller
– USB PD 3.0 compliant (TID: 1067)
– Fast role swap support
– Physical layer and policy engine
– Configurable at boot and host-controlled
USB Type-C specification compliant
– Cable attach and orientation detection
– Default, 1.5-A, or 3-A power advertisement
– Up to 600-mA VConn current
Port power switch
– Two 5 V to 20 V, 5-A bidirectional switches to
or from VBUS
– Up to 10-A Adjustable current limiting
– Ideal diode reverse current protection
– Undervoltage, and overvoltage protection
– Slew rate control
– 5-V, 600-mA VConn source
BC1.2 Support
– Advertisement as DCP and CDP
– Automatic DCP modes selection:
– Shorted mode per BC1.2 and YD/T 15912009
– 2.7-V Divider 3 mode
– 1.2-V Mode
– Data contact detect
– Primary and secondary detection
I2C Master write control for alt mode muxes and
variable DCDCs
•
•
Alternate mode support
– Displayport
– Thunderbolt™
Power management
– Power supply from 3.3 V or VBUS source
– 3.3-V LDO Output for dead battery support
7-mm × 7-mm QFN package
– 0.4-mm Pitch
– 56 Pin
2 Applications
•
•
•
•
Notebook computers
Docking systems
Tablets and ultrabooks
Displayport, and Thunderbolt™ systems
3 Description
The TPS65987DDJ is a stand-alone USB Type-C and
Power Delivery (PD) controller providing cable plug
and orientation detection for a single USB Type-C
connector. Upon cable detection, the TPS65987DDJ
communicates on the CC wire using the USB PD
protocol. When cable detection and USB PD
negotiation are complete, the TPS65987DDJ enables
the appropriate power path and configures alternate
mode settings for external multiplexers.
Device Information(1)
PART NUMBER
TPS65987DDJ
PACKAGE
QFN (56)
BODY SIZE (NOM)
7.00 mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
5-20 V
5A
5-20 V
VBUS
5A
3.3 V
Host
Host
Interface
Type-C Cable Detection
and
USB PD Controller
CC1/2
CC
VCONN
2
USB
Type-C
Connector
TPS65987D
BC1.2
USB P/N
2
D+/-
GND
Alternate Mode Mux Ctrl
GPIO or I2C
SuperSpeed Mux/Retimer
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65987DDJ
SLVSF34 – MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 40
1
1
1
2
3
6
9
9.1 Application Information............................................ 43
9.2 Typical Application ................................................. 43
10 Power Supply Recommendations ..................... 53
10.1 3.3-V Power .......................................................... 53
10.2 1.8-V Power .......................................................... 53
10.3 Recommended Supply Load Capacitance............ 53
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Power Supply Requirements and Characteristics..... 7
Power Consumption Characteristics......................... 8
Power Switch Characteristics ................................... 8
Cable Detection Characteristics.............................. 10
USB-PD Baseband Signal Requirements and
Characteristics ......................................................... 11
6.10 BC1.2 Characteristics ........................................... 12
6.11 Thermal Shutdown Characteristics ....................... 12
6.12 Oscillator Characteristics ...................................... 13
6.13 I/O Characteristics................................................. 13
6.14 I2C Requirements and Characteristics.................. 13
6.15 SPI Master Timing Requirements ......................... 15
6.16 HPD Timing Requirements ................................... 15
6.17 Typical Characteristics .......................................... 15
7
8
Application and Implementation ........................ 43
11 Layout................................................................... 54
11.1
11.2
11.3
11.4
Layout Guidelines ................................................. 54
Layout Example .................................................... 54
Component Placement.......................................... 55
Routing PP_HV1/2, VBUS, PP_CABLE, VIN_3V3,
LDO_3V3, LDO_1V8 ............................................... 56
11.5 Routing CC and GPIO .......................................... 58
11.6 Thermal Dissipation for FET Drain Pads .............. 59
11.7 USB2 Recommended Routing For BC1.2
Detection/Advertisement .......................................... 61
12 Device and Documentation Support ................. 63
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Parameter Measurement Information ................ 16
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 18
Device Support ....................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
63
63
63
63
63
63
64
13 Mechanical, Packaging, and Orderable
Information ........................................................... 64
4 Revision History
2
DATE
REVISION
NOTES
May 2019
*
Initial release.
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5 Pin Configuration and Functions
43 ± GPIO15 (PWM)
44 ± HRESET
45 ± GND
46 ± GND
47 ± GND
48 ± GPIO16 (PEXT1)
49 ± GPIO17 (PEXT2)
51 ± GND
50 ± C_USB_P (GPIO18)
53 ± C_USB_N (GPIO19)
52 ± DRAIN2
54 ± GPIO20
55 ± GPIO21
56 ± DRAIN2
RSH Package
56-Pin QFN
Top View
PP_HV2 ± 1
42 ± GPIO14 (PWM)
PP_HV2 ± 2
41 ± GPIO13
VBUS2 ± 3
40 ± GPIO12
57
DRAIN2
VBUS2 ± 4
39 ± SPI_SS (GPIO11)
VIN_3V3 ± 5
38 ± SPI_CLK (GPIO10)
ADCIN1 ± 6
37 ± SPI_MOSI (GPIO9)
DRAIN2 ± 7
36 ± SPI_MISO (GPIO8)
59
GND
DRAIN1 ± 8
35 ± LDO_1V8
34 ± I2C2_IRQ
LDO_3V3 ± 9
ADCIN2 ± 10
33 ± I2C2_SDA
58
DRAIN1
PP_HV1 ± 11
32 ± I2C2_SCL
PP_HV1 ± 12
31 ± GPIO4
VBUS1 ± 13
30 ± HPD (GPIO3)
VBUS1 ± 14
29 ± I2C1_IRQ
28 ± I2C1_SDA
27 ± I2C1_SCL
26 ± C_CC2
25 ± PP_CABLE
24 ± C_CC1
23 ± I2C3_IRQ (GPIO7)
22 ± I2C3_SDA (GPIO6)
21 ± I2C3_SCL (GPIO5)
20 ± GND
19 ± DRAIN1
18 ± GPIO2
17 ± GPIO1
16 ± GPIO0
15 ± DRAIN1
Pin Functions
PIN
NAME
NO.
TYPE (1)
RESET STATE (2)
DESCRIPTION
ADCIN1
6
I
Input
Boot configuration Input. Connect to resistor
divider between LDO_3V3 and GND.
ADCIN2
10
I
Input
I2C address configuration Input. Connect to
resistor divider between LDO_3V3 and GND.
C_CC1
24
I/O
High-Z
(1)
(2)
Output to Type-C CC or VCONN pin. Filter noise
with capacitor to GND
I = input, O = output, I/O = bidirectional, GND = ground, PWR = power, NC = no connect
Reset State indicates the state of a given pin immediately following power application, prior to any configuration from firmware.
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Pin Functions (continued)
PIN
TYPE (1)
RESET STATE (2)
26
I/O
High-Z
C_USB_N (GPIO19)
53
I/O
Input (High-Z)
USB D– connection for BC1.2 support
C_USB_P (GPIO18)
50
I/O
Input (High-Z)
USB D+ connection for BC1.2 support
DRAIN1
8, 15, 19, 58
—
—
Drain of internal power path 1. Connect thermal
pad 58 to as big of pad as possible on PCB for
best thermal performance. Short the other pins to
this thermal pad
DRAIN2
7, 52, 56, 57
—
—
Drain of internal power path 2. Connect thermal
pad 57 to as big of pad as possible on PCB for
best thermal performance. Short the other pins to
this thermal pad
20, 45 , 46, 47, 51
—
—
Unused pin. Tie to GND.
NAME
NO.
C_CC2
GND
DESCRIPTION
Output to Type-C CC or VCONN pin. Filter noise
with capacitor to GND
GPIO0
16
I/O
Input (High-Z)
General Purpose Digital I/O 0. Float pin when
unused. GPIO0 is asserted low during the
TPS65987DDJ boot process. Once device
configuration and patches are loaded GPIO0 is
released
GPIO1
17
I/O
Input (High-Z)
General Purpose Digital I/O 1. Ground pin with a
1-MΩ resistor when unused in the application
GPIO2
18
I/O
Input (High-Z)
General Purpose Digital I/O 2. Float pin when
unused
GPIO3 (HPD)
30
I/O
Input (High-Z)
General Purpose Digital I/O 3. Configured as Hot
Plug Detect (HPD) TX and RX when DisplayPort
alternate mode is enabled. Float pin when unused
GPIO4
31
I/O
Input (High-Z)
General Purpose Digital I/O 4. Float pin when
unused
I2C3_SCL (GPIO5)
21
I/O
Input (High-Z)
I2C port 3 serial clock. Open-drain output. Tie pin
to I/O voltage through a 10-kΩ resistance when
used. Float pin when unused
I2C3_SDA (GPIO6)
22
I/O
Input (High-Z)
I2C port 3 serial data. Open-drain output. Tie pin to
I/O voltage through a 10-kΩ resistance when used.
Float pin when unused
I2C3_IRQ (GPIO7)
23
I/O
Input (High-Z)
I2C port 3 interrupt detection (port 3 operates as
an I2C Master Only). Active low detection. Connect
to the I2C slave's interrupt line to detect when the
slave issues an interrupt. Float pin when unused
GPIO12
40
I/O
Input (High-Z)
General Purpose Digital I/O 12. Float pin when
unused
GPIO13
41
I/O
Input (High-Z)
General Purpose Digital I/O 13. Float pin when
unused
GPIO14 (PWM)
42
I/O
Input (High-Z)
General Purpose Digital I/O 14. May also function
as a PWM output. Float pin when unused
GPIO15 (PWM)
43
I/O
Input (High-Z)
General Purpose Digital I/O 15. May also function
as a PWM output. Float pin when unused
GPIO16 (PP_EXT1)
48
I/O
Input (High-Z)
General Purpose Digital I/O 16. May also function
as single wire enable signal for external power
path 1. Pull-down with external resistor when used
for external path control. Float pin when unused
GPIO17 (PP_EXT2)
49
I/O
Input (High-Z)
General Purpose Digital I/O 17. May also function
as single wire enable signal for external power
path 2. Pull-down with external resistor when used
for external path control. Float pin when unused
GPIO20
54
I/O
Input (High-Z)
General Purpose Digital I/O 20. Float pin when
unused
GPIO21
55
I/O
Input (High-Z)
General Purpose Digital I/O 21. Float pin when
unused
4
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Pin Functions (continued)
PIN
NAME
NO.
TYPE (1)
RESET STATE (2)
DESCRIPTION
Active high hardware reset input. Will reinitialize all
device settings. Ground pin when HRESET
functionality will not be used
HRESET
44
I/O
Input
I2C1_IRQ
29
O
High-Z
I2C port 1 interrupt. Active low. Implement
externally as an open drain with a pull-up
resistance. Float pin when unused
I2C1_SCL
27
I/O
High-Z
I2C port 1 serial clock. Open-drain output. Tie pin
to I/O voltage through a 10-kΩ resistance when
used or unused
I2C1_SDA
28
I/O
High-Z
I2C port 1 serial data. Open-drain output. Tie pin to
I/O voltage through a 10-kΩ resistance when used
or unused
I2C2_IRQ
34
O
High-Z
I2C port 2 interrupt. Active low. Implement
externally as an open drain with a pull-up
resistance. Float pin when unused
I2C2_SCL
32
I/O
High-Z
I2C port 2 serial clock. Open-drain output. Tie pin
to I/O voltage through a 10-kΩ resistance when
used or unused
I2C2_SDA
33
I/O
High-Z
I2C port 2 serial data. Open-drain output. Tie pin to
I/O voltage through a 10-kΩ resistance when used
or unused
LDO_1V8
35
PWR
—
Output of the 1.8-V LDO for internal circuitry.
Bypass with capacitor to GND
LDO_3V3
9
PWR
—
Output of the VBUS to 3.3-V LDO or connected to
VIN_3V3 by a switch. Main internal supply rail.
Used to power external flash memory. Bypass with
capacitor to GND
PP_CABLE
25
PWR
—
5-V supply input for port 1 C_CC pins. Bypass with
capacitor to GND
PP_HV1
11, 12
PWR
—
System side of first VBUS power switch. Bypass
with capacitor to ground. Tie to ground when
unused
PP_HV2
1, 2
PWR
—
System side of second VBUS power switch.
Bypass with capacitor to ground. Tie to ground
when unused
SPI_CLK
38
I/O
Input
SPI serial clock. Ground pin when unused
SPI_MISO
36
I/O
Input
SPI serial master input from slave. Ground pin
when unused
SPI_MOSI
37
I/O
Input
SPI serial master output to slave. Ground pin when
unused
SPI_SS
39
I/O
Input
SPI slave select. Ground pin when unused
VBUS1
13, 14
PWR
—
Port side of first VBUS power switch. Bypass with
capacitor to ground. Tie to VBUS2
VBUS2
3, 4
PWR
—
Port side of second VBUS power switch. Bypass
with capacitor to ground. Tie to VBUS1
5
PWR
—
Supply for core circuitry and I/O. Bypass with
capacitor to GND
—
Ground reference for the device as well as thermal
pad used to conduct heat from the device. This
connection serves two purposes. The first purpose
is to provide an electrical ground connection for
the device. The second purpose is to provide a low
thermal-impedance path from the device die to the
PCB. This pad must be connected to a ground
plane
VIN_3V3
Thermal Pad (PPAD)
59
GND
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage (2)
Output
voltage (2)
I/O voltage
(2)
MIN
MAX
PP_CABLE
–0.3
6
VIN_3V3
–0.3
3.6
LDO_1V8
–0.3
2
LDO_3V3
–0.3
3.6
I2Cx _IRQ, SPI_MOSI, SPI_CLK, SPI_SS, SWD_CLK
–0.3
(3)
PP_HVx, VBUSx (4)
–0.3
I2Cx_SDA, I2Cx_SCL, SPI_MISO, GPIOn, HRESET, ADCINx
–0.3
C_USB_P, C_USB_N
–0.5
LDO_3V3 + 0.3
UNIT
V
V
24
LDO_3V3 + 0.3
(3)
V
6
C_CC1, C_CC2
–0.5
6
Operating junction temperature, TJ
–10
125
°C
Operating junction temperature PPHV switch, TJ
–10
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to underside power pad. The underside power pad should be directly connected to the ground plane
of the board.
Not to exceed 3.6V
For VBUSx a TVS with a break down voltage falling between the Recommended max and the Abs max value is recommended such as
TVS2200
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±1500
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VIN_3V3
Input voltage, VI (1)
MAX
3.45
2.95
5.5
4.5
22
VBUS
4
22
C_USB_P, C_USB_N
0
LDO_3V3
C_CC1, C_CC2
0
5.5
GPIOn, I2Cx_SDA, I2Cx_SCL, SPI, ADCIN1, ADCIN2
0
LDO_3V3
PP_CABLE
PP_HV
I/O voltage, VIO (1)
NOM
3.135
Operating ambient temperature, TA
–10
75
Operating junction temperature, TJ
–10
125
(1)
6
UNIT
V
V
°C
All voltage values are with respect to underside power pad. Underside power pad must be directly connected to ground plane of the
board.
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6.4 Thermal Information
TPS65987
THERMAL METRIC (1)
RSH (QFN)
UNIT
48 PINS
RθJA (2)
Junction-to-ambient thermal resistance
57.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
65.4
°C/W
RθJB (2)
Junction-to-board thermal resistance
30
°C/W
ψJT (2)
Junction-to-top characterization parameter
34.1
°C/W
ψJB (2)
Junction-to-board characterization parameter
29.9
°C/W
RθJC(bot_Controller)
Junction-to-case (bottom GND pad) thermal resistance
0.7
°C/W
RθJC(bot_FET)
Junction-to-case (bottom DRAIN 1/2 pad) thermal resistance
5.6
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Thermal metrics are not JDEC standard values and are based on the TPS65988 evaluation board.
6.5 Power Supply Requirements and Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.135
3.3
3.45
V
2.95
5
5.5
V
EXTERNAL
VIN_3V3
Input 3.3-V supply
PP_CABLE
Input to power Vconn output on C_CC
pins
PP_HV
Source power from PP_HV to VBUS
4.5
5
22
V
VBUS
Sink power from VBUS to PP_HV
4
5
22
V
CVIN_3V3
Recommended capacitance on the
VIN_3V3 pin
5
10
µF
CPP_CABLE
Recommended capacitance on
PPx_CABLE pins
2.5
4.7
µF
CPP_HV_SRC
Recommended capacitance on
PP_HVx pin when configured as a
source
2.5
4.7
µF
CPP_HV_SNK
Recommended capacitance on
PP_HVx pin when configured as a
sink
1
47
120
μF
CVBUS
Recommended capacitance on
VBUSx pins
0.5
1
12
μF
INTERNAL
VLDO_3V3
Output voltage of LDO from VBUS to
LDO_3V3
VIN_3V3 = 0 V, VBUS1 ≥ 4 V, 0 ≤
ILOAD ≤ 50mA
3.15
3.3
3.45
V
VDO_LDO_3V3
Drop out voltage of LDO_3V3 from
VBUS
ILOAD = 50mA
250
500
850
mV
ILDO_3V3_EX
Allowed External Load current on
LDO_3V3 pin
25
mA
VLDO_1V8
Output voltage of LDO_1V8
VFWD_DROP
Forward voltage drop across VIN_3V3
ILOAD = 50 mA
to LDO_3V3 switch
CLDO_3V3
Recommended capacitance on
LDO_3V3 pin
5
CLDO_1V8
Recommended capacitance on
LDO_1V8 pin
0 ≤ ILOAD ≤ 20mA
1.75
1.8
1.85
V
200
mV
10
25
μF
2.2
4.7
6
μF
SUPERVISORY
UV_LDO3V3
Undervoltage threshold for LDO_3V3.
Locks out 1.8-V LDOs
LDO_3V3 rising
2.2
2.325
2.45
V
UVH_LDO3V3
Undervoltage hysteresis for LDO_3V3 LDO_3V3 falling
20
80
150
mV
UV_PCBL
Undervoltage threshold for
PP_CABLE
2.5
2.625
2.75
V
PP_CABLE rising
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Power Supply Requirements and Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
20
50
80
mV
24
V
UVH_PCBL
Undervoltage hysteresis for
PP_PCABLE
PP_CABLE falling
OV_VBUS
Overvoltage threshold for VBUS. This
value is a 6-bit programmable
threshold
VBUS rising
OVLSB_VBUS
Overvoltage threshold step for VBUS.
This value is the LSB of the
programmable threshold
VBUS rising
OVH_VBUS
Overvoltage hysteresis for VBUS
VBUS falling, % of OV_VBUS
1.4
UV_VBUS
Undervoltage threshold for VBUS.
This value is a 6-bit programmable
threshold
VBUS falling
2.5
UVLSB_VBUS
Undervoltage threshold step for
VBUS. This value is the LSB of the
programmable threshold
VBUS falling
UVH_VBUS
Undervoltage hysteresis for VBUS
VBUS rising, % of UV_VBUS
5
UNIT
328
mV
1.65
1.9
%
18.21
V
249
0.9
mV
1.3
1.7
%
6.6 Power Consumption Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Sleep (Sink)
VIN_3V3 = 3.3 V, VBUS = 0 V, No
cable connected, Tj = 25C, configured
as sink, BC1.2 disabled
45
µA
Sleep (Source/DRP)
VIN_3V3 = 3.3 V, VBUS = 0 V, No
cable connected, Tj = 25C, configured
as source or DRP, BC1.2 disabled
55
µA
IVIN_3V3 (1)
Idle (Attached)
VIN_3V3 = 3.3 V, Cable connected,
No active PD communication, Tj = 25C
5
mA
IVIN_3V3 (1)
Active
VIN_3V3 = 3.3 V, Tj = 25C
8
mA
IVIN_3V3
(1)
(1)
Does not include current draw due to GPIO loading
6.7 Power Switch Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TYP
MAX
UNIT
4.7 ≤ PP_CABLE ≤ 5.5
TEST CONDITIONS
MIN
222
325
mΩ
2.95 ≤ PP_CABLE < 4.7
269
414
mΩ
25
33
mΩ
5
A
RPPCC
PP_CABLE to C_CCn power switch
resistance
RPPHV
PP_HVx to VBUSx power switch
resistance
IPPHV
Continuous current capabillity of
power path from PP_HVx to VBUSx
Continuous current capabillity of
power path from PP_CABLE to
C_CCn
TJ = 125C
320
mA
IPPCC
TJ = 85C
600
mA
IHVACT
Active quiescent current from
PP_HV pin, EN_HV = 1
Source Configuration, Comparator
RCP function enabled, ILOAD = 100mA
1
mA
IHVSD
Shutdown quiescent current from
PP_HV pin, EN_HV = 0
VPPHV = 20V
100
µA
8
Tj = 25C
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Power Switch Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
IOCC
TEST CONDITIONS
Over Current Clamp Firmware
Selectable Settings
IOCP
PP_HV Quick Response Current
Limit
ILIMPPCC
PP_CABLE current limit
MIN
TYP
MAX
UNIT
1.140
1.267
1.393
A
1.380
1.533
1.687
A
1.620
1.800
1.980
A
1.860
2.067
2.273
A
2.100
2.333
2.567
A
2.34
2.600
2.860
A
2.580
2.867
3.153
A
2.820
3.133
3.447
A
3.060
3.400
3.74
A
3.300
3.667
4.033
A
3.540
3.933
4.327
A
3.780
4.200
4.620
A
4.020
4.467
4.913
A
4.260
4.733
5.207
A
4.500
5.00
5.500
A
4.740
5.267
5.793
A
4.980
5.533
6.087
A
5.220
5.800
6.380
A
5.460
6.067
6.673
A
5.697
6.330
6.963
A
10
A
0.6
0.75
0.9
A
3.9
6
8.1
A/V
IHV_ACC 1
PP_HV current sense accuracy
I = 100 mA, Reverse current blocking
disabled
IHV_ACC 1
PP_HV current sense accuracy
I = 200 mA
4.8
6
7.2
A/V
IHV_ACC 1
PP_HV current sense accuracy
I = 500 mA
5.28
6
6.72
A/V
IHV_ACC 1
PP_HV current sense accuracy
I≥1A
5.4
6
6.6
A/V
tON_HV
PP_HV path turn on time from
enable to VBUS = 95% of PP_HV
voltage
Configured as a source or as a sink
with soft start disabled. PP_HV = 20 V,
CVBUS = 10 µF, ILOAD = 100 mA
8
ms
tON_FRS
PP_HV path turn on time from
enable to VBUS = 95% of PP_HV
voltage during an FRS enable
Configured as a source. PP_HV = 5 V,
CVBUS = 10 µF, ILOAD = 100 mA
150
μs
tON_CC
PP_CABLE path turn on time from
enable to C_CCn = 95% of the
PP_CABLE voltage
PP_CABLE = 5 V, C_CCn = 500 nF,
ILOAD = 100 mA
2
ms
SS
Configurable soft start slew rate for
sink configuration
VREVPHV
Reverse current blocking voltage
threshold for PP_HV switch
VSAFE0V
Voltage that is a safe 0 V per USBPD specification
tSAFE0V
SRPOS
ILOAD = 100mA, setting 0
0.270
0.409
0.45
V/ms
ILOAD = 100mA, setting 1
0.6
ILOAD = 100mA, setting 2
1.2
0.787
1
V/ms
1.567
1.7
ILOAD = 100mA, setting 3
2.3
V/ms
3.388
3.6
V/ms
Diode Mode
6
10
mV
Comparator Mode
3
6
mV
0
0.8
V
Voltage transition time to VSAFE0V
650
ms
Maximum slew rate for positive
voltage transitions
0.03
V/µs
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Power Switch Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
SRNEG
Maximum slew rate for negative
voltage transitions
tSTABLE
EN to stable time for both positive
and negative voltage transitions
VSRCVALID
Supply output tolerance beyond
VSRCNEW during time tSTABLE
VSRCNEW
Supply output tolerance
tVCONNDIS
VVCONNDIS
TEST CONDITIONS
MIN
TYP
MAX
–0.03
UNIT
V/µs
275
ms
–0.5
0.5
V
–5
5
%
Time from cable detach to
VVCONNDIS
250
ms
Voltage at which VCONN is
considered discharged
150
mV
6.8 Cable Detection Characteristics
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
IH_CC_USB
Source Current through each C_CC pin when
in a disconnected state and Configured as a
Source advertising Default USB current to a
peripheral device
PARAMETER
73.6
80
86.4
µA
IH_CC_1P5
Source Current through each C_CC pin when
in a disconnected state when Configured as a
Source advertising 1.5A to a UFP
165.6
180
194.4
µA
IH_CC_3P0
Source Current through each C_CC pin when
in a disconnected state and Configured as a
Source advertising 3.0A to a UFP.
303.6
330
356.4
µA
VD_CCH_USB
Voltage Threshold for detecting a Source
attach when configured as a Sink and the
Source is advertising Default USB current
source capability
0.15
0.2
0.25
V
VD_CCH_1P5
Voltage Threshold for detecting a Source
advertising 1.5A source capability when
configured as a Sink
0.61
0.66
0.7
V
VD_CCH_3P0
Voltage Threshold for detecting a Source
advertising 3A source capability when
configured as a Sink
1.16
1.23
1.31
V
VH_CCD_USB
Voltage Threshold for detecting a Sink attach
when configured as a Source and advertising
Default USB current source capability.
IH_CC = IH_CC_USB
1.5
1.55
1.65
V
VH_CCD_1P5
Voltage Threshold for detecting a Sink attach
when configured as a Source and advertising
1.5A source capability
IH_CC = IH_CC_1P5
1.5
1.55
1.65
V
VH_CCD_3P0
Voltage Threshold for detecting a Sink attach
when configured as a Source and advertising
3.0A source capability.
IH_CC = IH_CC_3P0
VIN_3V3 ≥ 3.135V
2.45
2.55
2.615
V
VH_CCA_USB
Voltage Threshold for detecting an active cable
attach when configured as a Source and
advertising Default USB current capability.
0.15
0.2
0.25
V
VH_CCA_1P5
Voltage Threshold for detecting active cables
attach when configured as a Source and
advertising 1.5A capability.
0.35
0.4
0.45
V
VH_CCA_3P0
Voltage Threshold for detecting active cables
attach when configured as a Source and
advertising 3A capability.
0.75
0.8
0.85
V
RD_CC
Pulldown resistance through each C_CC pin
when in a disconnect state and configured as a
Sink. LDO_3V3 powered.
4.59
5.1
5.61
kΩ
10
TEST CONDITIONS
VIN_3V3 ≥ 3.135 V, VCC <
2.6 V
V = 1V, 1.5V
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Cable Detection Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
RD_CC_OPEN
Pulldown resistance through each C_CC pin
when in a disabled state. LDO_3V3 powered.
V = 0V to LDO_3V3
500
RD_DB
Pulldown resistance through each C_CC pin
when LDO_3V3 unpowered
V = 1.5V, 2.0V
4.08
RFRSWAP
Fast Role Swap signal pull down
VTH_FRS
Fast role swap request detection voltage
threshold
TYP
MAX
UNIT
kΩ
5.1
6.12
kΩ
5
Ω
490
520
550
mV
MIN
TYP
MAX
UNIT
PD data bit rate
270
300
330
Kbps
Unit interval (1/PD_BITRATE)
3.03
3.33
3.7
µs
25
pF
65
Ω
6.9 USB-PD Baseband Signal Requirements and Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
COMMON
PD_BITRATE
UI
(1)
CCBLPLUG
(2)
Capacitance for a cable plug (each
plug on a cable may have up to
this value)
ZCABLE
Cable characteristic impedance
CRECEIVER
Receiver capacitance.
Capacitance looking into C_CCn
pin when in receiver mode.
(3)
32
100
pF
TRANSMITTER
ZDRIVER
TX output impedance. Source
output impedance at the Nyquist
frequency of USB2.0 low speed
(750kHz) while the source is
driving the C_CCn line.
tRISE
Rise time. 10 % to 90 % amplitude
points, minimum is under an
unloaded condition. Maximum set
by TX mask.
300
ns
tFALL
Fall time. 90 % to 10 % amplitude
points, minimum is under an
unloaded condition. Maximum set
by TX mask.
300
ns
VTX
Transmit high voltage
1.05
1.125
1.2
V
33
75
Ω
RECEIVER
VRXTR
Rx receive rising input threshold
Port configured as Source
840
875
910
mV
VRXTR
Rx receive rising input threshold
Port configured as Sink
504
525
546
mV
VRXTF
Rx receive falling input threshold
Port configured as Sink
240
250
260
mV
VRXTF
Rx receive falling input threshold
Port configured as Source
576
600
624
mV
NCOUNT
Number of transitions for signal
detection (number to count to
detect non-idle bus).
TTRANWIN
Time window for detecting non-idle
bus.
20
µs
(1)
(2)
(3)
3
12
UI denotes the time to transmit an unencoded data bit not the shortest high or low times on the wire after encoding with BMC. A single
data bit cell has duration of 1 UI, but a data bit cell with value 1 will contain a centrally place 01 or 10 transition in addition to the
transition at the start of the cell.
The capacitance of the bulk cable is not included in the CCBLPLUG definition. It is modeled as a transmission line.
CRECEIVER includes only the internal capacitance on a C_CCn pin when the pin is configured to be receiving BMC data. External
capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications. TI recommends adding capacitance
to bring the total pin capacitance to 300 pF for improved TX behavior.
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USB-PD Baseband Signal Requirements and Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ZBMCRX
TRXFILTER
(4)
TEST CONDITIONS
Does not include pull-up or pulldown
resistance from cable detect.
Transmitter is Hi-Z.
Receiver input impedance
Rx bandwidth limiting filter. Time
constant of a single pole filter to
limit broadband noise ingression
(4)
MIN
TYP
MAX
UNIT
5
MΩ
100
ns
Broadband noise ingression is because of coupling in the cable interconnect.
6.10 BC1.2 Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DATA CONTACT
DETECT
IDP_SRC
DCD source current
7
10
13
µA
RDM_DWN
DCD pulldown resistance
LDO_3V3 = 3.3 V
14.25
20
24.8
kΩ
RDP_DWN
DCD pulldown resistance
14.25
20
24.8
kΩ
VLGC_HI
Threshold for no connection
C_USB_P ≥ VLGC_HI, LDO_3V3 =
3.3 V
VLGC_LO
Threshold for connection
C_USB_P ≤ VLGC_LO
2
V
0.8
V
0.65
V
400
µA
125
µA
200
Ω
PRIMARY AND SECONDARY
DETECT
VDX_SRC
Source voltage
0.55
VDX_ILIM
VDX_SRC current limit
IDX_SNK
Sink Current
RDCP_DAT
Dedicated Charging Port Resistance
0.6
250
VC_USB_TN/BN ≥ 250 mV
25
75
DIVIDER MODE
VCx_USB_P
_2.7V
Cx_USB_P Output Voltage
No load on Cx_USB_P
2.57
2.7
2.79
V
VCx_USB_N
_2.7V
Cx_USB_N Output Voltage
No load on Cx_USB_N
2.57
2.7
2.79
V
RCx_USB_P
_30k
Cx_USB_P Output Impedance
5µA pulled from Cx_USB_P pin
24
30
36
kΩ
RCx_USB_N
_30k
Cx_USB_N Output Impedance
5µA pulled from Cx_USB_N pin
24
30
36
kΩ
RCx_USB_N
_102k
Cx_USB_N Output Impedance
5µA pulled from Cx_USB_N pin
80
102
130
kΩ
VCx_USB_P
_1.2V
Cx_USB_P Output Voltage
No load on Cx_USB_P
1.12
1.2
1.28
V
VCx_USB_N
_1.2V
Cx_USB_N Output Voltage
No load on Cx_USB_N
1.12
1.2
1.28
V
RCx_USB_P
_102k
Cx_USB_P Output Impedance
5µA pulled from Cx_USB_P pin
80
102
130
kΩ
MIN
TYP
MAX
UNIT
145
160
175
°C
1.2V MODE
6.11 Thermal Shutdown Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TSD_MAIN
Thermal Shutdown Temperature of the
Temperature rising
main thermal shutdown
TSDH_MAIN
Thermal Shutdown hysteresis of the
main thermal shutdown
12
Temperature falling
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°C
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Thermal Shutdown Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TSD_PWR
Thermal Shutdown Temperature of the
Temperature rising
power path block
TSDH_PWR
Thermal Shutdown hysteresis of the
power path block
MIN
TYP
MAX
UNIT
145
160
175
°C
Temperature falling
20
°C
6.12 Oscillator Characteristics
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
ƒOSC_24M
24-MHz oscillator
PARAMETER
TEST CONDITIONS
22.8
24
25.2
MHz
ƒOSC_100K
100-kHz oscillator
95
100
105
kHz
MIN
TYP
MAX
UNIT
6.13 I/O Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SPI
SPI_VIH
High-level input voltage
LDO_1V8 = 1.8V
SPI_VIL
Low input voltage
LDO_1V8 = 1.8V
1.3
V
SPI_HYS
Input hysteresis voltage
LDO_1V8 = 1.8V
SPI_ILKG
Leakage current
Output is Hi-Z, VIN = 0 to LDO_3V3
SPI_VOH
SPI output high voltage
IO = –2 mA, LDO_3V3 = 3.3 V
SPI_VOL
SPI output low voltage
IO = 2 mA
GPIO_VIH
High-level input voltage
LDO_1V8 = 1.8 V
GPIO_VIL
Low input voltage
LDO_1V8 = 1.8 V
GPIO_HYS
Input hysteresis voltage
LDO_1V8 = 1.8 V
GPIO_ILKG
I/O leakage current
INPUT = 0 V to VDD
–1
GPIO_RPU
Pullup resistance
Pullup enabled
50
GPIO_RPD
Pulldown resistance
Pulldown enabled
50
GPIO_DG
Digital input path deglitch
GPIO_VOH
GPIO output high voltage
IO = –2 mA, LDO_3V3 = 3.3 V
GPIO_VOL
GPIO output low voltage
IO = 2 mA, LDO_3V3 = 3.3 V
0.4
V
OD_VOL
Low-level output voltage
IOL = 2 mA
0.4
V
OD_LKG
Leakage current
Output is Hi-Z, VIN = 0 to LDO_3V3
1
µA
0.63
0.09
V
V
-1
1
2.88
µA
V
0.4
V
SWDIO
SWDCLK
GPIO
1.3
V
0.63
V
1
µA
100
150
kΩ
100
150
kΩ
0.09
V
20
ns
2.88
V
I2C_IRQx
–1
6.14 I2C Requirements and Characteristics
over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SDA AND SCL COMMON
CHARACTERISTICS
ILEAK
Input leakage current
Voltage on Pin = LDO_3V3
VOL
SDA output low voltage
IOL = 3 mA, LDO_3V3 = 3.3 V
IOL
SDA max output low current
–3
3
0.4
µA
V
VOL = 0.4 V
3
mA
VOL = 0.6 V
6
mA
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I2C Requirements and Characteristics (continued)
over operating free-air temperature range (unless otherwise noted).
PARAMETER
VIL
TEST CONDITIONS
Input low signal
VIH
MAX
UNIT
LDO_3V3 = 3.3 V
0.99
V
LDO_1V8 = 1.8 V
0.54
V
LDO_3V3 = 3.3 V
Input high signal
MIN
TYP
2.31
V
LDO_1V8 = 1.8 V
1.3
V
LDO_3V3 = 3.3 V
0.17
V
LDO_1V8 = 1.8 V
0.09
VHYS
Input hysteresis
tSP
I2C pulse width suppressed
50
ns
CI
Pin capacitance
10
pF
100
kHz
V
SDA AND SCL STANDARD
MODE CHARACTERISTICS
ƒSCL
I2C clock frequency
0
tHIGH
I2C clock high time
4
µs
tLOW
I2C clock low time
4.7
µs
250
ns
2
tSU;DAT
I C serial data setup time
tHD;DAT
I2C serial data hold time
tVD;DAT
I2C valid data time
SCL low to SDA output valid
3.45
µs
tVD;ACK
I2C valid data time of ACK condition
ACK signal from SCL low to SDA (out)
low
3.45
µs
10 pF to 400 pF bus
250
ns
0
2
tOCF
I C output fall time
tBUF
I2C bus free time between stop and
start
ns
4.7
µs
2
tSU;STA
I C start or repeated Start condition
setup time
4.7
µs
tHD;STA
I2C Start or repeated Start condition
hold time
4
µs
4
µs
2
tSU;STO
I C Stop condition setup time
SDA AND SCL FAST MODE
CHARACTERISTICS
I2C clock frequency
ƒSCL
Configured as Slave
2
Configured as Master
0
320
kHz
400
kHz
ƒSCL_MASTER
I C clock frequency
tHIGH
I2C clock high time
0.6
µs
tLOW
I2C clock low time
1.3
µs
tSU;DAT
I2C serial data setup time
100
ns
2
0
400
tHD;DAT
I C serial data hold time
tVD;DAT
I2C Valid data time
SCL low to SDA output valid
0
0.9
µs
ns
tVD;ACK
I2C Valid data time of ACK condition
ACK signal from SCL low to SDA (out)
low
0.9
µs
tOCF
I2C output fall time
10 pF to 400 pF bus, VDD = 3.3 V
12
250
ns
10 pF to 400 pF bus, VDD = 1.8 V
6.5
250
ns
2
tBUF
I C bus free time between stop and
start
1.3
µs
2
tSU;STA
I C start or repeated Start condition
setup time
0.6
µs
tHD;STA
I2C Start or repeated Start condition
hold time
0.6
µs
0.6
µs
tSU;STO
14
2
I C Stop condition setup time
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6.15 SPI Master Timing Requirements
MIN
NOM
MAX
UNIT
11.4
12
12.6
MHz
79.36
83.33
87.72
ns
ƒSPI
Frequency of SPI_CLK
tPER
Period of SPI_CLK (1/F_SPI)
tWHI
SPI_CLK high width
30
tWLO
SPI_CLK low width
30
tDACT
SPI_SZZ falling to SPI_CLK rising delay time
30
50
ns
tDINACT
SPI_CLK falling to SPI_SSZ rising delay time
158
180
ns
tDMOSI
SPI_CLK falling to SPI_MOSI Valid delay time
–10
10
ns
tSUMISO
SPI_MISO valid to SPI_CLK falling setup time
33
ns
tHDMSIO
SPI_CLK falling to SPI_MISO invalid hold time
0
ns
tRIN
SPI_MISO input rise time
tRSPI
SPI_SSZ/CLK/MOSI rise time
10% to 90%, CL = 5 to 50 pF, LDO_3V3 =
3.3 V
tFSPI
SPI_SSZ/CLK/MOSI fall time
90% to 10%, CL = 5 to 50 pF, LDO_3V3 =
3.3 V
ns
ns
5
ns
1
25
ns
1
25
ns
6.16 HPD Timing Requirements
MIN
NOM
MAX
UNIT
DP SOURCE SIDE (HPD
TX)
tIRQ_MIN
HPD IRQ minimum assert time
t2MS_MIN
HPD assert 2-ms min time
675
750
825
µs
3
3.33
3.67
ms
HPD_HDB_SEL = 0
300
375
450
µs
HPD_HDB_SEL = 1
100
111
122
ms
DP SINK SIDE (HPD
RX)
tHPD_HDB
HPD high debounce time
tHPD_LDB
HPD low debounce time
300
375
450
µs
tHPD_IRQ
HPD IRQ limit time
1.35
1.5
1.65
ms
6.17 Typical Characteristics
32
100
70
50
30
30
10
7
5
28
Id (A)
Resistance (m:)
20
3
2
26
1
0.7
0.5
24
100ms
10ms
1ms
100us
10us
0.3
0.2
22
-20
0
20
40
60
80
Temperature (°C)
100
120
140
0.1
0.5 0.7
D004
Figure 1. PPHVx Rdson vs Junction Temperature
1
2
3
4 5 6 7 8 10
Vds (V)
20
30 40 50
Figure 2. PPHVx SOA Curve
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7 Parameter Measurement Information
tf
SDA
tr
tSU;DAT
70 %
30 %
70 %
30 %
cont.
tHD;DAT
tf
tVD;DAT
tHIGH
tr
70 %
30 %
SCL
70 %
30 %
70 %
30 %
tHD;STA
70 %
30 %
cont.
tLOW
9th clock
1 / fSCL
S
1st clock cycle
tBUF
SDA
tSU;STA
tHD;STA
tVD;ACK
tSP
tSU;STO
70 %
30 %
SCL
Sr
P
9th clock
S
002aac938
Figure 3. I2C Slave Interface Timing
tper
SPI_SSZ
twhigh
twlow
tdact
tdinact
SPI_CLK
tdmosi
SPI_MOSI
tdmosi
Valid Data
tsumiso
SPI_MISO
Valid Data
thdmiso
Figure 4. SPI Master Timing
16
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8 Detailed Description
8.1 Overview
The TPS65987DDJ is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug
and orientation detection for a USB Type-C and PD plug or receptacles. The TPS65987DDJ communicates with
the cable and another USB Type-C and PD device at the opposite end of the cable, enables integrated port
power switch, controls an external high current port power switch and negotiates alternate modes. The
TPS65987DDJ may also control an attached super-speed multiplexer via GPIO or I2C to simultaneously support
USB3.0/3.1 data rates and DisplayPort video.
The TPS65987DDJ is divided into five main sections:
• USB-PD controller
• cable plug and orientation detection circuitry
• port power switches
• power management circuitry
• digital core
The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD data
is output through either the C_CC1 pin or the C_CC2 pin, depending on the orientation of the reversible USB
Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features and
more detailed circuitry, see the USB-PD Physical Layer section.
The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug insertion
and also automatically detects the cable orientation. For a high-level block diagram of cable plug and orientation
detection, a description of its features and more detailed circuitry, see Figure 14.
The port power switches provide power to the system port through the VBUS pin and also through the C_CC1 or
C_CC2 pins based on the detected plug orientation. For a high-level block diagram of the port power switches, a
description of its features and more detailed circuitry, see the Port Power Switches section.
The power management circuitry receives and provides power to the TPS65987DDJ internal circuitry and to the
LDO_3V3 output. For a high-level block diagram of the power management circuitry, a description of its features
and more detailed circuitry, see the Power Management section.
The digital core provides the engine for receiving, processing and sending all USB-PD packets as well as
handling control of all other TPS65987DDJ functionality. A portion of the digital core contains ROM memory
which contains all the necessary firmware required to execute Type-C and PD applications. In addition, a section
of the ROM called boot code, is capable of initializing the TPS65987DDJ, loading of device configuration
information and loading any code patches into volatile memory in the digital core. For a high-level block diagram
of the digital core, a description of its features and more detailed circuitry, see the Digital Core section.
The TPS65987DDJ is an I2C slave to be controlled by a host processor (see the I2C Interfaces section), and an
SPI master to write to and read from an optional external flash memory (see the SPI Master Interface section).
The TPS65987DDJ also integrates a thermal shutdown mechanism (see theThermal Shutdown section) and runs
off of accurate clocks provided by the integrated oscillators (see the Oscillators section).
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8.2 Functional Block Diagram
VBUS1
PP_HV1
5A
VBUS2
PP_HV2
PP_CABLE
5A
600mA
LDO_3V3
LDO_1V8
VIN_3V3
HRESET
ADCIN1
ADCIN2
GPIO0-4
GPIO12-17
GPIO20-21
I2C1_SDA/SCL/IRQ
I2C2_SDA/SCL/IRQ
I2C3_SDA/SCL/IRQ
SPI_MOSI/MISO/SS/CLK
Power & Supervisor
5
6
2
3
3
3
4
Core
&
Other Digital
Cable Detect &
USB-PD Phy
Cable Power
Charger
Detection &
Advertisement
C_CC1
C_CC2
2
C_USB_P/N
PPAD
8.3 Feature Description
8.3.1 USB-PD Physical Layer
Figure 5 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and
orientation detection block.
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Feature Description (continued)
Fast
current
limit
600 mA
PP_CABLE
C_CC1 Gate Control
and Current Limit
LDO_3V3
C_CC1
Digital
Core
USB-PD
Decode
C_CC2
LDO_3V3
C_CC1 Gate Control
and Current Limit
Fast
current
limit
Figure 5. USB-PD Physical Layer, Simplified Plug and Orientation Detection Circuitry
USB-PD messages are transmitted in a USB Type-C system using a BMC signaling. The BMC signal is output
on the same pin (C_CC1 or C_CC2) that is DC biased due to the DFP (or UFP) cable attach mechanism shown
in Figure 14.
8.3.1.1 USB-PD Encoding and Signaling
Figure 6 illustrates the high-level block diagram of the baseband USB-PD transmitter. Figure 7 illustrates the
high-level block diagram of the baseband USB-PD receiver.
4b5b
Encoder
Data
BMC
Encoder
to PD_TX
CRC
Figure 6. USB-PD Baseband Transmitter Block Diagram
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Feature Description (continued)
BMC
Decoder
from PD_RX
SOP
Detect
Data
4b5b
Decoder
CRC
Figure 7. USB-PD Baseband Receiver Block Diagram
The USB-PD baseband signal is driven on the C_CCn pins with a tri-state driver. The tri-state driver is slew rate
limited to reduce the high frequency components imparted on the cable and to avoid interference with
frequencies used for communication.
8.3.1.2 USB-PD Bi-Phase Marked Coding
The USBP-PD physical layer implemented in the TPS65987DDJ is compliant to the USB-PD Specifications. The
encoding scheme used for the baseband PD signal is a version of Manchester coding called Biphase Mark
Coding (BMC). In this code, there is a transition at the start of every bit time and there is a second transition in
the middle of the bit cell when a 1 is transmitted. This coding scheme is nearly DC balanced with limited disparity
(limited to 1/2 bit over an arbitrary packet, so a very low DC level). Figure 8 illustrates Biphase Mark Coding.
0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
0
1
1
Data in
BMC
Figure 8. Biphase Mark Coding Example
The USB PD baseband signal is driven onto the C_CC1 or C_CC2 pins with a tri-state driver. The tri-state driver
is slew rate to limit coupling to D+/D– and to other signal lines in the Type-C fully featured cables. When sending
the USB-PD preamble, the transmitter starts by transmitting a low level. The receiver at the other end tolerates
the loss of the first edge. The transmitter terminates the final bit by an edge to ensure the receiver clocks the
final bit of EOP.
8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
The USB-PD driver meets the defined USB-PD BMC TX masks. Since a BMC coded “1” contains a signal edge
at the beginning and middle of the UI, and the BMC coded “0” contains only an edge at the beginning, the masks
are different for each. The USB-PD receiver meets the defined USB-PD BMC Rx masks. The boundaries of the
Rx outer mask are specified to accommodate a change in signal amplitude due to the ground offset through the
cable. The Rx masks are therefore larger than the boundaries of the TX outer mask. Similarly, the boundaries of
the Rx inner mask are smaller than the boundaries of the TX inner mask. Triangular time masks are
superimposed on the TX outer masks and defined at the signal transitions to require a minimum edge rate that
has minimal impact on adjacent higher speed lanes. The TX inner mask enforces the maximum limits on the rise
and fall times. Refer to the USB-PD Specifications for more details.
8.3.1.4 USB-PD BMC Transmitter
The TPS65987DDJ transmits and receives USB-PD data over one of the C_CCn pins for a given CC pin pair
(one pair per USB Type-C port). The C_CCn pins are also used to determine the cable orientation (see
Figure 14) and maintain the cable/device attach detection. Thus, a DC bias exists on the C_CCn pins. The
transmitter driver overdrives the C_CCn DC bias while transmitting, but returns to a Hi-Z state allowing the DC
voltage to return to the C_CCn pin when not transmitting. Figure 9 shows the USB-PD BMC TX and RX driver
block diagram.
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Feature Description (continued)
LDO_3V3
PD_TX
Level
Shifter
Driver
C_CC1
PD_RX
Level
Shifter
C_CC2
Digitally
Adjustable
VREF
USB-PD Modem
Figure 9. USB-PD BMC TX/Rx Block Diagram
Figure 10 shows the transmission of the BMC data on top of the DC bias. Note, The DC bias can be anywhere
between the minimum threshold for detecting a UFP attach (VD_CCH_USB) and the maximum threshold for
detecting a UFP attach to a DFP (VD_CCH_3P0). This means that the DC bias can be below VOH of the
transmitter driver or above VOH.
VOH
DC Bias
DC Bias
VOL
DC Bias
VOH
DC Bias
VOL
Figure 10. TX Driver Transmission with DC Bias
The transmitter drives a digital signal onto the C_CCn lines. The signal peak, VTXP, is set to meet the TX masks
defined in the USB-PD Specifications.
When driving the line, the transmitter driver has an output impedance of ZDRIVER. ZDRIVER is determined by
the driver resistance and the shunt capacitance of the source and is frequency dependent. ZDRIVER impacts the
noise ingression in the cable.
Figure 11 shows the simplified circuit determining ZDRIVER. It is specified such that noise at the receiver is
bounded.
RDRIVER
ZDRIVER
Driver
CDRIVER
Figure 11. ZDRIVER Circuit
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Feature Description (continued)
8.3.1.5 USB-PD BMC Receiver
The receiver block of the TPS65987DDJ receives a signal that falls within the allowed Rx masks defined in the
USB PD specification. The receive thresholds and hysteresis come from this mask.
Figure 12 shows an example of a multi-drop USB-PD connection. This connection has the typical UFP (device)
to DFP (host) connection, but also includes cable USB-PD TX/Rx blocks. Only one system can be transmitting at
a time. All other systems are Hi-Z (ZBMCRX). The USB-PD Specification also specifies the capacitance that can
exist on the wire as well as a typical DC bias setting circuit for attach detection.
DFP
System
Tx
UFP
System
Pullup
for Attach
Detection
Cable
Connector
Connector
Tx
CRECEIVER
CRECEIVER
CCBLPLUG
CCBLPLUG
RD
for Attach
Detection
Rx
Rx
Tx
Rx
Tx
Rx
Figure 12. Example USB-PD Multi-Drop Configuration
8.3.2 Power Management
The TPS65987DDJ power management block receives power and generates voltages to provide power to the
TPS65987DDJ internal circuitry. These generated power rails are LDO_3V3 and LDO_1V8. LDO_3V3 may also
be used as a low power output for external flash memory. The power supply path is shown in Figure 13.
VIN_3V3
VBUS1
VREF
LDO_3V3
LDO
VREF
LDO_1V8
LDO
Figure 13. Power Supplies
The TPS65987DDJ is powered from either VIN_3V3, VBUS1, or VBUS2. The normal power supply input is
VIN3V3. In this mode, current flows from VIN_3V3 to LDO3V3 to power the core 3.3-V circuitry and I/Os. A
second LDO steps the voltage down from LDO_3V3 to LDO_1V8 to power the 1.8-V core digital circuitry. When
VIn_3V3 power is unavailable and power is available on VBUS1 or VBUS2 , the TPS65987DDJ is powered from
VBUS. In this mode, the voltage on VBUS1 or VBUS 2 is stepped down through an LDO to LDO_3V3.
8.3.2.1 Power-On And Supervisory Functions
A power-on reset (POR) circuit monitors each supply. This POR allows active circuitry to turn on only when a
good supply is present.
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Feature Description (continued)
8.3.2.2 VBUS LDO
The TPS65987DDJ contains an internal high-voltage LDO which is capable of converting up to 22 V from VBUS
to 3.3 V for powering internal device circuitry. The VBUS LDO is only used during dead battery operation while
the VIN_3V3 supply is not present. The VBUS LDO may be powered from either VBUS1 or VBUS2. The path
connecting each VBUS to the internal LDO blocks reverse current, preventing power on one VBUS from leaking
to the other. When power is present on both VBUS inputs, the internal LDO draws current from both VBUS pins.
8.3.2.3 Supply Switch Over
VIN_3V3 takes precedence over VBUS, meaning that when both supply voltages are present the TPS65987DDJ
powers from VIN_3V3. See Figure 13 for a diagram showing the power supply path block. There are two cases
in which a power supply switch-over occurs. The first is when VBUS is present first and then VIN_3V3 becomes
available. In this case, the supply automatically switches over to VIN_3V3 and brown-out prevention is verified by
design. The other way a supply switch-over occurs is when both supplies are present and VIN_3V3 is removed
and falls below 2.85 V. In this case, a hard reset of the TPS65987DDJ is initiated by device firmware, prompting
a re-boot.
8.3.3 Port Power Switches
The figure below shows the TPS65987DDJ internal power paths. The TPS65987DDJ features two internal highvoltage power paths. Each path contains two back to back common drain N-Fets, current monitor, overvoltage
monitor, undervoltage monitor, and temperature sensing circuitry. Each path may conduct up to 5 A safely.
Additional external paths may be controlled through the TPS65987DDJ GPIOs.
5A
Fast
current
limit
PP_HV2
VBUS2
Fast
current
limit
5A
PP_HV1
VBUS1
HV Gate Control and
Sense
HV Gate Control and
Sense
Dead
Battery
Supply
PP_EXT1 (GPIO16)
PP_EXT2(GPIO17)
Fast
current
limit
C_CC1 Gate
Control
PP_CABLE
C_CC1
600mA
C_CC2 Gate
Control
C_CC2
Figure 14. Port Power Switches
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Feature Description (continued)
8.3.3.1 PP_HV Power Switch
The TPS65987DDJ has two integrated bi-directional high-voltage switches that are rated for up to 5 A of current.
Each switch may be used as either a sink or source path for supporting USB-PD power up to 20 V at 5 A of
current.
NOTE
The power paths can sustain up to 5 A of continuous current as long as the internal
junction temperature of each path remains below 150°C. Care should be taken to follow
the layout recommendations described in Thermal Dissipation for FET Drain Pads
NOTE
It is recommended to use PPHV1 as a sink path and PPHV2 as a source path.
8.3.3.1.1 PP_HV Overcurrent Clamp
The internal source PP_HV path has an integrated overcurrent clamp circuit. The current through the internal
PP_HV paths are current limited to IOCC. The IOCC value is selected by application firmware and only enabled
while acting as a source. When the current through the switch exceeds IOCC, the current clamping circuit
activates and the path behaves as a constant current source. If the duration of the overcurrent event exceeds the
deglitch time, the switch is latched off.
8.3.3.1.2 PP_HV Overcurrent Protection
The TPS65987DDJ continuously monitors the forward voltage drop across the internal power switches. When a
forward drop corresponding to a forward current of IOCP is detected the internal power switch is latched off to
protect the internal switches as well as upstream power supplies.
8.3.3.1.3 PP_HV OVP and UVP
Both the overvoltage and undervoltage protection levels are configured by application firmware. When the
voltage on a port's VBUS pin exceeds the set overvoltage threshold or falls below the set undervoltage threshold
the associated PP_HV path is automatically disabled.
8.3.3.1.4 PP_HV Reverse Current Protection
The TPS65987DDJ reverse current protection has two modes of operation: Comparator Mode and Ideal Diode
Mode. Both modes disable the power switch in cases of reverse current. The comparator protection mode is
enabled when the switch is operating as a source, while the ideal diode protection is enabled while operating as
a sink.
In the Comparator mode of reverse current protection, the power switch is allowed to behave resistively until the
current reaches the amount calculated in Equation 1 and then blocks reverse current from VBUS to PP_HV.
Figure 15 shows the diode behavior of the switch with comparator mode enabled.
IREVHV = VREVHV/RPPHV
(1)
I
1/RPPHV
VREVHV
V
IREVHV
Figure 15. Comparator Mode (Source) Internal HV Switch I-V Curve
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Feature Description (continued)
In the Ideal Diode mode of reverse current protection, the switch behaves as an ideal diode and blocks reverse
current from PP_HV to VBUS. Figure 16 shows the diode behavior of the switch with ideal diode mode enabled.
I
1/RPPHV
VREVHV/RPPHV
VBUS-PP_HV
VREVHV
Figure 16. Ideal Diode Mode (Sink) Internal HV Switch I-V Curve
8.3.3.2 Schottky for Current Surge Protection
To prevent the possibility of large ground currents into the TPS65987DDJ during sudden disconnects due to
inductive effects in a cable, it is recommended that a Schottky diode be placed from VBUS to ground as shown
in Figure 17.
PP_HV2
VBUS2
PP_HV1
VBUS1
PPAD
Figure 17. Schottky for Current Surge Protection
8.3.3.3 PP_EXT Power Path Control
GPIO16 and GPIO17 of the TPS65987DDJ are intended for control of additional external power paths. These
GPIO are active high when configured for external path control and disables in response to an OVP or UVP
event. Overcurrent protection and thermal shutdown are not available for external power paths controlled by
GPIO16 and GPIO17.
NOTE
GPIO16 and GPIO17 must be pulled to ground through an external pull-down resistor
when used as external path control signals.
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Feature Description (continued)
8.3.3.4 PP_CABLE Power Switch
The TPS65987DDJ has an integrated 5-V unidirectional power mux that is rated for up to 600 mA of current. The
mux may supply power to either of the port CC pins for use as VCONN power.
8.3.3.4.1 PP_CABLE Overcurrent Protection
When enabled and providing VCONN power the TPS65987DDJ PP_CABLE power switches have a 600-mA
current limit. When the current through the PP_CABLE switch exceeds 600 mA, the current limiting circuit
activates and the switch behaves as a constant current source. The switches do not have reverse current
blocking when the switch is enabled and current is flowing to either C_CC1 or C_CC2.
8.3.3.4.2 PP_CABLE Input Good Monitor
The TPS65987DDJ monitors the voltage at the PP_CABLE pins prior to enabling the power switch. If the voltage
at PP_CABLE exceeds the input good threshold the switch is allowed to close, otherwise the switch remains
open. Once the switch has been enabled, PP_CABLE is allowed to fall below the input good threshold.
8.3.3.5 VBUS transition to VSAFE5V
The TPS65987DDJ has an integrated active pull-down on VBUS for transitioning from high voltage to VSAFE5V.
When the high voltage switch is disabled and VBUS > VSAFE5V, an amplifier turns on a current source and
pulls down on VBUS. The amplifier implements active slew rate control by adjusting the pull-down current to
prevent the slew rate from exceeding specification. When VBUS falls to VSAFE5V, the pull-down is turned off.
8.3.3.6 VBUS Transition to VSAFE0V
When VBUS transitions to near 0 V (VSAFE0V), the pull-down circuit in is turned on until VBUS reaches
VSAFE0V. This transition occurs within time TSAFE0V.
8.3.4 Cable Plug and Orientation Detection
Figure 18 shows the plug and orientation detection block at each C_CCn pin (C_CC1, C_CC2). Each pin has
identical detection circuitry.
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Feature Description (continued)
LDO_3V3
IH_CC_STD
IH_CC_1P5
IH_CC_3P0
VREF1
C_CCn
VREF2
VREF3
RD_CC
Figure 18. Plug and Orientation Detection Block
8.3.4.1 Configured as a DFP
When one of the TPS65987DDJ ports is configured as a DFP, the device detects when a cable or a UFP is
attached using the C_CC1 and C_CC2 pins. When in a disconnected state, the TPS65987DDJ monitors the
voltages on these pins to determine what, if anything, is connected. See USB Type-C Specification for more
information.
Table 1 shows the Cable Detect States for a DFP.
Table 1. Cable Detect States for a DFP
C_CC1
C_CC2
Open
Open
Nothing attached
CONNECTION STATE
Continue monitoring both C_CC pins for attach. Power is not applied to VBUS or
VCONN until a UFP connect is detected.
RESULTING ACTION
Rd
Open
UFP attached
Monitor C_CC1 for detach. Power is applied to VBUS but not to VCONN (C_CC2).
Open
Rd
UFP attached
Monitor C_CC2 for detach. Power is applied to VBUS but not to VCONN (C_CC1).
Ra
Open
Powered Cable-No UFP
attached
Monitor C_CC2 for a UFP attach and C_CC1 for cable detach. Power is not applied
to VBUS or VCONN (C_CC1) until a UFP attach is detected.
Open
Ra
Powered Cable-No UFP
attached
Monitor C_CC1 for a UFP attach and C_CC2 for cable detach. Power is not applied
to VBUS or VCONN (C_CC1) until a UFP attach is detected.
Ra
Rd
Powered Cable-UFP Attached
Provide power on VBUS and VCONN (C_CC1) then monitor C_CC2 for a UFP
detach. C_CC1 is not monitored for a detach.
Rd
Ra
Powered Cable-UFP attached
Provide power on VBUS and VCONN (C_CC2) then monitor C_CC1 for a UFP
detach. C_CC2 is not monitored for a detach.
Rd
Rd
Debug Accessory Mode
attached
Sense either C_CC pin for detach.
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Feature Description (continued)
Table 1. Cable Detect States for a DFP (continued)
C_CC1
C_CC2
Ra
Ra
CONNECTION STATE
Audio Adapter Accessory
Mode attached
RESULTING ACTION
Sense either C_CC pin for detach.
When a TPS65987DDJ port is configured as a DFP, a current IH_CC is driven out each C_CCn pin and each pin
is monitored for different states. When a UFP is attached to the pin a pull-down resistance of Rd to GND exists.
The current IH_CC is then forced across the resistance Rd generating a voltage at the C_CCn pin.
When configured as a DFP advertising Default USB current sourcing capability, the TPS65987DDJ applies
IH_CC_USB to each C_CCn pin. When a UFP with a pull-down resistance Rd is attached, the voltage on the
C_CCn pin pulls below VH_CCD_USB. The TPS65987DDJ can be configured to advertise default (500 mA or
900 mA), 1.5-A and 3-A sourcing capabilities when acting as a DFP.
When the C_CCn pin is connected to an active cable VCONN input, the pull-down resistance is different (Ra). In
this case the voltage on the C_CCn pin will pull below VH_CCA_USB/1P5/3P0 and the system recognizes the
active cable.
The VH_CCD_USB/1P5/3P0 thresholds are monitored to detect a disconnection from each of these cases
respectively. When a connection has been recognized and the voltage on the C_CCn pin rises above the
VH_CCD_USB/1P5/3P0 threshold, the system registers a disconnection.
8.3.4.2 Configured as a UFP
When a TPS65987DDJ port is configured as a UFP, the TPS65987DDJ presents a pull-down resistance RD_CC
on each C_CCn pin and waits for a DFP to attach and pull-up the voltage on the pin. The DFP pulls-up the
C_CCn pin by applying either a resistance or a current. The UFP detects an attachment by the presence of
VBUS. The UFP determines the advertised current from the DFP by the pull-up applied to the C_CCn pin.
8.3.4.3 Configured as a DRP
When a TPS65987DDJ port is configured as a DRP, the TPS65987DDJ alternates the port's C_CCn pins
between the pull-down resistance, Rd, and pull-up current source, Rp.
8.3.4.4 Fast Role Swap Signaling
The TPS65987DDJ cable plug block contains additional circuitry that may be used to support the Fast Role
Swap (FRS) behavior defined in the USB Power Delivery Specification. The circuitry provided for this
functionality is detailed in Figure 19.
C_CC1
To Cable
Detect and
Orientation
C_CC2
R_FRSWAP
To Digital Core
R_FRSWAP
VREF
Figure 19. Fast Role Swap Detection and Signaling
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When a TPS65987DDJ port is operating as a sink with FRS enabled, the TPS65987DDJ monitors the CC pin
voltage. If the CC voltage falls below VTH_FRS a fast role swap situation is detected and signaled to the digital
core. When this signal is detected the TPS65987DDJ ceases operating as a sink and begin operating as a
source.
When a TPS65987DDJ port is operating as a source with FRS enabled, the TPS65987DDJ digital core can
signal to the connected port partner that a fast role swap is required by enabling the R_FRSWAP pull down on
the connected CC pin. When this signal is sent the TPS65987DDJ ceases operating as the source and begin
operating as a sink.
8.3.5 Dead Battery Operation
8.3.5.1 Dead Battery Advertisement
The TPS65987DDJ supports booting from no-battery or dead-battery conditions by receiving power from VBUS.
Type-C USB ports require a sink to present Rd on the CC pin before a USB Type-C source provides a voltage
on VBUS. The TPS65987DDJ hardware is configured to present this Rd during a dead-battery or no-battery
condition. Additional circuitry provides a mechanism to turn off this Rd once the device no longer requires power
from VBUS. Figure 20 shows the configuration of the C_CCn pins, and elaborates on the basic cable plug and
orientation detection block shown in Figure 18. A resistance R_RPD is connected to the gate of the pull-down
FET on each C_CCn pin. During normal operation when configured as a sink, RD is RD_CC; however, while
dead-battery or no-battery conditions exist, the resistance is un-trimmed and is RD_DB. When RD_DB is
presented during dead-battery or no-battery, application code switches to RD_CC.
C_CCn
R_RPD
RD_DB
RD_DB_EN
RD_CC
RD_CC_EN
Figure 20. Dead Battery Pull-Down Resistor
In this case, the gate driver for the pull-down FET is Hi-Z at its output. When an external connection pulls up on
C_CCn (the case when connected to a DFP advertising with a pull-up resistance Rp or pull-up current), the
connection through R_RPD pulls up on the FET gate turning on the pull-down through RD_DB. In this condition,
the C_CCn pin acts as a clamp VTH_DB in series with the resistance RD_DB.
8.3.5.2 BUSPOWER (ADCIN1)
The BUSPOWER input to the internal ADC controls the behavior of the TPS65987DDJ in response to VBUS
being supplied during a dead battery condition. The pin must be externally tied to the LDO_3V3 output via a
resistive divider. At power-up the ADC converts the BUSPOWER voltage and the digital core uses this value to
determine start-up behavior. It is recommended to tie ADCin1 to LDO_3V3 through a resistor divider as shown in
Figure 21. For more information about how to use the ADCIN1 pin to configure the TPS65987DDJ, see the Boot
section.
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LDO_3V3
R1
ADC
ADCIN1
R2
Figure 21. ADCIN1 Resistor Divider
NOTE
Devices implementing the BP_WaitFor3V3_External configuration must use GPIO16 for
external sink path control.
8.3.6 Battery Charger Detection and Advertisement
The battery charger (BC1.2) block integrates circuitry to detect when the connected entity on the USB D+/D–
pins is a BC1.2 compliant charger, as well as advertise BC1.2 charging capabilities to connected devices. To
enable the required detection and advertisement mechanisms, the block integrates various voltage sources,
currents, and resistances. shows the connection of these elements to the TPS65987DDJ C_USB_P and
C_USB_N pins.
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VLGC_HI
IDP_SRC
RDCP_DAT
C_USB_P
To ADC
C_USB_N
R_DIV
R_DIV
VDX_SRC
R_1.2V
RDM_DWN
V_DIV
IDX_SNK
RDP_DWN
V_1.2V
Figure 22. Battery Charger Detection and Advertisement
NOTE
The pull-up and pull-down resistors required by the USB2 standard for a USB host or
device are not provided by the TPS65987DDJ and must be provided externally to the
device in final applications.
8.3.6.1 BC1.2 Data Contact Detect
The Data Contact Detect follows the definition in the USB BC1.2 specification. The detection scheme sources a
current IDP_SRC into the D+ pin of the USB connection. The current is sourced into the C_USB_P D+ pin. A
resistance RDM_DWN is connected between the D- pin and GND. The current source IDP_SRC and the pulldown resistance RDM_DWN, is activated during data contact detection.
8.3.6.2 BC1.2 Primary and Secondary Detection
The Primary and Secondary Detection follow the USB BC1.2 specification. This detection scheme looks for a
resistance between D+ and D– lines by forcing a known voltage on the first line, forcing a current sink on the
second line and then reading the voltage on the second line using the ADC integrated in the TPS65987DDJ. The
voltage source VDX_SRC and the current source IDX_SNK, are activated during primary and secondary
detection.
8.3.6.3 Charging Downstream Port Advertisement
The Charging Downstream Port (CDP) advertisement follows the USB BC1.2 specification. The advertisement
scheme monitors the D+ line using the ADC. When a voltage of 0.6 V is seen on the D+ line, TPS65987DDJ
forces a voltage of 0.6 V on the D- line until the D+ goes low. The voltage source VDX_SRC and the current
source IDX_SNK, are activated during CDP advertisement. CDP advertisement takes place with the USB Host
15-kΩ pull-down resistors on the D+ and D- lines from the USB Host Transceiver, because after CDP negotiation
takes place on the D+/D- lines, USB2.0 data transmission begins.
8.3.6.4 Dedicated Charging Port Advertisement
The Dedicated Charging Port (DCP) advertisement follows the USB BC1.2 specification (Shorted Mode per
BC1.2) and the YD/T 1591-2009 specification. The advertisement scheme shorts the D+ and D– lines through
the RDCP_DAT resistor.
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8.3.6.5 2.7-V Divider3 Mode Advertisement
The 2.7-V Divider3 Mode is a proprietary advertisement scheme used to charge popular devices in the market.
This advertisement places V_DIV on D+ with an R_DIV output impedance and V_DIV on D- with an R_DIV
output impedance. With this advertisement scheme present on D+ and D-, specific popular devices are allowed
to pull more than 1.5 A of current from VBUS. If enabling 2.7-V Divider3 Mode advertisement on a port, it is
recommended that VBUS be able to supply at least 2.4 A of current.
8.3.6.6 1.2-V Mode Advertisement
The 1.2-V Mode is a proprietary advertisement scheme used to charge popular devices in the market. This
advertisement places V_1.2 V on D- with an R_1.2 V output impedance and shorts D+ and D- together through
the RDCP_DAT resistor. With this advertisement scheme present on D+ and D-, specific popular devices are
allowed to pull more than 1.5 A of current from VBUS. If enabling 1.2-V Mode advertisement on a port, it is
recommended that VBUS be able to supply at least 2 A of current.
8.3.6.7 DCP Auto Mode Advertisement
The DCP Auto Mode Advertisement scheme is a special scheme that automatically advertises the correct
charging scheme depending on the device attached to the USB port. If a device that detects Dedicated Charging
Port Advertisement is connected, the DCP Advertising scheme will automatically be placed on D+/D-. If a device
that detects 2.7-V Divider3 Mode Advertisement is connected, the 2.7-V Divider3 Mode Advertising scheme will
automatically be placed on D+/D-. Likewise, if a device that detects 1.2-V Mode Advertisement is connected, the
1.2-V Mode Advertising scheme will automatically be placed on D+/D-. The TPS65987DDJ DCP Auto Mode
Advertisement circuit is able to place the correct advertisement scheme on D+/D- without needing to discharge
VBUS.
8.3.7 ADC
The TPS65987DDJ integrated ADC is accessible to internal firmware only. The ADC reads are not available for
external use.
8.3.8 DisplayPort HPD
To enable HPD signaling through PD messaging, a single pin is used as the HPD input and output for each port.
When events occur on these pins during a DisplayPort connection though the Type-C connector (configured by
firmware), hardware timers trigger and interrupt the digital core to indicate needed PD messaging. When one of
the TPS65987DDJ's ports is operating as a DP source, its corresponding HPD pin operates as an output (HPD
TX), and when a port is operating as a DP sink, its corresponding HPD pin operates as an input (HPD RX).
When DisplayPort is not enabled via firmware the HPD pin operates as a generic GPIO (GPIO3).
8.3.9 Digital Interfaces
The TPS65987DDJ contains several different digital interfaces which may be used for communicating with other
devices. The available interfaces include three I2C ports (I2C1 is a Master/Slave, I2C2 is a Slave, and I2C3 is a
Master), one SPI master, and 12 additional GPIOs.
8.3.9.1 General GPIO
Figure 23 shows the GPIO I/O buffer for all GPIOn pins. GPIOn pins can be mapped to USB Type-C, USB PD,
and application-specific events to control other ICs, interrupt a host processor, or receive input from another IC.
This buffer is configurable to be a push-pull output, a weak push-pull, or open drain output. When configured as
an input, the signal can be a de-glitched digital input. The push-pull output is a simple CMOS output with
independent pull-down control allowing open-drain connections. The weak push-pull is also a CMOS output, but
with GPIO_RPU resistance in series with the drain. The supply voltage to the output buffer is LDO_3V3 and
LDO_1V8 to the input buffer. When interfacing with non 3.3-V I/O devices the output buffer may be configured as
an open drain output and an external pull-up resistor attached to the GPIO pin. The pull-up and pull-down output
drivers are independently controlled from the input and are enabled or disabled via application code in the digital
core.
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LDO_3V3
GPIO_OD_EN
GPIO_OE
GPIO_DO
GPIO_PU_EN
GPIO_RPU
GPIO_RPD
GPIO_PD_EN
20ns
Deglitch
GPIO
GPIO_DI
GPIO_AI_EN
Figure 23. General GPIO Buffer
8.3.9.2 I2C
The TPS65987DDJ features three I2C interfaces. The I2C1 interface is configurable to operate as a master or
slave. The I2C2 interface may only operate as a slave. The I2C3 interface may only operate as a master. The I2C
I/O driver is shown in Figure 24. This I/O consists of an open-drain output and in input comparator with deglitching. The I2C input thresholds are set by LDO_1V8 and by default.
50ns
Deglitch
I2C_DI
I2C_SDA/SCL
I2C_DO
Figure 24. I2C Buffer
8.3.9.3 SPI
The TPS65987DDJ has a single SPI master interface for use with external memory devices. Figure 25 shows the
I/O buffers for the SPI interface.
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SPI_x
SPIin
CMOS
Output
SPIout
SPI_OE
Figure 25. SPI buffer
8.3.10 Digital Core
The figure below shows a simplified block diagram of the digital core.
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HRESET
GPIO 0-4
GPIO 12-17
GPIO 20-21
I2C1_SDA
I2C to
System Control
I2C
Port 1
I2C1_SCL
I2C1_IRQZ
I2C2_SDA
I2C to
Thunderbolt Controller
I2C
Port 2
I2C2_SCL
I2C2_IRQZ
Digital Core
CBL_DET
Bias CTL
and USB-PD
I2C3_SDA
I2C to
I2C Peripherals
USB PD Phy
I2C
Port 3
I2C3_SCL
I2C3_IRQZ
SPI_CLK
SPI to
Flash
(firmware)
SPI_MOSI
SPI
SPI_MISO
SPI_SSZ
OSC
Thermal
Shutdown
Temp
Sense
Figure 26. Digital Core Block Diagram
8.3.11 I2C Interfaces
The TPS65987DDJ has three I2C interface ports. I2C Port 1 is comprised of the I2C1_SDA, I2C1_SCL, and
I2C1_IRQ1 pins. I2C Port 2 is comprised of the I2C2_SDA, I2C2_SCL, and I2C2_IRQ pins. These interfaces
provide general status information about the TPS65987DDJ, as well as the ability to control the TPS65987DDJ
behavior, as well as providing information about connections detected at the USB-C receptacle and supporting
communications to/from a connected device and/or cable supporting BMC USB-PD. I2C Port 3 is comprised of
the I2C3_SDA, I2C3_SCL, and I2C3_IRQ1 pins. This interface is used as a general I2C master to control
external I2C devices such as a super-speed mux or re-timer.
The first port can be a master or a slave, but the default behavior is to be a slave. The second port operates as a
slave only. Port 1 and Port 2 are interchangeable as slaves. Both Port1 and Port2 operate in the same way and
has the same access in and out of the core. An interrupt mask is set for each that determines what events are
interrupted on that given port. Port 3 operates as a master only.
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8.3.11.1 I2C Interface Description
The TPS65987DDJ support Standard and Fast mode I2C interface. The bidirectional I2C bus consists of the
serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pull-up
resistor. Data transfer may be initiated only when the bus is not busy.
A master sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high
initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit (MSB)
first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input
and output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred during
each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period as
changes in the data line at this time are interpreted as control commands (Start or Stop). The master sends a
Stop condition, a low-to-high transition on the SDA input and output while the SCL input is high.
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a
slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must
generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to
ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. The master receiver holding the SDA line high does this. In this
event, the transmitter must release the data line to enable the master to generate a Stop condition.
Figure 27 shows the start and stop conditions of the transfer. Figure 28 shows the SDA and SCL signals for
transferring a bit. Figure 29 shows a data transfer sequence with the ACK or NACK at the last clock pulse.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 27. I2C Definition of Start and Stop Conditions
SDA
SCL
Data Line
Change
2
Figure 28. I C Bit Transfer
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Data Output
by Transmitter
Nack
Data Output
by Receiver
SCL From
Master
Ack
1
2
8
9
S
Clock Pulse for
Acknowledgement
Start
Condition
Figure 29. I2C Acknowledgment
8.3.11.2 I2C Clock Stretching
The TPS65987DDJ features clock stretching for the I2C protocol. The TPS65987DDJ slave I2C port may hold the
clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data.
The master communicating with the slave must not finish the transmission of the current bit and must wait until
the clock line actually goes high. When the slave is clock stretching, the clock line remains low.
The master must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs for
standard 100 kbps I2C) before pulling the clock low again.
Any clock pulse may be stretched but typically it is the interval before or after the acknowledgment bit.
8.3.11.3 I2C Address Setting
The boot flow sets the hardware configurable unique I2C address of the TPS65987DDJ before the port is
enabled to respond to I2C transactions. For the I2C1 interface, the unique I2C address is determined by the
analog level set by the analog ADCIN2 pin (three bits) as shown in Table 2.
Table 2. I2C Default Unique Address I2C1
Default I2C Unique Address
Bit 7
Bit 6
Bit 5
Bit 4
0
1
0
0
Bit 3
Bit 2
Bit 1
I2C_ADDR_DECODE[2:0]
Bit 0
R/W
2
Note 1: Any bit is maskable for each port independently providing firmware override of the I C address.
For the I2C2 interface, the unique I2C address is a fixed value as shown in Table 3.
Table 3. I2C Default Unique Address I2C2
Default I2C Unique Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
1
1
0
0
0
R/W
Note 1: Any bit is maskable for each port independently, providing firmware override of the I2C address.
NOTE
The TPS65987DDJ I2C address values are set and controlled by device firmware. Certain
firmware configurations may override the presented address settings.
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8.3.11.4 Unique Address Interface
The Unique Address Interface allows for complex interaction between an I2C master and a single TPS65987DDJ.
The I2C Slave sub-address is used to receive or respond to Host Interface protocol commands. Figure 30 and
Figure 31 show the write and read protocol for the I2C slave interface, and a key is included in Figure 32 to
explain the terminology used. The key to the protocol diagrams is in the SMBus Specification and is repeated
here in part.
1
7
1
1
8
1
8
1
8
1
S
Unique Address
Wr
A
Register Number
A
Byte Count = N
A
Data Byte 1
A
8
1
8
1
Data Byte 2
A
Data Byte N
A
P
Figure 30. I2C Unique Address Write Register Protocol
1
7
1
1
8
1
1
7
1
1
8
1
S
Unique Address
Wr
A
Register Number
A
Sr
Unique Address
Rd
A
Byte Count = N
A
8
1
8
1
8
1
Data Byte 1
A
Data Byte 2
A
Data Byte N
A
P
1
2
Figure 31. I C Unique Address Read Register Protocol
1
7
1
1
8
1
1
S
Slave Address
Wr
A
Data Byte
A
P
x
x
S
Start Condition
SR
Repeated Start Condition
Rd
Read (bit value of 1)
Wr
Write (bit value of 0)
x
Field is required to have the value x
A
Acknowledge (this bit position may be 0 for an ACK or
1 for a NACK)
P
Stop Condition
Master-to-Slave
Slave-to-Master
Continuation of protocol
Figure 32. I2C Read/Write Protocol Key
8.3.11.5 I2C Pin Address Setting (ADCIN2)
To enable the setting of multiple I2C addresses using a single TPS65987DDJ pin, a resistor divider is placed
externally on the ADCIN2 pin. The internal ADC then decodes the address from this divider value. Figure 33
shows the decoding.
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LDO_3V3
R1
ADC
ADCIN2
R2
Figure 33. I2C Address Divider
Table 4 lists the external divider needed to set bits [3:1] of the I2C Unique Address.
Table 4. I2C Address Selection
DIV = R2/(R1+R2) (1)
DIV_min
I2C UNIQUE ADDRESS [3:1]
DIV_max
Short ADCIN2 to GND
000b
0.20
0.38
001b
0.40
0.58
010b
Short ADCIN2 to LDO_3V3
(1)
I2C_ADDR_DECODE
011b
External resistor tolerance of 1% is required. Resistor values must be chosen to yield a DIV value centered nominally between listed
MIN and MAX values.
8.3.12 SPI Master Interface
The TPS65987DDJ loads any ROM patch and-or configuration from flash memory during the boot sequence.
The TPS65987DDJ is designed to power the flash from LDO_3V3 in order to support dead-battery or no-battery
conditions, and therefore pull-up resistors used for the flash memory must be tied to LDO_3V3. The flash
memory IC must support 12 MHz SPI clock frequency. The size of the flash must be at least 64 kB. The SPI
master of the TPS65987DDJ supports SPI Mode 0. For Mode 0, data delay is defined s0 that data is output on
the same cycle as chip select (SPI_SS pin) becomes active. The chip select polarity is active-low. The clock
phase is defined such that data (on the SPI_MISO and SPI_MOSI pins) is shifted out on the falling edge of the
clock (SPI_CLK pin) and data is sampled on the rising edge of the clock. The clock polarity for chip select is
defined such that when data is not being transferred the SPI_CLK pin is held (or idling) low. The minimum
erasable sector size of the flash must be 4 KB. The W25X05CL or similar is recommended.
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8.3.13 Thermal Shutdown
The TPS65987DDJ features a central thermal shutdown as well as independent thermal sensors for each
internal power path. The central thermal shutdown monitors the overall temperature of the die and disables all
functions except for supervisory circuitry when die temperature goes above a rising temperature of TSD_MAIN.
The temperature shutdown has a hysteresis of TSDH_MAIN and when the temperature falls back below this
value, the device resumes normal operation.
The power path thermal shutdown monitors the temperature of each internal power path and disables the power
path in response to an overtemperature event. Once the temperature falls below TSDH_PWR the path can be
configured to resume operation or remain disabled until re-enabled by firmware.
8.3.14 Oscillators
The TPS65987DDJ has two independent oscillators for generating internal clock domains. A 24-MHz oscillator
generates clocks for the core during normal operation. A 100-kHz oscillator generates clocks for various timers
and clocking the core during low power states.
8.4 Device Functional Modes
8.4.1 Boot
At initial power on the device goes through a boot routine. This routine is responsible for initializing device
register values and loading device patch and configuration bundles. The device's functional behavior after boot
can be configured through the use of pin straps on the SPI_MISO and ADCIN1 pins as shown in Table 5.
Table 5. Boot Mode Pin Strapping
SPI_MISO
ADCIN1
DIV = R2/(R1+R2) (1)
Dead Battery Mode
Device Configuration
0.18
BP_NoResponse
Safe Configuration
0.20
0.28
BP_WaitFor3V3_Internal
Safe Configuration
0.30
0.38
BP_ECWait_Internal
Infinite Wait
1
0.40
0.48
BP_WaitFor3V3_External
Safe Configuration
1
0.50
0.58
BP_ECWait_External
Infinite Wait
1
0.60
1.00
BP_NoWait
Safe Configuration
0
0.10
0.18
BP_NoResponse
Configuration 1
0
0.20
0.28
BP_NoResponse
Configuration 2
0
0.30
0.38
BP_ECWait_Internal
Infinite Wait
0
0.40
0.48
BP_NoWait
Configuration 3
0
0.50
0.58
BP_ECWait_External
Infinite Wait
0
0.60
0.68
BP_NoResponse
Configuration 4
0
0.70
0.78
BP_NoWait
Reserved
0
0.80
0.88
BP_NoResponse
Reserved
0
0.90
1.00
BP_NoWait
Configuration 5
DIV MIN
DIV MAX
1
0.00
1
1
(1)
External resistor tolerance of 1% is required. Resistor values must be chosen to yield a DIV value centered nominally between listed
MIN and MAX values.
The pin strapping configures two different parameters, Dead battery mode and device configuration. The dead
battery mode selects device behavior when powered from VBUS. The dead battery mode behaviors are detailed
in Table 6.
Table 6. Dead Battery Configurations
40
CONFIGURATION
DESCRIPTION
BP_NoResponse
No power switch is enabled and the device does not start-up until VIN_3V3 is
present
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Table 6. Dead Battery Configurations (continued)
CONFIGURATION
DESCRIPTION
BP_WaitFor3V3_Internal
The internal power switch from VBUSx to PP_HVx is enabled for the port receiving
power. The device does not continue to start-up or attempt to load device
configurations until VIN_3V3 is present.
BP_WaitFor3V3_External
The external power switch from VBUSx to PP_HVx is enabled for the port
receiving power. The device does not continue to start-up or attempt to load device
configurations until VIN_3V3 is present.
BP_ECWait_Internal
The internal power switch from VBUSx to PP_HVx is enabled for the port receiving
power. The device infinitely tries to load configuration.
BP_ECWait_External
The external power switch from VBUSx to PP_HVx is enabled for the port
receiving power. The device infinitely tries to load configuration.
BP_NoWait
The device continues to start-up and attempts to load configurations while
receiving power from VBUS. Once configuration is loaded the appropriate power
switch is closed based on the loaded configuration.
NOTE
Devices implementing the BP_WaitFor3V3_External or BP_ECWait_External configuration
must use GPIO16 for external sink path control, while devices implementing the
BP_WaitFor3V3_Internal or BP_ECWait_Internal must use PPHV1 as the sink path.
When powering up from VIN_3V3 or VBUS the device will attempt to load configuration information from the SPI
or I2C digital interfaces. The device configuration settings select the device behavior should configuration
information not be available during the device boot process. Table 7 shows the device behavior for each device
configuration setting.
Table 7. Device Default Configurations
Configuration
Description
Safe
Ports disabled, if powered from VBUS operates a legacy sink
Infinite Wait
Device infinitely waits in boot state for configuration information
Configuration 1
DFP only (Internal Switch)
5 V at 3-A Source capability
USB Type-C Only (No PD)
Configuration 2
DFP only (Internal Switch)
45-W Source (5/9/15/20-V Output)
TBT Alternate Modes not enabled
DisplayPort Alternate Modes not enabled
Configuration 3
UFP only (Internal Switch)
5-20 V at 0.9 - 3.0-A Sink capability
TBT Alternate Modes not enabled
DisplayPort Alternate Modes not enabled
Configuration 4
DFP only (Internal Switch)
60-W Source (5/9/15/20-V Output)
TBT Alternate Modes not enabled
DisplayPort Alternate Modes not enabled
Configuration 5
UFP only (External Switch))
5-20 V at 0.9-3.0-A Sink capability
5 V at 3.0-A Source capability
TBT Alternate Modes not enabled
DisplayPort Alternate Modes not enabled
8.4.2 Power States
The TPS65987DDJ may operate in one of three different power states: Active, Idle, or Sleep. The functionality
available in each state is summarized in Table 8.
Table 8. Power States
ACTIVE
IDLE
SLEEP
Type-C State
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Table 8. Power States (continued)
ACTIVE
IDLE
SLEEP
Type-C State
Connected or Unconnected
Connected or Unconnected
Unconnected
Type-C Port 2 State
Connected or Unconnected
Connected or Unconnected
Unconnected
LDO_3V3 (1)
Valid
Valid
Valid
LDO_1V8
Valid
Valid
Valid
Digital Core Clock Frequency
12 MHz
4 MHz - 6 MHz
100 kHz
100-kHz Oscillator Status
Enabled
Enabled
Enabled
24-MHz Oscillator Status
Enabled
Enabled
Disabled
Oscillator Status
Available Features
Type-C Detection
Yes
Yes
Yes
PD Communication
Yes
No
No
I2C Communication
Yes
Yes
No
SPI Communication
Yes
No
No
Yes
Wake Events
(1)
(2)
42
Wake on Attach/Detach
N/A
Yes
Wake on PD Communication
N/A
Yes (2)
No
Wake on I2C Communication
N/A
Yes
Yes
LDO_3V3 may be generated from either VIN_3V3 or VBUS. If LDO_3V3 is generated from VBUS, TPS65987DDJ port only operate as
sinks.
Wake up from Idle to Active upon a PD message is supported however the first PD message received is lost.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS65987DDJ firmware implements a host interface over I2C to allow for the configuration and control of all
device options. Initial device configuration is configured through a configuration bundle loaded onto the device
during boot. The bundle may be loaded via I2C or SPI. The TPS65987DDJ configuration bundle and host
interface allow the device to be customized for each specific application. The configuration bundle can be
generated through the Application Customization Tool.
9.2 Typical Application
Figure 34. Example Schematic
9.2.1 Type-C VBUS Design Considerations
USB Type-C and PD allows for voltages up to 20 V with currents up to 5 A. This introduces power levels that
could damage components touching or hanging off of VBUS. Under normal conditions, all high power PD
contracts should start at 5 V and then transition to a higher voltage. However, there some devices that are not
compliant to the USB Type-C and Power Delivery standards and could have 20 V on VBUS. This could cause a
20-V hot plug that can ring above 30 V. Adequate design considerations are recommended below for these noncompliant devices.
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Typical Application (continued)
9.2.1.1 Design Requirements
Table 9 shows VBUS conditions that can be introduced to a USB Type-C and PD Sink. The system should be
able to handle these conditions to ensure that the system is protected from non-compliant and/or damaged USB
PD sources. A USB Sink should be able to protect from the following conditions being applied to its VBUS. The
Detailed Design Procedure section explains how to protect from these conditions.
Table 9. VBUS Conditions
CONDITION
VOLTAGE APPLIED
Abnormal VBUS Hot Plug
4 V - 21.5 V
VBUS Transient Spikes
4 V - 43 V
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Type-C Connector VBUS Capacitors
C_VBUS
VBUS A4
VBUS B9
C_VBUS
10 nF
35V
10 nF
35V
GND
C_VBUS
Type-C
Connector
VBUS A9
VBUS B4
GND
C_VBUS
10 nF
35V
10 nF
35V
GND
GND
Figure 35. Type-C Connector VBUS Capacitors
The first level of protection starts at the Type-C connector and the VBUS pin capacitors. These capacitors help
filter out high frequency noise but can also help absorb short voltage transients. Each VBUS pin should have a
10-nF capacitor rated at or above 25 V and placed as close to the pin as possible. The GND pin on the
capacitors should have very short path to GND on the connector. The derating factor of ceramic capacitors
should be taken into account as they can lose more than 50% of their effective capacitance when biased. Adding
the VBUS capacitors can help reduce voltage spikes by 2 V to 3 V.
9.2.1.2.2 VBUS Schottky and TVS Diodes
Schottky diodes are used on VBUS to help absorb large GND currents when a Type-C cable is removed while
drawing high current. The inductance in the cable will continue to draw current on VBUS until the energy stored
is dissipated. Higher currents could cause the body diodes on IC devices connected to VBUS to conduct. When
the current is high enough it could damage the body diodes of IC devices. Ideally a VBUS Schottky diode should
have a lower forward voltage so it can turn on before any other body diodes on other IC devices. Schottky diodes
on VBUS also help during hard shorts to GND which can occur with a faulty Type-C cable or damaged Type-C
PD device. VBUS could ring below GND which could damage devices hanging off of VBUS. The Schottky diode
will start to conduct once VBUS goes below the forward voltage. When the TPS65987DDJ is the only device
connected to VBUS place the Schottky Diode close to the VBUS pin of the TPS65987DDJ. The two figures
below show a short condition with and without a Schottky diode on VBUS. In Figure 37 without the Schottky
diode, VBUS rings 2 V below GND and oscillates after settling to 0 V. In Figure 38 with the Schottky diode,
VBUS drops 750 mV below GND (Schottky diode Vf) and the oscillations are minimized.
44
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TVS Diodes help suppress and clamp transient voltages. Most TVS diodes can fully clamp around 10 ns and can
keep the VBUS at their clamping voltage for a period of time. Looking at the clamping voltage of TVS diodes
after they settle during a transient will help decide which TVS diode to use. The peak power rating of a TVS
diode must be able to handle the worst case conditions in the system. A TVS diode can also act as a “pseudo
schottky diode” as they will also start to conduct when VBUS goes below GND.
9.2.1.2.3 VBUS Snubber Circuit
VBUS
4.7 …F
1 …F
3.48Ÿ
GND
Figure 36. VBUS Snubber
Another method of clamping the USB Type-C VBUS is to use a VBUS RC Snubber. An RC Snubber is a great
solution because in general it is much smaller than a TVS diode, and typically more cost effective as well. An RC
Snubber works by modifying the characteristic of the total RLC response in the USB Type-C cable hot-plug from
being under-damped to critically-damped or over-damped. So rather than clamping the overvoltage directly, it
actually changes the hot-plug response from under-damped to critically-damped, so the voltage on VBUS does
not ring at all; so the voltage is limited, but without requiring a clamping element like a TVS diode.
However, the USB Type-C and Power Delivery specifications limit the range of capacitance that can be used on
VBUS for the RC snubber. VBUS capacitance must have a minimum 1 µF and a maximum of 10 µF. The RC
snubber values chosen support up to 4 m USB Type-C cable (maximum length allowed in the USB Type-C
specification) being hot plugged, is to use 4.7-μF capacitor in series with a 3.48-Ω resistor. In parallel with the RC
Snubber a 1μF capacitor is used, which always ensures the minimum USB Type-C VBUS capacitance
specification is met. This circuit can be seen in the figure above.
9.2.1.3 Application Curves
Figure 37. VBUS Short without Schottky Diode
Figure 38. VBUS Short with Schottky Diode
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9.2.2 Notebook Design Supporting PD Charging
The TPS65987DDJ works very well in single port Notebooks that support PD charging. The two internal power
paths for the TPS65987DDJ source System 5 V on VBUS through the PPHV2 path and sink VBUS up to 20 V on
PPHV1. The TPS65987DDJ integrated reverse current protection allows the designer to connect PPHV1 to
another power source such as a standard barrel jack or proprietary dock connector power to charge the
notebook battery. The System 5-V supplies power to PP_CABLE on the TPS65987DDJ to supply VCONN to
Type-C e-marked cables and Type-C accessories. An embedded controller EC is used for additional control of
the TPS65987DDJ and to relay information back to the operating system. An embedded controller enables
features such as entering and exiting sleep modes, changing source and sink capabilities depending on the state
of the battery, UCSI support, control alternate modes, etc.
9.2.2.1 USB and DisplayPort Notebook Supporting PD Charging
For systems that support USB and DisplayPort Data, the USB and DisplayPort sources are muxed to the Type-C
connector through the TUSB1046 Super Speed mux. The TPS65987DDJ is capable of controlling the Super
Speed Mux over I2C and will configure it according to the connection at the Type-C connector. The
TPS65987DDJ can also set the configurations for the Super Speed mux equalizer settings for the USB Super
Speed and DisplayPort Lanes through an initializing set of I2C writes. Note that I2C1 is the I2C master controlling
the SS Mux and I2C2 is connected to the embedded controller. I2C1 can operate as an I2C master/slave and
I2C2 can only operate as an I2C slave. Alternatively the Super Speed mux can be controlled through GPIO
instead of I2C. The TPD6S300 provides Type-C protection features such as short to VBUS on the CC and SBU
pins and ESD protection for the USB2 DN/P. See the figure below for the system block diagram.
USB SSTX/RX
USB3.1 Source
SSTX/RX
SBU1/2
TUSB1046
I2C/GPIO
Type C
Receptacle
DP ML
SS Mux Control*
DP1.4 Source
USB2.0 Source
SSTX/RX
SBU1/2
USB2.0
TPD6S300
CC1/2
GPIO
BC1.2
SS Mux Control*
C_CC1/2
VBUS
VIN
PPHV1
BAT
BQ Battery
Charger
TPS65987D
VIN_3V3
+
System 3.3V
I2C
PPHV2
System 5V
PP_CABLE
I2C1 Master
I2C2
SS Mux Control*
EC
I2C MASTER
Copyright © 2017, Texas Instruments Incorporated
Figure 39. USB and DisplayPort Notebook Supporting PD Charging
9.2.2.1.1 Design Requirements
The table below summarizes the Power Design parameters for an USB Type-C PD Notebook.
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Table 10. Power Design Parameters
POWER DESIGN PARAMETERS
VALUE
CURRENT PATH
PPHV2 Input Voltage, Current
5 V, 1.5 A
VBUS Source
PP_CABLE1/2 Input Voltage, Current
5 V, 500 mA
VCONN Source
PPHV1 Voltage, Current
5 V – 20 V, 3 A (5 A Max)
VBUS Sink
VIN_3V3 Voltage, Current
3.3 V, 50 mA
Internal TPS65987DDJ Circuitry
9.2.2.1.2 Detailed Design Procedure
9.2.2.1.2.1 USB Power Delivery Source Capabilities
Most Type-C dongles (video and data) draw less than 900 mA and supplying 1.5 A on each Type-C port is
sufficient for a notebook supporting USB and DisplayPort. Table 11 shows the PDO for the Type-C port.
Table 11. Source PDOs
SOURCE PDO
PDO TYPE
VOLTAGE
CURRENT
PDO1
Fixed
5V
1.5 A
9.2.2.1.2.2 USB Power Delivery Sink Capabilities
Most notebooks support buck and boost charging which allows them to charge the battery from 5 V to 20 V. USB
PD sources must also follow the Source Power Rules defined by the USB Power Delivery specification. It is
recommended for notebooks to support all the voltages in the Source Power Rules to ensure compatibility with
most PD chargers and adapters.
Table 12. Sink PDOs
SINK PDO
PDO TYPE
VOLTAGE
CURRENT
PDO1
Fixed
5V
3A
PDO2
Fixed
9V
3A
PDO3
Fixed
15 V
3A
PDO4
Fixed
20 V
3 A (5 A Max)
9.2.2.1.2.3 f
The table below summarizes the data capabilities of the notebook supporting USB3 and DisplayPort.
Table 13. Data Capabilities
PROTOCOL
DATA
DATA ROLE
USB Data
USB3.1 Gen2
Host
DisplayPort
DP1.4
Host DFP_D (Pin Assignment C, D, and E)
9.2.2.1.2.4 TUSB1046 Super Speed Mux GPIO Control
The TUSB1046 requires GPIO control in GPIO control mode to determine whether if there is USB or DisplayPort
data connection. summarizes the TPS65987DDJ GPIO Events and the control pins for the TUSB1046. Note that
the pin strapping on the TUSB1046 will set the GPIO control mode and the required equalizer settings. For more
details refer to the TUSB1046 data sheet.
Table 14. GPIO Events for Super Speed Mux
TPS65987DDJ GPIO EVENT
TUSB1046 CONTROL
Port 0 Cable Orientation Event
FLIP
Port 0 USB3 Event
CTL0
Port 0 DP Mode Selection Event
CTL1
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9.2.2.2 Thunderbolt Notebook Supporting PD Charging
A Thunderbolt system is capable of source USB, DisplayPort, and Thunderbolt data. There is an I2C connection
between the TPS65987DDJ and the Thunderbolt controller. The TPS65987DDJ will determine the connection on
the Type-C and will generate an interrupt to the Thunderbolt controller to generate the appropriate data output.
An external mux for SBU may be needed to mux the LSTX/RX and AUX_P/N signal from the Thunderbolt
controller to the Type-C Connector. The TPD6S300 provides additional protection such as short to VBUS on the
CC and SBU pins and ESD for the USB2 DN/P. See Figure 40 for a block diagram of the system.
PB_TX0/1/RX0/1
SBU Mux Control
SBU1/2
LSTX/RX
PA_LSTX/RX
AUXP/N
PA_DPSRC_AUX_P/N
TS3DS10224
Type C
Receptacle
U1_TBT_I2C_SDA
USB2.0 Source
SSTX/RX
Thunderbolt
Controller I2C Master
U2_TBT_I2C_SCL
J4_TBTA_I2C_IRQZ
SBU1/2
USB2.0
TPD6S300
GPIO
BC1.2
SBU Mux Control
TBT RESETN
CC1/2
GPIO_0
C1_CC1/2
VBUS
RESETN
TBT RESETN
VIN
PPHV1
BAT
TPS65987D
BQ Battery
Charger
System 3.3V
VIN_3V3
PP_CABLE
System 5V
+
Thunderbolt Controller
I2C
PPHV2
Thunderbolt
Controller I2C Master
I2C2
EC
I2C1
I2C MASTER
Copyright © 2017, Texas Instruments Incorporated
Figure 40. Thunderbolt Notebook Supporting PD Charging
9.2.2.2.1 Design Requirements
Table 15 summarizes the Power Design parameters for an USB Type-C PD Thunderbolt Notebook.
Table 15. Power Design Parameters
POWER DESIGN PARAMETERS
VALUE
CURRENT PATH
PPHV2 Input Voltage, Current
5 V, 3 A
VBUS Source
PP_CABLE1/2 Input Voltage, Current
5 V, 500 mA
VCONN Source
PPHV1 Voltage, Current
5 V – 20 V, 3 A (5 A Max)
VBUS Sink
VIN_3V3 Voltage, Current
3.3 V, 50 mA
Internal TPS65987DDJ Circuitry
9.2.2.2.2 Detailed Design Procedure
9.2.2.2.2.1 USB Power Delivery Source Capabilities
All Thunderbolt systems must support sourcing 5 V at 3 A (15 W). See the Table 16 for the PDO information.
Table 16. Source PDOs
48
SOURCE PDO
PDO TYPE
VOLTAGE
CURRENT
PDO1
Fixed
5V
3A
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9.2.2.2.2.2 USB Power Delivery Sink Capabilities
Most notebooks support buck/boost charging which allows them to charge the battery from 5 V to 20 V. USB PD
sources must also follow the Source Power Rules defined by the USB Power Delivery specification. It is
recommended for notebooks to support all the voltages in the Source Power Rules to ensure compatibility with
most PD chargers and adapters.
Table 17. Sink PDOs
SINK PDO
PDO TYPE
VOLTAGE
CURRENT
PDO1
Fixed
5V
3A
PDO2
Fixed
9V
3A
PDO3
Fixed
15 V
3A
PDO4
Fixed
20 V
3 A (5 A Max)
9.2.2.2.2.3 Thunderbolt Supported Data Modes
Thunderbolt Controllers are capable of generating USB3, DisplayPort and Thunderbolt Data. The Thunderbolt
controller is also capable of muxing the appropriate super speed signal to the Type-C connector. Thunderbolt
systems do not need a super speed mux for the Type-C connector. Table 18 summarizes the data capabilities of
each Type-C port supporting Thunderbolt.
Table 18. Data Capabilities
PROTOCOL
DATA
USB Data
USB3.1 Gen2
DATA ROLE
Host
DisplayPort
DP1.4
Host DFP_D (Pin Assignment C, D, and E)
Thunderbolt
PCIe/DP
Host/Device
9.2.2.2.2.4 RESETN
The TPS65987DDJ and the Thunderbolt controller share the same flash and they must be able to access it at
different times. The TPS65987DDJ will access the flash first to load its configuration and then the Thunderbolt
controller will read the flash for its firmware. The TPS65987DDJ will hold the Thunderbolt controller in reset until
it has read its configuration from the flash. GPIO_0 is reserved to act as the reset signal for the Thunderbolt
controller. The RESET_N (Thunderbolt Controller Master Reset) signal must also be gated by the 3.3-V supply to
the Thunderbolt controller (VCC3P3_SX). When the RESET_N signal is de-asserted before the supply has come
up it may put the Thunderbolt controller in a latched state. The RESET_N signal must be de-asserted at least
100 µs after the Thunderbolt Controller supply has come up. For dead battery operation the GPIO_0 signal
should be “ANDed” with the 3.3-V supply to avoid de-asserting the RESETN when the Thunderbolt controller is
not powered. The figure below shows the RESET_N control with GPIO_0 and the 3.3-V supply. Alternatively, the
EC could configure GPIO_0 to de-assert RESETN when the system has successfully booted.
VCC3P3_SX
RESETN
GPIO_0
GND
Figure 41. RESETN Circuit
9.2.2.2.2.5 I2C Design Requirements
The I2C connection from the TPS65987DDJ and the Thunderbolt control allows the Thunderbolt controller to read
the current data status from the TPS65987DDJ when there is a connection on the Type-C port. The Thunderbolt
controller has an interrupt assigned for TPS65987DDJ and the Thunderbolt controller will read the I2C address
corresponding to the Type-C port. The I2C2 on the TPS65987DDJ is always connected to the Thunderbolt
controller and the I2C channel will respond to the 0x38 address.
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9.2.2.2.2.6 TS3DS10224 SBU Mux for AUX and LSTX/RX
The SBU signals must be muxed from the Type-C connector to the Thunderbolt controller. The AUX for
DisplayPort and LSTX/RX for Thunderbolt are connected to the TS3DS10224 and then muxed to the SBU pins.
The SBU mux is controlled through GPIOs from the TPS65987DDJ. The table below shows the TPS65987DDJ
GPIO events and the control signals from the TS3DS10224.
Table 19. GPIO Events for SBU Mux
TPS65987DDJ GPIO EVENT
TS3DS10224 CONTROL
Port 0 Cable Orientation Event
SAO, SBO
Port 0 DP Mode Selection Event
ENA
Port 0 TBT Event
ENB
N/A
SAI tied to VCC
N/A
SBI tied to GND
The table below shows the connections for the AUX, LSTXRX, and SBU pins for the TS3DS10224.
Table 20. TS3DS10224 Pin Connections
TS3DS10224 PIN
SIGNAL
INA+
SBU1
INA-
SBU2
OUTB0+
LSTX
OUTB0-
LSRX
OUTB1+
LSRX
OUTB1-
LSTX
OUTA0+
AUX_P
OUTA0-
AUX_N
OUTA1+
AUX_N
OUTA1-
AUX_P
9.2.2.2.2.7 Thunderbolt Flash Options
In most Thunderbolt systems the TPS65987DDJ will share the flash with the Thunderbolt controller. The flash
contains the Thunderbolt Controller firmware and the configuration data for the TPS65987DDJ. shows the
supported SPI flash options for Thunderbolt systems.
Table 21. Flash Supported for Thunderbolt Systems
MANUFACTURER
PART NUMBER
SIZE
Winbond
W25Q80JVNIQ
8 Mb
Spansion
S25FL208K
8 Mb
AMIC
A25L080
8 Mb
Macronix
MX25L8006EM1I
8 Mb
Micron
M25PE80-VMN6TP
8 Mb
Micron
M25PX80-VMN6TP
8 Mb
9.2.2.3 USB and DisplayPort Dock with Bus-Powered and Self-Powered Support
A flexible dock application that can work either on Bus-Power or Self-Power takes advantage of the two
integrated power paths. PPHV1 will sink power into the system when operating off Bus-Power and PPHV2 will
source power on VBUS when powered. When the dock can operate in both modes it allows the end-user to use
the dock in and out of an office.
The regulators that generate the required system voltages are powered from PPHV1 or the external dock supply.
These rails powered from a main 3.3-V rail to ensure that the all the voltages required are valid in Bus-Powered
and Self-Powered operation. This will also help for systems that support USB PD3.0 Fast Role Swap. There is a
variable regulator to provide 5 V, 9 V, 15 V, and 20 V per the Power Delivery Rules.
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The Super Speed signals from the Type-C connector are muxed to USB and MST Hubs through the TUSB1064.
The DisplayPort and USB signals from the Super Speed Mux will go to a MST and USB HUB to enable
additional video and USB connectors. The TPS65987DDJ can control the TUSB1064 Super Speed mux through
I2C or GPIO. The TPD6S300 provides additional protection such as short to VBUS on the CC and SBU pins and
ESD for the USB2 DN/P. See for the system block diagram.
DP ML
MST Hub
SSTX/RX
TUSB1064
I2C/GPIO
SS Mux Control*
SBU1/2
Type C
Receptacle
USB SSTX/RX
TUSB8044
USB Hub
SSTX/RX
SBU1/2
USB2.0
TPD6S300
GPIO
SS Mux Control*
I2C1 Master
SS Mux Control*
BC1.2
CC1/2
C_CC1/2
VBUS
PPHV1
TPS65987D
PP_CABLE
System 5V
VIN_3V3
System 3.3V
TPS54334
3.3V
TPS62097A
1.2V
PPHV2
TPS2500
5V
LM3489
5V/9V/15V/20V
EC
I2C2
I2C MASTER
Copyright © 2017, Texas Instruments Incorporated
Figure 42. USB and DisplayPort Dock Block Diagram
9.2.2.3.1 Design Requirements
The table below summarizes the Power Design parameters for a USB Type-C PD docking system.
Table 22. Power Design Parameters
POWER DESIGN PARAMETERS
VALUE
PPHV2 Input Voltage, Current
5 V/9 V/15 V/20 V, 3 A
CURRENT PATH
VBUS Source
PP_CABLE1/2 Input Voltage, Current
5 V, 500 mA
VCONN Source
PPHV1 Voltage, Current
5 V, 1.5 A
VBUS Sink
VIN_3V3 Voltage, Current
3.3 V, 50 mA
Internal TPS65987DDJ Circuitry
9.2.2.3.2 Detailed Design Procedure
9.2.2.3.2.1 USB Power Delivery Source Capabilities
When operating in Self-Powered mode the dock is recommended to support 60-W Power Delivery Rules to
charge most systems. The table below shows the source PDO for the Type-C port.
Table 23. Source PDOs
SOURCE PDO
PDO TYPE
VOLTAGE
CURRENT
PDO1
Fixed
5V
3A
PDO2
Fixed
9V
3A
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Table 23. Source PDOs (continued)
SOURCE PDO
PDO TYPE
VOLTAGE
CURRENT
PDO3
Fixed
15 V
3A
PDO4
Fixed
20 V
3A
9.2.2.3.2.2 USB Power Delivery Sink Capabilities
Most Type-C notebooks will support 1.5 A at 5 V on VBUS which should require the dock should be able to
operate at this current level. Table 24 shows the sink PDO for the Type-C port.
Table 24. Sink PDOs
SINK PDO
PDO TYPE
VOLTAGE
CURRENT
PDO1
Fixed
5V
1.5 A
9.2.2.3.2.3 USB and DisplayPort Supported Data Modes
The table below summarizes the data capabilities of the Type-C port supporting USB3 and DisplayPort.
Table 25. Data Capabilities
PROTOCOL
DATA
DATA ROLE
USB Data
USB3.1 Gen2
Device
DisplayPort
DP1.4
Host UFP_D (Pin Assignment C and D)
9.2.2.3.2.4 TUSB1064 Super Speed Mux GPIO Control
The TUSB1064 requires GPIO control in GPIO control mode to determine whether if there is USB or DisplayPort
data connection. summarizes the TPS65987DDJ GPIO Events and the control pins for the TUSB1064. Note that
the pin strapping on the TUSB1064 will set the GPIO control mode and the required equalizer settings. For more
details refer to the TUSB1064 datasheet.
Table 26. GPIO Events for Super Speed Mux
TPS65987DDJ GPIO EVENT
52
TUSB1064 CONTROL
Port 0 Cable Orientation Event
FLIP
Port 0 USB3 Event
CTL0
Port 0 DP Mode Selection Event
CTL1
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10 Power Supply Recommendations
10.1 3.3-V Power
10.1.1 VIN_3V3 Input Switch
The VIN_3V3 input is the main supply to the TPS65987DDJ device. The VIN_3V3 switch (see Figure 13) is a
unidirectional switch from VIN_3V3 to LDO_3V3, not allowing current to flow backwards from LDO_3V3 to
VIN_3V3. This switch is on when 3.3 V is available. See Table 27 for the recommended external capacitance on
the VIN_3V3 pin.
10.1.2 VBUS 3.3-V LDO
The 3.3-V LDO from VBUS steps down voltage from VBUS to LDO_3V3 which allows the TPS65987DDJ device
to be powered from VBUS when VIN_3V3 is unavailable. This LDO steps down any recommended voltage on
the VBUS pin. When VBUS is 20 V, as is allowable by USB PD, the internal circuitry of the TPS65987DDJ
device operates without triggering thermal shutdown; however, a significant external load on the LDO_3V3 pin
can increase the temperature enough to trigger a thermal shutdown. The VBUS 3.3-V LDO blocks reverse
current from LDO_3V3 back to VBUS allowing VBUS to be unpowered when LDO_3V3 is driven from another
source. See Table 27 for the recommended external capacitance on the VBUS and LDO_3V3 pins.
10.2 1.8-V Power
The internal circuitry is powered from 1.8 V. The 1.8-V LDO steps the voltage down from LDO_3V3 to 1.8 V. The
1.8-V LDO provides power to all internal low-voltage digital circuits which includes the digital core, memory and
other digital circuits. The 1.8-V LDO also provides power to all internal low-voltage analog circuits. See Table 27
for the recommended external capacitance on the LDO_1V8 pin.
10.3 Recommended Supply Load Capacitance
Table 27 lists the recommended board capacitances for the various supplies. The typical capacitance is the
nominally rated capacitance that must be placed on the board as close to the pin as possible. The maximum
capacitance must not be exceeded on pins for which it is specified. The minimum capacitance is minimum
capacitance allowing for tolerances and voltage derating ensuring proper operation.
Table 27. Recommended Supply Load Capacitance
CAPACITANCE
PARAMETER
DESCRIPTION
VOLTAGE
RATING
MIN
(ABSOLUTE)
TYP
(PLACED)
MAX
(ABSOLUTE)
CVIN_3V3
Capacitance on VIN_3V3
6.3 V
5 µF
10 μF
CLDO_3V3
Capacitance on LDO_3V3
6.3 V
5 µF
10 µF
25 µF
CLDO_1V8
Capacitance on LDO_1V8
4V
2.2 µF
4.7 µF
12 µF
CVBUS1
Capacitance on VBUS1
25 V
0.5 µF
1 µF
12 µF
CVBUS2
Capacitance on VBUS2
25 V
0.5 µF
1 µF
12 µF
CPP_HV_SRC
Capacitance on PP_HV when configured as a 5-V source
10 V
2.5 µF
4.7 µF
CPP_HV_SNK
Capacitance on PP_HV when configured as a 20-V sink
25 V
1 µF
47 µF
CPP_CABLE
Capacitance on PP_CABLE. When shorted to PP_HV congifured as a 5-V
source, the CPP_HV_SRC capacitance may be shared.
10 V
2.5 µF
4.7 µF
120 µF
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11 Layout
11.1 Layout Guidelines
Proper routing and placement will maintain signal integrity for high speed signals and improve the heat
dissipation from the TPS65987DDJ power paths. The combination of power and high speed data signals are
easily routed if the following guidelines are followed. It is a best practice to consult with board manufacturing to
verify manufacturing capabilities.
11.1.1 Top TPS65987DDJ Placement and Bottom Component Placement and Layout
When the TPS65987DDJ is placed on top and its components on bottom the solution size will be at its smallest.
11.2 Layout Example
Follow the differential impedances for Super and High Speed signals defined by their specifications (DisplayPort
- AUXN/P and USB2.0). All I/O will be fanned out to provide an example for routing out all pins, not all designs
will use all of the I/O on the TPS65987DDJ.
Figure 43. Example Schematic
54
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Layout Example (continued)
Copyright © 2017, Texas Instruments Incorporated
Figure 44. Example Schematic2
11.3 Component Placement
Top and bottom placement is used for this example to minimize solution size. The TPS65987DDJ is placed on
the top side of the board and the majority of its components are placed on the bottom side. When placing the
components on the bottom side, it is recommended that they are placed directly under the TPS65987DDJ. When
placing the VBUS and PPHV capacitors it is easiest to place them with the GND terminal of the capacitors to
face outward from the TPS65987DDJ or to the side since the drain connection pads on the bottom layer should
not be connected to anything and left floating. All other components that are for pins on the GND pad side of the
TPS65987DDJ should be placed where the GND terminal is underneath the GND pad.
The CC capacitors must be placed on the same side as the TPS65987DDJ close to the respective CC1 and CC2
pins. Do NOT via to another layer in between the CC pins to the CC capacitor, placing a via after the CC
capacitor is recommended.
The ADCIN1/2 voltage divider resistors can be placed where convenient. In this layout example they are placed
on the opposite layer of the TPS65987DDJ close to the LDO_3V3 pin to simplify routing.
The figures below show the placement in 2-D and 3-D.
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Component Placement (continued)
Figure 45. Top View Layout
Figure 46. Bottom View Layout
Figure 47. Top View 3-D
Figure 48. Bottom View 3-D
11.4 Routing PP_HV1/2, VBUS, PP_CABLE, VIN_3V3, LDO_3V3, LDO_1V8
On the top side, create pours for PP_HV1/2 and VBUS1/2 to extend area to place 8-mil hole and 16-mil diameter
vias to connect to the bottom layer. See the figure below for the recommended via sizing.
56
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Routing PP_HV1/2, VBUS, PP_CABLE, VIN_3V3, LDO_3V3, LDO_1V8 (continued)
Figure 49. Recommended Minimum Via Sizing
A minimum of four vias should be used to connect between the top and bottom layer power paths. For the
bottom layer, place pours that will connect the PP_HV1/2 and VBUS capacitors to their respective vias. For 5-A
systems, special consideration must be taken for ensuring enough copper is used to handle the higher current.
For 0.5-oz copper, top or bottom pours, with 0.5-oz plating will require about 120-mil pour width for 5-A support.
When routing the 5 A through a 0.5-oz internal layer, more than 200 mil will be required to carry the current.
The figures below show the pours used in this example.
Figure 50. Top Polygon Pours
Figure 51. Bottom Polygon Pours
For PP_CABLE, it is recommended to connect the capacitor to the pin with two vias. They should be placed side
by side and as close to the pin as possible to allow for routing the CC lines.
Connect the bottom side VIN_3V3 and LDO_3V3 capacitors with traces through a via. The vias should have a
straight connection to the respective pins. LDO_1V8 is connected through a via on the outside of the pin and
connected with a trace on the bottom side capacitor.
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11.5 Routing CC and GPIO
Routing the CC lines with a 8-mil trace will ensure the needed current for supporting powered Type-C cables
through VCONN. For more information on VCONN refer to the Type-C specification. For capacitor GND pin use
a 16-mil trace if possible.
Most of the GPIO signals can be fanned out on the top layer with a 4-mil trace. The PP_EXT1/2 GPIO control go
through a via to be routed on another layer.
Figure 52 below shows the CC and GPIO routing.
Figure 52. CC Routing and GPIO Fan-Out
Table 28. Routing Widths
58
ROUTE
WIDTH (mil minimum)
CC1, CC2, PP_CABLE1, PP_CABLE2
8
VIN_3V3, LDO_3V3, LDO_1V8
6
Component GND
10
GPIO
4
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11.6 Thermal Dissipation for FET Drain Pads
The TPS65987DDJ contains two internal FETs. To assist with thermal dissipation of these FETs, the drains of
the FETs are connected to two metal pads underneath the IC. When completing a board layout for the
TPS65987DDJ, it is important to provide copper pours on the top and bottom layer of the PCB for the thermal
pads of each FET.
When looking at the footprint for the TPS65987DDJ, pins 57 and 58 are two smaller pads underneath the device.
These are the drain pads for the two internal FETs. The dimensions are 1.75 mil x 2.6 mil and 1.75 mil x 2.55 mil
for pins 57 and 58 respectively. Each of these FET pads should contain a minimum of six thermal vias through
the PCB. This layout example contains 8 thermal vias through the PCB. On the bottom side of the PCB, the 1.75
mil x 2.6 mil and 1.75 mil x 2.55 mil thermal pads are mirrored to assist with thermal dissipation.
The figures below show the copper fills for the FET Drain pads.
Figure 53. Top Layer FET Pads
Figure 54. Bottom Layer FET Pads
As seen in the figures above, it is recommended to connect the Drain pins to their respective Drain pads
underneath the IC. This will help with thermal dissipation by moving some of the heat away from the device. To
further assist with thermal dissipation, it is possible to add copper fins on the top layer for both of the FET Drain
Pads. When calculating the relative thermal dissipation, the first 3 mm of copper away from the device contribute
largely to the thermal performance. Once the copper expands beyond 3 mm from the IC, there are diminishing
returns in thermal performance.
Figure 55 highlights an example with copper fins to improve thermal dissipation.
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Thermal Dissipation for FET Drain Pads (continued)
Figure 55. Copper Fins on Drain Pad
The thermal vias under each of the FET Drain Pads should be filled. Filling the vias will greatly improve the
thermal dissipation on the FETs as there is significantly more copper that is connecting the top layer pad to the
bottom layer copper. Alternatively, the vias can be epoxy filled but they will have higher thermal resistance. Each
8-/16-mil to 10-/20-mil via could have a thermal resistance ranging from 175°C/W to 200°C/W with board
manufacturing variation. When doing thermal calculations it is recommended to use the worst case 200°C/W
which will give a set of six vias a thermal resistance of approximately 33°C/W from the top to bottom pad. The
vias in the FET pads should only be connected to copper pads on the top and bottom layers of the PCB. These
should not be connected to GND. Refer to the image below to see which layers should be connected for the
GND vias and FET Pad vias.
Figure 49 shows a common stack-up for systems that require Super Speed and high power routing.
GND Vias
FET Pad Vias
Top Layer
GND1
Inner Layer 1
GND2
Inner Layer 2
Inner Layer 3
GND3
Bottom Layer
Figure 56. PCB Stack-Up
60
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11.7 USB2 Recommended Routing For BC1.2 Detection/Advertisement
When routing the USB2 signals to the TPS65987DDJ BC1.2 detection pins it is recommended to reduce the
amount of excess trace to get to the TPS65987DDJ pins, as this will cause antennae and degrade signal
integrity. The USB top/bottom signals are shorted together in this example and the same approach can be used
if an external USB mux is used. There are several approaches that can be used to get optimal routing; “tap” the
USB2 signals with vias that connect the TPS65987DDJ pins, via up to the layer where the pins are located and
continue to route on that layer, or a combination of both.
In this layout example, the D+/D- lines are routed to an internal layer from the connector. They are then via’d up
to the TPS65987DDJ directly at the pins. There is a small trace that is connecting the via to the pin on the top
layer. When routing the D+/D- in this manner, the added stub is minimal.
Figure 57. Via Connection for USB2
Figure 58 shows the entire routing from the Type-C connector, ESD Protection, and TPS65987DDJ BC1.2
Detection. This example does not take length matching into consideration but it is recommended to follow
standard USB2 rules for routing and length matching.
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USB2 Recommended Routing For BC1.2 Detection/Advertisement (continued)
Figure 58. Complete USB2 Routing
62
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Firmware Warranty Disclaimer
IN ORDER FOR THE TPS6598X DEVICE TO FUNCTION IN ACCORDANCE WITH THIS SPECIFICATIONS,
YOU WILL NEED TO DOWNLOAD THE LATEST VERSION OF THE FIRMWARE FOR THE DEVICE. IF YOU
DO NOT DOWNLOAD AND INCORPORATE THE LATEST VERSION OF THE FIRMWARE INTO THE DEVICE,
THEN THE DEVICE IS PROVIDED “AS IS” AND TI MAKES NO WARRANTY OR REPRESENTATION
WHATSOEVER IN RESPECT OF SUCH DEVICE, AND DISCLAIMS ANY AND ALL WARRANTIES AND
REPRESENTATIONS WITH RESPECT TO SUCH DEVICE. FURTHER, IF YOU DO NOT DOWNLOAD AND
INCORPORATE THE LATEST VERSION OF THE FIRMWARE INTO THE DEVICE, TI WILL NOT BE LIABLE
FOR AND SPECIFICALLY DISCLAIMS ANY DAMAGES, INCLUDING DIRECT DAMAGES, HOWEVER
CAUSED, WHETHER ARISING UNDER CONTRACT, TORT, NEGLIGENCE, OR OTHER THEORY OF
LIABILITY RELATING TO THE DEVICE, EVEN IF TI IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12.2 Documentation Support
12.2.1 Related Documentation
• TUSB1064 USB TYPE-C™ DP Alt Mode 10 Gbps Sink-Side Linear Redriver Crosspoint Switch data sheet
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
Thunderbolt is a trademark of Intel.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
64
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PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPS65987DDJRSHR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN
RSH
56
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-10 to 75
TPS65987D
DJ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS65987DDJRSHR
Package Package Pins
Type Drawing
VQFN
RSH
56
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
7.3
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.3
1.1
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65987DDJRSHR
VQFN
RSH
56
2500
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
RSH0056E
VQFN - 1 mm max height
SCALE 2.000
PLASTIC QUAD FLATPACK - NO LEAD
A
7.15
6.85
B
PIN 1 INDEX AREA
7.15
6.85
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
3.4 0.1
1.75 0.1
PKG
(0.2)
28
15
52X 0.4
29
14
2.55 0.1
5.5 0.1
58
SYMM
59
4X
5.2
57
2.6 0.1
1
PIN 1 ID
42
43
56
56X
(0.2) TYP
(0.35)
TYP
0.6
0.4
56X
0.25
0.15
0.1
0.05
C A B
C
4223928/B 09/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RSH0056E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3X 0.05 MAX
ALL AROUND
(3.4)
(0.65)
2X
(1.75)
4X (0.7)
48X (0.2)
PKG
43
56
48X (0.7)
SEE SOLDER MASK
OPTIONS
(0.2) TYP
1
42
8X (0.2)
1.18
(2.6)
(1.45)
52X (0.4)
57
1.32 TYP
SYMM
59
(6.7)
(5.5)
58
(1.475)
(0.875) TYP
4X SOLDER MASK
DEFINED PAD
(2.55)
29
14
PADS 57,58 & 59
NON SOLDER MASK
DEFINED
15
28
3X
(0.15)
(0.475) TYP
3X
(1.2)
(1.875)
( 0.2) TYP
VIA
SOLDER MASK
OPENING
5X (1.05)
(6.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
EXPOSED
METAL
METAL UNDER
SOLDER MASK
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK OPTIONS
NOT TO SCALE
4223928/A 09/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RSH0056E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
PKG
4X (0.7)
4X
(1.47)
(1.67)
TYP
(0.215)
TYP
(0.2) TYP
56
48X (0.2)
48X (0.7)
43
8X (0.2)
4X (1.15)
1
42
(1.35)
(0.775)
(1.32)
TYP
52X (0.4)
57
SYMM
(0.66) TYP
59
(6.7)
58
(0.8)
(1.35)
8X (1.12)
14
29
METAL UNDER
SOLDER MASK
TYP
SOLDER MASK
OPENING
TYP
15
28
(1.875)
8X (1.47)
METAL
TYP
(6.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 MM THICK STENCIL
EXPOSED PAD PRINTED SOLDER COVERAGE BY AREA
PAD 57 & 58: 75%
PAD 59: 70%
SCALE: 12X
4223928/B 09/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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