Texas Instruments | TUSB1042I USB Type-C™ 10 Gbps 2:1 Linear Redriver Switch (Rev. D) | Datasheet | Texas Instruments TUSB1042I USB Type-C™ 10 Gbps 2:1 Linear Redriver Switch (Rev. D) Datasheet

Texas Instruments TUSB1042I USB Type-C™ 10 Gbps 2:1 Linear Redriver Switch (Rev. D) Datasheet
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TUSB1042I
SLLSF15D – AUGUST 2017 – REVISED MAY 2019
TUSB1042I USB Type-C™ 10 Gbps 2:1 Linear Redriver Switch
1 Features
3 Description
•
•
•
•
•
The TUSB1042I is a redriving switch supporting USB
3.1 data rates up to 10 Gbps. The TUSB1042I
provides several levels of receive linear equalization
to compensate for inter-symbol interference (ISI) due
to cable and board trace loss. The device operates
on a single 3.3 V supply and comes in the industrial
temperature range.
1
•
•
•
•
•
USB Type-C™ 2:1 redriver switch
USB 3.1 Gen 1/Gen 2 up to 10 Gbps
Ultra-low-power architecture
Linear redriver with up to 14 dB equalization
Automatic LFPS de-emphasis control to meet
USB 3.1 certification requirements
Configuration through GPIO or I2C
Intel proprietary DCI capability on USB Type-C for
closed chassis debugging
Hot-plug capable
Industrial temperature range: -40ºC to 85ºC
4 mm x 6 mm, 0.4 mm pitch WQFN package
Device Information(1)
PART NUMBER
TUSB1042I
PACKAGE
WQFN (40)
BODY SIZE (NOM)
4.00 mm x 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
Tablets
Notebooks
Desktops
Docking stations
Simplified Schematics
TUSB1042I Eye Diagram
TUSB1042I
TUSB1042I
TX1
USB Host
RX2
SSRX
RX1
FLIP
Type-C Receptacle
TX2
SSTX
CTL0
CC1
PD Controller
CC2
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB1042I
SLLSF15D – AUGUST 2017 – REVISED MAY 2019
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
7
8
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Power Supply Characteristics ................................... 6
DC Electrical Characteristics .................................... 6
AC Electrical Characteristics..................................... 7
DCI Specific Electrical Characteristics...................... 8
Timing Requirements ................................................ 8
Switching Characteristics ........................................ 8
Typical Characteristics .......................................... 10
Parameter Measurement Information ................ 12
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 15
8.3
8.4
8.5
8.6
9
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
16
17
20
22
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application ................................................. 24
9.3 System Examples .................................................. 28
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Example .................................................... 30
12 Device and Documentation Support ................. 31
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
Changes from Revision C (August 2018) to Revision D
•
Added following to pin 11 description: If I2C_EN = “F”, then this pin must be set to “F” or “0”. ........................................... 4
Changes from Revision B (April 2018) to Revision C
•
Page
Page
Added Note 1 To pins 29 and 32 in the Pin Functions table.................................................................................................. 3
Changes from Revision A (October 2017) to Revision B
Page
•
Changed the appearance of the pinout image in the Pin Configuration and Function section .............................................. 3
•
Changed the USB3.1 Control/Status Registers reset value From: 00000000 To: 00000100.............................................. 23
•
Changed the Reset value of bit 3:2 From: 00 To: 01 in Table 12 ....................................................................................... 23
Changes from Original (August 2017) to Revision A
•
2
Page
Changed the Human-body model (HBM) value From: ±6000 To: ±5000 in the ESD Ratings ............................................... 5
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5 Pin Configuration and Functions
RX2p
RX2n
EQ0
TX2p
TX2n
EQ1
TX1n
TX1p
DCI_CLK
RX1n
RX1p
DCI_DAT
40
39
38
37
36
35
34
33
32
31
30
29
RNQ Package
40-Pin (WQFN)
Top View
VCC
1
28
VCC
TEST2
2
27
RSVD12
SSEQ1
3
26
RSVD11
SSRXn
4
25
RSVD10
24
RSVD9
Thermal
Pad
8
21
FLIP/SCL
VCC
RSVD8
RSVD7
I2C_EN
RSVD6
RSVD5
A1
RSVD4
RSVD3
SSEQ0/A0
RSVD2
9
RSVD1
20
SSTXp
19
CTL0/SDA
18
22
17
7
16
SSTXn
15
TEST1
14
23
13
6
12
VCC
11
5
10
SSRXp
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
RX1n
31
Diff I/O
Differential negative input for USB3.1 Downstream Facing port.
RX1p
30
Diff I/O
Differential positive input for USB3.1 Downstream Facing port.
TX1n
34
Diff O
Differential negative output for USB3.1 downstream facing port.
TX1p
33
Diff O
Differential positive output for USB 3.1 downstream facing port.
TX2p
37
Diff O
Differential positive output for USB 3.1 downstream facing port.
TX2n
36
Diff O
Differential negative output for USB 3.1 downstream facing port.
RX2p
40
Diff I/O
Differential positive input for USB3.1 Downstream Facing port.
RX2n
39
Diff I/O
Differential negative input for USB3.1 Downstream Facing port.
SSTXp
8
Diff I
Differential positive input for USB3.1 upstream facing port.
SSTXn
7
Diff I
Differential negative input for USB3.1 upstream facing port.
SSRXp
5
Diff O
Differential positive output for USB3.1 upstream facing port.
SSRXn
4
Diff O
Differential negative output for USB3.1 upstream facing port.
EQ1
35
4 Level I
This pin along with EQ0 sets the USB receiver equalizer gain for downstream facing RX1 and RX2
when USB used.
EQ0
38
4 Level I
This pin along with EQ1 sets the USB receiver equalizer gain for downstream facing RX1 and RX2
when USB used.
DCI_DAT
29 (1)
I/O
(PD)
When I2C_EN ! = 0, this pin functions as DCI data output Leave open if not used.
DCI_CLK
32 (1)
I/O
(PD)
When I2C_EN ! = 0, this pin functions as DCI clock output Leave open if not used.
(1)
Not a fail-safe I/O. Actively driving pin high while VCC is removed results in leakage voltage on VCC pins.
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Pin Functions (continued)
PIN
NAME
I/O
NO.
DESCRIPTION
I2C_EN
17
4 Level I
I2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is ‘0".
0 = GPIO mode (I2C disabled)
R = TI Test Mode (I2C enabled at 3.3 V)
F = I2C enabled at 1.8 V
1 = I2C enabled at 3.3 V.
A1
14
4 Level I
When I2C_EN is not ‘0’, this pin will set the TUSB1042I I2C address.
SSEQ1
3
4 Level I
Along with SSEQ0, sets the USB receiver equalizer gain for upstream facing SSTXP/N.
SSEQ0/A0
11
4 Level I
Along with SSEQ1, sets the USB receiver equalizer gain for upstream facing SSTXP/N. When
I2C_EN is not ‘0’, this pin will also set the TUSB1042I I2C address. If I2C_EN = “F”, then this pin
must be set to “F” or “0”.
FLIP/SCL
21
2 Level I
When I2C_EN=’0’ this is Flip control pin, otherwise this pin is I2C clock. . When used for I2C clock
pullup to I2C master's VCC I2C supply.
CTL0/SDA
22
2 Level I
When I2C_EN=’0’ this is a USB3.1 Switch control pin, otherwise this pin is I2C data. When used for
I2C data pullup to I2C master's VCC I2C supply.
9, 10, 12,
13, 15, 16,
18, 19, 24,
25, 26, 27
RSVD
23
2 Level I
(Failsafe)
(PD)
Test pin. Pull down to GND.
2
4 Level I
Test pin. Leave open.
1, 6, 20, 28
P
3.3-V Power Supply
G
Ground
RSVD1 - 12
TEST1
TEST2
VCC
Thermal Pad
4
Reserved. Leave open.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply Voltage Range (2), VCC
MIN
MAX
UNIT
–0.3
4
V
±2.5
V
V
Differential voltage between positive and
negative inputs
Voltage Range at any input or output pin
Voltage at differential inputs
–0.5
VCC + 0.5
CMOS Inputs
–0.5
VCC + 0.5
V
125
°C
150
°C
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminals.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±5000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Main power supply
VCC
MIN
NOM
MAX
3
3.3
3.6
V
100
ms
Supply Ramp Requirement
V(12C)
Supply that external resistors are pulled up to on SDA and SCL
V(PSN)
Supply Noise on VCC pins
TA
Operating free-air temperature
TUSB1042I
1.7
-40
UNIT
3.6
V
100
mV
85
°C
6.4 Thermal Information
TUSB1042I
THERMAL METRIC (1)
RNQ (WQFN)
UNIT
40 PINS
RθJA
Junction-to-ambient thermal resistance
37.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
20.7
°C/W
RθJB
Junction-to-board thermal resistance
9.5
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
9.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Power Supply Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PCC(ACTIVE-USB)
Average active power
USB Only
Link in U0 with GEN2 data transmission.
EN, EQ cntrl pins = NC, k28.5 pattern at
10 Gbps, VID = 1000 mVPP ;
CTL1 = L; CTL0 = H
PCC(ACTIVE-USB-DP1)
Average active power
USB + 2 Lane DP
Link in U0 with GEN2 data transmission.
EN, EQ cntrl pins = NC, k28.5 pattern at
10 Gbps, VID = 1000 mVPP;
CTL1 = H; CTL0 = H
634
mW
PCC(ACTIVE--DP)
Average active power
4 Lane DP Only
Four active DP lanes operating at
8.1Gbps;
CTL1 = H; CTL0 = L;
660
mW
PCC(NC-USB)
Average power with no connection
No GEN1 device is connected to
TXP/TXN;
CTL1 = L; CTL0 = H;
2.4
mW
PCC(U2U3)
Average power in U2/U3
Link in U2 or U3 USB Mode Only;
CTL1 = L; CTL0 = H;
3
mW
PCC(SHUTDOWN)
Device Shutdown
CTL1 = L; CTL0 = L; I2C_EN = 0;
0.85
mW
335
mW
6.6 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4-State CMOS Inputs(EQ[1:0], SSEQ[1:0], I2C_EN)
IIH
High level input current
VCC = 3.6 V; VIN = 3.6 V
IIL
Low level input current
VCC = 3.6 V; VIN = 0 V
Threshold 0 / R
VCC = 3.3 V
0.55
V
Threshold R/ Float
VCC = 3.3 V
1.65
V
Threshold Float / 1
VCC = 3.3 V
2.7
V
4-Level VTH
20
80
µA
–160
-40
µA
RPU
Internal pull-up resistance
35
kΩ
RPD
Internal pull-down resistance
95
kΩ
2-State CMOS Input (CTL0, TEST1, FLIP) TEST1, CTL0 and FLIP are Failsafe.
VIH
High-level input voltage
2
3.6
VIL
Low-level input voltage
0
0.8
V
RPD
Internal pull-down resistance for CTL1
500
kΩ
R(ENPD)
Internal pull-down resistance for pin 29
and pin 32
150
kΩ
IIH
High-level input current
VIN = 3.6 V
–25
25
µA
IIL
Low-level input current
VIN = GND, VCC = 3.6 V
–25
25
µA
V
2
I C Control Pins SCL, SDA
VIH
High-level input voltage
I2C_EN = 0
0.7 x V(I2C)
3.6
V
VIL
Low-level input voltage
I2C_EN = 0
0
0.3 x V(I2C)
V
VOL
Low-level output voltage
I2C_EN = 0; IOL = 3 mA
0
0.4
IOL
Low-level output current
I2C_EN = 0; VOL = 0.4 V
20
II(I2C)
Input current on SDA pin
0.1 x V(I2C) < Input voltage < 3.3 V
CI(I2C)
Input capacitance
C(I2C_FM+_BUS)
V
mA
10
µA
10
pF
I2C bus capacitance for FM+ (1MHz)
150
pF
C(I2C_FM_BUS)
I2C bus capacitance for FM (400kHz)
150
pF
R(EXT_I2C_FM+)
External resistors on both SDA and SCL
when operating at FM+ (1MHz)
C(I2C_FM+_BUS) = 150 pF
620
820
910
Ω
R(EXT_I2C_FM)
External resistors on both SDA and SCL
when operating at FM (400kHz)
C(I2C_FM_BUS) = 150 pF
620
1500
2200
Ω
6
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6.7 AC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USB Gen 2 Differential Receiver (RX1P/N, RX2P/N, SSTXP/N)
AC-coupled differential peak-to-peak
signal measured post CTLE through a
reference channel
V(RX-DIFF-PP)
Input differential peak-peak voltage
swing linear dynamic range
V(RX-DC-CM)
Common-mode voltage bias in the
receiver (DC)
R(RX-DIFF-DC)
Differential input impedance (DC)
Present after a GEN2 device is
detected on TXP/TXN
72
120
Ω
R(RX-CM-DC)
Receiver DC common mode
impedance
Present after a GEN2 device is
detected on TXP/TXN
18
30
Ω
Z(RX-HIGH-IMP-DC-POS)
Common-mode input impedance with
termination disabled (DC)
Present when no GEN2 device is
detected on TXP/TXN. Measured over
the range of 0-500mV with respect to
GND.
25
V(SIGNAL-DET-DIFF-PP)
Input differential peak-to-peak signal
detect assert level
At 10 Gbps, no input loss, PRBS7
pattern
80
mV
V(RX-IDLE-DET-DIFF-PP)
Input differential peak-to-peak signal
detect de-assert Level
At 10 Gbps, no input loss, PRBS7
pattern
60
mV
V(RX-LFPS-DET-DIFF-PP)
Low frequency periodic signaling
(LFPS) detect threshold
Below the minimum is squelched
V(RX-CM-AC-P)
Peak RX AC common-mode voltage
Measured at package pin
C(RX)
RX input capacitance to GND
At 5 GHz
0.5
50 MHz – 1.25 GHz at 90 Ω
–19
dB
2000
mVpp
0
V
kΩ
100
300
mV
150
mV
1
pF
RL(RX-DIFF)
Differential return Loss
5 GHz at 90 Ω
–10
dB
RL(RX-CM)
Common-mode return loss
50 MHz – 5 GHz at 90 Ω
–10
dB
EQ(SS_TX)
Receiver equalization for upstream
facing port
SSEQ[1:0] at 5 GHz
11
dB
EQ(SS_RX)
Receiver equalization for downstream
facing ports
EQ[1:0] at 5 GHz
9
dB
USB Gen 2 Differential Transmitter (TX1P/N, TX2P/N, SSRXP/N)
VTX(DIFF-PP)
Transmitter dynamic differential voltage swing range.
VTX(RCV-DETECT)
Amount of voltage change allowed during receiver detection
VTX(CM-IDLE-DELTA)
Transmitter idle common-mode voltage change while in U2/U3 and not actively
transmitting LFPS
VTX(DC-CM)
Common-mode voltage bias in the transmitter (DC)
1600
–600
mVPP
600
mV
600
mV
1.75
V
VTX(CM-AC-PP-ACTIVE)
Tx AC common-mode voltage active
Max mismatch from Txp + Txn for both
time and amplitude
VTX(IDLE-DIFF-AC-PP)
AC electrical idle differential peak-topeak output voltage
At package pins
VTX(IDLE-DIFF-DC)
DC electrical idle differential output
voltage
At package pins after low pass filter to
remove AC component
Absolute DC common-mode voltage
between U1 and U0
At package pin
DELTA)
RTX(DIFF)
Differential impedance of the driver
75
120
Ω
CAC(COUPLING)
AC coupling capacitor
75
265
nF
RTX(CM)
Common-mode impedance of the
driver
Measured with respect to AC ground
over
0–500 mV
18
30
Ω
ITX(SHORT)
TX short circuit current
TX± shorted to GND
67
mA
CTX(PARASITIC)
TX input capacitance for return loss
At package pins, at 5 GHz
1.25
pF
RLTX(DIFF)
Differential return loss
RLTX(CM)
VTX(CM-DC-ACTIVE-IDLE-
100
mVPP
0
10
mV
0
14
mV
200
mV
50 MHz – 1.25 GHz at 90 Ω
-15
dB
5 GHz at 90 Ω
-13
dB
Common-mode return loss
50 MHz – 5 GHz at 90 Ω
-13
dB
Crosstalk
Differential crosstalk between TX and
RX signal pairs
at 5 GHz
–30
dB
C(P1dB-LF)
Low frequency 1-dB compression
point
at 100 MHz, 200 mVPP < VID
< 2000 mVPP
1300
mVPP
AC Characteristics
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AC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
C(P1dB-HF)
High frequency 1-dB compression
point
at 5 GHz, 200 mVPP < VID
< 2000 mVPP
fLF
Low frequency cutoff
200 mVPP< VID < 2000 mVPP
TX output deterministic jitter
TX output total jitter
MIN
TYP
MAX
1000
20
UNIT
mVPP
50
kHz
200 mVPP < VID < 2000 mVPP, PRBS7,
10 Gbps
0.11
UIpp
200 mVPP < VID < 2000 mVPP, PRBS7,
5 Gbps
0.05
UIpp
200 mVPP < VID < 2000 mVPP, PRBS7,
10 Gbps
0.15
UIpp
200 mVPP < VID < 2000 mVPP, PRBS7,
5 Gbps
0.08
UIpp
6.8 DCI Specific Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.45
V
33
Ω
DCI_CLK and DCI_DAT LVCMOS Outputs
VOL
Low-Level output voltage
VCC = 3 V; IOL = 2 mA; CL = 10 pF
VOH
High-Level output voltage
VCC = 3 V; IOL = –2 mA;
RDCI
Output characteristic impedance
tPERIOD
DCI Clock period
tVALID
Rising edge of DCI clock to DCI
data valid
tDCI_RISE
DCI output rise time
Measured at 20% to 80%.
350
ps
tDCI_FALL
DCI output fall time
Measured at 80% to 20%
350
ps
2.4
V
21
Measured at 50%
25
6.67
ns
1
ns
6.9 Timing Requirements
MIN
NOM
MAX
UNIT
USB Gen 1
tIDLEEntry
Delay from U0 to electrical idle
See Figure 11
10
ns
tIDELExit_U1
U1 exist time: break in electrical idle to
the transmission of LFPS
See Figure 11
6
ns
tIDLEExit_U2U3
U2/U3 exit time: break in electrical idle to transmission of LFPS
tRXDET_INTVL
RX detect interval while in Disconnect
tIDLEExit_DISC
Disconnect Exit Time
10
µs
tExit_SHTDN
Shutdown Exit Time
1
ms
tDIFF_DLY
Differential Propagation Delay
See Figure 10
tR, tF
Output Rise/Fall time (see Figure 12)
20%-80% of differential
voltage measured 1.7 inch
from the output pin
tRF_MM
Output Rise/Fall time mismatch
20%-80% of differential
voltage measured 1.7 inch
from the output pin
10
µs
12
ms
300
ps
35
ps
2.6
ps
6.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1
MHz
2
I C (Refer to Figure 9)
fSCL
I2C clock frequency
tBUF
Bus free time between START and STOP conditions
8
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Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tHDSTA
TEST CONDITIONS
Hold time after repeated START condition. After this period, the first
clock pulse is generated
2
MIN
TYP
MAX
UNIT
0.26
µs
tLOW
Low period of the I C clock
0.5
µs
tHIGH
High period of the I2C clock
0.26
µs
tSUSTA
Setup time for a repeated START condition
0.26
µs
tHDDAT
Data hold time
0
μs
tSUDAT
Data setup time
50
ns
tR
Rise time of both SDA and SCL signals
tF
Fall time of both SDA and SCL signals
tSUSTO
Setup time for STOP condition
Cb
Capacitive load for each bus line
20 × (V(I2C)/5.5
V)
120
ns
120
ns
150
pF
0.26
μs
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15
15
10
10
5
5
SDD21 (dB)
SDD21 (dB)
6.11 Typical Characteristics
0
-5
0
-5
EQ0
EQ1
EQ2
EQ3
-10
-15
0.01
EQ4
EQ5
EQ6
EQ7
0.1
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
EQ0
EQ1
EQ2
EQ3
-10
1
Frequency (GHz)
-15
0.01
10
0.1
D002
1.2
1.4
1
0.8
0.6
0.4
0.2
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
1
Frequency (GHz)
10
D003
Figure 2. USB TX EQ Settings Curves
1.6
Differential Output Voltage (V)
Differential Output Voltage (V)
Figure 1. USB RX EQ Settings Curves
1.4
EQ0
EQ1
EQ2
EQ3
EQ4
EQ5
EQ6
EQ7
EQ12
EQ13
EQ14
EQ15
1.2
1
0.8
0.6
0.4
EQ0
EQ1
EQ2
EQ3
0.2
0
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
0
0
0.2
0.4
0.6 0.8
1
1.2 1.4
Differential Input Voltage (V)
1.6
1.8
2
0
0.2
0.4
D005
Figure 3. USB TX Linearity Curves at 5 GHz
0.6 0.8
1
1.2 1.4
Differential Input Voltage (V)
1.6
1.8
2
D006
Figure 4. USB RX Linearity Curves at 5 GHz
5
RX1
RX2
TX1
0
TX2
SSRX
SDD22 (dB)
-5
-10
-15
-20
-25
-30
0.01
0.1
1
Frequency (GHz)
10
D008
Figure 6. Output Return Loss Performance
Figure 5. Input Return Loss Performance
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Output Voltage (150 mV/Div)
Output Voltage (150 mV/Div)
Typical Characteristics (continued)
Time (33.33 ps/Div)
Time (16.67 ps/Div)
Figure 7. USB 3.1 Gen1 Eye-Pattern Performance with 12inch Input PCB Trace at 5 Gbps
Figure 8. USB 3.1 Gen2 Eye-Pattern Performance with
12-inch Input PCB Trace at 10 Gbps
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7 Parameter Measurement Information
70%
SDA
30%
tR
tLOW
tBUF
tHIGH
tHDSTA
tF
70%
SCL
P
30%
S
S
tHDDAT
tHDSTA
P
tSUDAT
tSUSTA
tSUSTO
Figure 9. I2C Timing Diagram Definitions
IN
TDIFF_DLY
TDIFF_DLY
OUT
Figure 10. Propagation Delay
IN+
VRX-LFPS-DET-DIFF-PP
Vcm
INTIDLEExit
TIDLEEntry
OUT+
Vcm
OUT-
Figure 11. Electrical Idle Mode Exit and Entry Delay
80%
20%
tr
tf
Figure 12. Output Rise and Fall Times
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Parameter Measurement Information (continued)
TDCI_CLK_PD
TDCI_CLK_PD
RX1N
or
RX2N
VIH_MIN
VIH_MAX
VOH_MIN
DCI_CLK
VOL_MAX
Figure 13. DCI Clock Propagation Delay
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8 Detailed Description
8.1 Overview
The TUSB1042I is a USB Type-C redriving switch supporting data rates up to 10 Gbps. This device utilizes 5th
generation USB redriver technology.
The TUSB1042I provides several levels of receive equalization to compensate for inter-symbol interference (ISI)
due to cable and board trace loss when USB 3.1 Gen1/Gen2 signals travel across a PCB or cable. This device
requires a 3.3-V power supply. It comes in the industrial temperature range.
For a host or device application the TUSB1042I enables the system to pass both transmitter compliance and
receiver jitter tolerance tests for USB 3.1 Gen1/Gen2. The re-driver recovers incoming data by applying
equalization that compensates for channel loss, and drives out signals with a high differential voltage. Each
channel has a receiver equalizer with selectable gain settings. The equalization should be set based on the
amount of insertion loss before or after the TUSB1042I receivers. Independent equalization control for each
channel can be set using EQ[1:0] and SSEQ[1:0] pins.
The TUSB1042I advanced state machine makes it transparent to hosts and devices. After power up, the
TUSB1042I. periodically performs receiver detection on the TX pairs. If it detects a USB 3.1 Gen1/Gen2 receiver,
the RX termination is enabled, and the TUSB1042I is ready to re-drive.
The device ultra-low-power architecture operates at a 3.3-V power supply and achieves enhanced performance.
The automatic LFPS de-emphasis control further enables the system to be USB3.1 compliant.
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8.2 Functional Block Diagram
SSRXn
Driver
RX2p
Term
SSRXp
Detect
Term
EQ
Term
EQ_SEL
Driver
RX2n
SSEQ_SEL
SSTXn
EQ
Term
Detect
Term
SSTXp
Driver
TX2p
TX2n
RSVD1
Term
Detect
MUX
RSVD2
Driver
RSVD3
TX1n
TX1p
RSVD4
Term
RX1n
RSVD5
Driver
RX1p
RSVD6
EQ
RSVD8
RSVD9
Term
RSVD7
EQ_SEL
RSVD10
RSVD11
RSVD12
TEST2
SSEQ_SEL
A1
SSEQ[1:0]/A0
I2C_EN
FLIP/SCL
CTL0/SDA
EQ_SEL
EQ[1:0]
I2C
Slave
FSM, Control Logic and
Registers
DCI_CLK
TEST1
DCI_DAT
VCC
VREG
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8.3 Feature Description
8.3.1 USB 3.1
The TUSB1042I supports USB 3.1 Gen1/Gen2 data rates up to 10 Gbps. The TUSB1042I supports all the USB
defined power states (U0, U1, U2, and U3). Because the TUSB1042I is a linear redriver, it can’t decode USB3.1
physical layer traffic. The TUSB1042I monitors the actual physical layer conditions like receiver termination,
electrical idle, LFPS, and SuperSpeed signaling rate to determine the USB power state of the USB 3.1 interface.
The TUSB1042I features an intelligent low frequency periodic signaling (LFPS) detector. The LFPS detector
automatically senses the low frequency signals and disables receiver equalization functionality. When not
receiving LFPS, the TUSB1042I will enable receiver equalization based on the EQ[1:0] and SSEQ[1:0] pins or
values programmed into EQ1_SEL, EQ2_SEL, and SSEQ_SEL registers.
8.3.2 4-level Inputs
The TUSB1042I has (I2C_EN, EQ[1:0], and SSEQ[1:0]) 4-level inputs pins that are used to control the
equalization gain and place TUSB1042I into different modes of operation. These 4-level inputs utilize a resistor
divider to help set the 4 valid levels and provide a wider range of control settings. There is an internal 30 kΩ pullup and a 94 kΩ pull-down. These resistors, together with the external resistor connection combine to achieve the
desired voltage level.
Table 1. 4-Level Control Pin Settings
LEVEL
SETTINGS
0
Option 1: Tie 1 KΩ 5% to GND.
Option 2: Tie directly to GND.
R
Tie 20 KΩ 5% to GND.
F
Float (leave pin open)
1
Option 1: Tie 1 KΩ 5%to VCC.
Option 2: Tie directly to VCC.
NOTE
All four-level inputs are latched on rising edge of internal reset. After tcfg_hd, the internal
pull-up and pull-down resistors will be isolated in order to save power.
8.3.3 Receiver Linear Equalization
The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in
the system before the input or after the output of the TUSB1042I. The receiver overcomes these losses by
attenuating the low frequency components of the signals with respect to the high frequency components. The
proper gain setting should be selected to match the channel insertion loss. Two 4-level input pins enable up to 16
possible equalization settings. USB3.1 upstream path and USB3.1 downstream path each have their own two 4level inputs. The TUSB1042I also provides the flexibility of adjusting settings through I2C registers.
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8.4 Device Functional Modes
8.4.1 Device Configuration in GPIO Mode
The TUSB1042I is in GPIO configuration when I2C_EN = “0”. The TUSB1042I supports USB 3.1 operation. The
TEST1 pin needs to be pulled down to GND. CTL0 pins enables or disables USB 3.1 operation as detailed in
Table 2.
After power-up (VCC from 0 V to 3.3 V), the TUSB1042I defaults to USB3.1 mode. The USB PD controller upon
detecting no device attached to Type-C port or USB3.1 operation not required by attached device must take
TUSB1042I out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.
Table 2. GPIO Configuration Control
CTL0 PIN
FLIP PIN
TUSB1042I CONFIGURATION
L
L
Power Down
L
H
Power Down
H
L
One Port USB 3.1 - No Flip
H
H
One Port USB 3.1 – With Flip
Table 3 Details the TUSB1042I’s mux routing. This table is valid for both I2C and GPIO configuration modes.
Table 3. INPUT to OUTPUT Mapping
FROM
TO
INPUT PIN
OUTPUT PIN
NA
NA
CTL0 PIN
FLIP PIN
L
L
L
H
NA
NA
RX1P
SSRXP
RX1N
SSRXN
H
L
H
H
SSTXP
TX1P
SSTXN
TX1N
RX2P
SSRXP
RX2N
SSRXN
SSTXP
TX2P
SSTXN
TX2P
8.4.2 Device Configuration In I2C Mode
The TUSB1042I is in I2C mode when I2C_EN is not equal to “0”. The same configurations defined in GPIO mode
are also available in I2C mode. The TUSB1042I USB3.1 configuration is controlled based on Table 4.
Table 4. I2C Configuration Control
REGISTERS
TUSB1042I CONFIGURATION
CTLSEL1
CTLSEL0
FLIPSEL
0
0
0
0
0
1
Power Down
0
1
0
USB 3.1 - No Flip
0
1
1
USB 3.1 – With Flip
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Power Down
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8.4.3 Linear EQ Configuration
Each of the TUSB1042I receiver lanes has individual controls for receiver equalization. The receiver equalization
gain value can be controlled either through I2C registers or through GPIOs. Table 5 details the gain value for
each available combination when TUSB1042I is in GPIO mode. These same options are also available in I2C
mode by updating registers EQ1_SEL, EQ2_SEL, and SSEQ_SEL.
Table 5. TUSB1042I Receiver Equalization GPIO Control
USB3.1 DOWNSTREAM FACING PORTS
Equalization Setting #
EQ1 PIN LEVEL
USB 3.1 UPSTREAM FACING PORT
EQ0 PIN LEVEL
EQ GAIN at 5 GHz
(dB)
SSEQ1 PIN LEVEL
SSEQ0 PIN LEVEL
EQ GAIN at 5 GHz (dB)
0
0
0
-3.9
0
0
-1.8
1
0
R
-1.7
0
R
0.2
2
0
F
-0.1
0
F
1.7
3
0
1
1.4
0
1
3.2
4
R
0
2.4
R
0
4.2
5
R
R
3.5
R
R
5.3
6
R
F
4.4
R
F
6.1
7
R
1
5.2
R
1
7.0
8
F
0
5.9
F
0
7.7
9
F
R
6.6
F
R
8.3
10
F
F
7.1
F
F
8.8
11
F
1
7.6
F
1
9.3
12
1
0
8.0
1
0
9.7
13
1
R
8.5
1
R
10.1
14
1
F
8.8
1
F
10.4
15
1
1
9.2
1
1
10.8
8.4.4 USB3.1 Modes
The TUSB1042I monitors the physical layer conditions like receiver termination, electrical idle, LFPS, and
SuperSpeed signaling rate to determine the state of the USB3.1 interface. Depending on the state of the USB
3.1 interface, the TUSB1042I can be in one of four primary modes of operation when USB 3.1 is enabled (CTL0
= H or CTLSEL0 = 1b1): Disconnect, U2/U3, U1, and U0.
The Disconnect mode is the state in which TUSB1042I has not detected far-end termination on both upstream
facing port (UFP) or downstream facing port (DFP). The disconnect mode is the lowest power mode of each of
the four modes. The TUSB1042I remains in this mode until far-end receiver termination has been detected on
both UFP and DFP. The TUSB1042I immediately exits this mode and enter U0 once far-end termination is
detected.
Once in U0 mode, the TUSB1042I will redrive all traffic received on UFP and DFP. U0 is the highest power mode
of all USB3.1 modes. The TUSB1042I remains in U0 mode until electrical idle occurs on both UFP and DFP.
Upon detecting electrical idle, the TUSB1042I immediately transitions to U1.
The U1 mode is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB1042I UFP
and DFP receiver termination remains enabled. The UFP and DFP transmitter DC common mode is maintained.
The power consumption in U1 is similar to power consumption of U0.
Next to the disconnect mode, the U2/U3 mode is next lowest power state. While in this mode, the TUSB1042I
periodically performs far-end receiver detection. Anytime the far-end receiver termination is not detected on
either UFP or DFP, the TUSB1042I leaves the U2/U3 mode and transitions to the Disconnect mode. It also
monitors for a valid LFPS. Upon detection of a valid LFPS, the TUSB1042I immediately transitions to the U0
mode. In U2/U3 mode, the TUSB1042I receiver terminations remain enabled but the TX DC common mode
voltage is not maintained.
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8.4.5 Operation Timing – Power Up
Tctl_db
TUSB1042I
In I2C mode
USB3.1
FLIP = 0
DISABLED
TUSB1042I
In GPIO mode
DISABLED
USB3.1
FLIP = 0
Mode of operation
determined by value of
FLIPSEL bit and CTLSEL[1:0]
bits at offset 0x0A.
If (CTL0 == 1'b1 & FLIP == 0) {
USB3.1 no FLIP;
} ELSEIF (CTL0 == 1'b1 & FLIP == 1) {
USB3.1 with FLIP;
} ELSEIF (CTL0 == 1'b0 & FLIP == 0) {
USB3.1 disabled;
} ELSEIF (CTL0 == 1'b0 & FLIP == 1) {
USB3.1 disabled;
};
CTL0, TEST1 pins
FLIP pin
VCC (min)
VCC
Td_pg
Internal
Power
Good
T Cfg_su
TCfg_hd
CFG pins
Figure 14. Power-Up Timing
Table 6. Power-Up Timing (1) (2)
PARAMETER
MIN
MAX
UNIT
500
µs
td_pg
VCC (minimum) to Internal Power Good asserted high
tcfg_su
CFG(1) pins setup(2)
250
tcfg_hd
CFG(1) pins hold
10
tCTL_DB
TEST1, CTL0 and FLIP pin debounce
16
ms
tVCC_RAMP
VCC supply ramp requirement
100
ms
(1)
(2)
µs
µs
Following pins comprise CFG pins: I2C_EN, EQ[1:0], and SSEQ[1:0].
Recommend CFG pins are stable when VCC is at min.
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8.5 Programming
For further programmability, the TUSB1042I can be controlled using I2C. The SCL and SDA pins are used for I2C
clock and I2C data respectively.
Table 7. TUSB1042I I2C Target Address
A1
PIN LEVEL
SSEQ0/A0
PIN LEVEL
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (W/R)
0
0
1
0
0
0
1
0
0
0/1
0
R
1
0
0
0
1
0
1
0/1
0
F
1
0
0
0
1
1
0
0/1
0
1
1
0
0
0
1
1
1
0/1
R
0
0
1
0
0
0
0
0
0/1
R
R
0
1
0
0
0
0
1
0/1
R
F
0
1
0
0
0
1
0
0/1
R
1
0
1
0
0
0
1
1
0/1
F
0
0
0
1
0
0
0
0
0/1
F
R
0
0
1
0
0
0
1
0/1
F
F
0
0
1
0
0
1
0
0/1
F
1
0
0
1
0
0
1
1
0/1
1
0
0
0
0
1
1
0
0
0/1
1
R
0
0
0
1
1
0
1
0/1
1
F
0
0
0
1
1
1
0
0/1
1
1
0
0
0
1
1
1
1
0/1
The following procedure should be followed to write to TUSB1042I I2C registers:
1. The master initiates a write operation by generating a start condition (S), followed by the TUSB1042I 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB1042I acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TUSB1042I) to be written, consisting of one byte of
data, MSB-first.
4. The TUSB1042I acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The TUSB1042I acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the TUSB1042I.
8. The master terminates the write operation by generating a stop condition (P).
The following procedure should be followed to read the TUSB1042I I2C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the TUSB1042I 7-bit
address and a one-value “W/R” bit to indicate a read cycle.
2. The TUSB1042I acknowledges the address cycle.
3. The TUSB1042I transmit the contents of the memory registers MSB-first starting at register 00h or last read
sub-address+1. If a write to the T I2C register occurred prior to the read, then the TUSB1042I shall start at
the sub-address specified in the write.
4. The TUSB1042I shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master
after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the TUSB1042I transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
The following procedure should be followed for setting a starting sub-address for I2C reads:
1. The master initiates a write operation by generating a start condition (S), followed by the TUSB1042I 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB1042I acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TUSB1042I) to be written, consisting of one byte of
data, MSB-first.
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4. The TUSB1042I acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).
NOTE
If no sub-addressing is included for the read procedure, and reads start at register offset
00h and continue byte by byte through the registers until the I2C master terminates the
read operation. If a I2C address write occurred prior to the read, then the reads start at the
sub-address specified by the address write.
Table 8. Register Legend
ACCESS TAG
NAME
R
Read
The field may be read by software
W
Write
The field may be written by software
S
Set
C
Clear
U
Update
NA
No Access
MEANING
The field may be set by a write of one. Writes of zeros to the field have no effect.
The field may be cleared by a write of one. Write of zero to the field have no effect.
Hardware may autonomously update this field.
Not accessible or not applicable
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8.6 Register Maps
8.6.1 General Register (address = 0x0A) [reset = 00000001]
Figure 15. General Registers
7
Reserved
6
5
Reserved
R
R/W
4
EQ_OVERRID
E
R/W
3
Reserved
2
FLIPSEL
R/W
R/W
1
0
CTLSEL[1:0].
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. General Registers
Bit
Field
Type
Reset
Description
7:6
Reserved
R
00
Reserved.
5
Reserved
R
0
Reserved.
4
EQ_OVERRIDE
R/W
0
Setting of this field will allow software to use EQ settings from
registers instead of value sample from pins.
0 – EQ settings based on sampled state of the EQ pins
(SSEQ[1:0], EQ[1:0], and DPEQ[1:0]).
1 – EQ settings based on programmed value of each of the EQ
registers
3
Reserved
R
0
Reserved.
2
FLIPSEL
R/W
0
FLIPSEL. Refer to Table 4 for this field functionality.
01
00 –
01 –
10 –
11 –
1:0
CTLSEL[1:0].
R/W
Disabled. All RX and TX for USB3 are disabled.
USB3.1 enabled. (Default)
Reserved.
Reserved.
8.6.2 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
Figure 16. USB3.1 Control/Status Registers (0x20)
7
6
5
4
3
EQ2_SEL
R/W/U
2
1
0
EQ1_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. USB3.1 Control/Status Registers (0x20)
Bit
7:4
3:0
22
Field
EQ2_SEL
EQ1_SEL
Type
R/W/U
R/W/U
Reset
Description
0000
Field selects between 0 to 9 dB of EQ for USB3.1 RX2 receiver.
When EQ_OVERRIDE = 1’b0, this field reflects the sampled
state of EQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software
can change the EQ setting for USB3.1 RX2 receiver based on
value written to this field.
0000
Field selects between 0 to 9 dB of EQ for USB3.1 RX1 receiver.
When EQ_OVERRIDE = 1’b0, this field reflects the sampled
state of EQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software
can change the EQ setting for USB3.1 RX1 receiver based on
value written to this field.
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8.6.3 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
Figure 17. USB3.1 Control/Status Registers (0x21)
7
6
5
4
3
2
Reserved
R
1
0
SSEQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. USB3.1 Control/Status Registers (0x21)
Bit
Field
Type
Reset
Description
7:4
Reserved
R
0000
Reserved
0000
Field selects between 0 to 11 dB of EQ for USB3.1 SSTXP/N
receiver. When EQ_OVERRIDE = 1’b0, this field reflects the
sampled state of SSEQ[1:0] pins. When EQ_OVERRIDE = 1’b1,
software can change the EQ setting for USB3.1 SSTXP/N
receiver based on value written to this field.
3:0
SSEQ_SEL
R/W/U
8.6.4 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000100]
Figure 18. USB3.1 Control/Status Registers (0x22)
7
CM_ACTIVE
6
LFPS_EQ
R/U
R/W
5
U2U3_LFPS_D
EBOUNCE
R/W
4
DISABLE_U2U
3_RXDET
R/W
3
2
DFP_RXDET_INTERVAL
1
0
USB3_COMPLIANCE_CTRL
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. USB3.1 Control/Status Registers (0x22)
Bit
7
Field
Type
Reset
Description
CM_ACTIVE
R/U
0
0 –device not in USB 3.1 compliance mode. (Default)
1 –device in USB 3.1 compliance mode
6
LFPS_EQ
R/W
0
Controls whether settings of EQ based on EQ1_SEL, EQ2_SEL
and SSEQ_SEL applies to received LFPS signal.
0 – EQ set to zero when receiving LFPS (default)
1 – EQ set to EQ1_SEL, EQ2_SEL, and SSEQ_SEL when
receiving LFPS.
5
U2U3_LFPS_DEBOUNCE
R/W
0
0 – No debounce of LFPS before U2/U3 exit. (Default)
1 – 200 µs debounce of LFPS before U2/U3 exit.
4
DISABLE_U2U3_RXDET
R/W
0
0 – Rx.Detect in U2/U3 enabled. (Default)
1 – Rx.Detect in U2/U3 disabled.
01
This field controls the Rx.Detect interval for the Downstream
facing port (TX1P/N and TX2P/N).
00 – 8 ms
01 – 12 ms (default)
10 – 48 ms
11 – 96 ms
00
00 – FSM determined compliance mode. (Default)
01 – Compliance Mode enabled in DFP direction (SSTX ->
TX1/TX2)
10 – Compliance Mode enabled in UFP direction (RX1/RX2 ->
SSRX)
11 – Compliance Mode Disabled.
3:2
1:0
DFP_RXDET_INTERVAL
USB3_COMPLIANCE_CTRL
R/W
R/W
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TUSB1042I is a linear redriver switch designed specifically to compensate for intersymbol interference (ISI)
jitter caused by signal attenuation through a passive medium like PCB traces and cables. Because the
TUSB1042I has one upstream facing USB 3.1 Gen1/Gen2 input, and two downstream facing USB 3.1
Gen1/Gen2 inputs, it can be optimized to correct ISI on all those three inputs through 16 different equalization
choices. Placing the TUSB1042I between a USB3.1 Host and a USB3.1 Type-C receptacle can correct signal
integrity issues resulting in a more robust system.
9.2 Typical Application
A
B
F
E
PCB Trace of Length XAB
PCB Trace of Length XEF
RX2P
RX2N
TX2P
TX2N
SSRXP
SSTXP
Type-C
Receptacle
SSRXN
USB3.1
Host
TUSB1042I
SSTXN
TX1N
TX1P
RX1N
RX1P
Copyright © 2017, Texas Instruments Incorporated
Figure 19. TUSB1042I in a Host Application
24
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters shown in Table 13.
Table 13. Design Parameters
PARAMETER
VALUE
A to B PCB trace length, XAB
12 inches
E to F PCB trace length, XEF
2 inches
PCB trace width
4 mils
AC-coupling capacitor (75 nF to 265 nF)
100 nF
VCC supply (3 V to 3.6 V)
3.3 V
I2C Mode or GPIO Mode
I2C Mode. (I2C_EN pin != "0")
1.8V or 3.3V I2C Interface
3.3V I2C. Pull-up the I2C_EN pin to 3.3V with a 1K
ohm resistor.
9.2.2 Detailed Design Procedure
A typical usage of the TUSB1042I device is shown in Figure 20. The device can be controlled either through its
GPIO pins or through its I2C interface. In the example shown below, a Type-C PD controller is used to configure
the device through the I2C interface. When configured for I2C mode, pins 29 (DCI_DAT) and 32 (DCI_CLK) can
be used for the DCI interface. In I2C mode, the equalization settings for each receiver can be independently
controlled through I2C registers. For this reason, all of the equalization pins (EQ[1:0] and SSEQ[1:0]) can be left
unconnected. If these pins are left unconnected, the TUSB1042I 7-bit I2C slave address will be 0x12 because
both A1 and SSEQ0/A0 will be at pin level "F". If a different I2C slave address is desired, A1 and SSEQ0/A0 pins
should be set to a level which produces the desired I2C slave address.
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3.3V
10PF
100nF
100nF
SSRXP
RX2P
SSRXN
RX2N
100nF
SSRXN
SSTXP
USB Type-C
Receptacle
100nF
100nF
SSTXP
TX2P
SSTXN
TX2N
100nF
SSTXN
100nF
VCC
VCC
VCC
100nF
SSRXP
VCC
USB 3.1 Host
100nF
100nF
22O
RSVD1
DCI_CLK
22O
DCI_DAT
RSVD2
To PCH DCI
» Clock
Input
To PCH DCI
» DATA
Input
RSVD3
A12
GND
A11
RXP2
A10
RXN2
A9
VBUS
A8
SBU1
TEST2
RSVD4
RSVD6
RSVD7
TUSB1042I
RSVD5
A7
DN1
A6
DP1
A5
CC1
A4
VBUS
A3
TXN1
A2
TXP1
A1
GND
RSVD8
100 nF
RSVD9
TX1N
B1
GND
B2
TXP2
B3
TXN2
B4
VBUS
B5
CC2
B6
DP2
B7
DN2
B8
SBU2
B9
VBUS
B10
RXN1
B11
RXP1
B12
GND
100 nF
TX1P
RSVD10
RX1N
RSVD11
RX1P
3.3V
RSVD12
I2C_EN
3.3V
3.3V
SSEQ0/A0
VI2C
SSEQ1
R
R
A1
FLIP/SCL
3.3V
3.3V
3.3V
EQ0
CTL0/SDA
EQ1
TEST1
Type-C
PD
Controller
TP
Copyright © 2017, Texas Instruments Incorporated
Figure 20. Application Circuit
26
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9.2.3 Application Curve
0
-5
-10
Insertion Loss (dB)
-15
-20
-25
-30
-35
Length=12in, Width=6mil
Length=16in, Width=6mil
Length=20in, Width=6mil
Length=24in, Width=6mil
Length=4in, Width=4mil
Length=8in, Width=10mil
Length=8in, Width=6mil
-40
-45
-50
-55
-60
0
2
4
6
8
10
Frequency (GHz)
12
14
16
D009
Figure 21. Insertion Loss of FR4 PCB Traces
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9.3 System Examples
9.3.1 USB 3.1
The TUSB1042I is in USB3.1 mode when the CTL0 pin is high.
D+/-
USB Host
SSTX
D+/-
1 Port USB
TUSB1042I
TUSB1042I
SSRX
SSRX
USB Hub
SSTX
TX2
RX1
TX1
RX1
FLIP
CTL0
PD Controller
Type-C Receptacle
TX1
Type-C Receptacle
RX2
RX2
TX2
FLIP
CC1
CC1
CC2
CC2
CTL0/FLIP=H/L
CTL0
PD Controller
CTL0/FLIP=H/L
Copyright © 2017, Texas Instruments Incorporated
Figure 22. USB3.1 – No Flip (CTL0 = H, FLIP = L)
28
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System Examples (continued)
D+/-
USB Host
SSTX
D+/-
1 Port USB
TUSB1042I
TUSB1042I
SSRX
USB Hub
SSTX
SSRX
TX2
RX1
TX1
RX1
FLIP
Type-C Receptacle
TX1
Type-C Receptacle
RX2
RX2
TX2
FLIP
CTL0
PD Controller
CC1
CC1
CC2
CC2
CTL0
PD Controller
CTL0/FLIP=H/H
CTL0/FLIP=H/H
Copyright © 2017, Texas Instruments Incorporated
Figure 23. USB3.1 – With Flip (CTL0 = H, FLIP = H)
10 Power Supply Recommendations
The TUSB1042I is designed to operate with a 3.3-V power supply. Levels above those listed in the Absolute
Maximum Ratings table should not be used. If using a higher voltage system power supply, a voltage regulator
can be used to step down to 3.3 V. Decoupling capacitors should be used to reduce noise and improve power
supply integrity. A 0.1-µF capacitor should be used on each power pin.
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11 Layout
11.1 Layout Guidelines
1.
2.
3.
4.
5.
6.
RXP/N and TXP/N pairs should be routed with controlled 90-Ω differential impedance (±15%).
Keep away from other high speed signals.
Intra-pair routing should be kept to within 2 mils.
Length matching should be near the location of mismatch.
Each pair should be separated at least by 3 times the signal trace width.
The use of bends in differential traces should be kept to a minimum. When bends are used, the number of
left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This
will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on
EMI.
7. Route all differential pairs on the same of layer.
8. The number of vias should be kept to a minimum. It is recommended to keep the vias count to 2 or less.
9. Keep traces on layers adjacent to ground plane.
10. Do not route differential pairs over any plane split.
11. Adding Test points will cause impedance discontinuity, and therefore, negatively impact signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes a stub on the differential pair.
11.2 Layout Example
AC Coupling
capacitors
SSRX
SSTX
To USB Host
DTX2
GND
DTX1
To USB Type-C
Receptacle
DRX2
DRX1
Figure 24. Layout Example
30
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 14. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TUSB1042I
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
USB Type-C is a trademark of USB Implementers Forum.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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9-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TUSB1042IRNQR
ACTIVE
WQFN
RNQ
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
T1042
TUSB1042IRNQT
ACTIVE
WQFN
RNQ
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
T1042
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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9-May-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TUSB1042IRNQR
WQFN
RNQ
40
3000
330.0
12.4
4.3
6.3
1.1
8.0
12.0
Q2
TUSB1042IRNQT
WQFN
RNQ
40
250
180.0
12.4
4.3
6.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-May-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TUSB1042IRNQR
WQFN
RNQ
40
3000
367.0
367.0
35.0
TUSB1042IRNQT
WQFN
RNQ
40
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RNQ0040A
WQFN - 0.8 mm max height
SCALE 2.500
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
A
B
PIN 1 INDEX AREA
4.1
3.9
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08
4.7±0.1
2X 4.4
(0.2) TYP
9
36X 0.4
20
8
EXPOSED
THERMAL PAD
21
2X
2.8
2.7±0.1
1
PIN 1 ID
(OPTIONAL)
28
29
40
40X
0.5
0.3
0.25
0.15
0.1
C A
0.05
40X
B
4222125/B 01/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.7)
2X (2.1)
6X (0.75)
40
29
40X (0.6)
1
28
40X (0.2)
4X
(1.1)
SYMM
(3.8)
(2.7)
36X (0.4)
8
21
(R0.05) TYP
9
20
SYMM
( 0.2) TYP
VIA
(5.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222125/B 01/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (1.5)
40
29
40X (0.6)
1
28
40X (0.2)
6X
(0.695)
SYMM
(3.8)
6X
(1.19)
36X (0.4)
8
21
(R0.05) TYP
METAL
TYP
9
6X (1.3)
20
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
73% PRINTED SOLDER COVERAGE BY AREA
SCALE:18X
4222125/B 01/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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