Texas Instruments | THVD14xx 3.3-V to 5-V RS-485 Transceivers with ±18-kV IEC ESD Protection (Rev. E) | Datasheet | Texas Instruments THVD14xx 3.3-V to 5-V RS-485 Transceivers with ±18-kV IEC ESD Protection (Rev. E) Datasheet

Texas Instruments THVD14xx 3.3-V to 5-V RS-485 Transceivers with ±18-kV IEC ESD Protection (Rev. E) Datasheet
Product
Folder
Order
Now
Technical
Documents
Support &
Community
Tools &
Software
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
THVD14xx 3.3-V to 5-V RS-485 Transceivers with ±18-kV IEC ESD Protection
1 Features
•
1
•
•
•
•
•
•
•
•
•
•
•
•
Meets or Exceeds the Requirements of the
TIA/EIA-485A Standard
3 V to 5.5 V Supply Voltage
Differential Output Exceeds 2.1 V for PROFIBUS
Compatibility with 5-V Supply
Bus I/O ESD Protection
– ±30 kV HBM
– ±18 kV IEC 61000-4-2 Contact Discharge
– ±25 kV IEC 61000-4-2 Air-Gap Discharge
– ±4 kV IEC 61000-4-4 Fast Transient Burst
Extended Operational Common-mode
Range: ±15 V
Low EMI 500 kbps and 50 Mbps Data Rates
Large Receiver Hysteresis for Noise Rejection
Low Power Consumption
– Standby Supply Current: < 1 µA
– Current During Operation: < 3 mA
Extended Ambient Temperature
Range: –40°C to 125°C
Glitch-Free Power-Up/Down for Hot Plug-in
Capability
Open, Short, and Idle Bus Failsafe
1/8 Unit Load (Up to 256 Bus Nodes)
Small-Size VSON and VSSOP Packages Save
Board Space or SOIC for Drop-in Compatibility
Each of these devices operates from a single supply
between 3 V and 5.5 V. The devices in this family
feature an extended common-mode voltage range
which makes them suitable for multi-point
applications over long cable runs.
THVD14xx family of devices is available in small
VSON and VSSOP packages for space constrained
applications. These devices are characterized over
ambient free-air temperatures from –40°C to 125°C.
Device Information(1)
PART NUMBER
PACKAGE
THVD1410
THVD1450
THVD1451
THVD1452
BODY SIZE (NOM)
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.91 mm
VSON (8)
3.00 mm × 3.00 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.91 mm
VSON (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (10)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
THVD1410 and THVD1450 Simplified Schematic
R
RE
DE
D
1
2
7
3
6
B
A
4
2 Applications
•
•
•
•
•
•
•
•
Motor Drives
Factory Automation & Control
Grid Infrastructure
Building Automation
HVAC Systems
Video Surveillance
Process Analytics
Wireless Infrastructure
3 Description
THVD14xx is a family of noise-immune RS-485/RS422 transceivers designed to operate in rugged
industrial environments. The bus pins of these
devices are robust to high levels of IEC electrical fast
transients (EFT) and IEC electrostatic discharge
(ESD) events, eliminating the need for additional
system level protection components.
THVD1451 Simplified Schematic
R
D
2
8
A
7
B
3
6
Z
5
Y
THVD1452 Simplified Schematic
R
RE
DE
D
2 (1)
3 (2)
(9 ) 12
A
(8 ) 11
B
4 (3)
5 (4)
(7 ) 10
Z
(6) 9
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
8
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Absolute Maximum Ratings ...................................... 8
ESD Ratings.............................................................. 8
ESD Ratings [IEC] .................................................... 8
Recommended Operating Conditions....................... 9
Thermal Information .................................................. 9
Power Dissipation ..................................................... 9
Electrical Characteristics......................................... 10
Switching Characteristics ........................................ 11
Typical Characteristics: All Devices ........................ 12
Typical Characteristics: THD1450, THVD1451 and
THVD1452 ............................................................... 14
7.11 Typical Characteristics: THVD1410 ...................... 15
8
9
Parameter Measurement Information ................ 16
Detailed Description ............................................ 18
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
18
18
19
19
10 Application and Implementation........................ 22
10.1 Application Information...................................... 22
10.2 Typical Application ............................................... 22
11 Power Supply Recommendations ..................... 28
12 Layout................................................................... 29
12.1 Layout Guidelines ................................................. 29
12.2 Layout Example .................................................... 29
13 Device and Documentation Support ................. 30
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
Device Support......................................................
Third-Party Products Disclaimer ...........................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
30
30
30
14 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
Changes from Revision D (March 2019) to Revision E
•
Page
Changed THVD1451 From: Product Preview To: Production data ....................................................................................... 1
Changes from Revision C (February 2019) to Revision D
•
Page
Changed THVD1410 From: Product Preview To: Production data ....................................................................................... 1
Changes from Revision B (December 2018) to Revision C
•
Page
Changed THVD1452 From: Product Preview To: Production data ....................................................................................... 1
Changes from Revision A (May 2018) to Revision B
Page
•
Added Feature: "Differential Output Exceeds 2.1 V..."........................................................................................................... 1
•
Changed Feature: ±18 kV IEC 61000-4-2 Air-Gap Discharge To: ±25 kV IEC 61000-4-2 Air-Gap Discharge ..................... 1
•
Added SOIC (8) package to THVD1451 ............................................................................................................................... 1
•
Added Thermal Pad to the THVD1450 DRB package ........................................................................................................... 5
•
Added Thermal Pad to the THVD1451 DRB package ........................................................................................................... 6
•
Changed all pins HBM ESD rating from 4 kV to 8 kV ............................................................................................................ 8
•
Changed IEC ESD air-gap discharge rating from 18 kV to 25 kV.......................................................................................... 8
•
Changed THVD1410 power dissipation numbers .................................................................................................................. 9
•
Changed THVD1410 driver tr, tf TYP from 400 ns to 460 ns and MAX from 600 ns to 680 ns ........................................... 11
•
Changed THVD1410 receiver tr, tf TYP from 13 ns to 10 ns................................................................................................ 11
•
Changed THVD1410 receiver tPHL, tPLH TYP from 60 ns to 35 ns ....................................................................................... 11
•
Added Typical Characteristics, THD1450D .......................................................................................................................... 14
2
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3E – MAY 2018 – REVISED MAY 2019
•
Added condition to Figure 8 to Figure 3 ............................................................................................................................... 14
•
Added Typical Characteristics, THD1410............................................................................................................................. 15
•
Changed A to A/Y and B to B/Z in Figure 20 to Figure 24................................................................................................... 16
•
Added 3rd paragraph to the Overview section ..................................................................................................................... 18
Changes from Original (November 2017) to Revision A
•
Page
Changed the document status From: Advanced Information To: Production Mix data ......................................................... 1
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
3
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
www.ti.com
5 Device Comparison Table
4
PART NUMBER
DUPLEX
ENABLES
SIGNALING RATE
THVD1410
Half
DE, RE
up to 500 kbps
THVD1450
Half
DE, RE
THVD1451
Full
None
THVD1452
Full
DE, RE
Submit Documentation Feedback
up to 50 Mbps
NODES
256
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3E – MAY 2018 – REVISED MAY 2019
6 Pin Configuration and Functions
THVD1410, THVD1450 Devices
8-Pin D Package (SOIC)
Top View
THVD1410, THVD1450 Devices
8-Pin DGK Package (VSSOP)
Top View
R
1
8
VCC
RE
2
7
B
DE
3
6
A
D
4
5
GND
R
1
8
VCC
RE
2
7
B
DE
3
6
A
D
4
5
GND
Not to scale
Not to scale
THVD1450 Device
8-Pin DRB Package (VSON)
Top View
R
1
RE
2
DE
3
D
4
Th ermal
Pad
8
VCC
7
B
6
A
5
GND
No t to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
D
DGK
DRB
A
6
6
6
Bus input/output
Bus I/O port, A (complementary to B)
B
7
7
7
Bus input/output
Bus I/O port, B (complementary to A)
D
4
4
4
Digital input
Driver data input
DE
3
3
3
Digital input
Driver enable, active high (2-MΩ internal pull-down)
GND
5
5
5
Ground
R
1
1
1
Digital output
Receive data output
VCC
8
8
8
Power
3.3-V to 5-V supply
RE
2
2
2
Digital input
Thermal
Pad
—
—
I/O
Copyright © 2018–2019, Texas Instruments Incorporated
Device ground
Receiver enable, active low (2-MΩ internal pull-up)
No electrical connection. Should be connected to GND for optimal
thermal performance.
Submit Documentation Feedback
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
5
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
www.ti.com
THVD1451 Device
8-Pin D Package (SOIC)
Top View
THVD1451 Device
8-Pin DRB Package (VSON)
Top View
VCC
1
8
A
R
2
7
B
VCC
1
D
3
6
Z
R
2
GND
4
5
Y
D
3
GND
4
Th ermal
Pad
8
A
7
B
6
Z
5
Y
No t to scale
No t to scale
Pin Functions
PIN
I/O
Description
NAME
D
DRB
A
8
8
Bus input
Bus input, A (complementary to B)
B
7
7
Bus input
Bus input, B (complementary to A)
D
3
3
GND
4
4
Ground
Device ground
Digital
output
Receive data output
3.3-V to 5-V supply
Digital input Driver data input
R
2
2
VCC
1
1
Power
Y
5
5
Bus output
Digital bus output, Y (Complementary to Z)
Z
6
6
Bus output
Digital bus output, Z (Complementary to Y)
Thermal
Pad
—
6
I/O
Submit Documentation Feedback
No electrical connection. Should be connected to GND for optimal thermal
performance.
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3E – MAY 2018 – REVISED MAY 2019
THVD1452 Device
14-Pin D Package (SOIC)
Top View
THVD1452 Device
10-Pin DGS Package (VSSOP)
Top View
NC
1
14
VCC
R
2
13
VCC
RE
3
12
A
DE
4
11
B
D
5
10
Z
GND
6
9
Y
GND
7
8
NC
R
1
10
VCC
RE
2
9
A
DE
3
8
B
D
4
7
Z
GND
5
6
Y
Not to scale
Not to scale
NC – No internal connection
Pin Functions
PIN
I/O
DESCRIPTION
NAME
D
DGS
A
12
9
Bus input
Bus input, A (complementary to B)
B
11
8
Bus input
Bus input, B (complementary to A)
D
5
4
Digital input
Driver data input
DE
4
3
Digital input
Driver enable, active high (2-MΩ internal pull-down)
6, 7 (1)
5
Ground
1, 8
—
—
2
1
Digital output
Receive data output
13, 14 (1)
10
Power
3.3-V to 5-V supply
Y
9
6
Bus output
Digital bus output, Y (Complementary to Z)
Z
10
7
Bus output
Digital bus output, Z (Complementary to Y)
RE
3
2
Digital input
Receiver enable, active low (2-MΩ internal pull-up)
GND
NC
R
VCC
(1)
Device ground
Internally not connected
These pins are internally connected
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
7
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Supply voltage
VCC
-0.5
7
V
Bus voltage
Range at any bus pin (A, B, Y, or Z) as differential
or common-mode with respect to GND
-18
18
V
Input voltage
Range at any logic pin (D, DE, or RE)
-0.3
5.7
V
Receiver output
current
IO
-24
24
mA
-65
150
℃
Storage temperature range
(1)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Bus pins and
GND
±30
kV
All other pins
±8
kV
Charged device model (CDM), per
JEDEC JESD22-C101 (2)
All pins
±1.5
kV
Machine model (MM), per JEDEC
JESD22-A115-A
All pins
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 ESD Ratings [IEC]
V(ESD)
V(EFT)
8
Electrostatic discharge
Electrical fast transient
Submit Documentation Feedback
VALUE
UNIT
Bus pins and
GND
±18
kV
Air-gap discharge, per IEC 61000-4- Bus pins and
2
GND
±25
kV
Bus pins and
GND
±4
kV
Contact discharge, per IEC 610004-2
Per IEC 61000-4-4
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3E – MAY 2018 – REVISED MAY 2019
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
Supply voltage
VI
Input voltage at any bus terminal (1)
NOM
MAX
UNIT
3
5.5
V
-15
15
V
VIH
High-level input voltage (driver, driver
enable, and receiver enable inputs)
2
VCC
V
VIL
Low-level input voltage (driver, driver
enable, and receiver enable inputs)
0
0.8
V
VID
Differential input voltage
-15
15
V
IO
Output current, driver
-60
60
mA
IOR
Output current, receiver
-8
8
mA
RL
Differential load resistance
54
1/tUI
Signaling rate: THVD1410
1/tUI
Signaling rate: THVD1450, THVD1451,
THVD1452
TA
Operating ambient temperature
TJ
Junction temperature
(1)
Ω
500
kbps
50
Mbps
-40
125
℃
-40
150
℃
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
7.5 Thermal Information
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal
resistance
THVD1410
THVD1450
THVD1451
THVD1452
THVD1410
THVD1450
THVD1452
THVD1450
THVD1451
D (SOIC)
D (SOIC)
DGK (VSSOP)
DGS (VSSOP)
DRB (VSON)
8 PINS
14 PINS
8 PINS
10 PINS
8 PINS
114.3
86.4
155.2
155.6
48.6
°C/W
56.7
43.7
47.2
49.3
49.1
°C/W
RθJC(to Junction-to-case (top) thermal
resistance
p)
UNIT
RθJB
Junction-to-board thermal
resistance
57.7
42.5
76.1
77.1
21.1
°C/W
ΨJT
Junction-to-top characterization
parameter
12.8
10.2
3.9
4.5
0.8
°C/W
ΨJB
Junction-to-board
characterization parameter
57
42.2
74.8
75.7
21.1
°C/W
RθJC(b
Junction-to-case (bottom)
thermal resistance
N/A
N/A
N/A
N/A
2.7
°C/W
ot)
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Power Dissipation
PARAMETE
R
PD
Description
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver and receiver enabled, VCC = 5.5 Unterminated: RL = 300 Ω, CL = 50 pF
V, TA = 1250C, 50% duty cycle square
RS-422 load: RL = 100 Ω, CL = 50 pF
wave at 500kbps signaling rate,
RS-485 load: RL = 54 Ω, CL = 50 pF
THVD1410
360
mW
370
mW
410
mW
Driver and receiver enabled, VCC = 5.5 Unterminated: RL = 300 Ω, CL = 50 pF
V, TA = 1250C, 50% duty cycle square
RS-422 load: RL = 100 Ω, CL = 50 pF
wave at 50Mbps signaling rate,
RS-485 load: RL = 54 Ω, CL = 50 pF
THVD145x devices
360
mW
320
mW
330
mW
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
9
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
www.ti.com
7.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted). All typical values are at 25°C and supply voltage of VCC =
5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
RL = 60 Ω, -15 V ≤ Vtest ≤ 15 V (See
Figure 20) (1)
1.5
3.5
RL = 60 Ω, -15 V ≤ Vtest ≤ 15 V, 4.5 V ≤ VCC ≤
5.5 V, (See Figure 20)
2.1
MAX
UNIT
Driver
Driver differential output voltage
magnitude
|VOD|
RL = 100 Ω (See Figure 21)
RL = 54 Ω (See Figure 21)
Δ|VOD|
Change in differential output
voltage
VOC
Common-mode output voltage
ΔVOC(SS)
Change in steady-state commonmode output voltage
IOS
Short-circuit output current
V
2
4
V
1.5
3.5
V
-200
RL = 54 Ω (See Figure 21)
1
DE = VCC, -7 V ≤ VO ≤ 12 V
V
200
VCC/2
3
mV
V
-200
200
mV
-250
250
mA
125
µA
Receiver
DE = 0 V, VCC = 0 V or 5.5 V
II
Bus input current
DE = 0 V, VCC = 0 V or 5.5 V
VTH+
Positive-going input threshold
voltage
VTH-
Negative-going input threshold
voltage
VHYS
Input hysteresis
VI = 12V
VI = -7V
50
-100
VI = 15V
VI = -15V
Over common-mode range of ± 15 V
-65
60
µA
125
-130
µA
See (2)
-100
-20
mV
-200
-130
See (2)
mV
VCC –
0.4
VCC –
0.2
30
VOH
Output high voltage
IOH = -8 mA
VOL
Output low voltage
IOL = 8 mA
IOZR
Output high-impedance current
VO = 0 V or VCC, RE = VCC
Input current (D, DE, RE)
3 V ≤ VCC ≤ 5.5 V, 0 V ≤ VIN ≤ VCC
µA
-200
0.2
mV
V
0.4
V
-1
1
µA
-6.2
6.2
µA
Logic
IIN
Device
ICC
TSD
(1)
(2)
10
Driver and receiver enabled
RE = 0 V ,
DE = VCC,
No load
2.4
3
mA
Driver enabled, receiver disabled
RE = VCC,
DE = VCC,
No load
2
2.5
mA
Driver disabled, receiver enabled
RE = 0 V,
DE = 0 V,
No load
700
960
µA
Driver and receiver disabled
RE = VCC,
DE = 0 V, D
= open, No
load
0.1
1
µA
Supply current (quiescent)
Thermal shutdown temperature
170
℃
|VOD| ≥ 1.4 V when TA > 85 ℃, Vtest < -7 V and VCC < 3.135 V.
Under any specific conditions, VTH+ is assured to be at least VHYS higher than VTH–.
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3E – MAY 2018 – REVISED MAY 2019
7.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted). All typical values are at 25°C and supply voltage of VCC =
5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
250
460
680
ns
250
500
ns
10
ns
80
200
ns
RE = 0 V, See Figure 23 and
Figure 24
100
600
ns
RE = VCC, See Figure 23 and
Figure 24
4
11
µs
10
20
ns
35
110
ns
7
ns
30
60
ns
DE = VCC, See Figure 26
60
140
ns
DE = 0 V, See Figure 27
6
14
µs
1
3
6
ns
3
10
Driver: THVD1410
tr, tf
Differential output rise/fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time
tPZH, tPZL
RL = 54 Ω, CL = 50 pF, See Figure 22
Enable time
Receiver: THVD1410
tr, tf
Output rise/fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time
CL = 15 pF, See Figure 25
tPZH(1), tPZL(1),
tPZH(2),
Enable time
tPZL(2),
Driver: THVD1450, THVD1451, THVD1452
tr, tf
Differential output rise/fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time
tPZH, tPZL
RL = 54 Ω, CL = 50 pF, See Figure 22
Enable time
20
ns
3.5
ns
15
25
ns
RE = 0 V, See Figure 23 and
Figure 24
20
50
ns
RE = VCC, See Figure 23 and
Figure 24
2.5
10
µs
2
6
ns
CL = 15 pF, See Figure 25
25
40
ns
Receiver: THVD1450, THVD1451, THVD1452
tr, tf
Output rise/fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time
tPZH(1), tPZL(1),
tPZH(2),
Enable time
tPZL(2),
Copyright © 2018–2019, Texas Instruments Incorporated
3.5
ns
14
28
ns
DE = VCC, See Figure 26
50
110
ns
DE = 0V, See Figure 27
4
14
µs
Submit Documentation Feedback
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
11
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
www.ti.com
7.9 Typical Characteristics: All Devices
6
VOL
VOH
5
VO Driver Output Voltage (V)
VO Driver Differential Output Voltage (V)
6
4
3
2
1
0
5
4
3
2
1
0
0
10
20
30 40 50 60 70 80
IO Driver Output Current (mA)
VCC = 5 V
90
100 110
0
10
20
30 40 50 60 70 80
IO Driver Output Current (mA)
D001
DE = VCC
D=0V
VCC = 5 V
Figure 1. Driver Output Voltage vs Driver Output Current
6
90
100 110
D002
DE = VCC
D=0V
Figure 2. Driver Differential Output voltage vs Driver Output
Current
6
5
5
4
4
3
3
2
2
1
VTH ( 7 V) 1
VTH (0 V)
VTH (12 V)
0
-170 -160 -150 -140 -130 -120 -110 -100 -90
-80
-70
VID Differential Input Voltage (mV)
VCC = 5 V
-60
VO Driver Output Voltage (V)
Receiver Output (V)
3.2
VOL
VOH
2.8
2.4
2
1.6
1.2
0.8
0.4
0
0
-50
0
D007
TA = 25°C
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
IO Driver Output Current (mA)
D101
VCC = 3.3 V
DE = VCC
D=0V
Figure 3. Receiver Output vs Input
Figure 4. Driver Output Voltage vs Driver Output Current
3.5
3
3
2.8
2.6
2.4
2.2
2
1.8
1.6
2.5
2
1.5
1
0.5
1.4
1.2
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
IO Driver Output Current (mA)
D102
VCC = 3.3 V
DE = VCC
D=0V
Figure 5. Driver Differential Output Voltage vs Driver Output
Current
12
VTH (12V)
VTH (0V)
VTH (-7V)
3.2
Receiver Output (V)
VO Driver Differential Output Voltage (V)
3.4
Submit Documentation Feedback
0
-180
-160
-140
-120
-100
-80
VID Differential Input Voltage (mV)
VCC = 3.3 V
-60
-40
D106
TA = 25°C
Figure 6. Receiver Output vs Input
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3E – MAY 2018 – REVISED MAY 2019
Typical Characteristics: All Devices (continued)
80
IO Driver Output Current (mA)
70
60
50
40
30
20
10
0
0
0.5
TA = 25°C
RL = 54 Ω
1
1.5
2 2.5 3 3.5 4 4.5
VCC Supply Voltage (V)
5
5.5
6
D003
DE = VCC
D = VCC
Figure 7. Driver Output Current vs Supply Voltage
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
13
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
www.ti.com
7
16
6
14
VO Driver Propagation Delay (ns)
VO Driver Rise and Fall Time (ns)
7.10 Typical Characteristics: THD1450, THVD1451 and THVD1452
5
4
3
2
1
0
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
12
10
8
6
4
2
0
-40
140
VCC = 5 V
Figure 8. Driver Rise or Fall Time vs Temperature
40
60
80
Temperature (qC)
100
120
140
D005
Figure 9. Driver Propagation Delay vs Temperature
VO Driver Rise and Fall Time (ns)
ICC Supply Current (mA)
20
4
100
80
60
40
20
0
5
10
15
20
25
30
35
SIgnaling Rate (Mbps)
RL = 54 Ω
40
45
3.8
3.6
3.4
3.2
3
2.8
-40
0
50
-20
0
D006
VCC = 5 V
TA = 25°C
20
40
60
80
Temperature (0C)
100
120
140
D103
VCC = 3.3 V
Figure 11. Driver Rise or Fall Time vs Temperature
Figure 10. Supply Current vs Signal Rate
17
85
16.5
82.5
80
16
ICC Supply Current (mA)
VO Driver Propagation Delay (ns)
0
VCC = 5 V
120
15.5
15
14.5
14
13.5
77.5
75
72.5
70
67.5
65
62.5
13
60
12.5
-40
57.5
-20
0
20
40
60
80
Temperature (0C)
100
120
140
0
5
10
D104
RL = 54 Ω
VCC = 3.3 V
Figure 12. Driver Propagation Delay vs Temperature
14
-20
D004
Submit Documentation Feedback
15
20
25
30
35
SIgnaling Rate (Mbps)
VCC = 3.3 V
40
45
50
D105
TA = 25°C
Figure 13. Supply Current vs Signal Rate
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3E – MAY 2018 – REVISED MAY 2019
600
276
580
273
VO Driver Propagation Delay (ns)
VO Driver Rise and Fall Time (ns)
7.11 Typical Characteristics: THVD1410
560
540
520
500
480
460
440
420
400
-40
-20
0
20
40
60
80
Temperature (0C)
100
120
270
267
264
261
258
255
252
249
246
-40
140
VCC = 5 V
Figure 14. Driver Rise or Fall Time vs Temperature
20
40
60
80
Temperature (0C)
100
120
140
D108
Figure 15. Driver Propagation Delay vs Temperature
550
V0 Driver Rise and Fall Time (ns)
100
ICC Supply Current (mA)
0
VCC = 5 V
105
95
90
85
80
75
525
500
475
450
425
400
375
350
325
70
50
100
150
200 250 300 350
Signaling Rate (kbps)
RL = 54 Ω
400
450
300
-40
500
-20
0
D109
VCC = 5 V
TA = 25°C
20
40
60
80
Temperature (0C)
100
120
140
D110
VCC = 3.3 V
Figure 16. Supply Current vs Signal Rate
Figure 17. Driver Rise or Fall Time vs Temperature
345
58
340
56
335
ICC Supply Current (mA)
VO Driver Propagation Delay (ns)
-20
D107
330
325
320
315
310
305
300
54
52
50
48
46
295
290
-40
-20
0
20
40
60
80
Temperature (0C)
100
120
140
44
50
100
150
D111
RL = 54 Ω
VCC = 3.3 V
Figure 18. Driver Propagation Delay vs Temperature
Copyright © 2018–2019, Texas Instruments Incorporated
200 250 300 350
Signaling Rate (kbps)
VCC = 3.3 V
400
450
500
D112
TA = 25°C
Figure 19. Supply Current vs Signal Rate
Submit Documentation Feedback
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
15
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
www.ti.com
8 Parameter Measurement Information
Vcc
375 Ÿ
DE
A/Y
D
VOD
0V or Vcc
R
Vtest
L
B/Z
375 Ÿ
Figure 20. Measurement of Driver Differential Output Voltage With Common-Mode Load
A/Y
VA
RL/2
A/Y
B/Z
D
VB
VOD
0V or Vcc
RL/2
B/Z
VOC(PP)
CL
ûVOC(SS)
VOC
VOC
Figure 21. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
Vcc
Vcc
50 %
V
I
DE
A/Y
0V
tPLH
D
VOD
R L=
54 Ÿ
tPHL
CL= 50 pF
~2 V
~
Input
Gen erator
VI
90 %
B/Z
50 Ÿ
50 %
V
OD
10 %
tr
~± 2 V
~
tf
Figure 22. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
A/Y
S1
D
V
Vcc
O
V
50 %
I
0V
B/Z
DE
Input
Gen erator
VI
CL =
RL =
50 pF
110 Ÿ
tPZH
V
90
50 Ÿ
OH
%
50 %
V
O
tPHZ
~
~ 0V
Figure 23. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down
Load
16
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3E – MAY 2018 – REVISED MAY 2019
Parameter Measurement Information (continued)
Vcc
Vcc
RL= 110 Ÿ
A/Y
50 %
VI
S1
0V
VO
D
B/Z
tPZL
tPLZ
DE
§ Vcc
VO
C L=
50 pF
Input
50%
VI
Gen erator
50Ÿ
10%
VOL
Figure 24. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
3V
A
Input
Generator
R VO
VI
50 Ÿ
1.5V
0V
50 %
VI
B
0V
tPLH
tPHL
VOH
90%
CL=15 pF
50%
RE
VOD
10 %
tr
VOL
tf
Figure 25. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
Vcc
Vcc
Vcc
VI
50 %
DE
0V or Vcc
0V
A
D
R
B
1 kŸ
VO
tPZH(1)
tPHZ
S1
VO
CL=15 pF
90 %
50 %
tPZL(1)
VI
D at Vcc
S1 to GND
§ 0V
RE
Input
Generator
VOH
50 Ÿ
tPLZ
VO
50 %
VCC D at 0V
S1 to Vcc
10 %
VOL
Figure 26. Measurement of Receiver Enable/Disable Times With Driver Enabled
Vcc
Vcc
VI
50%
0V
A
V or 1.5V
R
1.5 V or 0V
B
RE
VO
1 NŸ
tPZH(2)
S1
CL=15 pF
VOH
50%
VO
§ 0V
A at 1.5 V
B at 0 V
S1 to GND
tPZL(2)
Input
Generator
VI
VCC
50 Ÿ
VO
50%
VOL
A at 0V
B at 1.5V
S1 to VCC
Figure 27. Measurement of Receiver Enable Times With Driver Disabled
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
17
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
www.ti.com
9 Detailed Description
9.1 Overview
THVD1410 and THVD1450 are low-power, half duplex RS-485 transceivers available in two speed grades
suitable for data transmission up to 500 kbps and 50 Mbps respectively.
THVD1451 is fully enabled with no external enabling pins. THVD1452 has active-high driver enable and activelow receiver enable. A standby current of less than 1 µA can be achieved by disabling both driver and receiver.
THVD14xx family of devices have a higher typical differential output voltage (VOD) than traditional transceivers for
better noise immunity. A minimum differential output voltage of 2.1 V is specified with VCC voltage of 5 V ±10% to
meet the requirements of PROFIBUS applications.
9.2 Functional Block Diagrams
VCC
R
RE
A
DE
B
D
GND
Figure 28. THVD1410 and THVD1450
VCC
A
R
R
B
VCC
D
Z
D
Y
GND
Figure 29. THVD1451
VCC
A
R
R
B
RE
DE
D
Z
D
Y
GND
Figure 30. THVD1452
18
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3E – MAY 2018 – REVISED MAY 2019
9.3 Feature Description
Internal ESD protection circuits protect the transceiver against electrostatic discharges (ESD) according to IEC
61000-4-2 of up to ±18 kV and against electrical fast transients (EFT) according to IEC 61000-4-4 of up to ±4 kV.
With careful system design, one could achieve ±4 kV EFT Criterion A (no data loss when transient noise is
present).
The THVD14xx device family provides internal biasing of the receiver input thresholds in combination with large
input-threshold hysteresis. The receiver output remains logic high under a bus-idle or bus-short conditions
without the need for external failsafe biasing resistors. Device operation is specified over a wide ambient
temperature range from –40°C to 125°C.
9.4 Device Functional Modes
9.4.1 Device Functional Modes for THVD1410 and THVD1450
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as
VOD = VA – VB is positive. When D is low, the output states reverse: B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
Table 1. Driver Function Table for THVD1410 and THVD1450
INPUT
ENABLE
D
DE
A
OUTPUTS
B
H
H
H
L
Actively drive bus high
Actively drive bus low
FUNCTION
L
H
L
H
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drive bus high by default
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high.
When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+
and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not
actively driven (idle bus).
Table 2. Receiver Function Table for THVD1410 and THVD1450
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = VA – VB
RE
R
VTH+ < VID
L
H
Receive valid bus high
VTH- < VID < VTH+
L
?
Indeterminate bus state
VID < VTH-
L
L
Receive valid bus low
X
H
Z
Receiver disabled
FUNCTION
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
Fail-safe high output
Idle (terminated) bus
L
H
Fail-safe high output
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
19
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
www.ti.com
9.4.2 Device Functional Modes for THVD1451
For this device, the driver and receiver are fully enabled, thus the differential outputs Y and Z follow the logic
states at data input D at all times. A logic high at D causes Y to turn high and Z to turn low. In this case, the
differential output voltage defined as VOD = VY – VZ is positive. When D is low, the output states reverse: Z turns
high, Y becomes low, and VOD is negative. The D pin has an internal pull-up resistor to VCC, thus, when left
open while the driver is enabled, output Y turns high and Z turns low.
Table 3. Driver Function Table for THVD1451
INPUT
OUTPUTS
FUNCTIONS
D
Y
Z
H
H
L
L
L
H
Actively drive bus low
OPEN
H
L
Actively drive bus High by default
Actively drive bus high
When the differential input voltage defined as VID = VA – VB is higher than the positive input threshold, VTH+, the
receiver output, R, turns high. When VID is less than the negative input threshold, VTH–, the receiver output, R,
turns low. If VID is between VTH+ and VTH– the output is indeterminate. Internal biasing of the receiver inputs
causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus
lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).
Table 4. Receiver Function Table for THVD1451
20
DIFFERENTIAL INPUT
OUTPUT
VID = VA – VB
R
VTH+ < VID
H
Receive valid bus high
VTH- < VID < VTH+
?
Indeterminate bus state
FUNCTION
VID < VTH-
L
Receive valid bus low
Open-circuit bus
H
Fail-safe high output
Short-circuit bus
H
Fail-safe high output
Idle (terminated) bus
H
Fail-safe high output
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3E – MAY 2018 – REVISED MAY 2019
9.4.3 Device Functional Modes for THVD1452
When the driver enable pin, DE, is logic high, the differential outputs Y and Z follow the logic states at data input
D. A logic high at D causes Y to turn high and Z to turn low. In this case the differential output voltage defined as
VOD = VY – VZ is positive. When D is low, the output states reverse: Z turns high, Y becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
Y turns high and Z turns low.
Table 5. Driver Function Table for THVD1452
INPUT
ENABLE
OUTPUTS
D
DE
Y
H
H
H
L
Actively drive bus high
L
H
L
H
Actively drive bus low
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drive bus high by default
Z
FUNCTION
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high.
When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+
and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not
actively driven (idle bus).
Table 6. Receiver Function Table for THVD1452
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = VA – VB
RE
R
VTH+ < VID
L
H
Receive valid bus high
VTH- < VID < VTH+
L
?
Indeterminate bus state
Receive valid bus low
FUNCTION
VID < VTH-
L
L
X
H
Z
Receiver disabled
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
Fail-safe high output
Idle (terminated) bus
L
H
Fail-safe high output
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
21
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
www.ti.com
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The THVD14xx family consists of half-duplex and full-duplex RS-485 transceivers commonly used for
asynchronous data transmissions. For half-duplex devices, the driver and receiver enable pins allow for the
configuration of different operating modes. Full-duplex implementation requires two signal pairs (four wires), and
allows each node to transmit data on one pair while simultaneously receiving data on the other pair.
10.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, generally allows for higher data rates
over longer cable length.
R
R
R
A
RE
D
RT
B
DE
R
A
RT
D
A
R
B
A
R
D
R RE DE D
RE
B
DE
D
B
D
D
R RE DE D
Figure 31. Typical RS-485 Network With Half-Duplex Transceivers
Y
R
D
Z
A
RT
RT
B
R
R
DE
RE
Master
RE
D
Slave
B
R
A
DE
Z
RT
RT
A
B
Z
Y
D
D
Y
R Slave
D
R RE DE D
Figure 32. Typical RS-485 Network With Full-Duplex Transceivers
22
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3E – MAY 2018 – REVISED MAY 2019
Typical Application (continued)
10.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
10.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
short the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at
distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or
10%.
10000
Cable Length (ft)
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10 k
100 k
1M
10 M
100 M
Data Rate (bps)
Figure 33. Cable Length vs Data Rate Characteristic
Even higher data rates are achievable (that is, 50 Mbps for the THVD1450, THVD1451 and THVD1452) in cases
where the interconnect is short enough (or has suitably low attenuation at signal frequencies) to not degrade the
data.
10.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections of varying phase as the length of the stub increases. As a general guideline, the electrical length, or
round-trip delay, of a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum
physical stub length as shown in Equation 1.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
10.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to drive 32 unit loads (UL), where 1 unit load
represents a load impedance of approximately 12 kΩ. Because the THVD14xx family consists of 1/8 UL
transceivers, connecting up to 256 receivers to the bus is possible.
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
23
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
www.ti.com
Typical Application (continued)
10.2.1.4 Receiver Failsafe
The differential receivers of the THVD14xx family are failsafe to invalid bus states caused by the following:
• Open bus conditions, such as a disconnected connector
• Shorted bus conditions, such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic high state so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver
output must output a high when the differential input VID is more positive than 200 mV, and must output a Low
when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are
VTH+, VTH–, and VHYS (the separation between VTH+ and VTH–). As shown in the table, differential signals more
negative than –200 mV will always cause a low receiver output, and differential signals more positive than 200
mV will always cause a high receiver output.
When the differential input signal is close to zero, it is still above the VTH+ threshold, and the receiver output will
be High. Only when the differential input is more than VHYS below VTH+ will the receiver output transition to a Low
state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver
hysteresis value, VHYS, as well as the value of VTH+.
24
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3E – MAY 2018 – REVISED MAY 2019
Typical Application (continued)
10.2.1.5 Transient Protection
The bus pins of the THVD14xx transceiver family include on-chip ESD protection against ±30-kV HBM and ±18kV IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD test is far more
severe than the HBM ESD test. The 50% higher charge capacitance, C(S), and 78% lower discharge resistance,
R(D), of the IEC model produce significantly higher discharge currents than the HBM model. As stated in the IEC
61000-4-2 standard, contact discharge is the preferred transient protection test method.
R(C)
R(D)
High-Voltage
Pulse
Generator
330 Ω
(1.5 kΩ)
Device
Under
Test
150 pF
(100 pF)
C(S)
Current (A)
50 M
(1 M)
40
35
30 10-kV IEC
25
20
15
10
5
0
0
50
100
10-kV HBM
150
200
250
300
Time (ns)
Figure 34. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur because of human contact with connectors and cables. Designers may choose to
implement protection against longer duration transients, typically referred to as surge transients.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often
result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the
switching of power systems, including load changes and short circuit switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
Figure 35 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automation.
22
20
18
16
14
12
10
8
6
4
2
0
Pulse Power (MW)
Pulse Power (kW)
The right hand diagram shows the pulse power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
0.5-kV Surge
4-kV EFT
10-kV ESD
0
5
10
15
20
25
Time (µs)
30
35
40
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
0.5-kV Surge
0
5
10
15
20
25
30
35
40
Time (µs)
Figure 35. Power Comparison of ESD, EFT, and Surge Transients
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
25
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
www.ti.com
Typical Application (continued)
If the surge transients, high-energy content is characterized by long pulse duration and slow decaying pulse
power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver is
converted into thermal energy, which heats and destroys the protection cells, thus destroying the transceiver.
Figure 36 shows the large differences in transient energies for single ESD, EFT, surge transients, and an EFT
pulse train that is commonly applied during compliance testing.
1000
100
Surge
10
1
Pulse Energy (J)
EFT Pulse Train
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5
1
2
4
6
8 10
15
Peak Pulse Voltage (kV)
Figure 36. Comparison of Transient Energies
26
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3E – MAY 2018 – REVISED MAY 2019
Typical Application (continued)
10.2.2 Detailed Design Procedure
Figure 37 and Figure 38 suggest a protection circuit against 1 kV surge (IEC 61000-4-5) transients. Table 7
shows the associated bill of materials.
5V
100nF
100nF
10k
VCC
R1
R
RxD
MCU/
UART
DIR
RE
A
DE
B
TVS
D
TxD
R2
GND
10k
Figure 37. Transient Protection Against Surge Transients for Half-Duplex Devices
5V
100nF
R1
10k
VCC
A
TVS
R
RxD
B
RE
DIR
R2
R1
MCU/
UART
DE
DIR
Z
TVS
D
TxD
Y
10k
GND
R2
Figure 38. Transient Protection Against Surge Transients for Full-Duplex Devices
Table 7. Bill of Materials
DEVICE
FUNCTION
ORDER NUMBER
MANUFACTURER
XCVR
RS-485 transceiver
THVD14xx
TI
10-Ω, pulse-proof thick-film resistor
CRCW0603010RJNEAHP
Vishay
Bidirectional 400-W transient suppressor
CDSOT23-SM712
Bourns
R1
R2
TVS
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
27
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
www.ti.com
10.2.3 Application Curves
50 Mbps
VCC = 5 V
Figure 39. THVD1450 Waveforms with 54-Ω Termination
11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100
nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
28
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3E – MAY 2018 – REVISED MAY 2019
12 Layout
12.1 Layout Guidelines
Robust and reliable bus node design often requires the use of external transient protection devices in order to
protect against surge transients that may occur in industrial environments. Since these transients have a wide
frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be
applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your
board.
2. Use VCC and ground planes to provide low-inductance. Note that high-frequency currents tend to follow the
path of least impedance and not the path of least resistance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF decoupling capacitors as close as possible to the VCC pins of transceiver, UART
and/or controller ICs on the board.
5. Use at least two vias for VCC and ground connections of decoupling capacitors and protection devices to
minimize effective via inductance.
6. Use 1-kΩ to 10-kΩ pull-up and pull-down resistors for enable lines to limit noise currents in theses lines
during transient events.
7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
12.2 Layout Example
5
Via to ground
C
R
Via to VCC
R
1
JMP
6
4
R
MCU
5
6
R
TVS
5
THVD14x0
Figure 40. Half-Duplex Layout Example
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
29
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3E – MAY 2018 – REVISED MAY 2019
www.ti.com
13 Device and Documentation Support
13.1 Device Support
13.2 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 8. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
THVD1410
Click here
Click here
Click here
Click here
Click here
THVD1450
Click here
Click here
Click here
Click here
Click here
THVD1451
Click here
Click here
Click here
Click here
Click here
THVD1452
Click here
Click here
Click here
Click here
Click here
13.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document..
13.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
30
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3E – MAY 2018 – REVISED MAY 2019
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
31
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THVD1410D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1410
THVD1410DGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1410
THVD1410DGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1410
THVD1410DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1410
THVD1450D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1450
THVD1450DGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1450
THVD1450DGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1450
THVD1450DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1450
THVD1450DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1450
THVD1450DRBT
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1450
THVD1451D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1451
THVD1451DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD1451
THVD1451DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1451
THVD1451DRBT
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1451
THVD1452D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1452
THVD1452DGS
ACTIVE
VSSOP
DGS
10
1040
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1452
THVD1452DGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1452
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
7-Jun-2019
Status
(1)
THVD1452DR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
D
14
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
1452
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
15-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
THVD1410DGKR
Package Package Pins
Type Drawing
VSSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
THVD1410DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
THVD1450DGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
THVD1450DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
THVD1450DRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
THVD1450DRBT
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
THVD1451DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
THVD1451DRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
THVD1451DRBT
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.0
8.0
12.0
Q2
THVD1452DGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
THVD1452DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-May-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THVD1410DGKR
VSSOP
DGK
8
2500
364.0
364.0
27.0
THVD1410DR
SOIC
D
8
2500
340.5
338.1
20.6
THVD1450DGKR
VSSOP
DGK
8
2500
364.0
364.0
27.0
THVD1450DR
SOIC
D
8
2500
340.5
338.1
20.6
THVD1450DRBR
SON
DRB
8
3000
346.0
346.0
35.0
THVD1450DRBT
SON
DRB
8
250
203.0
203.0
35.0
THVD1451DR
SOIC
D
8
2500
340.5
338.1
20.6
THVD1451DRBR
SON
DRB
8
3000
346.0
346.0
35.0
THVD1451DRBT
SON
DRB
8
250
203.0
203.0
35.0
THVD1452DGSR
VSSOP
DGS
10
2500
364.0
364.0
27.0
THVD1452DR
SOIC
D
14
2500
333.2
345.9
28.6
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008F
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.05)
SECTION A-A
SECTION A-A
SCALE 30.000
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
EXPOSED
THERMAL PAD
1.6 0.05
(0.2) TYP
4
5
A
A
2X
1.95
2.4 0.05
8
1
6X 0.65
8X
PIN 1 ID
(OPTIONAL)
8X
0.5
0.3
0.35
0.25
0.1
0.05
C A B
C
4222121/C 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008F
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.55)
( 0.2) VIA
TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222121/C 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008F
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
8X (0.6)
METAL
TYP
1
8
8X (0.3)
(0.635)
SYMM
(1.07)
6X (0.65)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4222121/C 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
SCALE 3.200
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
10
1
3.1
2.9
NOTE 3
8X 0.5
2X
2
5
6
B
10X
3.1
2.9
NOTE 4
SEE DETAIL A
0.27
0.17
0.1
C A
1.1 MAX
B
0.23
TYP
0.13
0.25
GAGE PLANE
0 -8
0.15
0.05
0.7
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (0.3)
10X (1.45)
(R0.05)
TYP
SYMM
1
10
SYMM
8X (0.5)
6
5
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
10X (0.3)
SYMM
1
(R0.05) TYP
10
SYMM
8X (0.5)
6
5
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising