Texas Instruments | TUSB1046-DCI USB Type-C™ DisplayPort™ ALT Mode 10 Gbps Linear Redriver Crosspoint Switch (Rev. D) | Datasheet | Texas Instruments TUSB1046-DCI USB Type-C™ DisplayPort™ ALT Mode 10 Gbps Linear Redriver Crosspoint Switch (Rev. D) Datasheet

Texas Instruments TUSB1046-DCI USB Type-C™ DisplayPort™ ALT Mode 10 Gbps Linear Redriver Crosspoint Switch (Rev. D) Datasheet
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TUSB1046-DCI
SLLSEW2D – AUGUST 2016 – REVISED APRIL 2019
TUSB1046-DCI USB Type-C™ DisplayPort™ ALT Mode 10 Gbps Linear Redriver
Crosspoint Switch
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
USB Type-C crosspoint switch supporting
– USB 3.1 SSP + 2 DisplayPort lanes
– 4 DisplayPort lanes
USB 3.1 Gen 1/Gen 2 up to 10 Gbps
DisplayPort 1.4 up to 8.1 Gbps (HBR3)
VESA® DisplayPort Alt mode DFP redriving
crosspoint switch supporting C, D, E and F
configurations
Ultra-low-power architecture
Linear redriver with up to 14 dB equalization
Transparent to DisplayPort link training
Automatic LFPS de-emphasis control to meet
USB 3.1 certification requirements
Configuration through GPIO or I2C
Hot-plug capable
Industrial temperature range: -40ºC to 85ºC
(TUSB1046I-DCI)
Commercial temperature range: 0ºC to 70ºC
(TUSB1046-DCI)
4 mm x 6 mm, 0.4 mm pitch WQFN package
Tablets
Notebooks
Desktops
Docking stations
3 Description
The TUSB1046-DCI is a VESA USB Type-C™ Alt
Mode redriving switch supporting USB 3.1 data rates
up to 10 Gbps and DisplayPort 1.4 up to 8.1 Gbps for
downstream facing port (Host). The device is used for
configurations C, D, E, and F from the VESA
DisplayPort Alt Mode on USB Type-C Standard
Version 1.1. This protocol-agnostic linear redriver is
also capable of supporting other USB Type-C Alt
Mode interfaces.
The TUSB1046-DCI provides several levels of
receive linear equalization to compensate for cable
and board trace loss due to inter-symbol interference
(ISI). The device operates on a single 3.3 V supply
and comes in a commercial temperature range and
industrial temperature range.
Device Information(1)
PART NUMBER
TUSB1046-DCI
TUSB1046I-DCI
PACKAGE
WQFN (40)
BODY SIZE (NOM)
4.00 mm x 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematics
TUSB1046-DCI Eye Diagram
D+/TUSB1046-DCI
USB Host
SSTX
TUSB1046-DCI
SSRX
-
DCI
TX2
DP0
TX1
DP1
RX1
DP2
GPU
DP3
AUXp
SBU1
AUXn
SBU2
Type-C Receptacle
RX2
HPDIN
FLIP 0 1 CTL
CC1
HPD
Control
PD Controller
CC2
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB1046-DCI
SLLSEW2D – AUGUST 2016 – REVISED APRIL 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
8
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Power Supply Characteristics ................................... 6
DC Electrical Characteristics .................................... 6
AC Electrical Characteristics..................................... 7
Timing Requirements ................................................ 8
Switching Characteristics .......................................... 9
Typical Characteristics .......................................... 10
Parameter Measurement Information ................ 12
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 15
8.3
8.4
8.5
8.6
9
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
16
17
22
24
Application and Implementation ........................ 29
9.1 Application Information............................................ 29
9.2 Typical Application ................................................. 29
9.3 System Examples .................................................. 33
10 Power Supply Recommendations ..................... 38
11 Layout................................................................... 39
11.1 Layout Guidelines ................................................. 39
11.2 Layout Example .................................................... 39
12 Device and Documentation Support ................. 40
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
40
40
40
40
40
40
13 Mechanical, Packaging, and Orderable
Information ........................................................... 40
4 Revision History
Changes from Revision C (April 2018) to Revision D
•
Page
Added following to pin 11 description: If I2C_EN = “F”, then this pin must be set to “F” or “0”. ........................................... 4
Changes from Revision B (June 2017) to Revision C
Page
•
Changed the appearance of the pinout image in the Pin Configuration and Function section .............................................. 3
•
Added Note 1 to the Pin Functions table................................................................................................................................ 3
•
Changed the USB3.1 Control/Status Registers reset value From: 00000000 To: 00000100.............................................. 28
•
Changed the Reset value of bit 3:2 From: 00 To: 01 in Table 18 ....................................................................................... 28
Changes from Revision A (April 2017) to Revision B
•
Page
Changed the Human-body model (HBM) value From: ±6000 V To: ±5000 in the ESD Ratings ........................................... 5
Changes from Original (August 2016) to Revision A
Page
•
Changed title of Figure 2 From: USB TX EQ Settings Curves To: USB RX EQ Settings Curves ...................................... 10
•
Changed title of Figure 3 From: USB RX EQ Settings Curves To: USB TX EQ Settings Curves ...................................... 10
2
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SLLSEW2D – AUGUST 2016 – REVISED APRIL 2019
5 Pin Configuration and Functions
RX2p
RX2n
EQ0
TX2p
TX2n
EQ1
TX1n
TX1p
HPDIN/ RSVD2
RX1n
RX1p
CAD_SNK/ RSVD1
40
39
38
37
36
35
34
33
32
31
30
29
RNQ Package
40-Pin (WQFN)
Top View
VCC
1
28
VCC
DPEQ1
2
27
SBU1
SSEQ1
3
26
SBU2
SSRXn
4
25
AUXn
SSRXp
5
24
AUXp
VCC
6
23
CTL1/HPDIN
SSTXn
7
22
CTL0/SDA
SSTXp
8
21
FLIP/SCL
Thermal
20
VCC
19
DP3n
18
DP3p
17
I2C_EN
16
DP2n
15
DP2p
14
DPEQ0/A1
13
DP1n
12
DP1p
11
SSEQ0/A0
10
DP0n
DP0p
9
Pad
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
DP0p
9
Diff I
DP Differential positive input for DisplayPort Lane 0.
DP0n
10
Diff I
DP Differential negative input for DisplayPort Lane 0.
DP1p
12
Diff I
DP Differential positive input for DisplayPort Lane 1.
DP1n
13
Diff I
DP Differential negative input for DisplayPort Lane 1.
DP2p
15
Diff I
DP Differential positive input for DisplayPort Lane 2.
DP2n
16
Diff I
DP Differential negative input for DisplayPort Lane 2.
DP3p
18
Diff I
DP Differential positive input for DisplayPort Lane 3.
DP3n
19
Diff I
DP Differential negative input for DisplayPort Lane 3.
RX1n
31
Diff I/O
Differential negative output for DisplayPort or differential negative input for USB3.1 Downstream
Facing port.
RX1p
30
Diff I/O
Differential positive output for DisplayPort or differential positive input for USB3.1 Downstream
Facing port.
TX1n
34
Diff O
Differential negative output for DisplayPort or USB3.1 downstream facing port.
TX1p
33
Diff O
Differential positive output for DisplayPort or USB 3.1 downstream facing port.
TX2p
37
Diff O
Differential positive output for DisplayPort or USB 3.1 downstream facing port.
TX2n
36
Diff O
Differential negative output for DisplayPort or USB 3.1 downstream facing port.
RX2p
40
Diff I/O
Differential positive output for DisplayPort or differential positive input for USB3.1 Downstream
Facing port.
RX2n
39
Diff I/O
Differential negative output for DisplayPort or differential negative input for USB3.1 Downstream
Facing port.
SSTXp
8
Diff I
Differential positive input for USB3.1 upstream facing port.
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
SSTXn
7
Diff I
Differential negative input for USB3.1 upstream facing port.
SSRXp
5
Diff O
Differential positive output for USB3.1 upstream facing port.
SSRXn
4
Diff O
Differential negative output for USB3.1 upstream facing port.
EQ1
35
4 Level I
This pin along with EQ0 sets the USB receiver equalizer gain for downstream facing RX1 and RX2
when USB used.
EQ0
38
4 Level I
This pin along with EQ1 sets the USB receiver equalizer gain for downstream facing RX1 and RX2
when USB used.
CAD_SNK/ RSVD1 (1)
29
I/O
(PD)
When I2C_EN ! = 0, this pin is reserved. Leave open if not used. When I2C_EN = 0 , this pin is
CAD_SNK (L = AUX snoop enabled and H = AUX snoop disabled with all lanes active).
HPDIN/ RSVD2 (1)
32
I/O
(PD)
When I2C_EN ! = 0, this pin is reserved. Leave open if not used. When I2C_EN = 0, this pin is an
input for Hot Plug Detect received from DisplayPort sink. When HPDIN is Low for greater than
2ms, all DisplayPort lanes are disabled while the AUX to SBU switch will remain closed.
I2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is ‘0".
0 = GPIO mode (I2C disabled)
R = TI Test Mode (I2C enabled at 3.3 V)
F = I2C enabled at 1.8 V
1 = I2C enabled at 3.3 V.
I2C_EN
17
4 Level I
SBU1
27
I/O, CMOS
SBU1. This pin should be DC coupled to the SBU1 pin on the Type-C receptacle. A 2-M ohm
resistor to GND is also recommended.
SBU2
26
I/O, CMOS
SBU2. This pin should be DC coupled to the SBU2 pin on the Type-C receptacle. A 2-M ohm
resistor to GND is also recommended.
AUXp
24
I/O, CMOS
AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source through a AC coupling
capacitor. In addition to AC coupling capacitor, this pin also requires a 100K resistor to GND. This
pin along with AUXN is used by the TUSB1046-DCI for AUX snooping and is routed to SBU1/2
based on the orientation of the Type-C.
AUXn
25
I/O, CMOS
AUXn. DisplayPort AUX negative I/O connected to the DisplayPort source through a AC coupling
capacitor. In addition to AC coupling capacitor, this pin also requires a 100K resistor to DP_PWR
(3.3V). This pin along with AUXP is used by the TUSB1046-DCI for AUX snooping and is routed to
SBU1/2 based on the orientation of the Type-C.
DPEQ1
2
4 Level I
DisplayPort Receiver EQ. This along with DPEQ0 will select the DisplayPort receiver equalization
gain.
DPEQ0/A1
14
4 Level I
DisplayPort Receiver EQ. This along with DPEQ1 will select the DisplayPort receiver equalization
gain. When I2C_EN is not ‘0’, this pin will also set the TUSB1046-DCI I2C address.
SSEQ1
3
4 Level I
Along with SSEQ0, sets the USB receiver equalizer gain for upstream facing SSTXP/N.
SSEQ0/A0
11
4 Level I
Along with SSEQ1, sets the USB receiver equalizer gain for upstream facing SSTXP/N. When
I2C_EN is not ‘0’, this pin will also set the TUSB1046-DCI I2C address. If I2C_EN = “F”, then this
pin must be set to “F” or “0”.
FLIP/SCL
21
2 Level I
When I2C_EN=’0’ this is Flip control pin, otherwise this pin is I2C clock. . When used for I2C clock
pullup to I2C master's VCC I2C supply.
CTL0/SDA
22
2 Level I
When I2C_EN=’0’ this is a USB3.1 Switch control pin, otherwise this pin is I2C data. When used
for I2C data pullup to I2C master's VCC I2C supply.
2 Level I
(Failsafe)
(PD)
DP Alt mode Switch Control Pin. When I2C_EN = ‘0’, this pin will enable or disable DisplayPort
functionality. Otherwise, when I2C_EN is not "0", DisplayPort functionality is enabled and disabled
through I2C registers.
L = DisplayPort Disabled.
H = DisplayPort Enabled.
When I2C_EN is not "0" this pin is an input for Hot Plug Detect received from DisplayPort sink.
When this HPDIN is Low for greater than 2 ms, all DisplayPort lanes are disabled and AUX to SBU
switch will remain closed.
CTL1/HPDIN
VCC
23
1, 6, 20, 28
Thermal Pad
(1)
4
P
3.3-V Power Supply
G
Ground
Not a fail-safe I/O. Actively driving pin high while VCC is removed results in leakage voltage on VCC pins.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply Voltage Range (2), VCC
MIN
MAX
UNIT
–0.3
4
V
±2.5
V
V
Differential voltage between positive and
negative inputs
Voltage Range at any input or output pin
Voltage at differential inputs
–0.5
VCC + 0.5
CMOS Inputs
–0.5
VCC + 0.5
V
125
°C
150
°C
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminals.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±5000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Main power supply
VCC
MIN
NOM
MAX
3
3.3
3.6
V
100
ms
3.6
V
Supply Ramp Requirement
V(12C)
Supply that external resistors are pulled up to on SDA and SCL
V(PSN)
Supply Noise on VCC pins
TA
Operating free-air temperature
1.7
UNIT
100
mV
TUSB1046-DCI
0
70
°C
TUSB1046I-DCI
–40
85
°C
6.4 Thermal Information
TUSB1046-DCI
THERMAL METRIC
(1)
RNQ (WQFN)
UNIT
40 PINS
RθJA
Junction-to-ambient thermal resistance
37.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
20.7
°C/W
RθJB
Junction-to-board thermal resistance
9.5
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
9.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Power Supply Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PCC(ACTIVE-USB)
Average active power
USB Only
Link in U0 with GEN2 data transmission.
EN, EQ cntrl pins = NC, k28.5 pattern at
10 Gbps, VID = 1000 mVPP ;
CTL1 = L; CTL0 = H
PCC(ACTIVE-USB-DP1)
Average active power
USB + 2 Lane DP
Link in U0 with GEN2 data transmission.
EN, EQ cntrl pins = NC, k28.5 pattern at
10 Gbps, VID = 1000 mVPP;
CTL1 = H; CTL0 = H
634
mW
PCC(ACTIVE--DP)
Average active power
4 Lane DP Only
Four active DP lanes operating at
8.1Gbps;
CTL1 = H; CTL0 = L;
660
mW
PCC(NC-USB)
Average power with no connection
No GEN1 device is connected to
TXP/TXN;
CTL1 = L; CTL0 = H;
2.4
mW
PCC(U2U3)
Average power in U2/U3
Link in U2 or U3 USB Mode Only;
CTL1 = L; CTL0 = H;
3
mW
PCC(SHUTDOWN)
Device Shutdown
CTL1 = L; CTL0 = L; I2C_EN = 0;
0.85
mW
335
mW
6.6 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4-State CMOS Inputs(EQ[1:0], SSEQ[1:0], DPEQ[1:0], I2C_EN)
IIH
High level input current
VCC = 3.6 V; VIN = 3.6 V
IIL
Low level input current
VCC = 3.6 V; VIN = 0 V
Threshold 0 / R
VCC = 3.3 V
0.55
V
Threshold R/ Float
VCC = 3.3 V
1.65
V
Threshold Float / 1
VCC = 3.3 V
2.7
V
4-Level VTH
20
80
µA
–160
-40
µA
RPU
Internal pull-up resistance
35
kΩ
RPD
Internal pull-down resistance
95
kΩ
2-State CMOS Input (CTL0, CTL1, FLIP, CAD_SNK, HPDIN) CTL1, CTL0 and FLIP are Failsafe.
VIH
High-level input voltage
2
3.6
VIL
Low-level input voltage
0
0.8
V
RPD
Internal pull-down resistance for CTL1
500
kΩ
R(ENPD)
Internal pull-down resistance for
CAD_SNK (pin 29), and HPDIN (pin 32)
150
kΩ
IIH
High-level input current
VIN = 3.6 V
–25
25
µA
IIL
Low-level input current
VIN = GND, VCC = 3.6 V
–25
25
µA
V
2
I C Control Pins SCL, SDA
VIH
High-level input voltage
I2C_EN = 0
0.7 x V(I2C)
3.6
V
VIL
Low-level input voltage
I2C_EN = 0
0
0.3 x V(I2C)
V
VOL
Low-level output voltage
I2C_EN = 0; IOL = 3 mA
0
0.4
IOL
Low-level output current
I2C_EN = 0; VOL = 0.4 V
20
II(I2C)
Input current on SDA pin
0.1 x V(I2C) < Input voltage < 3.3 V
CI(I2C)
Input capacitance
C(I2C_FM+_BUS)
V
mA
10
µA
10
pF
I2C bus capacitance for FM+ (1MHz)
150
pF
C(I2C_FM_BUS)
I2C bus capacitance for FM (400kHz)
150
pF
R(EXT_I2C_FM+)
External resistors on both SDA and SCL
when operating at FM+ (1MHz)
C(I2C_FM+_BUS) = 150 pF
620
820
910
Ω
R(EXT_I2C_FM)
External resistors on both SDA and SCL
when operating at FM (400kHz)
C(I2C_FM_BUS) = 150 pF
620
1500
2200
Ω
6
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6.7 AC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USB Gen 2 Differential Receiver (RX1P/N, RX2P/N, SSTXP/N)
V(RX-DIFF-PP)
Input differential peak-peak voltage
swing linear dynamic range
V(RX-DC-CM)
Common-mode voltage bias in the
receiver (DC)
R(RX-DIFF-DC)
Differential input impedance (DC)
R(RX-CM-DC)
AC-coupled differential peak-to-peak
signal measured post CTLE through a
reference channel
2000
mVpp
0
2
V
Present after a GEN2 device is
detected on TXP/TXN
72
120
Ω
Receiver DC common mode
impedance
Present after a GEN2 device is
detected on TXP/TXN
18
30
Ω
Z(RX-HIGH-IMP-DC-POS)
Common-mode input impedance with
termination disabled (DC)
Present when no GEN2 device is
detected on TXP/TXN. Measured over
the range of 0-500mV with respect to
GND.
25
V(SIGNAL-DET-DIFF-PP)
Input differential peak-to-peak signal
detect assert level
At 10 Gbps, no input loss, PRBS7
pattern
80
mV
V(RX-IDLE-DET-DIFF-PP)
Input differential peak-to-peak signal
detect de-assert Level
At 10 Gbps, no input loss, PRBS7
pattern
60
mV
V(RX-LFPS-DET-DIFF-PP)
Low frequency periodic signaling
(LFPS) detect threshold
Below the minimum is squelched
V(RX-CM-AC-P)
Peak RX AC common-mode voltage
Measured at package pin
C(RX)
RX input capacitance to GND
At 5 GHz
0.5
50 MHz – 1.25 GHz at 90 Ω
–19
dB
kΩ
100
300
mV
150
mV
1
pF
RL(RX-DIFF)
Differential return Loss
5 GHz at 90 Ω
–10
dB
RL(RX-CM)
Common-mode return loss
50 MHz – 5 GHz at 90 Ω
–10
dB
EQ(SS_TX)
Receiver equalization for upstream
facing port
SSEQ[1:0] at 5 GHz
11
dB
EQ(SS_RX)
Receiver equalization for downstream
facing ports
EQ[1:0] at 5 GHz
9
dB
USB Gen 2 Differential Transmitter (TX1P/N, TX2P/N, SSRXP/N)
VTX(DIFF-PP)
Transmitter dynamic differential voltage swing range.
VTX(RCV-DETECT)
Amount of voltage change allowed during receiver detection
VTX(CM-IDLE-DELTA)
Transmitter idle common-mode voltage change while in U2/U3 and not actively
transmitting LFPS
VTX(DC-CM)
Common-mode voltage bias in the transmitter (DC)
1600
mVPP
600
mV
–600
600
mV
0
2
V
VTX(CM-AC-PP-ACTIVE)
Tx AC common-mode voltage active
Max mismatch from Txp + Txn for both
time and amplitude
VTX(IDLE-DIFF-AC-PP)
AC electrical idle differential peak-topeak output voltage
At package pins
VTX(IDLE-DIFF-DC)
DC electrical idle differential output
voltage
At package pins after low pass filter to
remove AC component
Absolute DC common-mode voltage
between U1 and U0
At package pin
DELTA)
RTX(DIFF)
Differential impedance of the driver
75
120
Ω
CAC(COUPLING)
AC coupling capacitor
75
265
nF
RTX(CM)
Common-mode impedance of the
driver
Measured with respect to AC ground
over
0–500 mV
18
30
Ω
ITX(SHORT)
TX short circuit current
TX± shorted to GND
67
mA
CTX(PARASITIC)
TX input capacitance for return loss
At package pins, at 5 GHz
1.25
pF
RLTX(DIFF)
Differential return loss
RLTX(CM)
VTX(CM-DC-ACTIVE-IDLE-
100
mVPP
0
10
mV
0
14
mV
200
mV
50 MHz – 1.25 GHz at 90 Ω
-15
dB
5 GHz at 90 Ω
-13
dB
Common-mode return loss
50 MHz – 5 GHz at 90 Ω
-13
dB
Crosstalk
Differential crosstalk between TX and
RX signal pairs
at 5 GHz
–30
dB
C(P1dB-LF)
Low frequency 1-dB compression
point
at 100 MHz, 200 mVPP < VID
< 2000 mVPP
1300
mVPP
AC Characteristics
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AC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
C(P1dB-HF)
High frequency 1-dB compression
point
at 5 GHz, 200 mVPP < VID
< 2000 mVPP
fLF
Low frequency cutoff
200 mVPP< VID < 2000 mVPP
TX output deterministic jitter
TX output total jitter
MIN
TYP
MAX
1000
20
UNIT
mVPP
50
kHz
200 mVPP < VID < 2000 mVPP, PRBS7,
10 Gbps
0.11
UIpp
200 mVPP < VID < 2000 mVPP, PRBS7,
8.1 Gbps
0.08
UIpp
200 mVPP < VID < 2000 mVPP, PRBS7,
10 Gbps
0.15
UIpp
200 mVPP < VID < 2000 mVPP, PRBS7,
8.1 Gbps
0.135
UIpp
2000
V
DisplayPort Receiver (DP[3:0]p or DP[3:0]n)
VID(PP)
Peak-to-peak input differential dynamic voltage range
VIC
Input common mode voltage
C(AC)
AC coupling capacitance
EQ(DP)
Receiver equalization
DPEQ[1:0] at 4.05 GHz
14
dB
dR
Data rate
HBR3
8.1
Gbps
R(ti)
Input termination resistance
120
Ω
67
mA
0
V
10
Ω
0
2
V
75
200
nF
80
100
DisplayPort Transmitter (TX1p or TX1n, TX2p or TX2n, RX1p or RX1n, RX2p or RX2n)
ITX(SHORT)
TX short circuit current
VTX(DC-CM)
Common-mode voltage bias in the transmitter (DC)
TX± shorted to GND
0
AUXp or AUXn and SBU1 or SBU2
RON
Output ON resistance
VCC = 3.3V; VI = 0 to 0.4 V for AUXp;
VI = 2.7 V to 3.6 V for AUXn
ΔRON
ON resistance mismatch within pair
VCC = 3.3 V; VI = 0 to 0.4 V for AUXP;
VI = 2.7 V to 3.6 V for AUXN
2.5
Ω
RON(FLAT)
ON resistance flatness (RON max –
RON min) measured at identical VCC
and temperature
VCC = 3.3 V; VI = 0 to 0.4 V for AUXp;
VI = 2.7 V to 3.6 V for AUXn
2
Ω
V(AUXP_DC_CM)
AUX Channel DC common mode
voltage for AUXp and SBU1.
VCC = 3.3 V
0
0.4
V
V(AUXN_DC_CM)
AUX Channel DC common mode
voltage for AUXn and SBU2
VCC = 3.3 V
2.7
3.6
V
C(AUX_ON)
ON-state capacitance
VCC = 3.3 V; CTL1 = 1; VI = 0 V
or 3.3 V
4
7
pF
C(AUX_OFF)
OFF-state capacitance
VCC = 3.3 V; CTL1 = 0; VI = 0 V
or 3.3 V
3
6
pF
5
6.8 Timing Requirements
MIN
NOM
MAX
UNIT
USB Gen 1
tIDLEEntry
Delay from U0 to electrical idle
See Figure 14
10
ns
tIDELExit_U1
U1 exist time: break in electrical idle to
the transmission of LFPS
See Figure 14
6
ns
tIDLEExit_U2U3
U2/U3 exit time: break in electrical idle to transmission of LFPS
tRXDET_INTVL
RX detect interval while in Disconnect
tIDLEExit_DISC
Disconnect Exit Time
tExit_SHTDN
Shutdown Exit Time
tDIFF_DLY
Differential Propagation Delay
See Figure 13
tR, tF
Output Rise/Fall time (see Figure 15)
20%-80% of differential
voltage measured 1.7 inch
from the output pin
tRF_MM
Output Rise/Fall time mismatch
20%-80% of differential
voltage measured 1.7 inch
from the output pin
8
10
µs
12
10
µs
1
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ms
ms
300
35
ps
ps
2.6
ps
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6.9 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUXp or AUXn and SBU1 or SBU2
tAUX_PD
Switch propagation delay
400
ps
tAUX_SW_OFF
Switching time CTL1 to switch OFF. Not including
TCTL1_DEBOUNCE.
500
ns
tAUX_SW_ON
Switching time CTL1 to switch ON
500
ns
tAUX_INTRA
Intra-pair output skew
100
ps
USB3.1 and DisplayPort mode transition requirement GPIO mode
tGP_USB_4DP
Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only
mode to 4-Lane DisplayPort mode or vice versa.
4
CTL1 and HPDIN debounce time when transitioning from H to L.
2
µs
CTL1 and HPDIN
tCTL1_DEBOUNCE
10
ms
1
MHz
2
I C (Refer to Figure 11)
fSCL
I2C clock frequency
tBUF
Bus free time between START and STOP conditions
tHDSTA
Hold time after repeated START condition. After this period, the first
clock pulse is generated
2
0.5
µs
0.26
µs
tLOW
Low period of the I C clock
0.5
µs
tHIGH
High period of the I2C clock
0.26
µs
tSUSTA
Setup time for a repeated START condition
0.26
µs
tHDDAT
Data hold time
0
μs
tSUDAT
Data setup time
50
ns
tR
Rise time of both SDA and SCL signals
tF
Fall time of both SDA and SCL signals
tSUSTO
Setup time for STOP condition
Cb
Capacitive load for each bus line
20 × (V(I2C)/5.5
V)
120
ns
120
ns
150
pF
0.26
μs
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15
15
10
10
5
5
SDD21 (dB)
SDD21 (dB)
6.10 Typical Characteristics
0
0
-5
-5
EQ0
EQ1
EQ2
EQ3
-10
-15
0.01
EQ4
EQ5
EQ6
EQ7
0.1
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
1
Frequency (GHz)
EQ0
EQ1
EQ2
EQ3
-10
-15
0.01
10
0.1
D001
Figure 1. DisplayPort EQ Settings Curves
1
Frequency (GHz)
10
D002
1.4
Differential Output Voltage (V)
5
SDD21 (dB)
EQ12
EQ13
EQ14
EQ15
1.6
10
0
-5
EQ0
EQ1
EQ2
EQ3
-10
-15
0.01
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
1.2
1
0.8
0.6
0.4
EQ0
EQ1
EQ2
EQ3
0.2
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
0
0.1
1
Frequency (GHz)
10
0
1.2
1.4
Differential Output Voltage (V)
1.6
1
0.8
0.6
0.4
0.2
EQ4
EQ5
EQ6
EQ7
0.4
EQ8
EQ9
EQ10
EQ11
0.6 0.8
1
1.2 1.4
Differential Input Voltage (V)
1.6
1.8
2
D004
Figure 4. DisplayPort Linearity Curves at 4.05 GHz
1.4
EQ0
EQ1
EQ2
EQ3
0.2
D003
Figure 3. USB TX EQ Settings Curves
Differential Output Voltage (V)
EQ8
EQ9
EQ10
EQ11
Figure 2. USB RX EQ Settings Curves
15
EQ12
EQ13
EQ14
EQ15
1.2
1
0.8
0.6
0.4
EQ0
EQ1
EQ2
EQ3
0.2
0
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
0
0
0.2
0.4
0.6 0.8
1
1.2 1.4
Differential Input Voltage (V)
1.6
1.8
2
0
0.2
D005
Figure 5. USB TX Linearity Curves at 5 GHz
10
EQ4
EQ5
EQ6
EQ7
0.4
0.6 0.8
1
1.2 1.4
Differential Input Voltage (V)
1.6
1.8
2
D006
Figure 6. USB RX Linearity Curves at 5 GHz
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Typical Characteristics (continued)
5
0
-5
5
DP0
DP1
DP2
DP3
SSTX
RX1
RX2
0
TX2
SSRX
-5
SDD22 (dB)
-10
SDD11 (dB)
RX1
RX2
TX1
-15
-20
-25
-10
-15
-20
-30
-25
-35
-40
0.01
0.1
1
Frequency (GHz)
-30
0.01
10
0.1
D007
10
D008
Figure 8. Output Return Loss Performance
Output Voltage (75 mV/Div)
Output Voltage (75 mV/Div)
Figure 7. Input Return Loss Performance
1
Frequency (GHz)
Time (20.57 ps/Div)
Time (16.67 ps/Div)
Figure 9. DisplayPort HBR3 Eye-Pattern Performance with
12-inch Input PCB Trace at 8.1 Gbps
Figure 10. USB 3.1 Gen2 Eye-Pattern Performance with
12-inch Input PCB Trace at 10 Gbps
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7 Parameter Measurement Information
70%
SDA
30%
tLOW
tBUF
tR
tHIGH
tHDSTA
tF
70%
SCL
P
30%
S
S
tHDSTA
tHDDAT
P
tSUDAT
tSUSTA
tSUSTO
Figure 11. I2C Timing Diagram Definitions
4us
(min)
CTL1 pin
CTL0 pin
Figure 12. USB3.1 to 4-Lane DisplayPort in GPIO Mode
IN
TDIFF_DLY
TDIFF_DLY
OUT
Figure 13. Propagation Delay
12
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Parameter Measurement Information (continued)
IN+
VRX-LFPS-DET-DIFF-PP
Vcm
INTIDLEExit
TIDLEEntry
OUT+
Vcm
OUT-
Figure 14. Electrical Idle Mode Exit and Entry Delay
80%
20%
tr
tf
Figure 15. Output Rise and Fall Times
50%
50%
CTL1
90%
10%
VOUT
TAUX_SW_ON
TAUX_SW_OFF + TCTL1_DEBOUNCE
Figure 16. AUX and SBU Switch ON and OFF Timing Diagram
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8 Detailed Description
8.1 Overview
The TUSB1046-DCI is a VESA USB Type-C Alt Mode redriving switch supporting data rates up to 8.1 Gbps for
downstream facing port. These devices utilize 5th generation USB redriver technology. The devices are utilized
for DFP configurations C, D, E, and F from the VESA DisplayPort Alt Mode on USB Type-C.
The TUSB1046-DCI provides several levels of receive equalization to compensate for cable and board trace loss
due to inter-symbol interference (ISI) when USB 3.1 Gen1/Gen2 or DisplayPort 1.4 signals travel across a PCB
or cable. This device requires a 3.3-V power supply. It comes in a commercial temperature range and industrial
temperature range.
For a host application the TUSB1046-DCI enables the system to pass both transmitter compliance and receiver
jitter tolerance tests for USB 3.1 Gen1/Gen2 and DisplayPort version 1.4 HBR3. The re-driver recovers incoming
data by applying equalization that compensates for channel loss, and drives out signals with a high differential
voltage. Each channel has a receiver equalizer with selectable gain settings. The equalization should be set
based on the amount of insertion loss before the TUSB1046-DCI receivers. Independent equalization control for
each channel can be set using EQ[1:0], SSEQ[1:0], and DPEQ[1:0] pins.
The TUSB1046-DCI advanced state machine makes it transparent to hosts and devices. After power up, the
TUSB1046-DCI. periodically performs receiver detection on the TX pairs. If it detects a USB 3.1 Gen1/Gen2
receiver, the RX termination is enabled, and the TUSB1046-DCI is ready to re-drive.
The device ultra-low-power architecture operates at a 3.3-V power supply and achieves enhanced performance.
The automatic LFPS de-emphasis control further enables the system to be USB3.1 compliant.
14
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SSRXn
Driver
EQ_SEL
EQ
SSEQ_SEL
Term
SSRXp
Detect
Term
8.2 Functional Block Diagram
SSTXn
RX2p
EQ
Term
Term
SSTXp
Driver
RX2n
DPEQ_SEL
DP0n
EQ
Term
Detect
Term
DP0p
Driver
Term
Detect
MUX
Driver
Term
DP1p
TX2p
TX2n
TX1n
TX1p
EQ
DP1n
DPEQ_SEL
Term
RX1n
Driver
DP2n
RX1p
EQ
EQ
Term
Term
DP2p
EQ_SEL
Term
DP3p
EQ
DP3n
DPEQ_SEL
SSEQ_SEL
DPEQ_SEL
DPEQ[1:0]/A1
SSEQ[1:0]/A0
I2C_EN
FLIP/SCL
CTL0/SDA
EQ_SEL
EQ[1:0]
I2C
Slave
FSM, Control Logic and
Registers
HPDIN/RSVD2
CTL1/HPDIN
CAD_SNK/RSVD1
AUX
RX
M
U
X
AUXp
AUXn
VCC
SBU1
SBU2
VREG
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8.3 Feature Description
8.3.1 USB 3.1
The TUSB1046-DCI supports USB 3.1 Gen1/Gen2 datarates up to 10 Gbps. The TUSB1046-DCI supports all
the USB defined power states (U0, U1, U2, and U3). Because the TUSB1046-DCI is a linear redriver, it can’t
decode USB3.1 physical layer traffic. The TUSB1046-DCI monitors the actual physical layer conditions like
receiver termination, electrical idle, LFPS, and SuperSpeed signaling rate to determine the USB power state of
the USB 3.1 interface.
The TUSB1046-DCI features an intelligent low frequency periodic signaling (LFPS) detector. The LFPS detector
automatically senses the low frequency signals and disables receiver equalization functionality. When not
receiving LFPS, the TUSB1046-DCI will enable receiver equalization based on the EQ[1:0] and SSEQ[1:0] pins
or values programmed into EQ1_SEL, EQ2_SEL, and SSEQ_SEL registers.
8.3.2 DisplayPort
The TUSB1046-DCI supports up to 4 DisplayPort lanes at datarates up to 8.1Gbps (HBR3). The TUSB1046-DCI,
when configured in DisplayPort mode, monitors the native AUX traffic as it traverses between DisplayPort source
and DisplayPort sink. For the purposes of reducing power, the TUSB1046-DCI manages the number of active
DisplayPort lanes based on the content of the AUX transactions. The TUSB1046-DCI snoops native AUX writes
to DisplayPort sink’s DPCD registers 0x00101 (LANE_COUNT_SET) and 0x00600 (SET_POWER_STATE).
TUSB1046-DCI disables/enables lanes based on value written to LANE_COUNT_SET. The TUSB1046-DCI
disables all lanes when SET_POWER_STATE is in the D3. Otherwise active lanes will be based on value of
LANE_COUNT_SET.
DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE
register. Once AUX snoop is disabled, management of TUSB1046-DCI DisplayPort lanes are controlled through
various configuration registers. When TUSB1046-DCI is enabled for GPIO mode (I2C_EN = "0"), the CAD_SNK
pin can be used to disable AUX snooping. When CAD_SNK pin is high, the AUX snooping functionality is
disabled and all four DisplayPort lanes will be active.
8.3.3 4-level Inputs
The TUSB1046-DCI has (I2C_EN, EQ[1:0], DPEQ[1:0], and SSEQ[1:0]) 4-level inputs pins that are used to
control the equalization gain and place TUSB1046-DCI into different modes of operation. These 4-level inputs
utilize a resistor divider to help set the 4 valid levels and provide a wider range of control settings. There is an
internal 30 kΩ pull-up and a 94 kΩ pull-down. These resistors, together with the external resistor connection
combine to achieve the desired voltage level.
Table 1. 4-Level Control Pin Settings
16
LEVEL
SETTINGS
0
Option 1: Tie 1 KΩ 5% to GND.
Option 2: Tie directly to GND.
R
Tie 20 KΩ 5% to GND.
F
Float (leave pin open)
1
Option 1: Tie 1 KΩ 5%to VCC.
Option 2: Tie directly to VCC.
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NOTE
All four-level inputs are latched on rising edge of internal reset. After tcfg_hd, the internal
pull-up and pull-down resistors will be isolated in order to save power.
8.3.4 Receiver Linear Equalization
The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in
the system before the input of the TUSB1046-DCI. The receiver overcomes these losses by attenuating the low
frequency components of the signals with respect to the high frequency components. The proper gain setting
should be selected to match the channel insertion loss before the input of the TUSB1046-DCI receivers. Two 4level inputs pins enable up to 16 possible equalization settings. USB3.1 upstream path, USB3.1 downstream
path, and DisplayPort each have their own two 4-level inputs. The TUSB1046-DCI also provides the flexibility of
adjusting settings through I2C registers.
8.4 Device Functional Modes
8.4.1 Device Configuration in GPIO Mode
The TUSB1046-DCI is in GPIO configuration when I2C_EN = “0”. The TUSB1046-DCI supports the following
configurations: USB 3.1 only, 2 DisplayPort lanes + USB 3.1, or 4 DisplayPort lanes (no USB 3.1). The CTL1 pin
controls whether DisplayPort is enabled. The combination of CTL1 and CTL0 selects between USB 3.1 only, 2
lanes of DisplayPort, or 4-lanes of DisplayPort as detailed in Table 2. The AUXp or AUXn to SBU1 or SBU2
mapping is controlled based on Table 3.
After power-up (VCC from 0 V to 3.3 V), the TUSB1046-DCI defaults to USB3.1 mode. The USB PD controller
upon detecting no device attached to Type-C port or USB3.1 operation not required by attached device must
take TUSB1046-DCI out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.
Table 2. GPIO Configuration Control
FLIP PIN
TUSB1046-DCI CONFIGURATION
VESA DisplayPort ALT MODE
DFP_D CONFIGURATION
L
L
Power Down
—
L
H
Power Down
—
L
H
L
One Port USB 3.1 - No Flip
—
CTL1 PIN
CTL0 PIN
L
L
L
H
H
One Port USB 3.1 – With Flip
—
H
L
L
4 Lane DP - No Flip
C and E
H
L
H
4 Lane DP – With Flip
C and E
H
H
L
One Port USB 3.1 + 2 Lane DP- No Flip
D and F
H
H
H
One Port USB 3.1 + 2 Lane DP– With Flip
D and F
Table 3. GPIO AUXp or AUXn to SBU1 or SBU2 Mapping
CTL1 PIN
FLIP PIN
MAPPING
H
L
AUXp → SBU1
AUXn → SBU2
H
H
AUXp → SBU2
AUXn → SBU1
L > 2 ms
X
Open
Table 4 Details the TUSB1046-DCI’s mux routing. This table is valid for both I2C and GPIO.
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Table 4. INPUT to OUTPUT Mapping
CTL1 PIN
CTL0 PIN
L
L
L
L
L
L
H
H
H
H
18
H
H
L
L
H
H
FROM
TO
INPUT PIN
OUTPUT PIN
L
NA
NA
H
NA
NA
RX1P
SSRXP
RX1N
SSRXN
FLIP PIN
L
H
L
H
L
H
SSTXP
TX1P
SSTXN
TX1N
RX2P
SSRXP
RX2N
SSRXN
SSTXP
TX2P
SSTXN
TX2P
DP0P
RX2P
DP0N
RX2N
DP1P
TX2P
DP1N
TX2N
DP2P
TX1P
DP2N
TX1N
DP3P
RX1P
DP3N
RX1N
DP0P
RX1P
DP0N
RX1N
DP1P
TX1P
DP1N
TX1N
DP2P
TX2P
DP2N
TX2N
DP3P
RX2P
DP3N
RX2N
RX1P
SSRXP
RX1N
SSRXN
SSTXP
TX1P
SSTXN
TX1N
DP0P
RX2P
DP0N
RX2N
DP1P
TX2P
DP1N
TX2N
RX2P
SSRXP
RX2N
SSRXN
SSTXP
TX2P
SSTXN
TX2N
DP0P
RX1P
DP0N
RX1N
DP1P
TX1P
DP1N
TX1N
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8.4.2 Device Configuration In I2C Mode
The TUSB1046-DCI is in I2C mode when I2C_EN is not equal to “0”. The same configurations defined in GPIO
mode are also available in I2C mode. The TUSB1046-DCI USB3.1 and DisplayPort configuration is controlled
based on Table 5. The AUXp or AUXn to SBU1 or SBU2 mapping control is based on Table 6.
Table 5. I2C Configuration Control
REGISTERS
TUSB1046-DCI CONFIGURATION
VESA DisplayPort ALT MODE
DFP_D CONFIGURATION
0
Power Down
—
1
Power Down
—
1
0
One Port USB 3.1 - No Flip
—
0
1
1
One Port USB 3.1 – With Flip
—
1
0
0
4 Lane DP - No Flip
C and E
1
0
1
4 Lane DP – With Flip
C and E
1
1
0
One Port USB 3.1 + 2 Lane DP- No Flip
D and F
1
1
1
One Port USB 3.1 + 2 Lane DP– With Flip
D and F
CTLSEL1
CTLSEL0
FLIPSEL
0
0
0
0
0
Table 6. I2C AUXp or AUXn to SBU1 or SBU2 Mapping
REGISTERS
MAPPING
AUX_SBU_OVR
1
AUX_SBU_OVR0
CTLSEL1
FLIPSEL
0
0
1
0
AUXp → SBU1
AUXn → SBU2
0
0
1
1
AUXp → SBU2
AUXn → SBU1
0
0
0
X
Open
0
1
X
X
AUXp → SBU1
AUXn → SBU2
1
0
X
X
AUXp → SBU2
AUXn → SBU1
1
1
X
X
Open
8.4.3 DisplayPort Mode
The TUSB1046-DCI supports up to four DisplayPort lanes at datarates up to 8.1 Gbps. TUSB1046-DCI can be
enabled for DisplayPort through GPIO control or through I2C register control. When I2C_EN is ‘0’, DisplayPort is
controlled based on Table 2. When not in GPIO mode, enable of DisplayPort functionality is controlled through
I2C registers.
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8.4.4 Linear EQ Configuration
Each of the TUSB1046-DCI receiver lanes has individual controls for receiver equalization. The receiver
equalization gain value can be controlled either through I2C registers or through GPIOs. Table 7 details the gain
value for each available combination when TUSB1046-DCI is in GPIO mode. These same options are also
available in I2C mode by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, DP3EQ_SEL, EQ1_SEL,
EQ2_SEL, and SSEQ_SEL.
Table 7. TUSB1046-DCI Receiver Equalization GPIO Control
USB3.1 DOWNSTREAM FACING PORTS
Equalization
Setting #
EQ1 PIN
LEVEL
USB 3.1 UPSTREAM FACING PORT
EQ0 PIN LEVEL
EQ GAIN at
5 GHz (dB)
SSEQ1 PIN
LEVEL
ALL DISPLAYPORT LANES
SSEQ0 PIN
LEVEL
EQ GAIN at 5
GHz (dB)
DPEQ1 PIN
LEVEL
DPEQ0 PIN
LEVEL
EQ GAIN at
4.05 GHz (dB)
0
0
0
-3.9
0
0
-1.8
0
0
1.0
1
0
R
-1.7
0
R
0.2
0
R
3.3
2
0
F
-0.1
0
F
1.7
0
F
4.9
3
0
1
1.4
0
1
3.2
0
1
6.5
4
R
0
2.4
R
0
4.2
R
0
7.5
5
R
R
3.5
R
R
5.3
R
R
8.6
6
R
F
4.4
R
F
6.1
R
F
9.5
7
R
1
5.2
R
1
7.0
R
1
10.4
8
F
0
5.9
F
0
7.7
F
0
11.1
9
F
R
6.6
F
R
8.3
F
R
11.7
10
F
F
7.1
F
F
8.8
F
F
12.3
11
F
1
7.6
F
1
9.3
F
1
12.8
12
1
0
8.0
1
0
9.7
1
0
13.2
13
1
R
8.5
1
R
10.1
1
R
13.6
14
1
F
8.8
1
F
10.4
1
F
14.0
15
1
1
9.2
1
1
10.8
1
1
14.4
8.4.5 USB3.1 Modes
The TUSB1046-DCI monitors the physical layer conditions like receiver termination, electrical idle, LFPS, and
SuperSpeed signaling rate to determine the state of the USB3.1 interface. Depending on the state of the USB
3.1 interface, the TUSB1046-DCI can be in one of four primary modes of operation when USB 3.1 is enabled
(CTL0 = H or CTLSEL0 = 1b1): Disconnect, U2/U3, U1, and U0.
The Disconnect mode is the state in which TUSB1046-DCI has not detected far-end termination on both
upstream facing port (UFP) or downstream facing port (DFP). The disconnect mode is the lowest power mode of
each of the four modes. The TUSB1046-DCI remains in this mode until far-end receiver termination has been
detected on both UFP and DFP. The TUSB1046-DCI immediately exits this mode and enter U0 once far-end
termination is detected.
Once in U0 mode, the TUSB1046-DCI will redrive all traffic received on UFP and DFP. U0 is the highest power
mode of all USB3.1 modes. The TUSB1046-DCI remains in U0 mode until electrical idle occurs on both UFP and
DFP. Upon detecting electrical idle, the TUSB1046-DCI immediately transitions to U1.
The U1 mode is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB1046-DCI
UFP and DFP receiver termination remains enabled. The UFP and DFP transmitter DC common mode is
maintained. The power consumption in U1 is similar to power consumption of U0.
Next to the disconnect mode, the U2/U3 mode is next lowest power state. While in this mode, the TUSB1046DCI periodically performs far-end receiver detection. Anytime the far-end receiver termination is not detected on
either UFP or DFP, the TUSB1046-DCI leaves the U2/U3 mode and transitions to the Disconnect mode. It also
monitors for a valid LFPS. Upon detection of a valid LFPS, the TUSB1046-DCI immediately transitions to the U0
mode. In U2/U3 mode, the TUSB1046-DCI receiver terminations remain enabled but the TX DC common mode
voltage is not maintained.
20
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8.4.6 Operation Timing – Power Up
Tctl_db
TUSB1046-DCI
In I2C mode
DISABLED
TUSB1046-DCI
In GPIO mode
DISABLED
Mode of operation
determined by value of
FLIPSEL bit and CTLSEL[1:0]
bits at offset0x0A. Default
is USB3.1- only no Flip.
USB3.1- only
FLIP = 0
USB3.1- only
FLIP = 0
If (( CTL[1:0 ] == 2'b 00 | CTL[1:0 ] == 2'b 01 ) & FLIP == 0 ) {
USB3.1- only no FLIP;
} ELSEIF((CTL[1:0 ] == 2'b 00 | CTL[1:0 ] == 2'b01 ) & FLIP == 1 ) {
USB3.1- only with FLIP;
} ELSEIF(CTL[1:0 ] == 2'b 10 & FLIP == 0 ) {
4- Lane DP no FLIP;
} ELSEIF(CTL[1:0 ] == 2'b 10 & FLIP == 1 ) {
4- Lane DP with FLIP;
} ELSEIF(CTL[1:0 ] == 2'b 11 & FLIP == 0 ) {
2- Lane DP USB3. 1 no FLIP;
} ELSE{
2- lane DP USB3. 1 with FLIP;
};
CTL[1:0 ] pins
FLIP pin
VCC (min)
VCC
Td_pg
Internal
Power
Good
T Cfg_su
TCfg_hd
CFG pins
Figure 17. Power-Up Timing
Table 8. Power-Up Timing (1) (2)
PARAMETER
MIN
MAX
UNIT
500
µs
td_pg
VCC (minimum) to Internal Power Good asserted high
tcfg_su
CFG(1) pins setup(2)
250
tcfg_hd
CFG(1) pins hold
10
tCTL_DB
CTL[1:0] and FLIP pin debounce
16
ms
tVCC_RAMP
VCC supply ramp requirement
100
ms
(1)
(2)
µs
µs
Following pins comprise CFG pins: I2C_EN, EQ[1:0], SSEQ[1:0], and DPEQ[1:0].
Recommend CFG pins are stable when VCC is at min.
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8.5 Programming
For further programmability, the TUSB1046-DCI can be controlled using I2C. The SCL and SDA pins are used for
I2C clock and I2C data respectively.
Table 9. TUSB1046-DCI I2C Target Address
DPEQ0/A1
PIN LEVEL
SSEQ0/A0
PIN LEVEL
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (W/R)
0
0
1
0
0
0
1
0
0
0/1
0
R
1
0
0
0
1
0
1
0/1
0
F
1
0
0
0
1
1
0
0/1
0
1
1
0
0
0
1
1
1
0/1
R
0
0
1
0
0
0
0
0
0/1
R
R
0
1
0
0
0
0
1
0/1
R
F
0
1
0
0
0
1
0
0/1
R
1
0
1
0
0
0
1
1
0/1
F
0
0
0
1
0
0
0
0
0/1
F
R
0
0
1
0
0
0
1
0/1
F
F
0
0
1
0
0
1
0
0/1
F
1
0
0
1
0
0
1
1
0/1
1
0
0
0
0
1
1
0
0
0/1
1
R
0
0
0
1
1
0
1
0/1
1
F
0
0
0
1
1
1
0
0/1
1
1
0
0
0
1
1
1
1
0/1
The following procedure should be followed to write to TUSB1046-DCI I2C registers:
1. The master initiates a write operation by generating a start condition (S), followed by the TUSB1046-DCI 7bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB1046-DCI acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TUSB1046-DCI) to be written, consisting of one
byte of data, MSB-first.
4. The TUSB1046-DCI acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The TUSB1046-DCI acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the TUSB1046-DCI.
8. The master terminates the write operation by generating a stop condition (P).
The following procedure should be followed to read the TUSB1046-DCI I2C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the TUSB1046-DCI 7-bit
address and a one-value “W/R” bit to indicate a read cycle.
2. The TUSB1046-DCI acknowledges the address cycle.
3. The TUSB1046-DCI transmit the contents of the memory registers MSB-first starting at register 00h or last
read sub-address+1. If a write to the T I2C register occurred prior to the read, then the TUSB1046-DCI shall
start at the sub-address specified in the write.
4. The TUSB1046-DCI shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the
master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the TUSB1046-DCI transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
The following procedure should be followed for setting a starting sub-address for I2C reads:
1. The master initiates a write operation by generating a start condition (S), followed by the TUSB1046-DCI 7bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB1046-DCI acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TUSB1046-DCI) to be written, consisting of one
byte of data, MSB-first.
22
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4. The TUSB1046-DCI acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).
NOTE
If no sub-addressing is included for the read procedure, and reads start at register offset
00h and continue byte by byte through the registers until the I2C master terminates the
read operation. If a I2C address write occurred prior to the read, then the reads start at the
sub-address specified by the address write.
Table 10. Register Legend
ACCESS TAG
NAME
R
Read
The field may be read by software
W
Write
The field may be written by software
S
Set
C
Clear
U
Update
NA
No Access
MEANING
The field may be set by a write of one. Writes of zeros to the field have no effect.
The field may be cleared by a write of one. Write of zero to the field have no effect.
Hardware may autonomously update this field.
Not accessible or not applicable
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8.6 Register Maps
8.6.1 General Register (address = 0x0A) [reset = 00000001]
Figure 18. General Registers
7
Reserved
6
5
SWAP_HPDIN
R
R/W
4
EQ_OVERRID
E
R/W
3
HPDIN_OVRRI
DE
R/W
2
FLIPSEL
1
0
CTLSEL[1:0].
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. General Registers
Bit
Field
Type
Reset
Description
7:6
Reserved.
R
00
Reserved.
SWAP_HPDIN
R/W
0
0 – HPDIN is in default location (Default)
1 – HPDIN location is swapped (PIN 23 to PIN 32, or PIN 32 to
PIN23).
5
4
EQ_OVERRIDE
R/W
0
Setting of this field will allow software to use EQ settings from
registers instead of value sample from pins.
0 – EQ settings based on sampled state of the EQ pins
(SSEQ[1:0], EQ[1:0], and DPEQ[1:0]).
1 – EQ settings based on programmed value of each of the EQ
registers
3
HPDIN_OVRRIDE
R/W
0
0 – HPD IN based on state of HPD_IN pin (Default)
1 – HPD_IN high.
2
FLIPSEL
R/W
0
FLIPSEL. Refer to Table 5 and Table 6 for this field functionality.
01
00 – Disabled. All RX and TX for USB3 and DisplayPort are
disabled.
01 – USB3.1 only enabled. (Default)
10 – Four DisplayPort lanes enabled.
11 – Two DisplayPort lanes and one USB3.1
1:0
CTLSEL[1:0].
R/W
8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
Figure 19. DisplayPort Control/Status Registers (0x10)
7
6
5
4
3
DP1EQ_SEL
R/W/U
2
1
0
DP0EQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. DisplayPort Control/Status Registers (0x10)
Bit
7:4
3:0
24
Field
DP1EQ_SEL
DP0EQ_SEL
Type
R/W/U
R/W/U
Reset
Description
0000
Field selects between 0 to 14dB of EQ for DP lane 1. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 1 based on value written to
this field.
0000
Field selects between 0 to 14dB of EQ for DP lane 0. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 0 based on value written to
this field.
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8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
Figure 20. DisplayPort Control/Status Registers (0x11)
7
6
5
4
3
2
DP3EQ_SEL
R/W/U
1
0
DP2EQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. DisplayPort Control/Status Registers (0x11)
Bit
7:4
3:0
Field
Type
DP3EQ_SEL
R/W/U
DP2EQ_SEL
R/W/U
Reset
Description
0000
Field selects between 0 to 14dB of EQ for DP lane 3. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 3 based on value written to
this field.
0000
Field selects between 0 to 14dB of EQ for DP lane 2. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 2 based on value written to
this field.
8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
Figure 21. DisplayPort Control/Status Registers (0x12)
7
Reserved
R
6
5
SET_POWER_STATE
RU
4
3
2
LANE_COUNT_SET
RU
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. DisplayPort Control/Status Registers (0x12)
Bit
7
6:5
4:0
Field
Type
Reset
Description
Reserved
R
0
Reserved
00
This field represents the snooped value of the AUX write to
DPCD address 0x00600. When AUX_SNOOP_DISABLE = 1’b0,
the TUSB1046-DCI will enable/disable DP lanes based on the
snooped value. When AUX_SNOOP_DISABLE = 1’b1, then DP
lane enable/disable are determined by state of DPx_DISABLE
registers, where x = 0, 1, 2, or 3. This field is reset to 2’b00 by
hardware when CTLSEL1 changes from a 1’b1 to a 1’b0.
00000
This field represents the snooped value of AUX write to DPCD
address 0x00101 register. When AUX_SNOOP_DISABLE =
1’b0, TUSB1046-DCI will enable DP lanes specified by the
snoop value. Unused DP lanes will be disabled to save power.
When AUX_SNOOP_DISABLE = 1’b1, then DP lanes
enable/disable are determined by DPx_DISABLE registers,
where x = 0, 1, 2, or 3. This field is reset to 0x0 by hardware
when CTLSEL1 changes from a 1’b1 to a 1’b0.
SET_POWER_STATE
LANE_COUNT_SET
R/U
R/U
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8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
Figure 22. DisplayPort Control/Status Registers (0x13)
7
AUX_SNOOP_
DISABLE
R/W
6
Reserved
5
4
AUX_SBU_OVR
3
DP3_DISABLE
2
DP2_DISABLE
1
DP1_DISABLE
0
DP0_DISABLE
R
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. DisplayPort Control/Status Registers (0x13)
Bit
Field
Type
Reset
Description
7
AUX_SNOOP_DISABLE
R/W
0
0 – AUX snoop enabled. (Default)
1 – AUX snoop disabled.
6
Reserved
R
0
Reserved
00
This field overrides the AUXp or AUXn to SBU1 or SBU2
connect and disconnect based on CTL1 and FLIP. Changing this
field to 1’b1 will allow traffic to pass through AUX to SBU
regardless of the state of CTLSEL1 and FLIPSEL register
00 – AUX to SBU connect/disconnect determined by CTLSEL1
and FLIPSEL (Default)
01 – AUXp -> SBU1 and AUXn -> SBU2 connection always
enabled.
10 – AUXp -> SBU2 and AUXn -> SBU1 connection always
enabled.
11 = AUX to SBU open.
0
When AUX_SNOOP_DISABLE = 1’b1, this field can be used to
enable or disable DP lane 3. When AUX_SNOOP_DISABLE =
1’b0, changes to this field will have no effect on lane 3
functionality.
0 – DP Lane 3 Enabled (default)
1 – DP Lane 3 Disabled.
0
When AUX_SNOOP_DISABLE = 1’b1, this field can be used to
enable or disable DP lane 2. When AUX_SNOOP_DISABLE =
1’b0, changes to this field will have no effect on lane 2
functionality.
0 – DP Lane 2 Enabled (default)
1 – DP Lane 2 Disabled.
0
When AUX_SNOOP_DISABLE = 1’b1, this field can be used to
enable or disable DP lane 1. When AUX_SNOOP_DISABLE =
1’b0, changes to this field will have no effect on lane 1
functionality.
0 – DP Lane 1 Enabled (default)
1 – DP Lane 1 Disabled.
0
DISABLE. When AUX_SNOOP_DISABLE = 1’b1, this field can
be used to enable or disable DP lane 0. When
AUX_SNOOP_DISABLE = 1’b0, changes to this field will have
no effect on lane 0 functionality.
0 – DP Lane 0 Enabled (default)
1 – DP Lane 0 Disabled.
5:4
3
2
1
0
26
AUX_SBU_OVR
DP3_DISABLE
DP2_DISABLE
DP1_DISABLE
DP0_DISABLE
R/W
R/W
R/W
R/W
R/W
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8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
Figure 23. USB3.1 Control/Status Registers (0x20)
7
6
5
4
3
2
1
EQ2_SEL
R/W/U
0
EQ1_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. USB3.1 Control/Status Registers (0x20)
Bit
Field
7:4
Type
EQ2_SEL
3:0
R/W/U
EQ1_SEL
R/W/U
Reset
Description
0000
Field selects between 0 to 9 dB of EQ for USB3.1 RX2 receiver.
When EQ_OVERRIDE = 1’b0, this field reflects the sampled
state of EQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software
can change the EQ setting for USB3.1 RX2 receiver based on
value written to this field.
0000
Field selects between 0 to 9 dB of EQ for USB3.1 RX1 receiver.
When EQ_OVERRIDE = 1’b0, this field reflects the sampled
state of EQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software
can change the EQ setting for USB3.1 RX1 receiver based on
value written to this field.
8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
Figure 24. USB3.1 Control/Status Registers (0x21)
7
6
5
4
3
Reserved
R
2
1
0
SSEQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. USB3.1 Control/Status Registers (0x21)
Bit
Field
Type
Reset
Description
7:4
Reserved
R
0000
Reserved
0000
Field selects between 0 to 11 dB of EQ for USB3.1 SSTXP/N
receiver. When EQ_OVERRIDE = 1’b0, this field reflects the
sampled state of SSEQ[1:0] pins. When EQ_OVERRIDE = 1’b1,
software can change the EQ setting for USB3.1 SSTXP/N
receiver based on value written to this field.
3:0
SSEQ_SEL
R/W/U
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8.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000100]
Figure 25. USB3.1 Control/Status Registers (0x22)
7
CM_ACTIVE
6
LFPS_EQ
R/U
R/W
5
U2U3_LFPS_D
EBOUNCE
R/W
4
DISABLE_U2U
3_RXDET
R/W
3
2
DFP_RXDET_INTERVAL
1
0
USB3_COMPLIANCE_CTRL
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. USB3.1 Control/Status Registers (0x22)
Bit
7
Type
Reset
Description
CM_ACTIVE
R/U
0
0 –device not in USB 3.1 compliance mode. (Default)
1 –device in USB 3.1 compliance mode
6
LFPS_EQ
R/W
0
Controls whether settings of EQ based on EQ1_SEL, EQ2_SEL
and SSEQ_SEL applies to received LFPS signal.
0 – EQ set to zero when receiving LFPS (default)
1 – EQ set to EQ1_SEL, EQ2_SEL, and SSEQ_SEL when
receiving LFPS.
5
U2U3_LFPS_DEBOUNCE
R/W
0
0 – No debounce of LFPS before U2/U3 exit. (Default)
1 – 200us debounce of LFPS before U2/U3 exit.
4
DISABLE_U2U3_RXDET
R/W
0
0 – Rx.Detect in U2/U3 enabled. (Default)
1 – Rx.Detect in U2/U3 disabled.
01
This field controls the Rx.Detect interval for the Downstream
facing port (TX1P/N and TX2P/N).
00 – 8 ms
01 – 12 ms (default)
10 – 48 ms
11 – 96 ms
00
00 – FSM determined compliance mode. (Default)
01 – Compliance Mode enabled in DFP direction (SSTX ->
TX1/TX2)
10 – Compliance Mode enabled in UFP direction (RX1/RX2 ->
SSRX)
11 – Compliance Mode Disabled.
3:2
1:0
28
Field
DFP_RXDET_INTERVAL
USB3_COMPLIANCE_CTRL
R/W
R/W
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TUSB1046-DCI is a linear redriver designed specifically to compensation for intersymbol interference (ISI)
jitter caused by signal attenuation through a passive medium like PCB traces and cables. Because the
TUSB1046-DCI has four independent DisplayPort 1.4 inputs, one upstream facing USB 3.1 Gen1/Gen2 input,
and two downstream facing USB 3.1 Gen1/Gen2 inputs, it can be optimized to correct ISI on all those seven
inputs through 16 different equalization choices. Placing the TUSB1046-DCI between a USB3.1 Host/DisplayPort
1.4 GPU and a USB3.1 Type-C receptacle can correct signal integrity issues resulting in a more robust system.
9.2 Typical Application
A
B
F
E
PCB Trace of Length XAB
PCB Trace of Length XEF
SSRXP
SSRXN
USB3.1
Host
SSTXP
RX2P
SSTXN
RX2N
TX2P
Type-C
Receptacle
TX2N
TUSB1046-DCI
DP0P
DP0N
DP 1.4
GPU
DP1P
TX1N
DP1N
TX1P
DP2P
RX1N
DP2N
RX1P
DP3P
DP3N
PCB Trace of Length XCD
C
PCB Trace of Length XGH
D
G
H
Copyright © 2016, Texas Instruments Incorporated
Figure 26. TUSB1046-DCI in a Host Application
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters shown in Table 19.
Table 19. Design Parameters
PARAMETER
VALUE
A to B PCB trace length, XAB
12 inches
C to D PCB trace length, XCD
12 inches
E to F PCB trace length, XEF
2 inches
G to H PCB trace length, XGH
2 inches
PCB trace width
4 mils
AC-coupling capacitor (75 nF to 265 nF)
100 nF
VCC supply (3 V to 3.6 V)
3.3 V
I2C Mode or GPIO Mode
I2C Mode. (I2C_EN pin != "0")
1.8V or 3.3V I2C Interface
3.3V I2C. Pull-up the I2C_EN pin to 3.3V with a 1K
ohm resistor.
9.2.2 Detailed Design Procedure
A typical usage of the TUSB1046-DCI device is shown in Figure 27. The device can be controlled either through
its GPIO pins or through its I2C interface. In the example shown below, a Type-C PD controller is used to
configure the device through the I2C interface. When configured for I2C mode, pins 29 (RSVD1) and 32 (RSVD2)
can be left unconnected. In I2C mode, the equalization settings for each receiver can be independently controlled
through I2C registers. For this reason, all of the equalization pins (EQ[1:0], SSEQ[1:0], and DPEQ[1:0]) can be
left unconnected. If these pins are left unconnected, the TUSB1046-DCI 7-bit I2C slave address will be 0x12
because both DPEQ/A1 and SSEQ0/A0 will be at pin level "F". If a different I2C slave address is desired,
DPEQ/A1 and SSEQ0/A0 pins should be set to a level which produces the desired I2C slave address.
30
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3.3V
10PF
100nF
100nF
SSRXP
RX2P
SSRXN
RX2N
100nF
SSRXN
USB Type-C
Receptacle
100nF
100nF
SSTXP
SSTXP
TX2P
SSTXN
TX2N
100nF
SSTXN
100nF
VCC
VCC
VCC
100nF
SSRXP
VCC
USB 3.1 Host
100nF
A12
100nF
GND
A11
RXP2
A10
RXN2
A9
VBUS
SBU1
A8
SBU1
SBU2
A7
DN1
A6
DP1
A5
CC1
A4
VBUS
A3
TXN1
A2
TXP1
A1
GND
RSVD2
B1
GND
B2
TXP2
B3
TXN2
B4
VBUS
B5
CC2
B6
DP2
B7
DN2
B8
SBU2
B9
VBUS
B10
RXN1
B11
RXP1
B12
GND
100K
DP1.4
GPU
AUXP
AUXN
100nF
RSVD1
AUXP
100nF
AUXN
100nF
DP_ML0P
DP0P
100nF
DP_ML0N
TUSB1046-DCI
DP_PWR (3.3V)
100K
2M
2M
DP0N
100nF
DP_ML1P
DP1P
100nF
DP1N
DP_ML1N
100 nF
100nF
DP_ML2P
DP2P
TX1N
100 nF
100nF
DP_ML2N
DP2N
TX1P
DP3P
RX1N
100nF
DP_ML3P
100nF
DP_ML3N
RX1P
DP3N
3.3V
I2C_EN
3.3V
3.3V
SSEQ0/A0
VI2C
SSEQ1
R
R
DPEQ0/A1
3.3V
FLIP/SCL
DPEQ1
3.3V
3.3V
3.3V
EQ0
CTL0/SDA
EQ1
CTL1/HPDIN
Type-C
PD
Controller
TP
Copyright © 2016, Texas Instruments Incorporated
Figure 27. Application Circuit
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9.2.3 Application Curve
0
-5
-10
Insertion Loss (dB)
-15
-20
-25
-30
-35
Length=12in, Width=6mil
Length=16in, Width=6mil
Length=20in, Width=6mil
Length=24in, Width=6mil
Length=4in, Width=4mil
Length=8in, Width=10mil
Length=8in, Width=6mil
-40
-45
-50
-55
-60
0
2
4
6
8
10
Frequency (GHz)
12
14
16
D009
Figure 28. Insertion Loss of FR4 PCB Traces
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9.3 System Examples
9.3.1 USB 3.1 Only
The TUSB1046-DCI is in USB3.1 only when the CTL1 pin is low and CTL0 pin is high.
D+/-
USB Host
SSTX
D+/-
1 Port USB
TUSB1064-DCI
TUSB1046-DCI
SSTX
SSRX
TX2
RX1
TX1
DP1
RX1
DP2
GPU
DP3
AUXp
SBU1
AUXn
SBU2
HPDIN
Type-C Receptacle
TX1
Type-C Receptacle
RX2
DP0
RX2
DP0
TX2
DP1
DP2
DP RX
DP3
SBU2
AUXp
HPDIN
FLIP 0 1 CTL
CC1
PD Controller
AUXn
SBU1
FLIP 0 1 CTL
HPD
Control
USB Hub
SSRX
CC2
CC1
CC2
HPD
PD Controller
Control
CTL1/0/FLIP=L/H/H
CTL1/0/FLIP=L/H/H
Copyright © 2016, Texas Instruments Incorporated
Figure 29. USB3.1 Only – No Flip (CTL1 = L, CTL0 = H, FLIP = L)
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System Examples (continued)
D+/-
USB Host
SSTX
D+/-
1 Port USB
TUSB1064-DCI
TUSB1046-DCI
SSTX
SSRX
TX2
RX1
TX1
DP1
RX1
DP2
GPU
DP3
AUXp
SBU1
AUXn
SBU2
HPDIN
Type-C Receptacle
TX1
Type-C Receptacle
RX2
DP0
RX2
DP0
TX2
DP1
DP2
DP RX
DP3
SBU2
AUXp
HPDIN
FLIP 0 1 CTL
CC1
PD Controller
AUXn
SBU1
FLIP 0 1 CTL
HPD
Control
USB Hub
SSRX
CC2
CC1
CC2
HPD
PD Controller
Control
CTL1/0/FLIP=L/H/H
CTL1/0/FLIP=L/H/H
Copyright © 2016, Texas Instruments Incorporated
Figure 30. USB3.1 Only – With Flip (CTL1 = L, CTL0 = H, FLIP = H)
34
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System Examples (continued)
9.3.2 USB 3.1 and 2 Lanes of DisplayPort
The TUSB1046-DCI operates in USB3.1 and 2 Lanes of DisplayPort mode when the CTL1 pin is high and CTL0
pin is high.
1 Port USB &
2 Lane DP
D+/-
USB Host
SSTX
D+/-
TUSB1046-DCI
TUSB1064-DCI
SSTX
SSRX
TX2
RX1
TX1
DP1
RX1
DP2
GPU
DP3
Type-C Receptacle
TX1
Type-C Receptacle
RX2
DP0
RX2
DP0
TX2
DP1
DP2
DP RX
DP3
AUXp
SBU1
SBU1
AUXn
SBU2
SBU2
AUXn
AUXp
HPDIN
HPD
Control
USB Hub
SSRX
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
PD Controller
CC1
CC1
CC2
CC2
CTL1/0/FLIP=H/H/L
HPD
PD Controller
Control
CTL1/0/FLIP=H/H/L
Copyright © 2016, Texas Instruments Incorporated
Figure 31. USB3.1 + 2 Lane DP – No Flip (CTL1 = H, CTL0 = H, FLIP = L)
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System Examples (continued)
1 Port USB &
2 Lane DP
D+/-
USB Host
D+/-
TUSB1046-DCI
SSTX
TUSB1064-DCI
SSRX
SSTX
SSRX
TX2
RX1
TX1
DP1
RX1
DP2
GPU
DP3
Type-C Receptacle
TX1
Type-C Receptacle
RX2
DP0
RX2
DP0
TX2
DP1
DP2
DP RX
DP3
AUXp
SBU1
SBU1
AUXn
SBU2
SBU2
AUXn
AUXp
HPDIN
HPDIN
FLIP 0 1 CTL
HPD
Control
USB Hub
PD Controller
FLIP 0 1 CTL
CC1
CC1
CC2
CC2
HPD
PD Controller
Control
CTL1/0/FLIP=H/H/H
CTL1/0/FLIP=H/H/H
Copyright © 2016, Texas Instruments Incorporated
Figure 32. USB 3.1 + 2 Lane DP – Flip (CTL1 = H, CTL0 = H, FLIP = H)
36
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System Examples (continued)
9.3.3 DisplayPort Only
The TUSB1046-DCI operates in 4 Lanes of DisplayPort only mode when the CTL1 pin is high and CTL0 pin is
low.
D+/-
USB Host
SSTX
D+/-
4 Lane DP
TUSB1064-DCI
TUSB1046-DCI
SSRX
SSTX
SSRX
TX2
RX1
TX1
DP1
RX1
DP2
GPU
DP3
Type-C Receptacle
TX1
Type-C Receptacle
RX2
DP0
RX2
DP0
TX2
DP1
DP2
DP RX
DP3
AUXp
SBU1
SBU1
AUXn
AUXn
HPDIN
SBU2
SBU2
AUXp
HPDIN
HPD
Control
USB Hub
FLIP 0 1 CTL
PD Controller
FLIP 0 1 CTL
CC1
CC1
CC2
CC2
HPD
PD Controller
Control
CTL1/0/FLIP=H/L/L
CTL1/0/FLIP=H/L/L
Copyright © 2016, Texas Instruments Incorporated
Figure 33. Four Lane DP – No Flip (CTL1 = H, CTL0 = L, FLIP = L)
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System Examples (continued)
D+/-
USB Host
SSTX
D+/-
4 Lane DP
TUSB1046-DCI
TUSB1064-DCI
SSRX
SSTX
TX2
RX1
TX1
DP1
RX1
DP2
GPU
DP3
Type-C Receptacle
TX1
Type-C Receptacle
RX2
DP0
RX2
DP0
TX2
DP1
DP2
DP RX
DP3
AUXp
SBU1
SBU1
AUXn
HPDIN
SBU2
SBU2
AUXn
AUXp
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
Control
USB Hub
SSRX
PD Controller
CC1
CC1
CC2
CC2
CTL1/0/FLIP=H/L/H
PD Controller
HPD
Control
CTL1/0/FLIP=H/L/H
Copyright © 2016, Texas Instruments Incorporated
Figure 34. Four Lane DP – With Flip (CTL1 = H, CTL0 = L, FLIP = H)
10 Power Supply Recommendations
The TUSB1046-DCI is designed to operate with a 3.3-V power supply. Levels above those listed in the Absolute
Maximum Ratings table should not be used. If using a higher voltage system power supply, a voltage regulator
can be used to step down to 3.3 V. Decoupling capacitors should be used to reduce noise and improve power
supply integrity. A 0.1-µF capacitor should be used on each power pin.
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11 Layout
11.1 Layout Guidelines
1.
2.
3.
4.
5.
6.
RXP/N and TXP/N pairs should be routed with controlled 90-Ω differential impedance (±15%).
Keep away from other high speed signals.
Intra-pair routing should be kept to within 2 mils.
Length matching should be near the location of mismatch.
Each pair should be separated at least by 3 times the signal trace width.
The use of bends in differential traces should be kept to a minimum. When bends are used, the number of
left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This
will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on
EMI.
7. Route all differential pairs on the same of layer.
8. The number of vias should be kept to a minimum. It is recommended to keep the vias count to 2 or less.
9. Keep traces on layers adjacent to ground plane.
10. Do not route differential pairs over any plane split.
11. Adding Test points will cause impedance discontinuity, and therefore, negatively impact signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes a stub on the differential pair.
11.2 Layout Example
SSRX
SSTX
To USB Host
DP1
TX2
DP2
TX1
DP3
RX1
To USB Type-C
Receptacle
RX2
SBU
DP0
AUX
To GPU
AC Coupling
capacitors
Figure 35. Layout Example
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 20. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TUSB1046-DCI
Click here
Click here
Click here
Click here
Click here
TUSB1046I-DCI
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
VESA is a registered trademark of Video Electronics Standards Association Corporation California.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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21-Mar-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TUSB1046-DCIRNQR
ACTIVE
WQFN
RNQ
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
TUSB46D
TUSB1046-DCIRNQT
ACTIVE
WQFN
RNQ
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
TUSB46D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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21-Mar-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TUSB1046-DCIRNQR
WQFN
RNQ
40
3000
330.0
12.4
4.3
6.3
1.1
8.0
12.0
Q2
TUSB1046-DCIRNQT
WQFN
RNQ
40
250
180.0
12.4
4.3
6.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TUSB1046-DCIRNQR
WQFN
RNQ
40
3000
367.0
367.0
35.0
TUSB1046-DCIRNQT
WQFN
RNQ
40
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RNQ0040A
WQFN - 0.8 mm max height
SCALE 2.500
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
A
B
PIN 1 INDEX AREA
4.1
3.9
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08
4.7±0.1
2X 4.4
(0.2) TYP
9
36X 0.4
20
8
EXPOSED
THERMAL PAD
21
2X
2.8
2.7±0.1
1
PIN 1 ID
(OPTIONAL)
28
29
40
40X
0.5
0.3
0.25
0.15
0.1
C A
0.05
40X
B
4222125/B 01/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.7)
2X (2.1)
6X (0.75)
40
29
40X (0.6)
1
28
40X (0.2)
4X
(1.1)
SYMM
(3.8)
(2.7)
36X (0.4)
8
21
(R0.05) TYP
9
20
SYMM
( 0.2) TYP
VIA
(5.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222125/B 01/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (1.5)
40
29
40X (0.6)
1
28
40X (0.2)
6X
(0.695)
SYMM
(3.8)
6X
(1.19)
36X (0.4)
8
21
(R0.05) TYP
METAL
TYP
9
6X (1.3)
20
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
73% PRINTED SOLDER COVERAGE BY AREA
SCALE:18X
4222125/B 01/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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