Texas Instruments | TCA9555 Low-Voltage 16-Bit I2C and SMBus I/O Expander with Interrupt Output and Configuration Registers (Rev. E) | Datasheet | Texas Instruments TCA9555 Low-Voltage 16-Bit I2C and SMBus I/O Expander with Interrupt Output and Configuration Registers (Rev. E) Datasheet

Texas Instruments TCA9555 Low-Voltage 16-Bit I2C and SMBus I/O Expander with Interrupt Output and Configuration Registers (Rev. E) Datasheet
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TCA9555
SCPS200E – JULY 2009 – REVISED APRIL 2019
TCA9555 Low-Voltage 16-Bit I2C and SMBus I/O
Expander with Interrupt Output and Configuration Registers
1 Features
3 Description
•
This 16-bit I/O expander for the two-line bidirectional
bus (I2C) is designed for 1.65-V to 5.5-V VCC
operation. It provides general-purpose remote I/O
expansion for most microcontroller families via the I2C
interface.
1
•
•
•
•
•
•
•
•
•
•
Low Standby-Current Consumption of
3.5 μA Maximum
I2C to Parallel Port Expander
Open-Drain Active-Low Interrupt Output
5-V Tolerant I/O Ports
Compatible With Most Microcontrollers
400-kHz Fast I2C Bus
Configurable Slave Address with 3 Address Pins
Polarity Inversion Register
Latched Outputs With High-Current Drive
Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
The TCA9555 consists of two 8-bit Configuration
(input or output selection), Input Port, Output Port,
and Polarity Inversion (active high or active low
operation) registers. At power on, the I/Os are
configured as inputs. The system master can enable
the I/Os as either inputs or outputs by writing to the
I/O configuration bits. The data for each input or
output is kept in the corresponding Input or Output
register. The polarity of the Input Port register can be
inverted with the Polarity Inversion register.
Device Information(1)
PART NUMBER
TCA9555
2 Applications
•
•
•
•
•
•
Servers
Routers (Telecom Switching Equipment)
Personal Computers
Personal Electronics
Industrial Automation Equipment
Products with GPIO-Limited Processors
PACKAGE
BODY SIZE (NOM)
TSSOP (24) PW
7.80 mm x 4.40 mm
SSOP (24) DB
8.20 mm x 5.30 mm
WQFN (24) RTW
4.00 mm x 4.00 mm
VQFN (24) RGE
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VCC
I2C or SMBus Master
P00
Peripheral
Devices
SDA
P01
SCL
P02
INT
P03
x
P04
x
(e.g. Processor)
P05
P06
x
x
RESET, EN or
Control Inputs
INT or status
outputs
LEDs
Keypad
P07
TCA9555
P10
P11
P12
P13
A2
P14
A1
P15
A0
P16
GND
P17
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA9555
SCPS200E – JULY 2009 – REVISED APRIL 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
5
5
5
6
6
7
8
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Interface Timing Requirements..........................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 12
Detailed Description ............................................ 15
9.1 Overview ................................................................. 15
9.2 Functional Block Diagram ....................................... 15
9.3
9.4
9.5
9.6
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
15
16
16
24
10 Application and Implementation........................ 25
10.1 Application Information.......................................... 25
10.2 Typical Application ............................................... 25
11 Power Supply Recommendations ..................... 29
12 Layout................................................................... 31
12.1 Layout Guidelines ................................................. 31
12.2 Layout Example .................................................... 31
13 Device and Documentation Support ................. 32
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
32
14 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (July 2016) to Revision E
Page
•
Changed the Device Information table ................................................................................................................................... 1
•
Changed the Pin Configuration images ................................................................................................................................. 4
Changes from Revision C (June 2016) to Revision D
•
Added DB Package to the Device Information table .............................................................................................................. 1
Changes from Revision A (July 2009) to Revision B
•
Page
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision B (July 2015) to Revision C
Page
•
Added RGE Package to the Device Information table ........................................................................................................... 1
•
Changed VIH for I2C pins limited to VCC, with note allowing higher voltage .......................................................................... 5
•
Added IOL for different Tj ........................................................................................................................................................ 5
•
Removed ΔICC spec from the Electrical Characteristics table, added ΔICC typical characteristics graph .............................. 6
•
Changed ICC standby into different input states...................................................................................................................... 7
•
Changed Cio maximum .......................................................................................................................................................... 7
•
Changed Typical characteristic plots with updated data ........................................................................................................ 9
•
POR requirements, bounded lowest voltage allowed during glitch ..................................................................................... 30
2
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SCPS200E – JULY 2009 – REVISED APRIL 2019
5 Description (continued)
The TCA9555 is identical to the TCA9535, except for the inclusion of the internal I/O pull-up resistor, which pulls
the I/O to a default high when configured as an input and undriven.
Three hardware pins (A0, A1, and A2) are used to program the I2C address, which allows up to eight TCA9555
devices to share the same I2C bus or SMBus. The fixed I2C address of the TCA9555 is the same as the
PCF8575, PCF8575C, and PCF8574, allowing up to eight of these devices in any combination to share the same
I2C bus or SMBus.
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SCPS200E – JULY 2009 – REVISED APRIL 2019
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6 Pin Configuration and Functions
DB, PW Package
24-Pin TSSOP
Top View
P16
P03
7
18
P15
P04
8
17
P14
P05
9
16
P13
P06
10
15
P12
P07
11
14
P11
GND
12
13
P10
SCL
19
19
6
A0
P01
2
17
P17
P02
3
16
P16
P03
4
15
P15
P04
5
14
P14
P05
6
13
P13
Th ermal
Pad
12
P02
18
P12
P17
SDA
20
20
5
1
11
P01
P00
P11
A0
VCC
21
21
4
10
P00
P10
SCL
INT
22
22
3
9
A2
GND
SDA
A1
23
A2
2
23
A1
8
VCC
7
24
P07
1
P06
INT
24
RTW, RGE Package
24-Pin WQFN, VQFN with Exposed Thermal Pad
Top View
No t to scale
The exposed thermal pad, if used, must be
connected as a secondary ground or left
electrically open.
No t to scale
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
DB, PW
RTW,
RGE
A0
21
18
Input
Address input 0. Connect directly to VCC or ground
A1
2
23
Input
Address input 1. Connect directly to VCC or ground
A2
3
24
Input
Address input 2. Connect directly to VCC or ground
GND
12
9
GND
Ground
INT
1
22
Output
P00
4
1
I/O
P-port I/O. Push-pull design structure. At power on, P00 is configured as an input
P01
5
2
I/O
P-port I/O. Push-pull design structure. At power on, P01 is configured as an input
P02
6
3
I/O
P-port I/O. Push-pull design structure. At power on, P02 is configured as an input
P03
7
4
I/O
P-port I/O. Push-pull design structure. At power on, P03 is configured as an input
P04
8
5
I/O
P-port I/O. Push-pull design structure. At power on, P04 is configured as an input
P05
9
6
I/O
P-port I/O. Push-pull design structure. At power on, P05 is configured as an input
P06
10
7
I/O
P-port I/O. Push-pull design structure. At power on, P06 is configured as an input
P07
11
8
I/O
P-port I/O. Push-pull design structure. At power on, P07 is configured as an input
P10
13
10
I/O
P-port I/O. Push-pull design structure. At power on, P10 is configured as an input
P11
14
11
I/O
P-port I/O. Push-pull design structure. At power on, P11 is configured as an input
P12
15
12
I/O
P-port I/O. Push-pull design structure. At power on, P12 is configured as an input
P13
16
13
I/O
P-port I/O. Push-pull design structure. At power on, P13 is configured as an input
P14
17
14
I/O
P-port I/O. Push-pull design structure. At power on, P14 is configured as an input
P15
18
15
I/O
P-port I/O. Push-pull design structure. At power on, P15 is configured as an input
P16
19
16
I/O
P-port I/O. Push-pull design structure. At power on, P16 is configured as an input
P17
20
17
I/O
P-port I/O. Push-pull design structure. At power on, P17 is configured as an input
SCL
22
19
Input
Serial clock bus. Connect to VCC through a pull-up resistor
SDA
23
20
Input
Serial data bus. Connect to VCC through a pull-up resistor
VCC
24
21
Supply
4
Interrupt output. Connect to VCC through a pull-up resistor
Supply voltage
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6
V
(2)
–0.5
6
V
–0.5
6
V
VI
Input voltage
VO
Output voltage (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IIOK
Input-output clamp current
VO < 0 or VO > VCC
±20
mA
IOL
Continuous output low current
VO = 0 to VCC
50
mA
IOH
Continuous output high current
VO = 0 to VCC
–50
mA
Continuous current through GND
–250
Continuous current through VCC
160
Tj(MAX)
Maximum junction temperature
100
°C
Tstg
Storage temperature
150
°C
ICC
(1)
(2)
–65
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101
or ANSI/ESDA/JEDEC JS-002 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VCC
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current (2)
IOL
Low-level output current (2)
TA
Operating free-air temperature
(1)
(2)
MIN
MAX
1.65
5.5
SCL, SDA
0.7 × VCC
(1)
A2–A0, P07–P00, P17–P10
0.7 × VCC
Supply voltage
VCC
5.5
SCL, SDA
–0.5 0.3 × VCC
A2–A0, P07–P00, P17–P10
–0.5 0.3 × VCC
P07–P00, P17–P10
P07–P00, P17–P10
INT, SDA
–10
Tj ≤ 65°C
25
Tj ≤ 85°C
18
Tj ≤ 100°C
11
Tj ≤ 85°C
6
Tj ≤ 100°C
3.5
–40
85
UNIT
V
V
V
mA
mA
mA
°C
For voltages applied above VCC, an increase in ICC results.
The values shown apply to specific junction temperatures, which depend on the RθJA of the package used. See the Calculating Junction
Temperature and Power Dissipation section on how to calculate the junction temperature.
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7.4 Thermal Information
TCA9555
THERMAL METRIC
(1)
PW
(TSSOP)
DB
(SSOP)
RTW
(WQFN)
RGE
(VQFN)
24 PINS
24 PINS
24 PINS
24 PINS
108.8
92.9
43.6
48.4
°C/W
54
53.5
46.2
58.1
°C/W
22.1
27.1
°C/W
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
62.8
50.4
ψJT
Junction-to-top characterization parameter
11.1
21.9
1.5
3.3
°C/W
ψJB
Junction-to-board characterization parameter
62.3
50.1
22.2
27.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
10.7
15.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
Input diode clamp voltage
VCC
MIN
–1.2
II = –18 mA
1.65 V to 5.5 V
VPORR Power-on reset voltage, VCC rising
VI = VCC or GND, IO = 0
1.65 V to 5.5 V
VPORF Power-on reset voltage, VCC falling
VI = VCC or GND, IO = 0
1.65 V to 5.5 V
0.75
1.65 V
1.2
2.3 V
1.8
3V
2.6
4.75 V
4.1
1.65 V
1
2.3 V
1.7
3V
2.5
IOH = –8 mA
VOH
P-port high-level output voltage (2)
IOH = –10 mA
II
Low-level output current
Input leakage current
V
1.2
1.5
V
1
V
V
4.75 V
4
VOL = 0.4 V
1.65 V to 5.5 V
3
mA
VOL = 0.5 V
1.65 V to 5.5 V
8
mA
VOL = 0.7 V
1.65 V to 5.5 V
10
mA
INT
VOL = 0.4 V
1.65 V to 5.5 V
3
mA
SCL,
SDA
Input
leakage
VI = VCC or GND
1.65 V to 5.5 V
±1
μA
A2–A0
Input
leakage
VI = VCC or GND
1.65 V to 5.5 V
±1
μA
SDA
IOL
TYP (1) MAX UNIT
P port (3)
IIH
Input high leakage current
P port
VI = VCC
1.65 V to 5.5 V
1
μA
IIL
Input low leakage current
P port
VI = GND
1.65 V to 5.5 V
–100
μA
(1)
(2)
(3)
6
All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V VCC) and TA = 25°C.
Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07–P00 and P17–P10) must be limited to a maximum
current of 100 mA, for a device total of 200 mA.
The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10).
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IO = 0,
I/O = inputs, fSCL = 400 kHz, tr
= 3 ns, No load
Operating
mode
ICC
Low
inputs
Quiescent current
VI = GND, IO = 0, I/O = inputs,
fSCL = 0 kHz, No load
Standby
mode
CI
Input capacitance
Cio
Input-output pin capacitance
7.6
VCC
MIN
5.5 V
22
40
3.6 V
11
30
2.7 V
8
19
1.95 V
5
11
5.5 V
1.1
1.5
3.6 V
0.7
1.3
2.7 V
0.5
1
1.95 V
0.3
0.9
5.5 V
2.5
3.5
3.6 V
1
1.8
2.7 V
0.7
1.6
1.95 V
0.5
1
3
8
3
9.5
3.7
9.5
High
inputs
VI = VCC, IO = 0, I/O = inputs,
fSCL = 0 kHz, No load
SCL
VI = VCC or GND
1.65 V to 5.5 V
VIO = VCC or GND
1.65 V to 5.5 V
SDA
P port
TYP (1) MAX UNIT
μA
mA
μA
pF
pF
I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 19)
MIN
MAX
UNIT
100
kHz
2
I C BUS—STANDARD MODE
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
2
tscl
I C clock low time
tsp
I2C spike time
tsds
I2C serial-data setup time
µs
4.7
µs
50
250
2
ns
ns
tsdh
I C serial-data hold time
ticr
I2C input rise time
0
1000
ns
ticf
I2C input fall time
300
ns
tocf
I2C output fall time
300
ns
10-pF to 400-pF bus
2
ns
tbuf
I C bus free time between stop and start
4.7
µs
tsts
I2C start or repeated start condition setup
4.7
µs
tsth
I2C start or repeated start condition hold
4
µs
2
tsps
I C stop condition setup
tvd(data)
Valid data time
SCL low to SDA output valid
4
3.45
µs
µs
tvd(ack)
Valid data time of ACK condition
ACK signal from SCL low to
SDA (out) low
3.45
µs
Cb
I2C bus capacitive load
400
pF
400
kHz
2
I C BUS—FAST MODE
fscl
I2C clock frequency
0
2
tsch
I C clock high time
0.6
tscl
I2C clock low time
1.3
tsp
I2C spike time
I C serial-data setup time
tsdh
I2C serial-data hold time
ticr
I2C input rise time
µs
50
2
tsds
µs
100
ns
0
20
ns
300
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ns
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I2C Interface Timing Requirements (continued)
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 19)
MIN
MAX
UNIT
20 × (VCC /
5.5 V)
300
ns
20 × (VCC /
5.5 V)
300
ns
ticf
I2C input fall time
tocf
I2C output fall time
tbuf
I2C bus free time between stop and start
1.3
µs
tsts
I2C start or repeated start condition setup
0.6
µs
tsth
I2C start or repeated start condition hold
0.6
µs
10-pF to 400-pF bus
2
tsps
I C stop condition setup
tvd(data)
Valid data time
SCL low to SDA output valid
0.6
0.9
µs
µs
tvd(ack)
Valid data time of ACK condition
ACK signal from SCL low to
SDA (out) low
0.9
µs
Cb
I2C bus capacitive load
400
pF
7.7 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 20 and Figure 21)
PARAMETER
tiv
Interrupt valid time
tir
Interrupt reset delay time
tpv
Output data valid; For VCC = 2.3 V–5.5 V
Output data valid; For VCC = 1.65 V–2.3 V
FROM
(INPUT)
TO
(OUTPUT)
P port
INT
4
SCL
INT
4
μs
200
ns
300
ns
SCL
P port
MIN
MAX
UNIT
μs
tps
Input data setup time
P port
SCL
150
ns
tph
Input data hold time
P port
SCL
1
μs
8
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7.8 Typical Characteristics
TA = 25°C (unless otherwise noted)
40
2.2
Vcc = 1.65 V
Vcc = 1.8 V
Vcc = 2.5 V
32
Vcc = 3.3 V
Vcc = 3.6 V
Vcc = 5 V
Vcc = 5.5V
28
24
20
16
12
8
4
-15
10
35
TA - Temperature (°C)
60
Vcc = 5.5V
1.6
1.4
1.2
1
0.8
0.6
0.2
-40
85
-15
D001
Figure 1. Supply Current vs Temperature for Different
Supply Voltage (VCC)
10
35
TA - Temperature (°C)
60
85
D002
Figure 2. Standby Supply Current vs Temperature for
Different Supply Voltage (VCC)
30
30
-40qC
25qC
85qC
-40qC
25qC
85qC
25
IOL - Sink Current (mA)
25
ICC - Supply Current (µA)
1.8
Vcc = 3.3 V
Vcc = 3.6 V
Vcc = 5 V
0.4
0
-40
20
15
10
5
20 VCC = 1.65 V
15
10
5
0
1.5
0
2
2.5
3
3.5
4
4.5
VCC - Supply Voltage (V)
5
5.5
0
0.1
D003
Figure 3. Supply Current vs Supply Voltage for Different
Temperature (TA)
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
D004
Figure 4. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 1.65 V
60
35
25
IOL - Sink Current (mA)
-40qC
25qC
85qC
30
IOL - Sink Current (mA)
Vcc = 1.65 V
Vcc = 1.8 V
Vcc = 2.5 V
2
ICC - Supply Current (µA)
ICC - Supply Current (µA)
36
VCC = 1.8 V
20
15
10
50
-40qC
25qC
85qC
40
VCC = 2.5 V
30
20
10
5
0
0
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
0
D005
Figure 5. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 1.8 V
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
D006
Figure 6. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 2.5 V
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
80
70
-40qC
25qC
85qC
50
VCC = 3.3 V
40
30
20
10
60
VCC = 5 V
50
40
30
20
10
0
0
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0
0.7
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
D007
Figure 7. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 3.3 V
0.6
0.7
D009
Figure 8. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 5 V
300
90
70
VOL - Output Low Voltage (V)
-40qC
25qC
85qC
80
IOL - Sink Current (mA)
-40qC
25qC
85qC
70
IOL - Sink Current (mA)
IOL - Sink Current (mA)
60
VCC = 5.5 V
60
50
40
30
20
1.8 V, 1 mA
1.8 V, 10 mA
3.3 V, 1mA
250
3.3 V, 10 mA
5 V, 1 mA
5 V, 10 mA
200
150
100
50
10
0
-40
0
0
0.1
0.2
0.3
0.4
0.5
VOL - Output Low Voltage (V)
0.6
0.7
Figure 9. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 5.5 V
60
85
D011
25
-40qC
25qC
85qC
IOH - Source Current (mA)
IOH - Source Current (mA)
10
35
TA - Temperature (°C)
Figure 10. I/O Low Voltage vs Temperature for Different VCC
and IOL
20
15
VCC = 1.65 V
10
5
-40qC
25qC
85qC
20
VCC = 1.8 V
15
10
5
0
0
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
0
D012
Figure 11. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 1.65 V
10
-15
D010
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
D013
Figure 12. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 1.8 V
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
60
40
IOH - Source Current (mA)
35
IOH - Source Current (mA)
-40qC
25qC
85qC
30
VCC = 2.5 V
25
20
15
10
0
40
VCC = 3.3 V
30
20
0
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
D014
0.6
0.7
D015
Figure 13. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 2.5 V
Figure 14. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 3.3 V
70
80
-40qC
25qC
85qC
50
-40qC
25qC
85qC
70
IOH - Source Current (mA)
60
IOH - Source Current (mA)
-40qC
25qC
85qC
10
5
VCC = 5 V
40
30
20
10
60
VCC = 5.5 V
50
40
30
20
10
0
0
0
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
0
D016
Figure 15. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 5 V
350
0.1
0.2
0.3
0.4
0.5
VCC-VOH - Output High Voltage (V)
0.6
0.7
D017
Figure 16. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 5.5 V
400
18
1.65 V, 10 mA
2.5 V, 10 mA
3.6 V, 10 mA
5 V, 10 mA
5.5 V, 10 mA
15
1.65 V
1.8 V
2.5 V
3.3 V
5V
5.5 V
300
Delta ICC (µA)
VCC-VOH - I/O High Voltage (mV)
50
250
200
150
9
6
3
100
50
-40
12
-15
10
35
TA - Temperature (°C)
60
85
0
-40
D018
Figure 17. VCC – VOH Voltage vs Temperature for Different
VCC
-15
10
35
TA - Temperature (°C)
60
85
D019
Figure 18. Δ ICC vs Temperature for Different VCC (VI = VCC –
0.6 V)
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8 Parameter Measurement Information
VCC
RL = 1 kΩ
SDA
DUT
CL = 50 pF
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition
(P)
Start
Condition
(S)
Address
Address
Bit 7
Bit 6
(MSB)
Address
Bit 1
t scl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
t sch
0.7 × VCC
SCL
0.3 × VCC
t icr
t icf
t buf
t sts
t PHL
t PLH
t sp
0.7 × VCC
SDA
0.3 × VCC
t icf
t icr
t sth
t sdh
t sds
t sps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2, 3
P-port data
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 19. I2C Interface Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VCC
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
16 Bits
(Two Data Bytes)
From Port
R/W
Slave Address (TCA9555)
S
0
1
0
0 A2 A1 A0 1
A
1
2
3
4
A
5
6
7
8
Data 1
ACK
From Slave
Data 2
Data From Port
A
Data 3
1
P
A
t ir
t ir
B
B
INT
A
t iv
t sps
A
Data
Into
Port
Address
Data 1
0.7 × VCC
INT
SCL
0.3 × VCC
Data 2
Data 3
0.7 × VCC
R/W
t iv
A
0.3 × VCC
t ir
0.7 × VCC
Pn
0.7 × VCC
INT
0.3 × VCC
0.3 × VCC
View A−A
View B−B
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 20. Interrupt Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
DUT
Pn
CL = 100 pF
GND
P-PORT LOAD CONFIGURATION
0.7 × VCC
SCL
P00
A
P17
0.3 × VCC
Slave
ACK
SDA
t pv
(see Note A)
Pn
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
0.7 × VCC
SCL
P00
A
t ps
P17
0.3 × VCC
t ph
0.7 × VCC
Pn
0.3 × VCC
READ MODE (R/W = 1)
A.
CL includes probe and jig capacitance.
B.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 21. P-Port Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
The TCA9555 is a 16-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 1.65-V to 5.5-V VCC
operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C
interface.
One of the features of the TCA9555, is that the INT output can be connected to the interrupt input of a
microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there
is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA9555 can remain a
simple slave device.
9.2 Functional Block Diagram
TCA9555
INT
A0
A1
A2
SCL
SDA
1
Interrupt
Logic
LP Filter
21
2
P07-P00
3
22
23
I2C Bus
Control
Input
Filter
Shift
Register
16 Bits
I/O
Port
P17-P10
Write Pulse
VCC
GND
24
12
Read Pulse
Power-On
Reset
Pin numbers shown are for the PW package.
All I/Os are set to inputs at reset.
Figure 22. Logic Diagram (Positive Logic)
9.3 Feature Description
9.3.1 5-V Tolerant I/O Ports
The TCA9555 features I/O ports which are tolerant of up to 5 V. This allows the TCA9555 to be connected to a
large array of devices. To minimize ICC, any inputs must be sure that the input voltage stays within VIH and VIL of
the device as described in the Electrical Characteristics table.
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Feature Description (continued)
9.3.2 Hardware Address Pins
The TCA9555 features 3 hardware address pins (A0, A1, and A2) to allow the user to program the device's I2C
address by pulling each pin to either VCC or GND to signify the bit value in the address. This allows up to 8
TCA9555 to be on the same bus without address conflicts. See the Functional Block Diagram to see the 3 pins.
The voltage on the pins must not change while the device is powered up in order to prevent possible I2C glitches
as a result of the device address changing during a transmission. All of the pins must be tied either to VCC or
GND and cannot be left floating.
9.3.3 Interrupt (INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge
(ACK) bit after the rising edge of the SCL signal. Note that the INT is reset at the ACK just before the byte of
changed data is sent. Interrupts that occur during the ACK clock pulse can be lost (or be very short) because of
the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is
transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the
state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read
independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa.
INT has an open-drain structure and requires a pull-up resistor to VCC (typically 10 kΩ in value).
9.4 Device Functional Modes
9.4.1 Power-On Reset (POR)
When power (from 0 V) is applied to VCC, an internal power-on reset circuit holds the TCA9555 in a reset
condition until VCC has reached VPOR. At that time, the reset condition is released, and the TCA9555 registers
and I2C-SMBus state machine initialize to their default states. After that, VCC must be lowered to below VPORF
and back up to the operating voltage for a power-reset cycle.
9.4.2 Powered-Up
When power has been applied to VCC above VPOR, and the POR has taken place, the device is in a functioning
mode. In this state, the device is ready to accept any incoming I2C requests and is monitoring for changes on the
input ports.
9.5 Programming
9.5.1 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input
voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin must not exceed the recommended levels for proper operation. Figure 23 shows the
simplified schematic of P-Port I/Os.
16
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Programming (continued)
Data From
Shift Register
Output Port
Register Data
Configuration
Register
Data From
Shift Register
D
Q
100 kΩ
FF
Write Configuration
Pulse
VCC
Q1
D
CLK Q
Q
FF
I/O Pin
CLK Q
Write Pulse
Output Port
Register
Q2
Input Port
Register
D
GND
Q
Input Port
Register Data
FF
Read Pulse
CLK Q
To INT
Data From
Shift Register
D
Polarity
Register Data
Q
FF
Write Polarity
Pulse
CLK Q
Polarity Inversion
Register
Figure 23. Simplified Schematic of P-Port I/Os
9.5.2 I2C Interface
The TCA9555 has a standard bidirectional I2C interface that is controlled by a master device in order to be
configured or read the status of this device. Each slave on the I2C bus has a specific device address to
differentiate between other slave devices that are on the same I2C bus. Many slave devices require configuration
upon startup to set the behavior of the device. This is typically done when the master accesses internal register
maps of the slave, which have unique register addresses. A device can have one or multiple registers where
data is stored, written, or read. For more information see the Understanding the I2C Bus application report,
SLVA704.
The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines
must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by the amount
of capacitance on the I2C lines. For further details, refer to I2C Pull-up Resistor Calculation application report,
SLVA689. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL
lines are high after a STOP condition.
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Programming (continued)
Figure 24 and Figure 25 show the general procedure for a master to access a slave device:
1. If a master wants to send data to a slave:
– Master-transmitter sends a START condition and addresses the slave-receiver.
– Master-transmitter sends data to slave-receiver.
– Master-transmitter terminates the transfer with a STOP condition.
2. If a master wants to receive or read data from a slave:
– Master-receiver sends a START condition and addresses the slave-transmitter.
– Master-receiver sends the requested register to read to slave-transmitter.
– Master-receiver receives data from the slave-transmitter.
– Master-receiver terminates the transfer with a STOP condition.
SCL
SDA
Data Transfer
START
Condition
STOP
Condition
Figure 24. Definition of Start and Stop Conditions
SDA line stable while SCL line is high
SCL
1
0
1
0
1
0
1
0
ACK
MSB
Bit
Bit
Bit
Bit
Bit
Bit
LSB
ACK
SDA
Byte: 1010 1010 ( 0xAAh )
Figure 25. Bit Transfer
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Programming (continued)
Table 1 shows the interface definition.
Table 1. Interface Definition
BIT
BYTE
7 (MSB)
6
5
4
3
2
1
0 (LSB)
I2C slave address
L
H
L
L
A2
A1
A0
R/W
P0x I/O data bus
P07
P06
P05
P04
P03
P02
P01
P00
P1x I/O data bus
P17
P16
P15
P14
P13
P12
P11
P10
9.5.2.1 Bus Transactions
Data is exchanged between the master and the TCA9555 through write and read commands, and this is
accomplished by reading from or writing to registers in the slave device.
Registers are locations in the memory of the slave which contain information, whether it be the configuration
information or some sampled data to send back to the master. The master must write information to these
registers in order to instruct the slave device to perform a task.
9.5.2.1.1 Writes
To write on the I2C bus, the master sends a START condition on the bus with the address of the slave, as well
as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master
then sends the register address of the register to which it wishes to write. The slave acknowledges again, letting
the master know it is ready. After this, the master starts sending the register data to the slave until the master
has sent all the data necessary (which is sometimes only a single byte), and the master terminates the
transmission with a STOP condition.
See the Control Register and Command Byte section to see list of the TCA9555's internal registers and a
description of each one.
Figure 26 to Figure 28 show examples of writing a single byte to a slave register.
Master controls SDA line
Slave controls SDA line
Write to one register in a device
Register Address N (8 bits)
Device (Slave) Address (7 bits)
S
0
START
1
0
0
A2 A1 A0
0
R/W=0
A
Data Byte to Register N (8 bits)
B7 B6 B5 B4 B3 B2 B1 B0
ACK
A
ACK
D7 D6 D5 D4 D3 D2 D1 D0
A
ACK
P
STOP
Figure 26. Write to Register
<br/>
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Programming (continued)
Master controls SDA line
Slave controls SDA line
Register Address 0x02 (8 bits)
Device (Slave) Address (7 bits)
S
0
1
0
0
A2 A1 A0
START
0
A
0
R/W=0
0
0
0
1
0
0
Data Byte to Register 0x02 (8 bits)
0
ACK
A
D7 D6 D5 D4 D3 D2 D1 D0
ACK
A
ACK
P
STOP
Figure 27. Write to the Polarity Inversion Register
1
SCL
2
3
4
5
6
7
8
9
Command Byte
Slave Address
SDA
S
0
1
Start Condition
0
0
A2 A1 A0
0
A
0
0
R/W Acknowledge
From Slave
0
0
0
0
Data to Port 0
1
0
A
0.7
Data 0
Data to Port 1
0.0
Acknowledge
From Slave
A 1.7
Data 1
1.0
A
P
Acknowledge
From Slave
Write to Port
Data Out from Port 0
tpv
Data Valid
Data Out from Port 1
tpv
Figure 28. Write to Output Port Registers
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Programming (continued)
9.5.2.1.2 Reads
Reading from a slave is very similar to writing, but requires some additional steps. In order to read from a slave,
the master must first instruct the slave which register it wishes to read from. This is done by the master starting
off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0
(signifying a write), followed by the register address it wishes to read from. When the slave acknowledges this
register address, the master sends a START condition again, followed by the slave address with the R/W bit set
to 1 (signifying a read). This time, the slave acknowledges the read request, and the master releases the SDA
bus but continues supplying the clock to the slave. During this part of the transaction, the master becomes the
master-receiver, and the slave becomes the slave-transmitter.
The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data.
At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for
more data. When the master has received the number of bytes it is expecting, it sends a NACK, signaling to the
slave to halt communications and release the bus. The master follows this up with a STOP condition.
See the Control Register and Command Byte section to see list of the TCA9555's internal registers and a
description of each one.
Figure 29 to Figure 31 show examples of reading a single byte from a slave register.
Master controls SDA line
Slave controls SDA line
Read from one register in a device
Device (Slave) Address (7 bits)
S
0
START
1
0
0
A2 A1 A0
Register Address N (8 bits)
0
R/W=0
A
B7 B6 B5 B4 B3 B2 B1
ACK
Data Byte from Register N (8 bits)
Device (Slave) Address (7 bits)
B0
A
ACK
Sr
0
1
0
0
A2 A1 A0
Repeated START
1
R/W=1
A
D7 D6 D5 D4 D3 D2 D1 D0 NA
ACK
NACK
P
STOP
Figure 29. Read from Register
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. For example, if the command byte references Input Port 1 before the restart, the restart
occurs when Input Port 0 is being read. The original command byte is forgotten. If a subsequent restart occurs,
Input Port 0 is read first. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first
byte is read, additional bytes may be read, but the data now reflect the information in the other register in the
pair. For example, if Input Port 1 is read, the next byte read is Input Port 0.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
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Programming (continued)
1
SCL
2
3
4
5
6
7
8
9
I0.x
SDA
S
0
1
0
0
A2
A1
1
A0
A
R/W
7
6
5
4
3
I1.x
2
Acknowledge
From Slave
1
0
A
7
6
5
4
3
I0.x
2
1
0
A
7
6
5
4
3
I1.x
2
1
0
A
6
5
4
3
2
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Master
7
1
0
1
P
No Acknowledge
From Master
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
INT
t iv
t ir
A.
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B.
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port.
Figure 30. Read Input Port Register, Scenario 1
1
SCL
2
3
4
5
6
7
8
9
I0.x
SDA
S
0
1
0
0
A2
A1
A0
1
R/W
A
00
I1.x
A
10
A
03
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Slave
I0.x
I1.x
A
12
P
Acknowledge
From Master
No Acknowledge
From Master
tps
tph
1
Read From Port 0
Data Into Port 0
Data 00
Data 01
Data 02
Data 03
tph
tps
Read From Port 1
Data 10
Data Into Port 1
Data 11
Data 12
INT
t iv
t ir
A.
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B.
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port.
Figure 31. Read Input Port Register, Scenario 2
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Programming (continued)
9.5.3 Device Address
Figure 32 shows the address byte of the TCA9555.
R/W
Slave Address
0
1
0
0 A2 A1 A0
Fixed
Programmable
Figure 32. TCA9555 Address
Table 2 shows the TCA9555 address reference.
Table 2. Address Reference
INPUTS
I2C BUS SLAVE ADDRESS
A2
A1
A0
L
L
L
32 (decimal), 0x20 (hexadecimal)
L
L
H
33 (decimal), 0x21 (hexadecimal)
L
H
L
34 (decimal), 0x22 (hexadecimal)
L
H
H
35 (decimal), 0x23 (hexadecimal)
H
L
L
36 (decimal), 0x24 (hexadecimal)
H
L
H
37 (decimal), 0x25 (hexadecimal)
H
H
L
38 (decimal), 0x26 (hexadecimal)
H
H
H
39 (decimal), 0x27 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
9.5.4 Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte shown in
Table 3, that is stored in the control register in the TCA9555. Three bits of this data byte state the operation
(read or write) and the internal register (input, output, polarity inversion, or configuration) that is affected. This
register can be written or read through the I2C bus. The command byte is sent only during a write transmission.
When a command byte has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent. Figure 33 shows the control register bits.
0
0
0
0
0
B2
B1
B0
Figure 33. Control Register Bits
Table 3. Command Byte
CONTROL REGISTER BITS
B2
B1
B0
COMMAND
BYTE (HEX)
REGISTER
PROTOCOL
POWER-UP
DEFAULT
0
0
0
0x00
Input Port 0
Read byte
xxxx xxxx
0
0
1
0x01
Input Port 1
Read byte
xxxx xxxx
0
1
0
0x02
Output Port 0
Read-write byte
1111 1111
0
1
1
0x03
Output Port 1
Read-write byte
1111 1111
1
0
0
0x04
Polarity Inversion Port 0
Read-write byte
0000 0000
1
0
1
0x05
Polarity Inversion Port 1
Read-write byte
0000 0000
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Table 3. Command Byte (continued)
CONTROL REGISTER BITS
B2
B1
B0
COMMAND
BYTE (HEX)
REGISTER
PROTOCOL
POWER-UP
DEFAULT
1
1
0
0x06
Configuration Port 0
Read-write byte
1111 1111
1
1
1
0x07
Configuration Port 1
Read-write byte
1111 1111
9.6 Register Maps
9.6.1 Register Descriptions
The Input Port registers (registers 0 and 1) shown in Table 4 reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on
read operation. Writes to these registers have no effect. The default value, X, is determined by the externally
applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the
Input Port register is accessed next.
Table 4. Registers 0 and 1 (Input Port Registers)
Bit
Default
Bit
Default
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
X
X
X
X
X
X
X
X
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
X
X
X
X
X
X
X
X
The Output Port registers (registers 2 and 3) shown in Table 5 show the outgoing logic levels of the pins defined
as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In
turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual
pin value.
Table 5. Registers 2 and 3 (Output Port Registers)
Bit
Default
Bit
Default
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
1
1
1
1
1
1
1
O0.0
1
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
1
1
1
1
1
1
1
1
The Polarity Inversion registers (registers 4 and 5) shown in Table 6 allow polarity inversion of pins defined as
inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's
polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity
is retained.
Table 6. Registers 4 and 5 (Polarity Inversion Registers)
Bit
Default
Bit
Default
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
0
0
0
0
0
0
0
0
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
0
0
0
0
0
0
0
0
The Configuration registers (registers 6 and 7) shown in Table 7 configure the directions of the I/O pins. If a bit in
this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If
a bit in this register is cleared to 0, the corresponding port pin is enabled as an output.
Table 7. Registers 6 and 7 (Configuration Registers)
Bit
Default
Bit
Default
24
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
1
1
1
1
1
1
1
1
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
1
1
1
1
1
1
1
1
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
Applications of the TCA9555 has this device connected as a slave to an I2C master (processor), and the I2C bus
may contain any number of other slave devices. The TCA9555 is typically be in a remote location from the
master, placed close to the GPIOs to which the master needs to monitor or control.
IO Expanders such as the TCA9555 are typically used for controlling LEDs (for feedback or status lights),
controlling enable or reset signals of other devices, and even reading the outputs of other devices or buttons.
10.2 Typical Application
Figure 34 shows an application in which the TCA9555 can be used to control multiple subsystems, and even
read inputs from buttons.
Subsystem 1
(e.g., Temperature
Sensor)
INT
VCC
(5 V)
VCC
10 kΩ
10 kΩ
10 kΩ
24 Ω
10 kΩ
22
SCL
Master
Controller SDA
23
1
INT
Subsystem 2
(e.g., Counter)
2 kΩ
VCC
SCL
SDA
INT
P00
P01
P02
P03
GND
P04
P05
RESET
4
5
A
6
7
ENABLE
8
9
B
TCA9555
VCC
P06
P07
3
A2
P10
P11
2
A1
P12
P13
21
A0
P14
P15
P16
GND P17
12
A.
Device address is configured as 0100100 for this example.
B.
P00, P02, and P03 are configured as outputs.
C.
P01, P04–P07, and P10–P17 are configured as inputs.
D.
Pin numbers shown are for the PW package.
10
11
13
14
15
16
17
18
19
20
Controlled Switch
(e.g., CBT Device)
ALARM
Keypad
Subsystem 3
(e.g., Alarm)
Figure 34. Typical Application
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Typical Application (continued)
10.2.1 Design Requirements
The designer must take into consideration the system, to be sure not to violate any of the parameters. Table 8
shows some key parameters which must not be violated.
Table 8. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
I2C and Subsystem Voltage (VCC)
5V
Output current rating, P-port sinking (IOL)
25 mA
I2C bus clock (SCL) speed
400 kHz
10.2.2 Detailed Design Procedure
10.2.2.1 Calculating Junction Temperature and Power Dissipation
When designing with this device, it is important that the Recommended Operating Conditions not be violated.
Many of the parameters of this device are rated based on junction temperature. So junction temperature must be
calculated in order to verify that safe operation of the device is met. The basic equation for junction temperature
is shown in Equation 1.
Tj = TA + (qJA ´ Pd )
(1)
θJA is the standard junction to ambient thermal resistance measurement of the package, as seen in the Thermal
Information table. Pd is the total power dissipation of the device, and the approximation is shown in Equation 2.
(
Pd » ICC _ STATIC ´ VCC
) + å Pd _ PORT _ L + å Pd _ PORT _ H
(2)
Equation 2 is the approximation of power dissipation in the device. The equation is the static power plus the
summation of power dissipated by each port (with a different equation based on if the port is outputting high, or
outputting low. If the port is set as an input, then power dissipation is the input leakage of the pin multiplied by
the voltage on the pin). Note that this ignores power dissipation in the INT and SDA pins, assuming these
transients to be small. They can easily be included in the power dissipation calculation by using Equation 3 to
calculate the power dissipation in INT or SDA while they are pulling low, and this gives maximum power
dissipation.
Pd _ PORT _ L = (IOL ´ VOL )
(3)
Equation 3 shows the power dissipation for a single port which is set to output low. The power dissipated by the
port is the VOL of the port multiplied by the current it is sinking.
(
)
Pd _ PORT _H = IOH ´ (VCC - VOH )
(4)
Equation 4 shows the power dissipation for a single port which is set to output high. The power dissipated by the
port is the current sourced by the port multiplied by the voltage drop across the device (difference between VCC
and the output voltage).
10.2.2.2 Minimizing ICC When I/O Is Used to Control LED
When an I/O is used to control an LED, normally it is connected to VCC through a resistor as shown in Figure 34.
Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC
parameter in the Electrical Characteristics table shows how ICC increases as VIN becomes lower than VCC. For
battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC when the
LED is off to minimize current consumption.
Figure 35 shows a high-value resistor in parallel with the LED. Figure 36 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional
supply current consumption when the LED is off.
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VCC
LED
100 kΩ
VCC
Pn
Figure 35. High-Value Resistor in Parallel With LED
3.3 V
VCC
5V
LED
Pn
Figure 36. Device Supplied by Lower Voltage
10.2.2.3 Pull-Up Resistor Calculation
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all slaves on the I2C bus. The minimum pull-up resistance is a function of
VCC, VOL,(max), and IOL as shown in Equation 5.
VCC - VOL(max)
Rp(min) =
IOL
(5)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL =
400 kHz) and bus capacitance, Cb as shown in Equation 6.
tr
Rp(max) =
0.8473 ´ Cb
(6)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the TCA9555, Ci for SCL or
Cio for SDA, the capacitance of wires, connections and traces, and the capacitance of additional slaves on the
bus. For further details, see the I2C Pull-up Resistor Calculation application report, SLVA689.
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10.2.3 Application Curves
1.8
Standard-Mode
Fast-Mode
Minimum Pull-Up Resistance (k:)
Maximum Pull-Up Resistance (k:)
25
20
15
10
5
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
0
50
100
150 200 250 300
Bus Capacitance (pF)
350
400
450
0
0.5
D008
1
1.5 2 2.5 3 3.5 4
Pull-Up Reference Voltage (V)
4.5
5
5.5
D009
VOL = 0.2 × VCC, IOL = 2 mA when VCC ≤ 2 V
VOL = 0.4 V, IOL = 3 mA when VCC > 2 V
Standard-mode: fSCL = 100 kHz, tr = 1 µs
Fast-mode: fSCL = 400 kHz, tr = 300 ns
Figure 37. Maximum Pull-Up Resistance (Rp(max)) vs Bus
Capacitance (Cb)
28
VDPUX > 2 V
VDUPX </= 2
1.6
Figure 38. Minimum Pull-Up Resistance (Rp(min)) vs Pull-up
Reference Voltage (VCC)
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11 Power Supply Recommendations
In the event of a glitch (data output or input or even power) or data corruption, the TCA9555 can be reset to its
default conditions by using the power-on reset feature. Power-on reset requires that the device go through a
power cycle to be completely reset. This reset also happens when the device is powered on for the first time in
an application.
The two types of power-on reset are shown in Figure 39 and Figure 40.
VCC
Ramp-Up
Ramp-Down
Re-Ramp-Up
VCC_TRR_GND
Time
VCC_RT
VCC_FT
Time to Re-Ramp
VCC_RT
Figure 39. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC
VCC
Ramp-Up
Ramp-Down
VCC_TRR_VPOR50
VIN drops below POR levels
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 40. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 9 specifies the performance of the power-on reset feature for TCA9555 for both types of power-on reset.
Table 9. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES (1)
MAX
UNIT
VCC_FT
Fall rate of VCC
PARAMETER
See Figure 39
0.1
2000
ms
VCC_RT
Rise rate of VCC
See Figure 39
0.1
2000
ms
VCC_TRR_GND
Time to re-ramp (when VCC drops to GND)
See Figure 39
1
μs
VCC_TRR_POR50
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
See Figure 40
1
μs
VCC_GH
Level that VCCP can glitch down to, but not cause a functional
disruption when VCC_GW
See Figure 41
VCC_MV
The minimum voltage that VCC can glitch down to without
causing a reset (VCC_GH must also not be violated)
See Figure 41
VCC_GW
Glitch width that does not cause a functional disruption
See Figure 41
(1)
MIN
TYP
1.2
1.5
V
V
10
μs
TA = –40°C to +85°C (unless otherwise noted)
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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 41 and Table 9 provide more
information on how to measure these specifications.
VCC
VCC_GH
VCC_MV
Time
VCC_GW
Figure 41. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 42 and Table 9 provide more details on this specification.
VCC
VPOR
VPORF
Time
POR
Time
Figure 42. VPOR
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12 Layout
12.1 Layout Guidelines
For printed circuit board (PCB) layout of the TCA9555, common PCB layout practices must be followed, but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs
are not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away
from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry
higher amounts of current that commonly pass through power and ground traces. By-pass and de-coupling
capacitors are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide
additional power in the event of a short power supply glitch and a smaller capacitor to filter out highfrequency ripple. These capacitors must be placed as close to the TCA9555 as possible. These best
practices are shown in the Layout Example.
For the layout example provided in the Layout Example, it is possible to fabricate a PCB with only 2 layers by
using the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND).
However, a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is
common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and
dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power
and ground, vias are placed directly next to the surface mount component pad which needs to attach to VCC,
or GND and the via is connected electrically to the internal layer or the other side of the board. Vias are also
used when a signal trace needs to be routed to the opposite side of the board, but this technique is not
demonstrated in the Layout Example.
12.2 Layout Example
INT
0603
10k Pull-up
0603 Cap
SCL
SDA
VCC
A0
1
P00
INT
A2 A1
P04
P14
P05
P13
P12
P15
P11
P03
P10
P16
GND
P02
P07
P17
P06
P01
= Via to GND Plane
Figure 43. TCA9555 Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• I2C Pull-up Resistor Calculation, SLVA689
• Maximum Clock Frequency of I2C Bus Using Repeaters, SLVA695
• Introduction to Logic, SLVA700
• Understanding the I2C Bus, SLVA704
• IO Expander EVM User's Guide, SLVUA59A
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Mar-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TCA9555DBR
ACTIVE
SSOP
DB
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TD9555
TCA9555DBT
ACTIVE
SSOP
DB
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TD9555
TCA9555PWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PW555
TCA9555RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TD9555
TCA9555RTWR
ACTIVE
WQFN
RTW
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PW555
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
19-Mar-2019
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TCA9555DBR
Package Package Pins
Type Drawing
SSOP
DB
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.2
8.8
2.5
12.0
16.0
Q1
TCA9555DBT
SSOP
DB
24
250
330.0
16.4
8.2
8.8
2.5
12.0
16.0
Q1
TCA9555PWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
TCA9555RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
TCA9555RTWR
WQFN
RTW
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TCA9555DBR
SSOP
DB
24
2000
367.0
367.0
38.0
TCA9555DBT
SSOP
DB
24
250
367.0
367.0
38.0
TCA9555PWR
TSSOP
PW
24
2000
367.0
367.0
38.0
TCA9555RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
TCA9555RTWR
WQFN
RTW
24
3000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
13
B
0.30
0.19
0.1
C A B
24X
4.5
4.3
NOTE 4
1.2 MAX
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
13
12
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
WQFN - 0.8 mm max height
RTW0024B
PLASTIC QUAD FLATPACK-NO LEAD
4.1
3.9
B
A
4.1
3.9
PIN 1 INDEX AREA
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 2.5
EXPOSED
THERMAL PAD
12
7
(0.2) TYP
20X 0.5
6
2X
2.5
13
25
SYMM
2.45±0.1
1
PIN 1 ID
(OPTIONAL)
18
19
24
SYMM
24X 0.5
0.3
24X 0.34
0.24
0.1
0.05
C A B
C
4219135/A 11/2016
NOTES:
1.
2.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
RTW0024B
PLASTIC QUAD FLATPACK-NO LEAD
(
2.45)
SYMM
24
19
24X (0.6)
24X (0.24)
1
18
(0.97)
SYMM
25
(3.8)
20X (0.5)
(R0.05)
TYP
13
6
(Ø0.2) TYP
VIA
7
(0.97)
12
(3.8)
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOTES: (continued)
3.
For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
www.ti.com
4219135/A 11/2016
EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
RTW0024B
PLASTIC QUAD FLATPACK-NO LEAD
4X(
1.08)
(0.64) TYP
(R0.05) TYP
24
19
24X (0.6)
25
1
18
(0.64)
TYP
24X (0.24)
SYMM
20X (0.5)
(3.8)
13
6
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25:
78% PRINTED COVERAGE BY AREA UNDER PACKAGE
SCALE: 20X
4219135/A 11/2016
NOTES: (continued)
4.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024B
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
0.5
0.3
PIN 1 INDEX AREA
4.1
3.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 2.5
(0.2) TYP
2.45 0.1
7
SEE TERMINAL
DETAIL
12
EXPOSED
THERMAL PAD
13
6
2X
2.5
SYMM
25
18
1
20X 0.5
24
PIN 1 ID
(OPTIONAL)
0.3
0.2
0.1
C A B
0.05
24X
19
SYMM
24X
0.5
0.3
4219013/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP
25
SYMM
(3.8)
20X (0.5)
13
6
( 0.2) TYP
VIA
12
7
(0.975) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219013/A 05/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.08)
(0.64) TYP
24
19
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP
(0.64)
TYP
SYMM
(3.8)
20X (0.5)
13
6
METAL
TYP
12
7
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219013/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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