Texas Instruments | THVD14x9 3.3-V to 5-V RS-485 transceivers with surge protection (Rev. C) | Datasheet | Texas Instruments THVD14x9 3.3-V to 5-V RS-485 transceivers with surge protection (Rev. C) Datasheet

Texas Instruments THVD14x9 3.3-V to 5-V RS-485 transceivers with surge protection (Rev. C) Datasheet
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THVD1419, THVD1429
SLLSF32C – NOVEMBER 2018 – REVISED MARCH 2019
THVD14x9 3.3-V to 5-V RS-485 transceivers with surge protection
1 Features
3 Description
•
THVD1419 and THVD1429 are half-duplex RS-485
transceivers with integrated surge protection. Surge
protection is achieved by integrating transient voltage
suppressor (TVS) diodes in the standard 8-pin SOIC
(D) package. This feature provides a substantial
increase in reliability for better immunity to noise
transients coupled to the data cable, eliminating the
need for external protection components.
1
•
•
•
•
•
•
•
•
•
•
•
Meets or Exceeds the Requirements of the
TIA/EIA-485A Standard
3 V to 5.5 V Supply Voltage
Bus I/O Protection
– ± 16 kV HBM ESD
– ± 8 kV IEC 61000-4-2 Contact Discharge
– ± 30 kV IEC 61000-4-2 Air-Gap Discharge
– ± 4 kV IEC 61000-4-4 Electrical Fast Transient
– ± 2.5 kV IEC 61000-4-5 1.2/50-μs Surge
Available in Two Speed Grades
– THVD1419: 250 kbps
– THVD1429: 20 Mbps
Extended Ambient
Temperature Range: -40°C to 125°C
Extended Operational
Common-Mode Range: ± 12 V
Receiver Hysteresis for Noise Rejection: 30 mV
Low Power Consumption
– Standby Supply Current: < 2 µA
– Current During Operation: < 3 mA
Glitch-Free Power-Up/Down for Hot Plug-in
Capability
Open, Short, and Idle Bus Failsafe
1/8 Unit Load (Up to 256 Bus Nodes)
Industry Standard 8-Pin SOIC
for Drop-in Compatibility
2 Applications
•
•
•
•
•
•
•
•
Wireless Infrastructure
Building Automation
HVAC Systems
Factory Automation & Control
Grid Infrastructure
Smart Meters
Process Analytics
Video Surveillance
Each of these devices operates from a single 3.3 V or
5 V supply. The devices in this family feature a wide
common-mode voltage range which makes them
suitable for multi-point applications over long cable
runs.
The THVD1419 and THVD1429 devices are available
in the industry standard SOIC package for easy dropin without any PCB changes. These devices are
characterized over ambient free-air temperatures
from –40°C to 125°C.
Device Information(1)
PART NUMBER
THVD1419
THVD1429
PACKAGE
SOIC (8)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
(1) For all available devices, see the orderable addendum at the
end of the data sheet.
THVD1419 and THVD1429 Block Diagram
VCC
R
A
RE
B
DE
D
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THVD1419, THVD1429
SLLSF32C – NOVEMBER 2018 – REVISED MARCH 2019
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Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
5
5
5
6
6
6
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
ESD Ratings [IEC] ....................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Power Dissipation .....................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 11
Detailed Description ............................................ 13
9.1 Overview ................................................................. 13
9.2 Functional Block Diagrams ..................................... 13
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 16
10 Application and Implementation........................ 17
10.1 Application Information...................................... 17
10.2 Typical Application ............................................... 17
11 Power Supply Recommendations ..................... 20
12 Layout................................................................... 21
12.1 Layout Guidelines ................................................. 21
12.2 Layout Example .................................................... 21
13 Device and Documentation Support ................. 22
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
Device Support......................................................
Third-Party Products Disclaimer ...........................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
22
22
14 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Revision B (December 2018) to Revision C
Page
•
Changed THVD1419 From: Product Preview To: Production data ....................................................................................... 1
•
Changed power dissipation numbers of THVD1419 ............................................................................................................. 6
•
Changed THVD1419 driver switching characteristics ............................................................................................................ 8
•
Changed THVD1419 receiver switching characteristics......................................................................................................... 8
•
Added Figure 7 to Figure 9 .................................................................................................................................................... 9
Changes from Revision A (December 2018) to Revision B
•
2
Page
Changed THVD1429 From: Advanced Information To: Production data .............................................................................. 1
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SLLSF32C – NOVEMBER 2018 – REVISED MARCH 2019
5 Device Comparison Table
PART NUMBER
THVD1419
THVD1429
DUPLEX
Half
ENABLES
DE, RE
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SIGNALING RATE
up to 250 kbps
up to 20 Mbps
NODES
256
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6 Pin Configuration and Functions
THVD1419, THVD1429 Devices
8-Pin D Package (SOIC)
Top View
R
1
8
VCC
RE
2
7
B
DE
3
6
A
D
4
5
GND
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A
6
Bus input/output
Bus I/O port, A (complementary to B)
B
7
Bus input/output
Bus I/O port, B (complementary to A)
D
4
Digital input
Driver data input
DE
3
Digital input
Driver enable, active high (2-MΩ internal pull-down)
GND
5
Ground
R
1
Digital output
Receive data output
VCC
8
Power
3.3-V to 5-V supply
RE
2
Digital input
4
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Device ground
Receiver enable, active low (2-MΩ internal pull-up)
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SLLSF32C – NOVEMBER 2018 – REVISED MARCH 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Supply voltage
VCC
-0.5
7
V
Bus voltage
Range at any bus pin (A or B) as differential or
common-mode with respect to GND
-15
15
V
Input voltage
Range at any logic pin (D, DE, or /RE)
-0.3
5.7
V
Receiver output
current
IO
-24
24
mA
-65
150
℃
Storage temperature range
(1)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
V(ESD)
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, 2010
Electrostatic discharge
VALUE
UNIT
Bus terminals
and GND
±16
kV
All other pins
±8
kV
±1.5
kV
Charged device model (CDM), per
JEDEC JESD22-C101E
All pins
VALUE
UNIT
Contact Discharge, per IEC 610004-2
Bus pins and
GND
±8
kV
Air-Gap Discharge, per IEC 610004-2
Bus pins and
GND
±30
kV
7.3 ESD Ratings [IEC]
V(ESD)
Electrostatic discharge
V(EFT)
Electrical fast transient
Per IEC 61000-4-4
Bus pins and
GND
±4
kV
V(surge)
Surge
Per IEC 61000-4-5, 1.2/50 μs
Bus pins and
GND
±2.5
kV
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7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VCC
Supply voltage
VI
Input voltage at any bus terminal
(separately or common mode) (1)
VIH
NOM
MAX
UNIT
3
5.5
V
-12
12
V
High-level input voltage (driver, driver
enable, and receiver enable inputs)
2
VCC
V
VIL
Low-level input voltage (driver, driver
enable, and receiver enable inputs)
0
0.8
V
VID
Differential input voltage
-12
12
V
IO
Output current, driver
-60
60
mA
IOR
Output current, receiver
-8
8
mA
RL
Differential load resistance
54
1/tUI
Signaling rate: THVD1419
250
kbps
1/tUI
Signaling rate: THVD1429
20
Mbps
TA
Operating ambient temperature
-40
125
℃
TJ
Junction temperature
-40
150
℃
(1)
Ω
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
7.5 Thermal Information
THVD14x9
THERMAL METRIC (1)
D (SOIC)
UNIT
8-PINS
RθJA
Junction-to-ambient thermal resistance
120.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
50.3
°C/W
RθJB
Junction-to-board thermal resistance
62.8
°C/W
ΨJT
Junction-to-top characterization parameter
7.5
°C/W
ΨJB
Junction-to-board characterization parameter
62.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.6 Power Dissipation
PARAMETER
Description
TEST CONDITIONS
Unterminated: RL = 300 Ω, CL = 50 pF
PD
6
Driver and receiver enabled, VCC = 5.5 V, TA
= 125 0C, 50% duty cycle square wave at
RS-422 load: RL = 100 Ω, CL = 50 pF
maximum signaling rate, THVD1419
RS-485 load: RL = 54 Ω, CL = 50 pF
Unterminated: RL = 300 Ω, CL = 50 pF
Driver and receiver enabled, VCC = 5.5 V, TA
= 125 0C, 50% duty cycle square wave at
RS-422 load: RL = 100 Ω, CL = 50 pF
maximum signaling rate, THVD1429
RS-485 load: RL = 54 Ω, CL = 50 pF
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VALUE
UNIT
230
mW
350
mW
470
mW
350
mW
290
mW
300
mW
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7.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
3.5
MAX
UNIT
Driver
|VOD|
Driver differential output voltage
magnitude
RL = 60 Ω, -12 V ≤ Vtest ≤ 12 V, see Figure 10
1.5
|VOD|
Driver differential output voltage
magnitude
RL = 60 Ω, -12 V ≤ Vtest ≤ 12 V, 4.5 V ≤ VCC ≤
5.5 V, see Figure 10
2.1
|VOD|
Driver differential output voltage
magnitude
RL = 100 Ω, see Figure 11
|VOD|
Driver differential output voltage
magnitude
RL = 54 Ω, see Figure 11
Δ|VOD|
Change in differential output
voltage
VOC
Common-mode output voltage
ΔVOC(SS)
Change in steady-state commonmode output voltage
IOS
Short-circuit output current
V
2
4
V
1.5
3.5
V
-200
RL = 54 Ω, see Figure 11
1
DE = VCC, -7 V ≤ VO ≤ 12 V
V
200
VCC /
2
mV
3
V
-200
200
mV
-250
250
mA
125
µA
Receiver
VI = 12 V
II
Bus input current
VTH+
Positive-going input threshold
voltage
VTH-
Negative-going input threshold
voltage
VHYS
Input hysteresis
CA,B
Input differential capacitance
DE = 0 V, VCC = 0 V or 5.5 V
50
VI = -7 V
-100
-65
µA
VI = -12 V
-150
-100
µA
(1)
-100
-20
mV
-200
-130
See (1)
mV
See
Over common-mode range of ±12 V
Measured between A and B, f = 1 MHz
VOH
Output high voltage
IOH = -8 mA
VOL
Output low voltage
IOL = 8 mA
IOZR
Output high-impedance current
VO = 0 V or VCC, RE = VCC
Input current (D, DE, RE)
4.5 V ≤ VCC ≤ 5.5 V
VCC –
0.4
30
mV
220
pF
VCC –
0.3
V
0.2
0.4
V
-1
1
µA
-6.2
6.2
µA
Logic
IIN
Device
ICC
TSD
(1)
Driver and receiver enabled
RE = 0 V,
DE = VCC,
No load
2.4
3
mA
Driver enabled, receiver disabled
RE = VCC,
DE = VCC,
No load
2
2.6
mA
Driver disabled, receiver enabled
RE = 0 V,
DE = 0V,
No load
700
960
µA
Driver and receiver disabled
RE = VCC,
DE = 0 V, D
= open, No
load
0.1
2
µA
Supply current (quiescent)
Thermal shutdown temperature
170
℃
Under any specific conditions, VTH+ is assured to be at least VHYS higher than VTH–.
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7.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
300
500
ns
200
450
ns
40
ns
Driver: THVD1419
tr, tf
Differential output rise / fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time
tPZH, tPZL
Enable time
RL = 54 Ω, CL = 50 pF, see Figure 12
20
50
ns
RE = 0 V, see Figure 13
and Figure 14
60
250
ns
RE = VCC, see Figure 13
and Figure 14
3
11
µs
14
20
ns
30
50
ns
7
ns
35
45
ns
DE = VCC, see Figure 16
80
120
ns
DE = 0 V, see Figure 17
5
14
µs
9
16
ns
12
25
ns
6
ns
Receiver: THVD1419
tr, tf
Output rise / fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time
tPZH(1), tPZL(1),
tPZH(2),
Enable time
tPZL(2),
CL = 15 pF, see Figure 15
Driver: THVD1429
tr, tf
Differential output rise / fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time
tPZH, tPZL
Enable time
RL = 54 Ω, CL = 50 pF, see Figure 12
18
40
ns
RE = 0 V, see Figure 13
and Figure 14
16
40
ns
RE = VCC, see Figure 13
and Figure 14
2.8
11
µs
2
6
ns
12
45
ns
6
ns
14
28
ns
DE = VCC, see Figure 16
75
110
ns
DE = 0 V, see Figure 17
4.8
14
µs
Receiver: THVD1429
tr, tf
Output rise / fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time
tPZH(1), tPZL(1),
tPZH(2),
Enable time
tPZL(2),
8
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CL = 15 pF, see Figure 15
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7.9 Typical Characteristics
5
VOH VCC = 5 V
VOL VCC = 5 V
VOH VCC = 3.3 V
VOL VCC = 3.3 V
4.5
VO Driver Output Voltage (V)
VO Driver Differential Output Voltage (V)
5
4
3.5
3
2.5
2
1.5
1
0.5
0
4
3.5
3
2.5
2
1.5
1
0.5
0
0
10
20
30
40
50
60
70
IO Driver Output Current (mA)
DE = VCC
80
90
0
D=0V
1
1.5
2
2.5
3
3.5
4
VCC Supply Voltage (V)
DE = VCC
4.5
5
5.5
TA = 25°C
80
90
D102
D=0V
16
15.5
15
14.5
14
13.5
13
12.5
12
11.5
11
10.5
10
9.5
9
8.5
8
-40
VCC = 5 V
VCC = 3.3 V
-20
0
20
D103
RL = 54 Ω
40
60
80
Temperature (0C)
100
120
140
D104
THVD1429
Figure 3. Driver Output Current vs Supply Voltage
Figure 4. Driver Rise or Fall Time vs Temperature
19
90
VCC = 5 V
VCC = 3.3 V
18
VCC = 5 V
VCC = 3.3 V
85
17
ICC Supply Current (mA)
VO Driver Propagation Delay (ns)
30
40
50
60
70
IO Driver Output Current (mA)
Figure 2. Driver Differential Output voltage vs Driver Output
Current
VO Driver Rise and Fall Time (ns)
0.5
20
DE = VCC
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
-5
0
10
D101
Figure 1. Driver Output Voltage vs Driver Output Current
IO Driver Output Current (mA)
VCC = 5 V
VCC = 3.3 V
4.5
16
15
14
13
12
80
75
70
65
60
55
50
11
45
10
-40
40
-20
0
20
40
60
80
Temperature (0C)
100
120
140
0
2
4
D105
THVD1429
THVD1429
Figure 5. Driver Propagation Delay vs Temperature
6
8
10
12
14
Signaling Rate (Mbps)
TA = 25°C
16
18
20
D106
RL = 54 Ω
Figure 6. Supply Current vs Signal Rate
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Typical Characteristics (continued)
270
VCC = 5 V
VCC = 3.3 V
320
VO Driver Propagation Delay (ns)
VO Driver Rise and Fall Time (ns)
340
300
280
260
240
220
200
-40
-20
0
20
40
60
80
Temperature (0C)
100
120
140
D_TH
THVD1419
Figure 7. Driver Rise or Fall Time vs Temperature
VCC = 5V
VCC = 3.3V
260
250
240
230
220
210
200
190
180
-40
-20
0
20
40
60
80
Temperature (0C)
100
120
140
D_TH
THVD1419
Figure 8. Driver Propagation Delay vs Temperature
85
VCC = 5V
VCC = 3.3V
ICC Supply Current (mA)
80
75
70
65
60
55
50
45
40
0
25
50
THVD1419
75
100 125 150 175
Signaling Rate (kbps)
200
225
250
D_TH
TA = 25°C
RL = 54 Ω
Figure 9. Supply Current vs Signal Rate
10
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8 Parameter Measurement Information
375 Ÿ
Vcc
DE
A
D
0V or Vcc
VOD
Vtest
RL
B
375 Ÿ
Figure 10. Measurement of Driver Differential Output Voltage With Common-Mode Load
A
0V or Vcc
A
D
RL/2
VA
B
VB
VOD
RL/2
B
CL
VOC(PP)
VOC
ûVOC(SS)
VOC
Figure 11. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
Vcc
Vcc
DE
A
D
Input
Generator
VI
50%
VI
VOD
50 Ÿ
0V
tPHL
tPLH
RL=
54 Ÿ
CL= 50 pF
90%
50%
10%
B
VOD
tr
tf
~2 V
~ ±2V
Figure 12. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
A
D
S1
Vcc
VO
50%
VI
B
DE
Input
Generator
VI
RL =
110 Ÿ
CL =
50 pF
50 Ÿ
0V
tPZH
90%
VO
VOH
50%
~
~ 0V
tPHZ
Figure 13. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down
Load
Vcc
Vcc
A
S1
VO
B
D
DE
Input
Generator
RL= 110 Ÿ
CL=
50 pF
50%
VI
0V
tPZL
tPLZ
§ Vcc
VO
VI
50 %
10%
VOL
50 Ÿ
Figure 14. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
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Parameter Measurement Information (continued)
3V
A
Input
Generator
R VO
VI
50 Ÿ
1.5V
0V
50 %
VI
B
0V
tPLH
tPHL
VOH
90%
CL=15 pF
50%
RE
VOD
10 %
tr
VOL
tf
Figure 15. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
Vcc
Vcc
Vcc
VI
50 %
DE
0V or Vcc
0V
A
D
R
B
1 kŸ
VO
tPZH(1)
tPHZ
S1
VO
CL=15 pF
90 %
50 %
tPZL(1)
VI
D at Vcc
S1 to GND
§ 0V
RE
Input
Generator
VOH
50 Ÿ
tPLZ
VO
50 %
VCC D at 0V
S1 to Vcc
10 %
VOL
Figure 16. Measurement of Receiver Enable/Disable Times With Driver Enabled
Vcc
Vcc
VI
50%
0V
A
V or 1.5V
R
1.5 V or 0V
B
VO
RE
1 NŸ
tPZH(2)
S1
CL=15 pF
VOH
50%
VO
§ 0V
A at 1.5 V
B at 0 V
S1 to GND
tPZL(2)
Input
Generator
VI
50 Ÿ
VCC
VO
50%
VOL
A at 0V
B at 1.5V
S1 to VCC
Figure 17. Measurement of Receiver Enable Times With Driver Disabled
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9 Detailed Description
9.1 Overview
THVD1419 and THVD1429 are surge-protected, half duplex RS-485 transceivers available in two speed grades
suitable for data transmission up to 250 kbps and 20 Mbps respectively. Surge protection is achieved by
integrating transient voltage suppresser (TVS) diodes in the standard 8-pin SOIC (D) package.
These devices have active-high driver enables and active-low receiver enables. A standby current of less than 2
µA can be achieved by disabling both driver and receiver.
9.2 Functional Block Diagrams
VCC
R
A
RE
B
DE
D
GND
Figure 18. THVD1419 and THVD1429 Block Diagram
9.3 Feature Description
9.3.1 Electrostatic Discharge (ESD) Protection
The bus pins of the THVD14x9 transceiver family include on-chip ESD protection against ±16-kV HBM and ±8-kV
IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD test is far more
severe than the HBM ESD test. The 50% higher charge capacitance, C(S), and 78% lower discharge resistance,
R(D), of the IEC model produce significantly higher discharge currents than the HBM model. As stated in the IEC
61000-4-2 standard, contact discharge is the preferred transient protection test method.
R(D)
50 M
(1 M)
High-Voltage
Pulse
Generator
330 Ω
(1.5 kΩ)
C(S)
150 pF
(100 pF)
Device
Under
Test
Current (A)
R(C)
40
35
30 10-kV IEC
25
20
15
10
5
0
0
50
100
10-kV HBM
150
200
250
300
Time (ns)
Figure 19. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur because of human contact with connectors and cables.
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Feature Description (continued)
9.3.2 Electrical Fast Transient (EFT) Protection
Normalized Voltage
Inductive loads such as relays, switch contactors, or heavy-duty motors can create high-frequency bursts during
transition. The IEC 61000-4-4 test is intended to simulate the transients created by such switching of inductive
loads on AC power lines. Figure 20 shows the voltage waveforms in to 50-Ω termination as defined by the IEC
standard.
1
Time
Normalized Voltage
300 ms
15 ms at 5 kHz
0.75 ms at 100 kHz
1
Time
Normalized Voltage
200 µs at 5 kHz
10 µs at 100 kHz
1
0.5
Time
5 ns
50ns
Figure 20. EFT Voltage Waveforms
Internal ESD protection circuits of the THVD14x9 protect the transceivers against EFT ±4 kV.
9.3.3 Surge Protection
Surge transients often result from lightning strikes (direct strike or an indirect strike which induce voltages and
currents), or the switching of power systems, including load changes and short circuit switching. These transients
are often encountered in industrial environments, such as factory automation and power-grid systems.
Figure 21 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automation.
The right hand diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
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22
20
18
16
14
12
10
8
6
4
2
0
Pulse Power (MW)
Pulse Power (kW)
Feature Description (continued)
0.5-kV Surge
4-kV EFT
10-kV ESD
0
5
10
15
20
25
30
35
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
0.5-kV Surge
0
40
5
10
15
20
25
30
35
40
Time (µs)
Time (µs)
Figure 21. Power Comparison of ESD, EFT, and Surge Transients
Figure 22 shows the test setup used to validate THVD14x9 surge performance according to the IEC 61000-4-5
1.2/50-μs surge pulse.
80
A
Surge Generator
2 Source Impedance
80
B
THVD14x9
Coupling Network
GND
Figure 22. THVD14x9 Surge Test Setup
THVD14x9 product family is robust to ±2.5-kV surge transients without the need for any external components.
9.3.4 Failsafe Receiver
The differential receivers of the THVD14x9 family are failsafe to invalid bus states caused by the following:
• Open bus conditions, such as a disconnected connector
• Shorted bus conditions, such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic high state so that the output of the
receiver is not indeterminate.
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9.4 Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as
VOD = VA – VB is positive. When D is low, the output states reverse: B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
Table 1. Driver Function Table
INPUT
ENABLE
D
DE
A
OUTPUTS
H
H
H
L
Actively drive bus high
L
H
L
H
Actively drive bus low
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drive bus high by default
FUNCTION
B
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high.
When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+
and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not
actively driven (idle bus).
Table 2. Receiver Function Table
16
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = VA – VB
RE
R
VTH+ < VID
L
H
Receive valid bus high
VTH- < VID < VTH+
L
?
Indeterminate bus state
VID < VTH-
L
L
Receive valid bus low
X
H
Z
Receiver disabled
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
Fail-safe high output
Idle (terminated) bus
L
H
Fail-safe high output
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
THVD14x9 are half-duplex RS-485 transceivers with integrated system-level surge protection. Standard 8-pin
SOIC (D) package allows drop-in replacement into existing systems and eliminate system-level protection
components.
10.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer
cable length.
R
R
RE
B
DE
D
R
A
R
A
RT
RT
D
A
R
B
A
D
R RE DE D
DE
D
B
R
RE
B
D
D
R RE DE D
Figure 23. Typical RS-485 Network With Half-Duplex Transceivers
10.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
10.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
short the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at
distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or
10%.
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Typical Application (continued)
10000
Cable Length (ft)
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10 k
100 k
1M
10 M
100 M
Data Rate (bps)
Figure 24. Cable Length vs Data Rate Characteristic
Even higher data rates are achievable (that is, 20 Mbps for the THVD1429) in cases where the interconnect is
short enough (or has suitably low attenuation at signal frequencies) to not degrade the data.
10.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in Equation 1.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
10.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the THVD14x9 devices consist of 1/8 UL
transceivers, connecting up to 256 receivers to the bus is possible.
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Typical Application (continued)
10.2.2 Detailed Design Procedure
RS-485 transceivers operate in noisy industrial environments typically require surge protection at the bus pins.
Figure 25 compares 1-kV surge protection implementation with a regular RS-485 transceiver (such as
THVD14x0) against with the THVD14x9. The internal TVS protection of the THVD14x9 achieves ±2.5 kV IEC
61000-4-5 surge protection without any additional external components, reducing system level bill of materials.
System level surge protection implementation
using a typical RS-485 transceiver
3.3V ± 5 V
100nF
VCC
10k
10k
Pulse-proof,
thick-film resistor
R
RxD
DIR
MCU/
UART DIR
/RE
A
DE
B
TVS
D
TxD
Pulse-proof,
thick-film resistor
THVD14x0
10k
GND
System level surge protection implementation
using THVD14x9 transceiver
3.3V ± 5 V
100nF
VCC
10k
10k
R
RxD
DIR
MCU/
UART DIR
/RE
A
DE
B
D
TxD
THVD14x9
10k
GND
Figure 25. Implementation of System-Level Surge Protection Using THVD14x9
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Typical Application (continued)
10.2.3 Application Curves
VCC = 5 V
54-Ω Termination
TA = 25°C
Figure 26. THVD1429 Waveforms at 20 Mbps
11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
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12 Layout
12.1 Layout Guidelines
Additional external protection components generally are not needed when using THVD14x9 transceivers.
1. Use VCC and ground planes to provide low-inductance. Note that high-frequency currents tend to follow the
path of least impedance and not the path of least resistance. Apply 100-nF to 220-nF decoupling capacitors
as close as possible to the VCC pins of transceiver, UART and/or controller ICs on the board.
2. Use at least two vias for VCC and ground connections of decoupling capacitors to minimize effective viainductance.
3. Use 1-kΩ to 10-kΩ pull-up and pull-down resistors for enable lines to limit noise currents in theses lines
during transient events.
12.2 Layout Example
2
Via to GND
C
R
Via to VCC
R
JMP
3
1
R
MCU
3
R
THVD14x9
2
Figure 27. Half-Duplex Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.2 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 3. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
THVD1419
Click here
Click here
Click here
Click here
Click here
THVD1429
Click here
Click here
Click here
Click here
Click here
13.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document..
13.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.6 Trademarks
E2E is a trademark of Texas Instruments.
13.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THVD1419DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1419
THVD1419DT
ACTIVE
SOIC
D
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1419
THVD1429DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1429
THVD1429DT
ACTIVE
SOIC
D
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1429
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
THVD1419DR
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
THVD1419DT
SOIC
D
8
250
177.8
12.4
6.4
5.2
2.1
8.0
12.0
Q1
THVD1429DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
THVD1429DT
SOIC
D
8
250
177.8
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THVD1419DR
SOIC
D
8
2500
346.0
346.0
29.0
THVD1419DT
SOIC
D
8
250
213.0
191.0
35.0
THVD1429DR
SOIC
D
8
2500
346.0
346.0
29.0
THVD1429DT
SOIC
D
8
250
213.0
191.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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