Texas Instruments | TLIN2024-Q1 Fault Protected Quad Local Interconnect Network (LIN) Transceiver with Dominant State Timeout (Rev. B) | Datasheet | Texas Instruments TLIN2024-Q1 Fault Protected Quad Local Interconnect Network (LIN) Transceiver with Dominant State Timeout (Rev. B) Datasheet

Texas Instruments TLIN2024-Q1 Fault Protected Quad Local Interconnect Network (LIN) Transceiver with Dominant State Timeout (Rev. B) Datasheet
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TLIN2024-Q1
SLLSF05B – APRIL 2018 – REVISED DECEMBER 2019
TLIN2024-Q1 Fault Protected Quad Local Interconnect Network (LIN) Transceiver with
Dominant State Timeout
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
•
•
AEC Q100 Qualified for automotive applications
– Temperature: –40 to 125°C ambient
– HBM Classification level: ±8 kV
– CDM Classification level: ±1.5 kV
Compliant to LIN2.0, LIN2.1, LIN2.2, LIN2.2A and
ISO/DIS 17987–4.2
Conforms to SAE J2602 recommended practice
for LIN
Supports 12 V and 24 V battery applications
LIN transmit data rate up to 20 kbps
Wide operating ranges
– 4 V to 48 V supply voltage
– ±60 V LIN bus fault protection
– Sleep mode: ultra-low current consumption
allows wake up event from:
– LIN bus
– Local wake up through EN
– Power up and down glitch free operation
Protection features:
– Under voltage protection on VSUP
– TXD Dominant time out protection (DTO)
– Thermal shutdown protection
– Unpowered node or ground disconnection
failsafe at system level.
3.5 mm × 5.5 mm QFN package with improved
automated optical inspection (AOI) capability
Body Electronics and Lighting
Infotainment and Cluster
Hybrid Electric Vehicles and Power Train Systems
Passive Safety
3 Description
The TLIN2024-Q1 device is a quad Local
Interconnect Network (LIN) physical layer transceiver,
which integrates wake up and protection features,
compliant to LIN2.0, LIN2.1, LIN2.2, LIN2.2A and
ISO/DIS 17987–4.2 standards. LIN is a single wire
bidirectional bus typically used for low speed invehicle networks using data rates up to 20 kbps. The
LIN receiver supports data rates up to 100 kbps for
in-line programming. The TLIN2024-Q1 has two
separate dual LIN transceiver blocks. The VSUP1/2
control separate dual transceiver blocks. The
TLIN2024-Q1 converts the LIN protocol data stream
on the TXD input into a LIN bus signal using a
current-limited wave-shaping driver which reduces
electromagnetic emissions (EME). The receiver
converts the data stream to logic level signals that
are sent to the microprocessor through the opendrain RXD pin. Ultra-low current consumption is
possible using the sleep mode which allows wake up
via LIN bus or EN pin. The integrated resistor,
electrostatic discharge (ESD) protection, and fault
protection allow designers to save board space in
their applications.
Device Information(1)
PART NUMBER
TLIN2024-Q1
PACKAGE
VQFN (24)
BODY SIZE (NOM)
3.50 mm × 5.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Node 1
Master
Node 2
Node 3
Node n
MCU or DSP
MCU or DSP
MCU or DSP
MCU or DSP
LIN
Controller
LIN
Controller
LIN
Controller
LIN
Controller
TLIN2024
TLIN2022
TLIN2029
TLIN2029
LIN Bus
LIN Bus
LIN Bus
LIN Bus
VBAT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLIN2024-Q1
SLLSF05B – APRIL 2018 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
4
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
ESD Ratings - IEC ....................................................
Thermal Information ..................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 20
8.1 Overview ................................................................. 20
8.2 Functional Block Diagram ....................................... 21
8.3 Feature Description................................................. 21
8.4 Device Functional Modes........................................ 25
9
Application and Implementation ........................ 27
9.1 Application Information............................................ 27
9.2 Typical Application ................................................. 27
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Example .................................................... 31
12 Device and Documentation Support ................. 32
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
33
33
13 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2018) to Revision B
Page
•
Changed Feature From: HBM Classification level: ±6 kV To: HBM Classification level: ±8 kV............................................. 1
•
Changed Feature From: ±58 V LIN bus fault protection To: ±60 V LIN bus fault protection ................................................ 1
•
Changed the VSUP1/2 MAX value From: 58 V To: 60 V in the Absolute Maximum Ratings. ................................................... 4
•
Changed the VLIN values From: -58 V to 58 V To: -60 V to 60 V in the Absolute Maximum Ratings................................... 4
•
Changed the VLOGIC MAX value From: 5.5 V To: 6 V in the Absolute Maximum Ratings..................................................... 4
•
Deleted J2962-1 ESD and ISO Pulses from ESD Ratings..................................................................................................... 4
•
Changed the HBM value from ±6000 to ±8000 in the ESD Ratings ...................................................................................... 4
•
Changed IEC 61000-4-2 to IEC 62228-2 and made three rows, two for contact and added indirect ESD ........................... 4
•
Changed ICC to ISUP................................................................................................................................................................. 5
•
Changed the Supply Current 4 V Sleep Mode TYP values From: 20 µA To: 7 µA and the MAX value From: 40 µA
To: 20 µA ................................................................................................................................................................................ 5
•
Changed the Supply Current 14 V Sleep Mode MAX value From: 60 µA To: 30 µA .......................................................... 5
•
Changed the CLINPIN MAX value From: 45 pF To: 25 pF ....................................................................................................... 6
•
Added TEST CONDITION: VSUP = 14 V to CLINPIN ............................................................................................................... 6
•
Changed From ±58 V To: ±60 V in Overview Section ........................................................................................................ 20
•
Cleaned up wording in Overview section second paragraph .............................................................................................. 20
Changes from Original (April 2018) to Revision A
•
2
Page
Changed RSLAVE Typical value from 30 kΩ to 45 kΩ in the Electrical Characteristics ........................................................... 6
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SLLSF05B – APRIL 2018 – REVISED DECEMBER 2019
5 Pin Configuration and Functions
NC
RXD1
RGY Package
24-Pin RGY (VQFN)
Top View
2
23
NC
3
22
LIN1
RXD2
4
21
VSUP1
EN2
5
20
LIN2
19
GND1
TXD2
1
24
EN1
TXD1
Thermal
6
Pad
RXD3
7
18
NC
17
LIN3
9
16
VSUP2
RXD4
10
15
LIN4
EN4
11
14
GND2
NC
TXD4
13
8
12
EN3
TXD3
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
RXD1
1
O
Channel 1 RXD Output (open-drain) interface reporting state of LIN bus voltage
EN1
2
I
Channel 1 Enable Input
TXD1
3
I
Channel 1 TXD input interface to control state of LIN output
RXD2
4
O
Channel 2 RXD Output (open-drain) interface reporting state of LIN bus voltage
EN2
5
I
Channel 2 Enable Input
TXD2
6
I
Channel 2 TXD input interface to control state of LIN output
RXD3
7
O
Channel 3 RXD Output (open-drain) interface reporting state of LIN bus voltage
EN3
8
I
Channel 3 Enable Input
TXD3
9
I
Channel 3 TXD input interface to control state of LIN output
RXD4
10
O
Channel 4 RXD Output (open-drain) interface reporting state of LIN bus voltage
EN4
11
I
Channel 4 Enable Input
TXD4
12
I
Channel 4 TXD input interface to control state of LIN output
GND2
14
GND
LIN4
15
I/O
VSUP2
16
Supply
LIN3
17
I/O
GND1
19
GND
LIN2
20
I/O
VSUP1
21
Supply
LIN1
22
I/O
13, 18, 23, 24
–
NC
Ground pin for Channels 3 and 4
Channel 4 LIN Bus single-wire transmitter and receiver
Channels 3 and 4 Supply Voltage (connected to battery in series with external reverse blocking diode
Channel 3 LIN Bus single-wire transmitter and receiver
Ground pin for Channels 1 and 2
Channel 2 LIN Bus single-wire transmitter and receiver
Channels 1 and 2 Supply Voltage (connected to battery in series with external reverse blocking diode
Channel 1 LIN Bus single-wire transmitter and receiver
Not Connected
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Symbol
Parameter
MIN
MAX
–0.3
60
V
LIN Bus input voltage (ISO/DIS 17987 Param 82)
–60
60
V
Logic Pin Voltage (RXDx, TXDx, ENx)
–0.3
6
V
TA
Ambient temperature range
–40
125
°C
TJ
Junction temperature range
–55
150
°C
Tstg
Storage temperature range
–65
150
°C
VSUP1/2
Supply voltage range (ISO/DIS 17987 Param 10)
VLIN
VLOGIC
(1)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
Human body model (HBM) RXD, EN Pins, per AEC Q100-002 (1)
±4000
Human body model (HBM) LIN and VSUP, per AEC Q100-002 (2)
±8000
Charged device model (CDM),
per AEC Q100-011
±1500
All terminals
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
LIN bus a stressed with respect to GND.
6.3 ESD Ratings - IEC
ESD and Surge Protection Ratings
Electrostatic discharge, LIN and VSUP to
GND, per IEC 62228-2
V(ESD)
(1)
VALUE
UNIT
Contact discharge, without LIN bus filter
capacitor (1)
±5000
V
Contact discharge, with LIN bus filter
capacitor (1)
±9000
V
Indirect ESD (1)
±15000
V
IEC 62228-2 ESD test performed by a third party. Different system level configurations may lead to different results
6.4 Thermal Information
TLIN2024
THERMAL METRIC (1)
RGY (QFN)
UNIT
24-PINS
RΘJA
Junction-to-ambient thermal resistance
34.3
°C/W
RΘJC(top)
Junction-to-case (top) thermal resistance
30.8
°C/W
RΘJB
Junction-to-board thermal resistance
13.3
°C/W
ΨJT
Junction-to-top characterization parameter
0.5
°C/W
ΨJB
Junction-to-board characterization parameter
13.3
°C/W
RΘJC(bot)
Junction-to-case (bottom) thermal resistance
2.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER - DEFINITION
MIN
NOM
MAX
UNIT
VSUP1/2
Supply voltage
4
48
V
VLINx
LINx Bus input voltage
0
45
V
VLOGIC
Logic Pin Voltage (RXDx, TXDx, ENx)
0
5.5
V
4
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER - DEFINITION
TSD
Thermal shutdown edge
TSD(HYS)
Thermal shutdown hysteresis
MIN
NOM
MAX
UNIT
165
°C
15
°C
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply
Operational supply voltage (ISO/DIS
17987 Param 10, 53)
VSUP
Nominal supply voltage (ISO/DIS
17987 Param 10, 53): Normal Mode:
Ramp VSUP while LIN signal is a 10
kHZ Square Wave with 50 % duty
cycle and 36V swing. Watch RXD
UVSUP
Under voltage VSUP threshold
UVHYS
Delta hysteresis voltage for VSUP
under voltage threshold
Supply Current (1)
ISUP
4
45
V
Normal and Standby Modes Normal
Mode: Ramp VSUP while LIN signal is a
10 kHZ Square Wave with 50 % duty
cycle and 36V swing. See Figure 8
and Figure 9
4
45
V
4
45
V
2.9
3.85
V
Sleep Mode
0.2
V
Normal Mode: EN = High, bus
dominant: total bus load where RLIN >
500 Ω and CLIN < 10 nF (See
Figure 14)
3
15
mA
Standby Mode: EN = Low, bus
dominant: total bus load where RLIN >
500 Ω and CLIN < 10 nF (See
Figure 14)
2.2
8
mA
Normal Mode: EN = High, Bus
Recessive: LIN = VSUP,
1
2
mA
Standby Mode: EN = Low, Bus
Recessive: LIN = VSUP,
40
80
µA
7
20
µA
Sleep Mode: 14 V < VSUP < 36 V, LIN
= VSUP, EN = 0 V, TXD and RXD
Floating
30
µA
0.6
V
Sleep Mode: 4.0 V < VSUP < 14 V, LIN
= VSUP, EN = 0 V, TXD and RXD
Floating
Supply Current (1)
ISUP
Device is operational beyond the LIN
defined nominal supply voltage range
See Figure 8 and Figure 9
RXD OUTPUT PIN (OPEN DRAIN)
VOL
Output Low voltage
Based upon External pull up to VCC
IOL
Low level output current, open drain
LIN = 0 V, RXD = 0.4 V
1.5
IILG
Leakage current, high-level
LIN = VSUP, RXD = 5 V
–5
mA
0
5
µA
TXD INPUT PIN
VIL
Low level input voltage
–0.3
0.8
V
VIH
High level input voltage
2
5.5
V
VIT
Input threshold voltage, normal
modes& selective wake modes
30
500
mV
IILG
Low level input leakage current
–5
0
5
µA
RTXD
Interal pulldown resitor value
125
350
800
kΩ
VIL
Low level input voltage
–0.3
0.8
V
VIH
High level input voltage
2
5.5
V
TXD = Low
EN INPUT PIN
(1)
Values are for each VSUP pin
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIT
Hysteresis voltage
By design and characterization
30
500
V
IILG
Low level input current
EN = Low
-5
0
5
µA
REN
Internal Pulldown resistor
125
350
800
kΩ
LIN PIN
VOH
High level output voltage
VOL
Low level output voltage
LIN recessive, TXD = high, IO = 0 mA,
VSUP = 7 V to 45 V
0.85
VSUP
LIN recessive, TXD = high, IO = 0 mA,
4 V ≤ VSUP < 7 V
3.0
V
LIN dominant, TXD = low, VSUP = 7 V
to 45 V
0.2
VSUP
LIN dominant, TXD = low, 4 V ≤
VSUP < 7 V
1.2
V
58
V
200
mA
VSUP_NON_OP
VSUP where Impact of recessive LIN
Bus < 5% (ISO/DIS 17987 Param 56)
IBUS_LIM
TXD = 0 V, VLIN = 36 V, RMEAS = 440
Limiting current (ISO/DIS 17987 Param
Ω, VSUP = 36 V, VBUSdom < 4.518 V
57)
See Figure 13
75
IBUS_PAS_dom
Receiver leakage current, dominant
(ISO/DIS 17987 Param 58)
LIN = 0 V, VSUP = 24 V Driver
off/recessive See Figure 14
-1
IBUS_PAS_rec
Receiver leakage current, recessive
(ISO/DIS 17987 Param 59)
LIN > VSUP, 4 V < VSUP < 45 V Driver
off; See Figure 15
IBUS_NO_GND
Leakage current, loss of ground
(ISO/DIS 17987 Param 60)
GND = VSUP, 0 V ≤ VLIN ≤ 36 V, VSUP
= 24 V; See Figure 16
IBUS_NO_BAT
Leakage current, loss of supply
(ISO/DIS 17987 Param 16, 61)
LIN = 36 V, VSUP = GND;
See Figure 17
VBUSdom
Low level input voltage (ISO/DIS
17987 Param 17, 62)
LIN dominant (including LIN dominant
for wake up)
See Figure 11 and Figure 10
VBUSrec
High level input voltage (ISO/DIS
17987 Param 18, 63)
Lin recessive
See Figure 11 and Figure 10
0.6
VBUS_CNT
Receiver center threshold (ISO/DIS
17987 Param 19, 64)
VBUS_CNT = (VIL + VIH)/2
See Figure 11 and Figure 10
0.475
VHYS
Hysteresis voltage (ISO/DIS 17987
Param 20, 65)
VHYS = (VIL - VIH)
See Figure 11 and Figure 10
0.05
VSERIAL_DIODE
Serial diode LIN term pullup path
(ISO/DIS 17987 Param 21, 66)
By design and characterization
0.4
0.7
1
V
RSLAVE
Pullup resistor to VSUP (ISO/DIS
17987 Param 26, 71)
Normal and Standby modes
20
45
60
kΩ
IRSLEEP
Pullup current source to VSUP
Sleep mode, VSUP = 27 V, LIN = GND
-2
µA
CLINPIN
Capacitance of LIN pin
25
pF
TXD& RXD open LIN = 4 V to 58 V
-0.3
120
mA
-1.5
20
µA
1.5
mA
5
µA
0.4
VSUP
VSUP
0.5
-20
VSUP = 14 V
0.525
VSUP
0.175
VSUP
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
D112V
(1)
6
TEST CONDITIONS
Duty Cycle 1 (ISO/DIS 17987 Param
27) (1)
MIN
THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP, VSUP = 7
V to 18 V, tBIT = 50 µs (20 kbps), D1 =
tBUS_rec(min)/(2 x tBIT)
(See Figure 18 and Figure 19)
TYP
MAX
UNIT
0.396
Duty cycles: LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω. Duty cycles 3 and 4 are
defined for 10.4-kbps operation. The TLIN1029 also meets these lower data rate requirements, while it is capable of the higher speed
20-kbps operation as specified by duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle
definitions, for details see the SAEJ2602 specification
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Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
D112V
Duty Cycle 1
THREC(MAX) = 0.625 x VSUP,
THDOM(MAX) = 0.581 x VSUP, VSUP = 4
V to 7 V, tBIT = 50 µs (20 kbps), D1 =
tBUS_rec(min)/(2 x tBIT)
(See Figure 18 and Figure 19)
D212V
Duty Cycle 2 (ISO/DIS 17987 Param
28)
THREC(MAX) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP, VSUP = 4.6
V to 18 V, tBIT = 50 µs (20 kbps), D2 =
tBUS_rec(MAX)/(2 x tBIT)
(See Figure 18 and Figure 19)
Duty Cycle 3 (ISO/DIS 17987 Param
29)
THREC(MAX) = 0.778 x VSUP,
THDOM(MAX) = 0.616 x VSUP, VSUP = 7
V to 18 V, tBIT = 96 µs (10.4 kbps), D3
= tBUS_rec(min)/(2 x tBIT)
(See Figure 18 and Figure 19)
0.417
D312V
Duty Cycle
THREC(MAX) = 0.645 x VSUP,
THDOM(MAX) = 0.616 x VSUP, VSUP = 4
V to 7 V, tBIT = 96 µs (10.4 kbps), D3 =
tBUS_rec(min)/(2 x tBIT)
(See Figure 18 and Figure 19)
0.417
D412V
Duty Cycle 4 (ISO/DIS 17987 Param
30)
THREC(MIN) = 0.389 x VSUP, THDOM(MIN)
= 0.251 x VSUP, VSUP = 4.6 V to 18 V,
tBIT = 96 µs (10.4 kbps), D4 =
tBUS_rec(MAX)/(2 x tBIT)
(See Figure 18 and Figure 19)
D124V
Duty Cycle 1 (ISO/DIS 17987 Param
27) (1)
THREC(MAX) = 0.710 x VSUP,
THDOM(MAX) = 0.544 x VSUP, VSUP = 15
V to 36 V, tBIT = 50 µs (20 kbps), D1 =
tBUS_rec(min)/(2 x tBIT)
(See Figure 18 and Figure 19)
D224V
Duty Cycle 2 (ISO/DIS 17987 Param
28)
THREC(MAX) = 0.446 x VSUP,
THDOM(MIN) = 0.302 x VSUP, VSUP =
15.6 V to 36 V, tBIT = 50 µs (20 kbps),
D2 = tBUS_rec(MAX)/(2 x tBIT)
(See Figure 18 and Figure 19)
D324V
Duty Cycle 3 (ISO/DIS 17987 Param
29)
THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP, VSUP = 7
V to 36 V, tBIT = 96 µs (10.4 kbps), D3
= tBUS_rec(min)/(2 x tBIT)
(See Figure 18 and Figure 19)
0.386
Duty Cycle
THREC(MAX) = 0.645 x VSUP,
THDOM(MAX) = 0.581 x VSUP, VSUP = 4
V to 7 V, tBIT = 96 µs (10.4 kbps), D3 =
tBUS_rec(min)/(2 x tBIT)
(See Figure 18 and Figure 19)
0.386
Duty Cycle 4 (ISO/DIS 17987 Param
30)
THREC(MIN) = 0.442 x VSUP, THDOM(MIN)
= 0.284 x VSUP, VSUP = 4.6 V to 36 V,
tBIT = 96 µs (10.4 kbps), D4 =
tBUS_rec(MAX)/(2 x tBIT)
(See Figure 18 and Figure 19)
D312V
D324V
D424V
TYP
MAX
UNIT
0.396
0.581
0.59
0.33
0.642
0.591
6.8 Timing Requirements
SYMBOL
trx_pdr
trx_pdf
DESCRIPTION
TEST CONDITIONS
Receiver rising propagation delay time
(ISO/DIS 17987 Param 31)
RRXD = 2.4 kΩ, CRXD = 20 pF
Receiver falling propagation delay time (See Figure 20 and Figure 21)
(ISO/DIS 17987 Param 31)
MIN
NOM
MAX
6
µs
6
µs
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Timing Requirements (continued)
SYMBOL
DESCRIPTION
TEST CONDITIONS
MIN
trs_sym
Symmetry of receiver propagation
delay time Receiver rising propagation
delay time (ISO/DIS 17987 Param 32)
Rising edge with respect to falling
edge, (trx_sym = trx_pdf – trx_pdr),
RRXD = 2.4 kΩ, CRXD = 20 pF
(See Figure 20 and Figure 21)
tLINBUS
LIN wakeup time (Minimum dominant
time on LIN bus for wakeup)
See Figure 24, Figure 27,
and Figure 28
tCLEAR
Time to clear false wakeup prevention
logic if LIN bus had a bus stuck
dominant fault (recessive time on LIN
bus to clear bust stuck dominant fault)
See Figure 28
tDST
Dominant state time out
–2
25
NOM
MAX
UNIT
2
µs
100
150
µs
8
17
50
µs
20
34
80
ms
15
µs
tMODE_CHANGE
Mode change delay time
Time to change from standby mode to
normal mode or normal mode to sleep
mode through EN pin: See Figure 22
and Figure 29
tNOMINT
Normal mode initialization time
Time for normal mode to initialize and
data on RXD pin to be valid
See Figure 22
35
µs
tPWR
Power up time
Upon power up time it takes for valid
data on RXD
1.5
ms
2
6.9 Typical Characteristics
60
0.81
55
0.78
50
0.75
0.72
45
0.69
40
0.66
VOL (V)
VOH (V)
35
30
25
0.6
0.57
20
Lane 1 (-55°C)
Lane 1 (25°C)
Lane 1 (125°C)
Lane 2 (-55°C)
Lane 2 (25°C)
Lane 2 (125°C)
15
10
5
0.54
Lane 3 (-55°C)
Lane 3 (25°C)
Lane 3 (125°C)
Lane 4 (-55°C)
Lane 4 (25°C)
Lane 4 (125°C)
Lane 1 (-55°C)
Lane 1 (25°C)
Lane 1 (125°C)
Lane 2 (-55°C)
Lane 2 (25°C)
Lane 2 (125°C)
0.51
0.48
0.45
0
Lane 3 (-55°C)
Lane 3 (25°C)
Lane 3 (125°C)
Lane 4 (-55°C)
Lane 4 (25°C)
Lane 4 (125°C)
0.42
0
5
10
15
20
25
30
35
VSUP Voltage Supply (V)
40
45
50
55
60
0
5
10
15
D001
Figure 1. VOH vs VSUP and Temperature
8
0.63
20
25
30
35
VSUP Voltage Supply (V)
40
45
50
55
60
D002
Figure 2. VOL vs VSUP and Temperature
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15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2.6
-55°C
25°C
125°C
ISUP Normal Mode Recessive (mA)
ISUP Normal Mode Dominant (mA)
Typical Characteristics (continued)
-55°C
25°C
125°C
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0
5
10
15
20
25 30 35
VSUP (V)
40
45
50
55
60
0
5
15
20
25 30 35
VSUP (V)
40
45
50
55
60
D004
Figure 4. Normal Mode Recessive vs VSUP
30
-55°C
25°C
125°C
ISUP Standby Mode Recessive (µA)
ISUP Standby Mode Dominant (mA)
Figure 3. Normal Mode Dominant vs VSUP
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
10
D003
-55°C
25°C
125°C
28
26
24
22
20
18
16
14
12
10
0
5
10
15
20
25 30 35
VSUP (V)
40
45
50
55
60
0
5
10
15
20
D005
Figure 5. Standby Mode Dominant vs VSUP
25 30 35
VSUP (V)
40
45
50
55
60
D006
Figure 6. Standby Mode Recessive vs VSUP
28
-55°C
25°C
125°C
ISUP Sleep Current (µA)
26
24
22
20
18
16
14
12
0
5
10
15
20
25 30 35
VSUP (V)
40
45
50
55
60
D007
Figure 7. Sleep Mode vs VSUP
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7 Parameter Measurement Information
1,4,7,10
NC
RXD1/2/3/4
13,18,23,24
5V
VSUP1/2
EN1/2/3/4
16,21
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS
2,5,8,11
LIN1/2/3/4
3,6,9,12
TXD1/2/3/4
15,17,20,22
14,19
GND1/2
Pulse Generator
tR/tF: Square Wave: < 20 ns
:
tR/tF Triangle Wave: < 40ns
Frequency: 20 ppm
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
Figure 8. Test System: Operating Voltage Range with RX and TX Access
Trigger Point
Delta t = + 5 µs (tBIT = 50 µs)
x
x
RX
x
2 x tBIT = 100 µs (20 kBaud)
x
Figure 9. RX Response: Operating Voltage Range
Period T = 1/f
Amplitude
(signal range)
LIN Bus Input
Frequency: f = 20 Hz
Symmetry: 50%
Figure 10. LIN Bus Input Signal
10
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Parameter Measurement Information (continued)
1,4,7,10
NC 13,18,23,24
RXD1/2/3/4
5V
VSUP1/2
EN1/2/3/4
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
16,21
VPS
2,5,8,11
LIN1/2/3/4
2,6,9,12 TXD1/2/3/4
GND1/2
15,17,20,22
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
Jitter: < 25 ns
14,19
Measurement Tools
O-scope:
DMM
Figure 11. LIN Receiver Test with RX Access
1,4,7,10
NC 13,18,23,24
RXD1/2/3/4
5V
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VSUP1/2 16,21
EN1/2/3/4
2,5,8,11
VPS1
D
LIN1/2/3/4 15, 17, 20, 22
14,19
2,6,9,12 TXD1/2/3/4
GND1/2
RBUS
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS2
Measurement Tools
O-scope:
DMM
Figure 12. VSUP_NON_OP
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Parameter Measurement Information (continued)
1,4,7,10
NC
RXD1/2/3/4
13,18,23,24
5V
VSUP1/2
EN1/2/3/4
Power Supply
Resolution: 10 mV / 1mA
Accuracy: 0.2%
VPS
16,21
2,5, 8,11
15,17,20,22
LIN1/2/3/4
Pulse Generator
tR/tF: Square Wave: < 20 ns
:
tR/tF Triangle Wave: < 40ns
Frequency: 20 ppm
T = 10 ms
Jitter: < 25 ns
TXD1/2/3/4
RMEAS
14,19
GND1/2
Measurement Tools
O-scope:
DMM
Figure 13. Test Circuit for IBUS_LIM at Dominant State (Driver on)
1,4,7,10
NC 13,18,23,24
RXD1/2/3/4
5V
VSUP1/2
EN1/2/3/4
16,21
2,5, 8,11
15,17,20,22
LIN1/2/3/4
2,6,9,12 TXD1/2/3/4
Power Supply
Resolution: 10 mV / 1mA
Accuracy: 0.2%
VPS
RMEAS = 499 Ÿ
14,19
GND1/2
Measurement Tools
O-scope:
DMM
Figure 14. Test Circuit for IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V
12
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Parameter Measurement Information (continued)
1,4,7,10
NC 13,18,23,24
RXD1/2/3/4
Power Supply
Resolution: 10 mV / 1mA
Accuracy: 0.2%
VPS1
5V
VSUP1/2
EN1/2/3/4
16,21
2,5, 8,11
15,17,20,22
1 kŸ
LIN1/2/3/4
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS2
2,6,9,12 TXD1/2/3/4
14,19
GND1/2
VPS2 2 V/s ramp
[8 V à 36 V]
V Drop across resistor
< 20 mV
Measurement Tools
O-scope:
DMM
Figure 15. Test Circuit for IBUS_PAS_rec
1,4,7,10
NC 13,18,23,24
RXD1/2/3/4
Power Supply
Resolution: 10 mV / 1mA
Accuracy: 0.2%
VPS1
5V
VSUP1/2
EN1/2/3/4
16,21
2,5, 8,11
15,17,20,22
1 kŸ
LIN1/2/3/4
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS2
2,6,9,12 TXD1/2/3/4
14,19
GND1/2
VPS2 2 V/s ramp
[0 V Æ 36 V]
V Drop across resistor
< 1V
Measurement Tools
O-scope: DMM
Figure 16. Test Circuit for IBUS_NO_GND Loss of GND
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Parameter Measurement Information (continued)
1,4,7,10
NC 13,18,23,24
RXD1/2/3/4
5V
VSUP1/2
EN1/2/3/4
16,21
2,5, 8,11
15,17,20,22
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
1 kŸ
LIN1/2/3/4
VPS
2,6,9,12 TXD1/2/3/4
14,19
GND1/2
VPS2 2 V/s ramp
[0 V Æ 36 V]
V Drop across resistor
< 1V
Measurement Tools
O-scope: DMM
Figure 17. Test Circuit for IBUS_NO_BAT Loss of Battery
1,4,7,10
NC 13,18,23,24
RXD1/2/3/4
Power Supply
Resolution: 10 mV / 1mA
Accuracy: 0.2%
VPS1
5V
VSUP1/2
EN1/2/3/4
16,21
2,5, 8,11
15,17,20,22 RMEAS
LIN1/2/3/4
Pulse Generator
tR/tF: Square Wave: < 20 ns
:
tR/tF Triangle Wave: < 40ns
Frequency: 20 ppm
Jitter: < 25 ns
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS2
TXD1/2/3/4
2,6,9,12
14,19
GND1/2
Measurement Tools
O-scope:
DMM
Figure 18. Test Circuit Slope Control and Duty Cycle
14
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Parameter Measurement Information (continued)
tBIT
tBIT
RECESSIVE
D = 0.5
TXD (Input)
DOMINANT
THREC(MAX)
Thresholds
RX Node 1
THDOM(MAX)
LIN Bus
Signal
VSUP
THREC(MIN)
Thresholds
RX Node 2
THDOM(MIN)
tBUS_DOM(MAX)
tBUS_REC(MIN)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
D = tBUS_REC(MIN)/(2 x tBIT)
tBUS_DOM(MIN)
tBUS_REC(MAX)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
D = tBUS_REC(MAX)/(2 x tBIT)
Figure 19. Definition of Bus Timing Parameters
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Parameter Measurement Information (continued)
VCC
2.4 NŸ
1,4,7,10
NC 13,18,23,24
RXD1/2/3/4
20 pF
5V
VSUP1/2
EN1/2/3/4
Power Supply
Resolution: 10 mV / 1mA
Accuracy: 0.2%
VPS
16,21
2,5, 8,11
15,17,20,22
Pulse Generator
tR/tF: Square Wave: < 20 ns
:
tR/tF Triangle Wave: < 40ns
Frequency: 20 ppm
Jitter: < 25 ns
LIN1/2/3/4
2,6,9,12 TXD1/2/3/4
14,19
GND1/2
Measurement Tools
O-scope: DMM
Figure 20. Propagation Delay Test Circuit
THREC(MAX)
Thresholds
RX Node 1
THDOM(MAX)
LIN Bus
Signal
VSUP
THREC(MIN)
Thresholds
RX Node 2
THDOM(MIN)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
trx_pdr(1)
trx_pdf(1)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
trx_pdr(2)
trx_pdf(2)
Figure 21. Propagation Delay
16
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Parameter Measurement Information (continued)
Wake Event
tMODE_CHANGE
EN
tMODE_CHANGE
Normal
MODE
RXD
Mirrors Bus
tNOMINT
Transition
Sleep
Standby
Transition
Indeterminate
Ignore
Floating
Wake Request
RXD = Low
Indeterminate Ignore
Normal
Mirrors
Bus
Figure 22. Mode Transitions
EN
TXD
Weak Internal Pullup
Weak Internal Pullup
VSUP
LIN
RXD
Floating
MODE
Sleep
Normal
Figure 23. Wake Up Through EN
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Parameter Measurement Information (continued)
0.6 x VSUP
LIN
0.6 x VSUP
VSUP
0.4 x VSUP
0.4 x VSUP
t < tLINBUS
TXD
tLINBUS
Weak Internal Pullup
EN
RXD
MODE
Floating
Sleep
Standby
Normal
Figure 24. Wake Up Through LIN
18
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Parameter Measurement Information (continued)
RRXD1
RXD1
CLIN1
CRXD1
LIN1
EN1
RLIN1
TXD1
VSUP1
RRXD2
100 nF
RXD2
RLIN2
CRXD2
LIN2
CLIN2
EN2
GND1
TXD2
RRXD3
RXD3
CRXD3
CLIN3
LIN3
EN3
RLIN3
TXD3
RRXD4
VSUP2
RXD4
100 nF
CRXD4
RLIN4
EN4
LIN4
CLIN4
TXD4
GND2
Figure 25. Test Circuit for AC Characteristics
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8 Detailed Description
8.1 Overview
The TLIN2024-Q1 device is a Quad Local Interconnect Network (LIN) physical layer transceiver, compliant to LIN
2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4.2, with integrated wake-up and protection features. The
TLIN2024-Q1 has two separate dual LIN transceiver blocks. VSUP1/2 provides power to the separate dual
transceiver blocks. The LIN bus is a single wire bidirectional bus typically used for low speed in vehicle networks
using data rates up to 20 kbps. The TLIN2024-Q1 LIN receivers work up to 100 kbps supporting in-line
programming. The LIN protocol output data stream on the TXD in converted by the TLIN2024-Q1 into LIN bus
signal using a current-limited wave shaping driver as outlined by the LIN physical layer specification. The
receiver converts the data stream to logic level signals that are sent to the microprocessor through the open
drain RXD pin. The LIN bus has two states: dominant state (voltage near ground) and recessive state (voltage
near battery). In the recessive state, the LIN bus is pulled high by the internal pull-up resistor (45 kΩ) and a
series diode. No external pull-up components are required for slave applications. Master applications require an
external pull-up resistor (1 kΩ) plus a series diode per the LIN specification. The TLIN2024-Q1 provides many
protection features such as ESD, EMC and high bus standoff voltage.
The TLIN2024-Q1 support wide operating ranges with VSUP1/2 of 4 V to 48 V, ±60 V LIN bus fault protection, -40
to +125 C TA. Sleep mode is supported which is Ultra-Low current consumption. There are two methods to wake
up the TLIN2024-Q1 from sleep mode; by the LIN bus and local wake-up using the EN pin. The TLIN2024-Q1
provides protection features that include ±8 kV HBM and IEC ESD protection on LIN pins, under voltage
protection on VSUP1/2, TXD dominant time out protection (DTO), thermal shutdown protection and unpowered
node or ground disconnection failsafe at system level. VSUP1 and GND1 supplies transceivers 1 and 2 while
VSUP2 and GND2 supplies transceiver 3 and 4. The TLIN2024-Q1 is part of the LIN family that includes the
TLIN2022 and TLIN2029 LIN transceivers.
20
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8.2 Functional Block Diagram
VSUP1
RXD1 1
VSUP1/2
Comp
45 k
GND1
Filter
Wake Up
State &
EN1 2
350 k
Fault Detection
& Protection
22 LIN1
GND1
TXD1 3
350 k
Dominant
State
Timeout
21 VSUP1
DR/
Slope
CTL
18 GND1
GND1
GND1
GND1
RXD2 4
EN2 5
Channel 2 is same as Channel 1
20 LIN2
TXD2 6
VSUP2
RXD3 7
VSUP2/2
Comp
45 k
GND2
Filter
Wake Up
State &
EN3 8
350 k
Fault Detection
& Protection
17 LIN3
DR/
Slope
CTL
16 VSUP2
GND2
TXD3 9
350 k
Dominant
State
Timeout
14 GND2
GND2
GND2
GND2
RXD4 10
EN4 11
Channel 4 is same as Channel 3
15 LIN4
TXD4 12
8.3 Feature Description
8.3.1 LIN (Local Interconnect Network) Bus
These high voltage input/output pins are single wire LIN bus transmitters and receivers. The LIN pins can survive
excessive DC and transient voltages up to 58 V. Reverse currents from the LIN pins to supply (VSUP1/2) are
minimized with blocking diodes, even in the event of a ground shift or loss of supply (VSUP1/2).
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Feature Description (continued)
8.3.1.1 LIN Transmitter Characteristics
The transmitter has thresholds and AC parameters according to the LIN specification. The transmitter is a low
side transistor with and internal current limitation and thermal shutdown. During a thermal shutdown condition,
the transmitter is disabled to protect the device. There is an internal pull-up resistor with a serial diode structure
to VSUP1/2, so no external pull-up components are required for the LIN slave mode applications. An external pullup resistor and series diode to VSUP1/2 must be added when the device is used for a master node application.
8.3.1.2 LIN Receiver Characteristics
The receiver characteristic thresholds are ratio-metric with the device supply pin according to the LIN
specification.
The receiver is capable of receiving higher data rates (> 100 kbps) than supported by LIN or SAE J2602
specifications. This allows the TLIN2024-Q1 to be used for high speed downloads at the end-of-line production or
other applications. The actual data rate achievable depends on system time constants (bus capacitance and pullup resistance) and driver characteristics used in the system.
8.3.1.2.1 Termination
There is an internal pull-up resistor with a serial diode structure to VSUP1/2, so no external pull-up components are
required for the LIN slave mode applications. An external pull-up resistor (1 kΩ) and a series diode to VSUP1/2
must be added when the device is used for master node applications as per the LIN specification.
Figure 26 shows a Master Node configuration and how the voltage levels are defined
Simplified Transceiver
RXD
VLIN_Bus
VSUP
VSUP/2
Voltage drop across the
diodes in the pullup path
VSUP
VBattery
VSUP
Receiver
VLIN_Recessive
Filter
1 NŸ
45 NŸ
LIN 1/2/3/4
LIN
Bus
TXD
350 NŸ
GND
Transmitter
with slope control
VLIN_Dominant
t
Figure 26. Master Node Configuration with Voltage Levels
8.3.2 TXD (Transmit Input/Output)
TXD is the interface to the processors LIN protocol controller or SCI/UART that is used to control the state of the
LIN output. When TXD is low the LIN output is dominant (near ground). When TXD is high the LIN output is
recessive (near VBattery). See Figure 26. The TXD input structure is compatible with microprocessors with 3.3 V
and 5 V I/O. TXD has an internal pull-down resistor. The LIN bus is protected from being stuck dominant through
a system failure driving TXD low through the dominant state timer-out timer.
8.3.3 RXD (Receive Output)
RXD is the interface to the processors LIN protocol controller or SCI/UART, which reports the state of the LIN
bus voltage. LIN recessive (near VBattery) is represented by a high level on the RXD and LIN dominant (near
ground) is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage.
This allows the device to be used with 3.3 V and 5 V I/O microprocessors. If the microprocessor’s RXD pin does
not have an integrated pull-up, an external pull-up resistor to the microprocessor I/O supply voltage is required.
In standby mode the RXD pin is driven low to indicate a wake up request from the LIN bus.
22
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Feature Description (continued)
8.3.4 VSUP1/2 (Supply Voltage)
VSUP1/2 are the power supply pins. VSUP1/2 is connected to the battery through and external reverse battery
blocking diode (See Figure 26). If there is a loss of power at the ECU level, the device has extremely low
leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems in which some of
the nodes are unpowered (ignition supplied) while the rest of the network remains powered (battery supplied).
8.3.5 GND (Ground)
GND1/2 are the device ground connections. The device can operate with a ground shift as long as the ground
shift does not reduce VSUP1/2 below the minimum operating voltage. If there is a loss of ground at the ECU level,
the device has a low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN
systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains
powered (battery supplied).
8.3.6 EN (Enable Input)
EN controls the operational modes of the device. When EN is high the device is in normal operating mode
allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low the device is put into sleep
mode and there are no transmission paths available. The device can enter normal mode only after wake up. EN
has an internal pull-down resistor to endure the device remains in low power mode even if EN floats.
8.3.7 Protection Features
The TLIN2024-Q1 has several protection features that will now be described.
8.3.8 TXD Dominant Time Out (DTO)
During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application
failure, the LIN bus is protected by the dominant state timeout timer. This timer is triggered by a falling edge on
the TXD pin. If the low signal remains on TXD for longer than tDST, the transmitter is disabled, thus allowing the
LIN bus to return to recessive state and communication to resume on the bus. The protection is cleared and the
tDST timer is reset by a rising edge on TXD. The TXD pin has an internal pull-down to ensure the device fails to a
known state if TXD is disconnected. During this fault, the transceiver remains in normal mode (assuming no
change of stated request on EN), the transmitter is disabled, the RXD pin reflects the LIN bus and the LIN bus
pull-up termination remains on.
8.3.9 Bus Stuck Dominant System Fault: False Wake Up Lockout
The TLIN2024-Q1 contains logic to detect bus stuck dominant system faults and prevents the device from
waking up falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus.
If the bus is dominant, the wake up logic is locked out until a valid recessive on the bus “clears” the bus stuck
dominant, preventing excessive current use Figure 27 and Figure 28 show the behavior of this protection.
EN
LIN Bus
tLINBUS
< tLINBUS
< tLINBUS
Figure 27. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wakeup
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Feature Description (continued)
EN
tLINBUS
tLINBUS
tLINBUS
LIN Bus
tCLEAR
< tCLEAR
Figure 28. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wakeup
8.3.10 Thermal Shutdown
The LIN transmitter is protected limiting the current; however if the junction temperature of the device exceeds
the thermal shutdown threshold, the device puts the LIN transmitter into the recessive state. Once the over
temperature fault condition has been removed and the junction temperature has cooled beyond the hysteresis
temperature, the transmitter is re-enabled, assuming the device remained in the normal operation mode. During
this fault, the transceiver remains in normal mode (assuming no change of state request on EN), the transmitter
is in recessive state, the RXD pin reflects the LIN bus and LIN bus pull-up termination remains on.
8.3.11 Under Voltage on VSUP
The TLIN2024-Q1 contains a power on reset circuit to avoid false bus messages during under voltage conditions
when VSUP1/2 is less than UVSUP1/2.
8.3.12 Unpowered Device and LIN Bus
In automotive applications some LIN nodes in a system can be unpowered (ignition supplied) while others in the
network remains powered by the battery. The TLIN2024-Q1 has a low unpowered leakage current from the bus
so an unpowered node does not affect the network or load it down.
24
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8.4 Device Functional Modes
The TLIN2024-Q1 has three functional modes of operation, normal, sleep, and standby. The next sections
describe these modes as well as how the device moves between the different modes. Figure 29 graphically
shows the relationship while Table 1 shows the state of pins.
Table 1. Operating Modes
MODE
ENx
RXDx
LIN BUS
TERMINATION
TRANSMITTER
Sleep
Low
Floating
Weak Current Pullup
Off
Standby
Low
Low
45 kΩ (typical)
Off
Wake up event detected, waiting on
MCU to set EN
Normal
High
LINx Bus Data
45 kΩ (typical)
On
LINx transmission up to 20 kbps
COMMENT
Unpowered System
VSUP < VSUP_UNDER
VSUP < VSUP_UNDER
VSUP > VSUP_UNDER
EN = High
VSUP > VSUP_UNDER
EN = Low
VSUP < VSUP_UNDER
VSUP < VSUP_UNDER
Standby Mode
Driver: Off
RXD: Low
Termination: 45 kŸ
Normal Mode
EN = High
Driver: On
RXD: LIN Bus Data
Termination: 45 kŸ
LIN Bus Wake up
EN = Low
Sleep Mode
Driver: Off
RXD: Floating
Termination: Weak pullup
EN = High
Figure 29. Operating State Diagram
8.4.1 Normal Mode
If the EN pin is high at power up, the device powers up in normal mode. The EN pin controls the mode of the
device. In normal operational mode, the receiver and transmitter are active and the LIN transmission up to the
LIN specified maximum of 20 kbps is supported. The receiver detects the data stream on the LIN bus and
outputs it on RXD for the LIN controller. A recessive signal on the LIN bus is a digital high and a dominate signal
on the LIN bus is a digital low. The driver transmits input data from TXD to the LIN bus. Normal mode is entered
as EN transitions high while the TLIN2024-Q1 is in sleep or standby mode for > tMODE_CHANGE.
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8.4.2 Sleep Mode
Sleep Mode is the power saving mode for the TLIN2024-Q1. Even with extremely low current consumption in this
mode, the TLIN2024-Q1 can still wake up from LIN bus through a wake up signal or if EN is set high for >
tMODE_CHANGE. The Lin bus is filtered to prevent false wake up events. The wake up events must be active for the
respective time periods (tLINBUS).
The sleep mode is entered by setting EN low for longer than tMODE_CHANGE.
While the device is in sleep mode, the following conditions exist.
• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if
LIN is short circuited to ground). However, the weak current pull-up is active to prevent false wake up events
in case an external connection to the LIN bus is lost.
• The normal receiver is disabled.
• EN input and LIN wake up receiver are active.
8.4.3 Standby Mode
During power up if EN is low the device enters standby mode. Standby mode is entered whenever a wake up
event occurs through LIN bus while the device is in sleep mode. The LIN bus slave termination circuit is turned
on when standby mode is entered. Standby mode is signaled through a low level on RXD. See Standby Mode
Application Note for more application information.
When EN is set high for longer than tMODE_CHANGE while the device is in standby mode the device returns to
normal mode and the normal transmission paths from TXD to LIN bus and LIN bus to RXD are enabled.
8.4.4 Wake Up Events
There are two ways to wake up from sleep mode:
• Remote wake up initiated by the falling edge of a recessive (high) to dominant (low) state transition on LIN
bus where the dominant state is be held for tLINBUS filter time. After this tLINBUS filter time has been met and a
rising edge on the LIN bus going from dominate state to recessive state initiates a remote wake up event,
eliminating false wake ups from disturbances on the LIN bus or if the bus is shorted to ground.
• Local wake up through EN being set high for longer than tMODE_CHANGE.
8.4.4.1 Wake Up Request (RXD)
When the TLIN2024-Q1 encounters a wake up event from the LIN bus, RXD goes low and the device transitions
to standby mode until EN is reasserted high and the device enters normal mode. Once the device enters normal
mode the RXD pin is releasing the wake up request signal and the RXD pin then reflects the receiver output from
the LIN bus.
8.4.4.2 Mode Transitions
When the TLIN2024-Q1 is transitioning between modes the device needs the time, tMODE_CHANGE, to allow the
change to fully propagate from the EN pin through the device into the new state. When transitioning from sleep
or standby mode to normal mode the transition time is the sum of tMODE_CHANGE and tNOMINT.
26
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLIN2024-Q1 can be used as both a slave device and a master device in a LIN network. The device comes
with the ability to support both remote wake up request and local wake up request.
9.2 Typical Application
The device comes with an integrated 45 kΩ pull-up resistor and series diode for slave applications. For master
applications, an external 1 kΩ pull-up resistor with series blocking diode can be used. Figure 30 shows the
device being used in both master and slave applications.
24 V - VBAT
VSUP
VREG
VSUP
VDD
VDD
VSUP2
VDD
I/O
I/O
MCU
EN1
EN2
Master
Node
Pullup
VSUP1
16 21
2
1 NŸ
5
VDD I/O
MCU w/o
pullup(2)
22
LIN1
220 pF
1
RXD1
TXD1
3
20
VDD I/O
LIN2
MCU w/o
pullup(2)
220 pF
4
17
LIN Bus
TLIN2024
MCU w/o
pullup(2)
LIN Bus
TXD2
VDD I/O
LIN Bus
6
LIN Controller
Or
SCI/UART(1)
LIN Bus
RXD2
LIN3
7
RXD3
TXD3
220 pF
9
VDD I/O
MCU w/o
pullup(2)
RXD4
TXD4
I/O
EN3
I/O
EN4
GND
15
LIN4
10
220 pF
12
8
11
14
19
Figure 30. Typical LIN Bus
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Typical Application (continued)
9.2.1 Design Requirements
1. RXD on MCU or LIN slave has internal pull-up; no external pull-up resistor is needed.
2. RXD on MCU or LIN slave without internal pull-up requires external pull-up resistor.
3. Master node applications require and external 1 kΩ pull-up resistor and serial diode.
4. Decoupling capacitor values are system dependant but usually have a 100 nF, 1 µF and ≥ 10 µF.
9.2.2 Detailed Design Procedure
The RXD output structure is an open drain output stage. This allows the TLIN2024-Q1 to be used with 3.3 V and
5 V I/O microprocessors. If the RXD pin of the microprocessor does not have an integrated pull-up, an external
pull-up resistor to the microprocessor I/O supply voltage is required.
The VSUP1/2 pins of the device should be decoupled with a 100 nF capacitor as close to the supply pin on the
device as possible.
9.2.2.1 Normal Mode Application Note
When using the TLIN2024-Q1 in systems which are monitoring the RXD pin for a wake up request, special care
should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition period
between states as the receivers are switched. The application software should not look for an edge on the RXD
pin indicating a wake up request until tMODE_CHANGE plus tNOMINT when going from sleep or standby to normal
mode. This is shown in Figure 22
9.2.2.2 Standby Mode Application Note
If the TLIN2024-Q1 detects an under voltage on VSUP1/2, the RXD pin transitions low and would signal to the
software that the TLIN2024-Q1 is in standby mode and should be returned to sleep mode for the lowest power
state.
9.2.2.3 TXD Dominant State Timeout Application Note
The maximum dominant TXD time allowed by the TXD dominant state time out limits the minimum possible data
rate of the device. The LIN protocol has different constraints for master and slave applications thus there are
different maximum consecutive dominant bits for each application case and thus different minimum data rates.
28
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Typical Application (continued)
9.2.3 Application Curves
and show the propagation delay from the TXD pin to the LIN pin for both dominant to recessive and recessive to
dominant stated under lightly loaded conditions.
Figure 31. Dominant to Recessive Propagation
Figure 32. Recessive to Dominant Propagation
10 Power Supply Recommendations
The TLIN2024-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from 4 V to
45 V. A 100 nF decoupling capacitor should be placed as close to the VSUP1/2 pin of the device as possible. Most
applications will include a 1 µF and ≥ 10 µF decoupling capacitors.
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11 Layout
In order for the PCB design to be successful, start with design of the protection and filtering circuitry. Because ESD and EFT
transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high frequency layout techniques must be
applied during PCB design. Placement at the connector also prevents these noisy events from propagating further into the
PCB and system.
11.1 Layout Guidelines
•
•
•
•
•
•
•
Pins 1, 4, 7 and 10 (RXD1/2/3/4): The pins are open drain outputs and require an external pull-up resistor in
the range of 1 kΩ and 10 kΩ to function properly. If the microprocessor paired with the transceiver does not
have an integrated pull-up, an external resistor should be placed between RXD and the regulated voltage
supply for the microprocessor.
Pins 2, 5, 8 and 11 (EN1/2/3/4): EN is an input pin that is used to place the device in a low power sleep
mode. If this feature is not used the pin should be pulled high to the regulated voltage supply of the
microprocessor through a series resistor, values between 1 kΩ and 10 kΩ. Additionally, a series resistor may
be placed on the pinto limit current on the digital lines in the case of an over voltage fault.
Pin 13, 18, 23 and 24 (NC): Not Connected
Pins 3, 6, 9 and 12 (TXD1/2/3/4): The TXD pins are the transmitter input signals to the device from the
microprocessor. A series resistor can be placed to limit the input current to the device in the case of an
overvoltage on this pin. A capacitor to ground can be placed close to the input pin of the device to filter noise.
Pin 14, 19 (GND2/1): This is the ground connection for the device. This pin should be tied to the ground
plane through a short trace with the use of two vias to limit total return inductance.
Pins 22, 20, 17 and 15 (LIN1/2/3/4): This pin connects to the LIN bus. For slave applications a 220 pF
capacitor to ground is implemented. For maser applications and additional series resistor and blocking diode
should be placed between the LIN pin and the VSUP1/2 pin. See Figure 30.
Pin 21, 160 (VSUP1/2): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed
as close to the device as possible.
NOTE
All ground and power connections should be made as short as possible and use at least
two vias to minimize the total loop inductance.
30
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11.2 Layout Example
VDD
R1
RXD1
GND
C1
TXD1
R4
24
NC
NC
2
23
TXD1
GND
LIN1
3
C5
R2
Only needed for
the Master node
22
RXD2
EN2
R6
GND
C2
TXD2
R8
R9
RXD3
Only needed for
the Master node
LIN2
5
20
TXD2
GND1
6
19
GND GND
NC
Only needed for
the Master node
D1
LIN2
Thermal Pad
7
18
EN3
LIN3
8
C8
R10
GND
R19
R11
VSUP2
D4
EN3
GND
C7
VDD
C6
21
R18
R7
EN2
RXD3
VSUP1
4
D3
R5
VDD
LIN1
VSUP1
VDD
RXD2
R17
EN1
EN1
1
R3
D2
VDD
RXD1
VSUP1
17
LIN3
VSUP2
R12
9
RXD4
R13
RXD4
VDD
R15
EN4
R14
TXD3
VSUP2
GND2
11
14
C4
TXD4
R16
D5
LIN4
GND GND
13
EN4
NC
15
TXD4
10
GND
Only needed for
the Master node
LIN4
12
GND
C9
16
R20
TXD3
D6
C3
C10
GND
Figure 33. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
This device will conform to the following LIN standards. The core of what is needed is covered within this system
spec, however reference should be made to these standards and any discrepancies pointed out and discussed.
This document should provide all the basics of what is needed.
12.1.1 Related Documentation
For related documentation see the following:
LIN Standards:
• ISO/DIS 17987-1.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and use
case definition
• ISO/DIS 17987-4.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer
(EPL) specification 12V/24V
• SAE J2602-1: LIN Network for Vehicle Applications
EMC requirements:
• SAE J2962-2: TBD
• ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge
• ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband
radiated electromagnetic energy - Part 4: Harness excitation methods
• ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1: Definitions
and general considerations
• ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical transient
transmission by capacitive and inductive coupling via lines other than supply lines
• IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz - Part 4:
Direct RF power injection method
• IEC 6100-4-2
• IEC 61967-4
• CISPR25
Conformance Test requirements:
• ISO/DIS 17987-7.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer
(EPL) conformance test specification
• SAE J2602-2: LIN Network for Vehicle Applications Conformance Test
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
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12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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7-Feb-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLIN2024RGYRQ1
PREVIEW
VQFN
RGY
24
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
TL024
TLIN2024RGYTQ1
PREVIEW
VQFN
RGY
24
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
TL024
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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7-Feb-2019
Addendum-Page 2
GENERIC PACKAGE VIEW
RGY 24
5.5 x 3.5 mm, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4203539-5/J
PACKAGE OUTLINE
RGY0024C
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
3.65
3.35
B
A
PIN 1 INDEX AREA
5.65
5.35
0.1 MIN
(0.05)
SECTION A-A
A-A 30.000
TYPICAL
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2.1 0.1
2X 1.5
EXPOSED
THERMAL PAD
SYMM
(0.2) TYP
13
12
11
14
SYMM
25
2X 4.5
A
A
4.1 0.1
20X 0.5
2
23
24
1
PIN 1 ID
24X
0.5
0.3
24X
0.30
0.18
0.1
0.05
C A B
4224230/A 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGY0024C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.1)
(0.75)
SYMM
1
24X (0.6)
SEE SOLDER MASK
DETAIL
24
2
23
24X (0.24)
(1.12)
20X (0.5)
(4.1)
(0.68) TYP
SYMM
25
(5.3)
(R0.05) TYP
( 0.2) TYP
VIA
14
11
13
12
(0.8) TYP
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK DEFINED
SOLDER MASK DETAILS
4224230/A 03/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGY0024C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.75)
(0.57) TYP
24X (0.6)
1
24
2
23
24X (0.24)
20X (0.5)
(1.36) TYP
(R0.05) TYP
25
SYMM
(5.3)
6X (1.16)
14
11
13
12
6X (0.94)
SYMM
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 15X
EXPOSED PAD 25
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224230/A 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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