Texas Instruments | TLIN2022-Q1 Fault Protected Dual Local Interconnect Network (LIN) Transceiver with Dominant State Timeout (Rev. A) | Datasheet | Texas Instruments TLIN2022-Q1 Fault Protected Dual Local Interconnect Network (LIN) Transceiver with Dominant State Timeout (Rev. A) Datasheet

Texas Instruments TLIN2022-Q1 Fault Protected Dual Local Interconnect Network (LIN) Transceiver with Dominant State Timeout (Rev. A) Datasheet
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TLIN2022-Q1
SLLSF01A – DECEMBER 2017 – REVISED JANUARY 2019
TLIN2022-Q1 Fault Protected Dual Local Interconnect Network (LIN) Transceiver with
Dominant State Timeout
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
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•
•
•
AEC-Q100 Qualified for Automotive Applications
– Device Temperature: –40°C to 125°C Ambient
– Device HBM Certification Level: ±8 kV
– Device CDM Certification Level: ±1.5 kV
Compliant to LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A
and ISO/DIS 17987–4.2
Conforms to SAEJ2602 Recommended Practice
for LIN
Supports 24 V Battery Applications
LIN Transmit Data Rate up to 20 kbps.
Wide Operating Ranges
– 4 V to 45 V Supply Voltage
– ±58 V LIN Bus Fault Protection
Sleep Mode: Ultra-Low Current Consumption
Allows Wake-Up Event From:
– LIN Bus
– Local Wake up through EN
Power Up and Down Glitch Free Operation
Protection Features:
– Under Voltage Protection on VSUP
– TXD Dominant Time Out Protection (DTO)
– Thermal Shutdown Protection
– Unpowered Node or Ground Disconnection
Failsafe at System Level.
Available in SOIC (14) Package and Leadless
VSON (14) Package with Improved Automated
Optical Inspection (AOI) Capability
Body Electronics and Lighting
Hybrid, Electric and Power Train Systems
Infotainment and Cluster
Appliances
3 Description
The TLIN2022-Q1 device is a Dual Local Interconnect
Network (LIN) physical layer transceiver with
integrated wake-up and protection features, complaint
to LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS
17987–4.2 standards. LIN is a single wire
bidirectional bus typically used for low speed invehicle networks using data rates up to 20 kbps. The
TLIN2022-Q1 is designed to support 24 V
applications with wider operating voltage and
additional bus-fault protection. The LIN receiver
supports data rates up to 100 kbps for in-line
programming. The TLIN2022-Q1 converts the LIN
protocol data stream on the TXD input into a LIN bus
signal using a current-limited wave-shaping driver
which reduces electromagnetic emissions (EME). The
receiver converts the data stream to logic level
signals that are sent to the microprocessor through
the open-drain RXD pin. Ultra-low current
consumption is possible using the sleep mode which
allows wake-up via LIN bus or pin.
Device Information(1)
PART NUMBER
PACKAGE
TLIN2022-Q1
BODY SIZE (NOM)
SOIC (14) (D)
5.00 mm x 8.65 mm
VSON (14) (DMT)(2)
3.00 mm x 4.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Product Preview
Spacer
Simplified Schematics, Master Mode
VBAT
VSUP
MASTER
NODE
VREG
Simplified Schematics, Slave Mode
VBAT
VSUP
VSUP
VDD
SLAVE
NODE
VREG
VDD
VSUP
VSUP
VDD
VDD
EN1
I/O
2
NC
NC
6
14
VDD I/O
MCU w/o
pullup(2)
MCU
1 NŸ
13
RXD1
LIN Controller
Or
SCU/UART(1)
VSUP
VDD
LIN1
LIN Bus
1
TXD1
VDD
Master Node
Pullup
10
220 pF
14
10
13
LIN1
9
MCU w/o
pullup(2)
LIN2
TXD1
LIN Bus
220 pF
LIN Controller
Or
SCU/UART(1)
7
220 pF
3
TLIN2022
VDD I/O
9
MCU w/o
pullup(2)
LIN2
4
TXD2
5
LIN Bus
1
TLIN2022
VDD I/O
EN2
6
RXD1
4
I/O
2
NC
VDD I/O
MCU w/o
pullup(2)
MCU
3
RXD2
GND
EN1
I/O
NC
8
RXD2
12 NC
11 NC
LIN Bus
220 pF
7
TXD2
GND
I/O
EN2
5
8
12 NC
11 NC
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TLIN2022-Q1
SLLSF01A – DECEMBER 2017 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
3
4
4
4
4
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
ESD Ratings - IEC ....................................................
Thermal Information ..................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 21
9
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application ................................................. 24
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2017) to Revision A
•
2
Page
Changed the VSON Body Size From: 3.00 mm x 3.00 mm To: 3.00 mm x 4.50 mm ........................................................... 1
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TLIN2022-Q1
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SLLSF01A – DECEMBER 2017 – REVISED JANUARY 2019
5 Pin Configuration and Functions
D Package
14-Pin (SOIC)
Top View
DMT Package
14-Pin (VSON)
Top View
RXD1
1
14
NC
EN1
2
13
LIN1
TXD1
3
12
NC
RXD2
4
11
NC
EN2
5
10
NC
6
9
LIN2
TXD2
7
8
GND
RXD1
1
14
NC
EN1
2
13
LIN1
12
NC
11
NC
VSUP
TXD1
3
RXD2
4
EN2
5
10
NC
6
9
LIN2
TXD2
7
8
GND
Thermal
Pad
VSUP
Not to scale
Not to scale
(1)
Product Preview
Pin Functions
PIN
Type
DESCRIPTION
NO.
NAME
1
RXD1
O
Channel 1 RXD Output (open-drain) interface reporting state of LIN bus voltage
2
EN1
I
Channel 1 Enable Input
3
TXD1
I
Channel 1 TXD input interface to control state of LIN output
4
RXD2
O
Channel 2 RXD Output (open-drain) interface reporting state of LIN bus voltage
5
EN2
I
Channel 2 Enable Input
7
TXD2
I
Channel 2 TXD input interface to control state of LIN output
8
GND
GND
9
LIN2
HV I/O
Channel 2 High voltage LIN bus single-wire transmitter and receiver
10
VSUP
Supply
Device Supply Voltage (connected to battery in series with external reverse blocking diode)
13
LIN1
HV I/O
Channel 1 High voltage LIN bus single-wire transmitter and receiver
6, 11, 12,
14
NC
–
Ground
Not Connected
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VSUP
Symbol
Supply voltage range (ISO/DIS 17987 Param 10)
–0.3
58
V
VLIN
LIN Bus input voltage (ISO/DIS 17987 Param 82)
– 58
58
V
VLOGIC
Logic Pin Voltage (RXD, TXD, EN)
–0.3
5.5
V
TA
Ambient temperature range
–40
125
°C
TJ
Junction Temp
–55
150
°C
(1)
Parameter
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SLLSF01A – DECEMBER 2017 – REVISED JANUARY 2019
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6.2 ESD Ratings
ESD Ratings
V(ESD)
VALUE
Human body model (HBM) per
AEC Q100-002 (1)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
(1)
(2)
Pins RXD, RXD, EN
Pins LIN Bus
(2)
(1)
UNIT
±4000
and VSUP
±8000
All pins
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
LIN bus a stressed with respect to GND.
6.3 ESD Ratings - IEC
ESD and Surge Protection Ratings
VALUE
V(ESD)
IEC 61000-4-2 contact discharge
electrostatic discharge (1)
LIN bus and VSUP pin to GND (2)
±6000
V(ESD)
IEC 61000-4-2 air-gap discharge
electrostatic discharge (1)
LIN bus and VSUP pin to GND (2)
±15000
V(ESD)
Powered ESD Performance, per
SAEJ2962-1 (3)
contact discharge
±8000
V(ESD)
Powered ESD Performance, per
SAEJ2962-1 (3)
air-gap discharge
±15000
UNIT
V
V
ISO7637-2 (4) & IEC 62215-3 Transients according to IBEE Pulse 1
LIN EMC test spec LIN bus pin and VSUP
Pulse 2
–100
V
75
V
ISO7637-2 & IEC 62215-3 Transients according to IBEE Pulse 3a
LIN EMC test spec LIN bus pin and VSUP
Pulse 3b
–150
V
100
V
(4)
(1)
(2)
(3)
(4)
IEC 61000-4-2 is a system level ESD test. Results given here are specific to the IBEE LIN EMC Test specification conditions. Different
system level configurations may lead to different results
Testing performed at 3rd party IBEE Zwickau test house, test report available upon request
SAEJ2962-1 Testing performed at 3rd party US3 approved EMC test facility, test report available upon request
ISO7637 is a system level transient test. Results given here are specific to the IBEE LIN EMC Test specification conditions. Different
system level configurations may lead to different results.
6.4 Thermal Information
THERMAL METRIC
TLIN2022D-Q1
TLIN2022DMT-Q1
D (SOIC)
DMT (VSON)
14-PINS
14-PINS
(1)
UNIT
RΘJA
Junction-to-ambient thermal resistance
82.3
35.5
°C/W
RΘJC(top)
Junction-to-case (top) thermal resistance
41.5
18.1
°C/W
RΘJB
Junction-to-board thermal resistance
38.4
13.1
°C/W
ΨJT
Junction-to-top characterization parameter
8.9
0.6
°C/W
ΨJB
Junction-to-board characterization parameter
38.1
13.1
°C/W
RΘJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
2.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER - DEFINITION
MIN
NOM
MAX
UNIT
VSUP
Supply voltage
4
48
V
VLIN
LIN Bus input voltage
0
48
V
VLOGIC
Logic Pin Voltage (RXD, TXD, EN)
0
5.25
TSD
Thermal shutdown edge
TSD(HYS)
Thermal shutdown hysteresis
4
165
15
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V
°C
°C
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TLIN2022-Q1
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SLLSF01A – DECEMBER 2017 – REVISED JANUARY 2019
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply
Device is operational beyond the LIN
defined nominal supply voltage range
See Figure 8 and Figure 9
4
48
V
Normal and Standby Modes: Ramp VSUP
while LIN signal is a 10 kHZ Square
Wave with 50 % duty cycle and 36V
swing. See Figure 8 and Figure 9
4
48
V
4
48
V
2.9
3.85
V
VSUP
Operational supply voltage (ISO/DIS
17987 Param 10, 53)
VSUP
Nominal supply voltage (ISO/DIS 17987
Param 10, 53): Normal Mode: Ramp
VSUP while LIN signal is a 10 kHZ
Square Wave with 50 % duty cycle and
18V swing.
UVSUP
Under voltage VSUP threshold
UVHYS
Delta hysteresis voltage for VSUP under
voltage threshold
ISUP
Supply Current
Normal Mode: EN = High, bus dominant:
total bus load where RLIN > 500 Ω and
CLIN < 10 nF See Figure 14
1.2
7.5
mA
ISUP
Supply Current
Standby Mode: EN = Low, bus dominant:
total bus load where RLIN > 500 Ω and
CLIN < 10 nF See Figure 14
1.1
3.75
mA
ISUP
Supply Current
Normal Mode: EN = High, Bus
Recessive: LIN = VSUP,
670
1300
µA
ISUP
Supply Current
Standby Mode: EN = Low, Bus
Recessive: LIN = VSUP,
20
40
µA
ISUP
Supply Current
Sleep Mode: 4.0 V < VSUP < 14 V, LIN =
VSUP, EN = 0 V, TXD and RXD Floating
10
20
µA
ISUP
Supply Current
Sleep Mode: 14 V < VSUP < 36 V, LIN =
VSUP, EN = 0 V, TXD and RXD Floating
30
µA
Sleep Mode
0.2
V
RXD OUTPUT PIN (OPEN DRAIN)
VOL
Output Low voltage
Based upon External pull up to VCC
IOL
Low level output current, open drain
LIN = 0 V, RXD = 0.4 V
1.5
0.6
IILG
Leakage current, high-level
LIN = VSUP, RXD = 5 V
–5
V
mA
0
5
µA
TXD INPUT PIN
VIL
Low level input voltage
–0.3
0.8
V
VIH
High level input voltage
2
5.5
V
VHYS
Input threshold voltage, normal modes&
selective wake modes
50
500
mV
IILG
Low level input leakage current
–5
0
5
µA
RTXD
Interal pulldown resitor value
125
350
800
kΩ
VIL
Low level input voltage
–0.3
0.8
V
VIH
High level input voltage
2
5.5
V
VHYS
Hysteresis voltage
By design and characterization
IILG
Low level input current
EN = Low
REN
Internal Pulldown resistor
TXD = Low
EN INPUT PIN
50
500
mV
–5
0
5
µA
125
350
800
kΩ
LIN PIN
VOH
VOL
High level output voltage
Low level output voltage
LIN recessive, TXD = high, IO = 0 mA,
VSUP = 7 V to 58 V
0.85
LIN recessive, TXD = high, IO = 0 mA,
VSUP = 4 V ≤ VSUP < 7 V
3
VSUP
V
LIN dominant, TXD = low, VSUP = 7 V to
58 V
0.2
VSUP
LIN dominant, TXD = low, VSUP = 4 V ≤
VSUP < 7 V
1.2
V
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSUP_NON_OP
VSUP where Impact of recessive LIN Bus
< 5% (ISO/DIS 17987 Param 56)
TXD & RXD open LIN = 4 V to 58 V
IBUS_LIM
Limiting current (ISO/DIS 17987 Param
57)
TXD = 0 V, VLIN = 48 V, RMEAS = 440 Ω,
VSUP = 48 V, VBUSdom < 4.518 V
See Figure 13
75
IBUS_PAS_dom
Receiver leakage current, dominant
(ISO/DIS 17987 Param 58)
LIN = 0 V, VSUP = 24 V Driver
off/recessive See Figure 14
–2
IBUS_PAS_rec1
Receiver leakage current, recessive
(ISO/DIS 17987 Param 59)
LIN > VSUP, 8 V < VSUP < 48 V Driver
off; See Figure 15
IBUS_PAS_rec2
Receiver leakage current, recessive
(ISO/DIS 17987 Param , 59)
LIN = VSUP, Driver off; See Figure 15
IBUS_NO_GND
Leakage current, loss of ground
(ISO/DIS 17987 Param 60)
GND = VSUP, 0 V ≤ VLIN ≤ 36 V, VSUP =
24 V; See Figure 16
IBUS_NO_BAT
Leakage current, loss of supply (ISO/DIS 0 V ≤ VLIN ≤ 48 V, VSUP = GND;
17987 Param 61)
See Figure 17
VBUSdom
Low level input voltage (ISO/DIS 17987
Param , 62)
LIN dominant (including LIN dominant for
wake up) See Figure 10 and Figure 11
VBUSrec
High level input voltage (ISO/DIS 17987
Param , 63)
Lin recessive See Figure 10
and Figure 11
VBUS_CNT
Receiver center threshold (ISO/DIS
17987 Param , 64)
VBUS_CNT = (VI_DOM + VI_REC)/2
See Figure 10 and Figure 11
VHYS
Hysteresis voltage (ISO/DIS 17987
Param , 65)
VHYS = (VI_REC - VI_DOM) See Figure 10
and Figure 11
VSERIAL_DIODE
Serial diode LIN term pullup path
(ISO/DIS 17987 Param , 66)
By design and characterization
0.4
0.7
1
V
RSLAVE
Pullup resistor to VSUP (ISO/DIS 17987
Param , 71)
Normal and Standby modes
20
45
60
kΩ
IRSLEEP
Pullup current source to VSUP
Sleep mode, VSUP = 27 V, LIN = GND
–2
µA
CLINPIN
Capacitance of LIN pin
45
pF
–0.3
120
58
V
300
mA
mA
20
µA
–5
5
µA
–2
2
mA
5
µA
0.4
0.6
0.475
VSUP
VSUP
0.5
–20
0.525
VSUP
0.175
VSUP
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
D112V
D112V
D212V
D312V
(1)
6
TEST CONDITIONS
MIN
Duty Cycle 1 (ISO/DIS 17987 Param
27) (1)
THREC(MAX) = 0.744 x VSUP, THDOM(MAX)
= 0.581 x VSUP, VSUP = 7 V to 18 V, tBIT
= 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x
tBIT) (See Figure 18 and Figure 19)
0.396
Duty Cycle 1
THREC(MAX) = 0.625 x VSUP, THDOM(MAX)
= 0.581 x VSUP, VSUP = 4 V to 7 V, tBIT =
50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x
tBIT) (See Figure 18 and Figure 19)
0.396
Duty Cycle 2 (ISO/DIS 17987 Param 28)
THREC(MIN) = 0.422 x VSUP, THDOM(MIN) =
0.284 x VSUP, VSUP = 7.6 V to 18 V, tBIT
= 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x
tBIT) (See Figure 18 and Figure 19)
Duty Cycle 3 (ISO/DIS 17987 Param 29)
THREC(MAX) = 0.778 x VSUP, THDOM(MAX)
= 0.616 x VSUP, VSUP = 7 V to 18 V, tBIT
= 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2
x tBIT) (See Figure 18 and Figure 19)
TYP
MAX
UNIT
0.581
0.417
Duty cycles: LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω. Duty cycles 3 and 4 are
defined for 10.4-kbps operation. The TLIN1029 also meets these lower data rate requirements, while it is capable of the higher speed
20-kbps operation as specified by duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle
definitions, for details see the SAEJ2602 specification
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Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
D312V
Duty Cycle
THREC(MAX) = 0.645 x VSUP, THDOM(MAX)
= 0.616 x VSUP, VSUP = 4 V to 7 V, tBIT =
96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x
tBIT) (See Figure 18 and Figure 19)
D412V
Duty Cycle 4 (ISO/DIS 17987 Param 30)
THREC(MIN) = 0.389 x VSUP, THDOM(MIN) =
0.251 x VSUP, VSUP = 7.6 V to 18 V, tBIT
= 96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2
x tBIT) (See Figure 18 and Figure 19)
D124V
Duty Cycle 1 (ISO/DIS 17987 Param
27) (1)
THREC(MAX) = 0.710 x VSUP, THDOM(MAX)
= 0.544 x VSUP, VSUP = 15 V to 36 V, tBIT
= 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x
tBIT) (See Figure 18 and Figure 19)
D224V
Duty Cycle 2 (ISO/DIS 17987 Param 28)
THREC(MIN) = 0.446 x VSUP, THDOM(MIN) =
0.302 x VSUP, VSUP = 15.6 V to 36 V, tBIT
= 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x
tBIT) (See Figure 18 and Figure 19)
D324V
Duty Cycle 3 (ISO/DIS 17987 Param 29)
THREC(MAX) = 0.744 x VSUP, THDOM(MAX)
= 0.581 x VSUP, VSUP = 7 V to 36 V, tBIT
= 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2
x tBIT) (See Figure 18 and Figure 19)
0.386
D324V
Duty Cycle
THREC(MAX) = 0.645 x VSUP, THDOM(MAX)
= 0.581 x VSUP, VSUP = 4 V to 7 V, tBIT =
96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x
tBIT) (See Figure 18 and Figure 19)
0.386
D424V
Duty Cycle 4 (ISO/DIS 17987 Param 30)
THREC(MIN) = 0.442 x VSUP, THDOM(MIN) =
0.284 x VSUP, VSUP = 7.6 V to 36 V, tBIT
= 96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2
x tBIT) (See Figure 18 and Figure 19)
TYP
MAX
UNIT
0.417
0.59
0.33
0.642
0.591
6.8 Timing Requirements
SYMBOL
DESCRIPTION
TEST CONDITIONS
MIN
trx_pdr
Receiver rising propagation delay time
(ISO/DIS 17987 Param 31)
trx_pdf
Receiver falling propagation delay time
(ISO/DIS 17987 Param 31)
trs_sym
Symmetry of receiver propagation delay
time Receiver rising propagation delay
time (ISO/DIS 17987 Param 32)
Rising edge with respect to falling edge,
(trx_sym = trx_pdf – trx_pdr), RRXD = 2.4
kΩ, CRXD = 20 pF (See Figure 20 and
Figure 21)
–2
tLINBUS
LIN wakeup time (Minimum dominant
time on LIN bus for wakeup)
See Figure 24, Figure 27 and Figure 28
25
tCLEAR
Time to clear false wakeup prevention
logic if LIN bus had a bus stuck
dominant fault (recessive time on LIN
bus to clear bust stuck dominant fault)
See Figure 28
tDST
Dominant state time out
NOM
MAX
UNIT
6
µs
6
µs
2
µs
100
150
µs
8
17
50
µs
20
34
80
ms
15
µs
RRXD = 2.4 kΩ, CRXD = 20 pF
(See Figure 20 and Figure 21)
tMODE_CHANGE Mode change delay time
Time to change from standby mode to
normal mode or normal mode to sleep
mode through EN pin: See Figure 22
and Figure 29
tNOMINT
Normal mode initialization time
Time for normal mode to initialize and
data on RXD pin to be valid
See Figure 22
35
µs
tPWR
Power up time
Upon power up time it takes for valid
data on RXD
1.5
ms
2
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6.9 Typical Characteristics
60
Channel 1 (-55 °C)
Channel 1 (27 °C)
Channel 1 (125 °C)
Channel 2 (-55 °C)
Channel 2 (27 °C)
Channel 2 (125 °C)
55
50
45
35
VOL (V)
VOH (V)
40
30
25
20
15
10
5
0
0
5
10
15
20 25 30 35 40 45
VSUP Voltage Supply (V)
50
55
0.81
0.78
0.75
0.72
0.69
0.66
0.63
0.6
0.57
0.54
0.51
0.48
0.45
0.42
60
Channel 1 (-55 °C)
Channel 1 (27 °C)
Channel 1 (125 °C)
Channel 2 (-55 °C )
Channel 2 (27 °C)
Channel 2 (125 °C)
0
5
50
55
60
D002
-55 °C
27 °C
125 °C
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
5
10
15
20 25 30 35 40 45
VSUP Voltage Supply (V)
50
55
60
0
10
15
20 25 30 35 40 45
VSUP Voltage Supply (V)
50
55
60
D004
Normal Mode (Recessive)
Figure 3. Supply Current vs Voltage Supply Across
Temperature
3.5
3.25
3
2.75
2.5
2.25
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
5
D003
Normal Mode (Dominant)
Figure 4. Supply Current vs Voltage Supply Across
Temperature
15
-55 °C
27 °C
125 °C
-55 °C
27 °C
125 °C
14
ISUP Supply Current (PA)
ISUP Supply Current (mA)
20 25 30 35 40 45
VSUP Voltage Supply (V)
Figure 2. VOL vs VSUP and Temperature
-55 °C
27 °C
125 °C
0
13
12
11
10
9
8
7
6
5
0
5
10
15
20 25 30 35 40 45
VSUP Voltage Supply (V)
50
55
60
0
5
D005
10
15
20 25 30 35 40 45
VSUP Voltage Supply (V)
50
55
60
D006
Standby Mode (Recessive)
Standby Mode (Dominant)
Figure 5. Supply Current vs Voltage Supply and
Temperature
8
15
1.3
ISUP Supply Current (mA)
ISUP Supply Current (mA)
Figure 1. VOH vs VSUP and Temperature
8
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
10
D001
Figure 6. Supply Current vs Voltage Supply and
Temperature
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Typical Characteristics (continued)
15
-55 °C
27 °C
125 °C
ISUP Supply Current (PA)
14
13
12
11
10
9
8
7
6
0
5
10
15
20 25 30 35 40 45
VSUP Voltage Supply (V)
50
55
60
D007
Sleep Mode
Figure 7. Supply Current vs Voltage Supply and Temperature
7 Parameter Measurement Information
1, 4
NC
RXD1/2
11, 12, 14
5V
2, 5
6
VSUP
EN1/2
NC
LIN1/2
3, 7
TXD1/2
10
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS
9, 13
8
GND
Pulse Generator
tR/tF: Square Wave: < 20 ns
:
tR/tF Triangle Wave: < 40ns
Frequency: 20 ppm
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
Figure 8. Test System: Operating Voltage Range with RX and TX Access: Parameters 9, 10
Trigger Point
Delta t = + 5 µs
(tBIT = 50 µs)
RX
2 x tBIT = 100 µs (20 kBaud)
Copyright © 2017, Texas Instruments Incorporated
Figure 9. RX Response: Operating Voltage Range
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Parameter Measurement Information (continued)
Period T = 1/f
Amplitude
(signal range)
LIN Bus Input
Frequency: f = 20 Hz
Symmetry: 50%
Figure 10. LIN Bus Input Signal
1, 4
NC 11, 12, 14
RXD1/2
5V
2, 5
6
VSUP 10
EN1/2
NC
LIN1/2
3, 7
TXD1/2
Power Supply
Resolution: 10 mV / 1 mA
Accuracy: 0.2%
VPS
9, 13
Pulse Generator
tR/tF: Square Wave: < 20 ns
:
tR/tF Triangle Wave: < 40 ns
Frequency: 20 ppm
Jitter: < 25 ns
GND 8
Measurement Tools
O-scope:
DMM
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Figure 11. LIN Receiver Test with RX access Parameters 17, 18, 19, 20
1, 4
NC
RXD1/2
Power Supply 1
Resolution: 10 mV / 1mA
Accuracy: 0.2%
11, 12, 14
5V
2, 5
6
VSUP
EN1/2
VPS1
D
NC
LIN1/2
3, 7
10
TXD1/2
8
GND
Power Supply 2
Resolution: 10 mV / 1mA
Accuracy: 0.2%
9, 13
RBUS
VPS2
Measurement Tools
O-scope:
DMM
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Figure 12. VSUP_NON_OP Parameters 11
10
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Parameter Measurement Information (continued)
NC 11, 12, 14
1, 4 RXD1/2
5V
2, 5
VSUP
EN1/2
6 NC
LIN1/2
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
T = 10 ms
Jitter: < 25 ns
3, 7
10
9, 13
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS
RMEAS
GND 8
TXD1/2
Measurement Tools
O-scope:
DMM
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Figure 13. Test Circuit for IBUS_LIM at Dominant State (Driver on) Parameters 12
1, 4
RXD1/2
2, 5
EN1/2
6
NC 11, 12, 14
VSUP 10
NC
LIN1/2
3, 7
TXD1/2
GND
9, 13
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS
RMEAS = 499 Ÿ
8
Measurement Tools
O-scope:
DMM
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Figure 14. Test Circuit for IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V, Parameters 13
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Parameter Measurement Information (continued)
1, 4 RXD1/2
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
NC 11, 12, 14
VPS1
10
2, 5 EN1/2
VSUP
TLINx022
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
1 NŸ
6 NC
9, 13
VPS2
LIN1/2
VPS2 2 V/s ramp
[8 V à 27 V]
3, 7 TXD1/2
8
GND
V Drop across resistor
< 20 mV
Measurement Tools
O-scope:
DMM
Figure 15. Test Circuit for IBUS_PAS_rec Param 14
NC 11, 12, 14
1, 4 RXD1/2
5V
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS1
2, 5
VSUP 10
EN1/2
6 NC
LIN1/2
3, 7 TXD1/2
9, 13
GND 8
1 NŸ
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS2
VPS2 2 V/s ramp
[0 V à 27 V]
V Drop across resistor
< 1V
Measurement Tools
O-scope:
DMM
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Figure 16. Test Circuit for IBUS_NO_GND Loss of GND
12
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Parameter Measurement Information (continued)
NC
1, 4 RXD1/2
11, 12, 14
5V
2, 5
VSUP
EN1/2
10
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
10 NŸ
6 NC
LIN1/2
9, 13
VPS
VPS 2 V/s ramp
[0 V à 27 V]
3, 7 TXD1/2
GND
8
V Drop across resistor
< 1V
Measurement Tools
O-scope:
DMM
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Figure 17. Test Circuit for IBUS_NO_BAT Loss of Battery
5V
NC 11, 12, 14
1, 4 RXD1/2
2, 5 EN1/2
6 NC
Pulse Generator
tR/tF: Square Wave: < 20 ns
:
tR/tF Triangle Wave: < 40 ns
Frequency: 20 ppm
Jitter: < 25 ns
VSUP 10
LIN1/2
3, 7 TXD1/2
9, 13
GND 8
Power Supply 1
Resolution: 10 mV / 1mA
Accuracy: 0.2%
VPS1
RMEAS
Power Supply 2
Resolution: 10 mV / 1mA
Accuracy: 0.2%
VPS2
Measurement Tools
O-scope:
DMM
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Figure 18. Test Circuit Slope Control and Duty Cycle Parameters 27, 28, 29, 30
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Parameter Measurement Information (continued)
tBIT
tBIT
RECESSIVE
D = 0.5
TXD (Input)
DOMINANT
THREC(MAX)
THDOM(MAX)
LIN Bus
Signal
THREC(MIN)
THDOM(MIN)
D112: 0.744 * VSUP
D312: 0.778 * VSUP
D124: 0.710 * VSUP
D324: 0.744 * VSUP
D112: 0.581 * VSUP
D312: 0.616 * VSUP
D124: 0.554 * VSUP
D324: 0.581 * VSUP
D212: 0.422 * VSUP
D412: 0.389 * VSUP
D224: 0.446 * VSUP
D424: 0.442 * VSUP
D212: 0.284 * VSUP
D412: 0.251 * VSUP
D224: 0.302 * VSUP
D424: 0.284 * VSUP
Thresholds
RX Node 1
VSUP
Thresholds
RX Node 2
tBUS_REC(MAX)
tBUS_DOM(MAX)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
D = tBUS_REC(MIN)/(2 x tBIT)
tBUS_DOM(MIN)
tBUS_REC(MIN)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
D = tBUS_REC(MIN)/(2 x tBIT)
Figure 19. Definition of Bus Timing Parameters
VCC
2.4 NŸ
1, 4
NC 11, 12, 14
RXD1/2
5V
20 pF
2, 5
6
3, 7
VSUP 10
EN1/2
NC
LIN1/2 9, 13
TXD1/2
GND 8
Power Supply
Resolution: 10 mV / 1mA
Accuracy: 0.2%
VPS
Pulse Generator
tR/tF: Square Wave: < 20 ns
:
tR/tF Triangle Wave: < 40 ns
Frequency: 20 ppm
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
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Figure 20. Propagation Delay Test Circuit; Parameters 31, 32
14
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Parameter Measurement Information (continued)
THREC(MAX)
Thresholds
RX Node 1
THDOM(MAX)
LIN Bus
Signal
VSUP
THREC(MIN)
Thresholds
RX Node 2
THDOM(MIN)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
trx_pdr(1)
trx_pdf(1)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
trx_pdr(2)
trx_pdf(2)
Copyright © 2017, Texas Instruments Incorporated
Figure 21. Propagation Delay
Wake Event
tMODE_CHANGE
EN
tMODE_CHANGE
MODE
RXD
tNOMINT
Normal
Transition
Sleep
Standby
Transition
Mirrors Bus
Indetermin
ate Ignore
Floating
Wake Request
RXD = Low
Indeterminate Ignore
Normal
Mirrors
Bus
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Figure 22. Mode Transitions
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Parameter Measurement Information (continued)
EN1/2
TXD1/2
Weak Internal Pulldown
Weak Internal Pulldown
VSUP
LIN1/2
RXD1/2
Floating
MODE
Sleep
Normal
Figure 23. Wakeup Through EN
0.6 x
VSUP
LIN1/2
0.4 x
VSUP
0.4 x VSUP
t < tLINBUS
TXD1/2
0.6 x
VSUP
VSUP
tLINBUS
Weak Internal Pulldown
EN1/2
RXD1/2
Floating
MODE
Sleep
Standby
Normal
Figure 24. Wakeup through LIN
16
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Parameter Measurement Information (continued)
RRXD1
RXD1
NC
CRXD1
CLIN1
EN1
LIN1
TXD1
NC
RLIN1
RRXD2
NC
RXD2
CRXD2
VSUP
100 nF
EN2
RLIN2
NC
LIN2
CLIN2
TXD2
GND
Figure 25. Test Circuit for AC Characteristics
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8 Detailed Description
8.1 Overview
The TLIN2022-Q1 device is a Dual Local Interconnect Network (LIN) physical layer transceiver, compliant to LIN
2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4.2, with integrated wake-up and protection features. The
LIN bus is a single wire bidirectional bus typically used for low speed in-vehicle networks using data rates from
2.4 kbps to 20 kbps. The TLIN2022-Q1 LIN receiver works up to 100 kbps supporting in-line programming. The
LIN protocol data stream on the TXD input is converted by the TLIN2022-Q1 into a LIN bus signal using a
current-limited wave-shaping driver as outlined by the LIN physical layer specification. The receiver converts the
data stream to logic level signals that are sent to the microprocessor through the open-drain RXD pin. The LIN
bus has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In the
recessive state, the LIN bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode. No external
pull-up components are required for slave applications. Master applications require an external pull-up resistor (1
kΩ) plus a series diode per the LIN specification. The TLIN2022-Q1 provides many protection features such as
ESD, EMC and high bus standoff voltage. The device also provides three methods to wake up, EN and from the
LIN bus.
8.2 Functional Block Diagram
VSUP
RXD1
NC
VSUP/2
Comp
Filter
45 NŸ
Wake Up
State & Control
EN1
Dominant
State
Timeout
TXD1
Fault Detection
& Protection
LIN1
DR/
Slope
CTL
NC
NC
350 k
RXD2
VSUP/2
VSUP
Comp
Filter
45 NŸ
Wake Up
State & Control
EN2
NC
Fault Detection
& Protection
Dominant
State
Timeout
TXD2
LIN2
DR/
Slope
CTL
350 k
GND
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8.3 Feature Description
8.3.1 LIN (Local Interconnect Network) Bus
This high voltage input/output pin is a single wire LIN bus transmitter and receiver. The LIN pin can survive
transient voltages up to 58 V. Reverse currents from the LIN to supply (VSUP) are minimized with blocking diodes,
even in the event of a ground shift or loss of supply (VSUP).
8.3.1.1 LIN Transmitter Characteristics
The transmitter has thresholds and AC parameters according to the LIN specification. The transmitter is a low
side transistor with internal current limitation and thermal shutdown. During a thermal shut-down condition, the
transmitter is disabled to protect the device. There is an internal pull-up resistor with a serial diode structure to
VSUP, so no external pull-up components are required for the LIN slave mode applications. An external pull-up
resistor and series diode to VSUP must be added when the device is used for a master node application.
8.3.1.2 LIN Receiver Characteristics
The receiver characteristic thresholds are proportional to the device supply pin according to the LIN specification.
The receiver is capable of receiving higher data rates (> 100 kbps) than supported by LIN or SAEJ2602
specifications. This allows the TLIN2022-Q1 to be used for high speed downloads at the end-of-line production or
other applications. The actual data rate achievable depends on system time constants (bus capacitance and pullup resistance) and driver characteristics used in the system.
8.3.1.2.1 Termination
There is an internal pull-up resistor with a serial diode structure to VSUP, so no external pull-up components are
required for the LIN slave mode applications. An external pull-up resistor (1 kΩ) and a series diode to VSUP must
be added when the device is used for master node applications as per the LIN specification.
Figure 26 shows a Master Node configuration and how the voltage levels are defined
Simplified Transceiver
RXD
VLIN_Bus
VSUP
VSUP/2
Voltage drop across the
diodes in the pullup path
VSUP
VBattery
VSUP
Receiver
VLIN_Recessive
Filter
1 NŸ
45 NŸ
LIN
LIN
Bus
TXD
350 NŸ
GND
Transmitter
with slope control
VLIN_Dominant
t
Copyright © 2017, Texas Instruments Incorporated
Figure 26. Master Node Configuration with Voltage Levels
8.3.2 TXD (Transmit Input and Output)
TXD is the interface to the processors LIN protocol controller or SCI and UART that is used to control the state of
the LIN output. When TXD is low the LIN output is dominant (near ground). When TXD is high the LIN output is
recessive (near VBattery). See Figure 26. The TXD input structure is compatible with processors using 3.3 V and 5
V I/O. TXD has an internal pull-down resistor. The LIN bus is protected from being stuck dominant through a
system failure driving TXD low through the dominant state timer-out timer.
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Feature Description (continued)
8.3.3 RXD (Receive Output)
RXD is the interface to the processors LIN protocol controller or SCI and UART, which reports the state of the
LIN bus voltage. LIN recessive (near VBattery) is represented by a high level on the RXD and LIN dominant (near
ground) is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage.
This allows the device to be used with 3.3 V and 5 V I/O processors. If the processors RXD pin does not have an
integrated pull-up, an external pull-up resistor to the processors I/O supply voltage is required. In standby mode
the RXD pin is driven low to indicate a wake up request from the LIN bus.
8.3.4 VSUP (Supply Voltage)
VSUP is the power supply pin. VSUP is connected to the battery through and external reverse battery blocking
diode (See Figure 26). If there is a loss of power at the ECU level, the device has extremely low leakage from
the LIN pin, which does not load the bus down. This is optimal for LIN systems in which some of the nodes are
unpowered (ignition supplied) while the rest of the network remains powered (battery supplied).
8.3.5 GND (Ground)
GND is the device ground connection. The device can operate with a ground shift as long as the ground shift
does not reduce the VSUP below the minimum operating voltage. If there is a loss of ground at the ECU level, the
device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN
systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains
powered (battery supplied).
8.3.6 EN (Enable Input)
EN controls the operational modes of the device. When EN is high the device is in normal operating mode
allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low the device is put into sleep
mode and there are no transmission paths available. The device can enter normal mode only after wake up. EN
has an internal pull-down resistor to endure the device remains in low power mode even if EN floats.
8.3.7 Protection Features
The TLIN2022-Q1 has several protection features.
8.3.8 TXD Dominant Time Out (DTO)
During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application
failure, the LIN bus is protected by the dominant state timeout timer. This timer is triggered by a falling edge on
the TXD pin. If the low signal remains on TXD for longer than tDST, the transmitter is disabled, thus allowing the
LIN bus to return to recessive state and communication to resume on the bus. The protection is cleared and the
tDST timer is reset by a rising edge on TXD. The TXD pin has an internal pull-down to ensure the device fails to a
known state if TXD is disconnected. During this fault, the transceiver remains in normal mode (assuming no
change of stated request on EN), the transmitter is disabled, the RXD pin reflects the LIN bus and the LIN bus
pull-up termination remains on.
8.3.9 Bus Stuck Dominant System Fault: False Wake Up Lockout
The TLIN2022-Q1 contains logic to detect bus stuck dominant system faults and prevents the device from
waking up falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus.
If the bus is dominant, the wake up logic is locked out until a valid recessive on the bus “clears” the bus stuck
dominant, preventing excessive current use. Figure 27 and Figure 28 show the behavior of this protection.
20
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Feature Description (continued)
EN
LIN Bus
< tLINBUS
tLINBUS
< tLINBUS
Figure 27. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wakeup
EN
LIN Bus
tLINBUS
tLINBUS
tLINBUS
tCLEAR
< tCLEAR
Figure 28. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wakeup
8.3.10 Thermal Shutdown
The LIN transmitter is protected by limiting the current; however if the junction temperature of the device exceeds
the thermal shutdown threshold, the device puts the LIN transmitter into the recessive state. Once the over
temperature fault condition has been removed and the junction temperature has cooled beyond the hysteresis
temperature, the transmitter is re-enabled, assuming the device remained in the normal operation mode. During
this fault, the transceiver remains in normal mode (assuming no change of state request on EN), the transmitter
is in recessive state, the RXD pin reflects the LIN bus and LIN bus pull-up termination remains on.
8.3.11 Under Voltage on VSUP
The TLIN2022-Q1 contains a power on reset circuit to avoid false bus messages during under voltage conditions
when VSUP is less than UVSUP.
8.3.12 Unpowered Device and LIN Bus
In automotive applications some LIN nodes in a system can be unpowered (ignition supplied) while others in the
network remains powered by the battery. The TLIN2022-Q1 has a low unpowered leakage current from the bus
so an unpowered node does not affect the network or load it down.
8.4 Device Functional Modes
The TLIN2022-Q1 has three functional modes of operation, normal, sleep, and standby. The next sections
describe these modes as well as how the device moves between the different modes. Figure 29 graphically
shows the relationship while Table 1 shows the state of pins.
Table 1. Operating Modes
MODE
EN
RXD
LIN BUS
TERMINATION
TRANSMITTER
Sleep
Low
Floating
Weak Current Pullup
Off
Standby
Low
Low
45 kΩ (typical)
Off
Wake up event detected,
waiting on MCU to set EN
Normal
High
LIN Bus
Data
45 kΩ (typical)
Off
LIN transmission up to 20 kbps
COMMENT
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Unpowered System
VSUP < VSUP_UNDER
VSUP < VSUP_UNDER
VSUP > VSUP_UNDER
EN = High
VSUP > VSUP_UNDER
EN = Low
VSUP < VSUP_UNDER
VSUP < VSUP_UNDER
Standby Mode
Driver: Off
RXD: Low
Termination: 45 kŸ
Normal Mode
Driver: On
RXD: LIN Bus Data
Termination: 45 kŸ
EN = High
LIN Bus Wake up
Sleep Mode
Driver: Off
RXD: Floating
Termination: Weak pullup
EN = Low
EN = High
Copyright © 2017, Texas Instruments Incorporated
Figure 29. Operating State Diagram
8.4.1 Normal Mode
If the EN pin is high at power up, the device powers up in normal mode, and if in low, it powers up in standby
mode. The EN pin controls the mode of the device. In normal operational mode, the receiver and transmitter are
active and the LIN transmission up to the LIN specified maximum of 20 kbps is supported. The receiver detects
the data stream on the LIN bus and outputs it on RXD for the LIN controller. A recessive signal on the LIN bus is
a logic high and a dominate signal on the LIN bus is a logic low. The driver transmits input data from TXD to the
LIN bus. Normal mode is entered as EN transitions high while the TLIN2022-Q1 is in sleep or standby mode for
> tMODE_CHANGE.
8.4.2 Sleep Mode
Sleep Mode is the power saving mode for the TLIN2022-Q1. Even with extremely low current consumption in this
mode, the TLIN2022-Q1 can still wake up from LIN bus through a wake up signal or if EN is set high for
> tMODE_CHANGE. The Lin bus is filtered to prevent false wake up events. The wake up events must be active for
the respective time periods (tLINBUS).
Sleep mode is entered by setting EN low for longer than tMODE_CHANGE.
While the device is in sleep mode, the following conditions exist.
• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if
LIN is short circuited to ground). However, the weak current pull-up is active to prevent false wake up events
in case an external connection to the LIN bus is lost.
• The normal receiver is disabled.
• EN input and LIN wake up receiver are active.
22
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8.4.3 Standby Mode
This mode is entered whenever a wake up event occurs through LIN bus while the device is in sleep mode. The
LIN bus slave termination circuit is turned on when standby mode is entered. Standby mode is signaled through
a low level on RXD. See Standby Mode Application Note for more application information.
When EN is set high for longer than tMODE_CHANGE while the device is in standby mode, the device returns to
normal mode and the normal transmission paths from TXD to LIN bus and LIN bus to RXD are enabled.
8.4.4 Wake Up Events
There are two ways to wake up from sleep mode:
• Remote wake up initiated by the falling edge of a recessive (high) to dominant (low) state transition on LIN
bus where the dominant state is held for tLINBUS filter time. After this tLINBUS filter time has been met and a
rising edge on the LIN bus going from dominate state to recessive state initiates a remote wake up event,
eliminating false wake ups from disturbances on the LIN bus or if the bus is shorted to ground.
• Local wake up through EN being set high for longer than tMODE_CHANGE.
8.4.4.1 Wake Up Request (RXD)
When the TLIN2022-Q1 encounters a wake up event from the LIN bus, RXD goes low and the device transitions
to standby mode until EN is reasserted high and the device enters normal mode. Once the device enters normal
mode, the RXD pin is releasing the wake up request signal and the RXD pin then reflects the receiver output
from the LIN bus.
8.4.4.2 Mode Transitions
When the TLIN2022-Q1 is transitioning between modes, the device needs the time, tMODE_CHANGE, to allow the
change to fully propagate from the EN pin through the device into the new state. When transitioning from sleep
or standby mode to normal mode, the transition time is the sum of tMODE_CHANGE and tNOMINT
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLIN2022-Q1 can be used as both a slave device and a master device in a LIN network. The device comes
with the ability to support both remote wake up request and local wake up request.
9.2 Typical Application
The device comes with an integrated 45 kΩ pull-up resistor and series diode for slave applications. For master
applications, an external 1 kΩ pull-up resistor with series blocking diode can be used. shows the device being
used in both master and slave applications.
VSUP
MASTER
NODE
VREG
VSUP
VDD
24 V VBAT
VDD
VSUP
EN1
I/O
VDD
VDD I/O
NC NC NC
2 11 12 14
10
(4)
Master Node
Pullup(3)
MCU w/o
pullup(2)
RXD1
MCU
LIN Controller
Or
SCI/UART(1)
TXD1
VDD I/O
13
3
TLIN2022
1 NŸ
LIN1
1 NŸ
220 pF
MCU w/o
pullup(2)
RXD2
TXD2
GND
1
I/O
EN2
4
9
LIN2
7
5
220 pF
8
6
VSUP
LIN Bus
LIN Bus
NC
VREG
VSUP
24 V VBAT
VDD
SLAVE
NODE
VDD
VSUP
VDD
EN1
I/O
VDD I/O
NC NC NC
2 11 12 14
(4)
10
MCU w/o
pullup(2)
RXD1
MCU
LIN Controller
Or
SCI/UART(1)
TXD1
VDD I/O
TXD2
I/O
13
3
TLIN2022
LIN1
220 pF
MCU w/o
pullup(2)
RXD2
GND
1
EN2
4
9
LIN2
7
5
6
8
220 pF
NC
(1) If RXD on MCU or LIN slave has internal pullup; no external pullup resistor is needed.
(2) If RXD on MCU or LIN slave does not have an internal pullup requires external pullup resistor.
(3) Master node applications require and external 1 lQ ‰µooµ‰ Œ •]•š}Œ v • Œ] o ]} .
(4) Decoupling capacitor values are system dependent but usually have 100 nF, 1 R& v H10 µF
Copyright © 2017, Texas Instruments Incorporated
Figure 30. Typical LIN Bus
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Typical Application (continued)
9.2.1 Design Requirements
The RXD output structure is an open-drain output stage. This allows the TLIN2022-Q1 to be used with 3.3-V and
5-V I/O processor. If the RXD pin of the processor does not have an integrated pull-up, an external pull-up
resistor to the processor I/O supply voltage is required. The select external pull-up resistor value should be
between 1 kΩ to 10 kΩ. The VSUP pin of the device should be decoupled with a 100 nF capacitor as close to the
supply pin of the device as possible. The system should include 1 µF and ≥ 10 µF decoupling capacitors on VSUP
as per each application requirements.
9.2.2 Detailed Design Procedures
9.2.2.1 Normal Mode Application Note
When using the TLIN2022-Q1 in systems which are monitoring the RXD pin for a wake up request, special care
should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition period
between states as the receivers are switched. The application software should not look for an edge on the RXD
pin indicating a wake up request until tMODE_CHANGE when going from normal to sleep mode or tMODE_CHANGE plus
tNOMINT when going from sleep or standby to normal mode. This is shown in Figure 22
9.2.2.2 Standby Mode Application Note
If the TLIN2022-Q1 detects an under voltage on VSUP the RXD pin transitions low, and signals to the software
that the TLIN2022-Q1 is in standby mode and should be returned to sleep mode for the lowest power state.
9.2.2.3 TXD Dominant State Timeout Application Note
The maximum dominant TXD time allowed by the TXD dominant state time out limits the minimum possible data
rate of the device. The LIN protocol has different constraints for master and slave applications thus there are
different maximum consecutive dominant bits for each application case and thus different minimum data rates.
9.2.3 Application Curves
Figure 31 and Figure 32 show the propagation delay from the TXD pin to the LIN pin for both dominant to
recessive and recessive to dominant stated under lightly loaded conditions.
Figure 31. Dominant to Recessive Propagation
Figure 32. Recessive to Dominant Propagation
10 Power Supply Recommendations
The TLIN2022-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from 4 V to
45 V. A 100 nF decoupling capacitor should be placed as close to the VSUP pin of the device as possible.
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11 Layout
In order for the PCB design to be successful, start with design of the protection and filtering circuitry. Because
ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high frequency
layout techniques must be applied during PCB design. Placement at the connector also prevents these noisy
events from propagating further into the PCB and system.
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
Pin 1, 4 (RXD1/2): The pin is an open drain outputs and require an external pull-up resistor in the range of 1
kΩ and 10 kΩ to function properly. If the microprocessor paired with the transceiver does not have an
integrated pull-up, an external resistor should be placed between RXD and the regulated voltage supply for
the microprocessor.
Pin 2, 5 (EN1/2): EN is an input pin that is used to place the device in a low power sleep mode. If this feature
is not used, the pin should be pulled high to the regulated voltage supply of the microprocessor through a
series resistor, values between 1 kΩ and 10 kΩ. Additionally, a series resistor may be placed on the pinto
limit current on the digital lines in the event of an over voltage fault.
Pin 6 (NC): Not Connected.
Pin 3, 7 (TXD1/2): The TXD pins are the transmitter input signals to the device from the processor. A series
resistor can be placed to limit the input current to the device in the case of an over-voltage on this pin. A
capacitor to ground can be placed close to the input pin of the device to filter noise.
Pin 8 (GND): This is the ground connection for the device. This pin should be tied to the ground plane
through a short trace with the use of two vias to limit total return inductance.
Pin 9, 13 (LIN1/2): This pin connects to the LIN bus. For slave applications, a 220 pF capacitor to ground is
implemented. For maser applications and additional series resistor, a blocking diode should be placed
between the LIN pin and the VSUP pin. See Figure 30.
Pin 10 (VSUP): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed as close
to the device as possible.
Pin 11, 12 and 14 (NC): Not Connected.
NOTE
All ground and power connections should be made as short as possible and use at least
two vias to minimize the total loop inductance.
26
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11.2 Layout Example
VDD
VSUP
R1
RXD1
1
RXD1
NC
14
Only needed for
the Master node
D2
U1
VDD
R9
R3
EN1
LIN1
2
R2
EN1
LIN1
13
C3
GND
GND
C1
TXD1
3
R4
TXD1
NC
12
NC
11
VDD
R5
RXD2
4
RXD2
VDD
VSUP
R7
EN2
5
R6
EN2
VSUP
10
C5
D4
6
NC
R10
GND
Only needed for
the Master node
D1
LIN2
LIN2
9
C4
GND
GND
C2
TXD2
R8
7
TXD2
GND
8
GND
Figure 33. Layout Example
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12 Device and Documentation Support
This device will conform to the following LIN standards. The core of what is needed is covered within this system spec,
however reference should be made to these standards and any discrepancies pointed out and discussed. This document
should provide all the basics of what is needed.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
LIN Standards:
• ISO/DIS 17987-1.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and
use case definition
• ISO/DIS 17987-4.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer
(EPL) specification 12V/24V
• SAEJ2602-1: LIN Network for Vehicle Applications
• LIN2.0, LIN2.1, LIN2.2 and LIN2.2A specification
EMC requirements:
• SAEJ2962-2: TBD
• ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge
• ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband
radiated electromagnetic energy - Part 4: Harness excitation methods
• ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1:
Definitions and general considerations
• ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical
transient transmission by capacitive and inductive coupling via lines other than supply lines
• IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz Part 4: Direct RF power injection method
• IEC 61000-4-2
• IEC 61967-4
• CISPR25
Conformance Test requirements:
• ISO/DIS 17987-7.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer
(EPL) conformance test specification
• SAEJ2602-2: LIN Network for Vehicle Applications Conformance Test
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
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12.4 Trademarks (continued)
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
D0014A
SOIC - 1.75 mm max height
SCALE 1.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
6.2
TYP
5.8
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
12X 1.27
14
1
2X
7.62
8.75
8.55
NOTE 3
7
8
B
14X
4.0
3.8
NOTE 4
SEE DETAIL A
0.51
0.31
0.25
C A B
1.75 MAX
0.25
TYP
0.13
0.25
GAGE PLANE
0 -8
0.25
0.10
1.27
0.40
DETAIL A
TYPICAL
4220718/A 09/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.
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EXAMPLE BOARD LAYOUT
D0014A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
14X (1.55)
SYMM
1
14
14X (0.6)
12X (1.27)
SYMM
8
7
(R0.05)
TYP
(5.4)
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220718/A 09/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0014A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
14X (1.55)
SYMM
1
14
14X (0.6)
12X (1.27)
SYMM
7
8
(5.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:8X
4220718/A 09/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OUTLINE
DMT0014A
VSON - 0.9 mm max height
SCALE 3.200
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.05)
SECTION A-A
SECTION A-A
SCALE 30.000
TYPICAL
C
0.9 MAX
SEATING PLANE
0.05
0.00
0.08 C
1.6 0.1
EXPOSED
THERMAL PAD
SYMM
(0.2) TYP
7
8
A
2X
3.9
A
15
SYMM
4.2 0.1
14
1
12X 0.65
PIN 1 ID
(OPTIONAL)
14X
0.45
0.35
14X
0.35
0.25
0.1
0.05
C A B
C
4223033/B 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DMT0014A
VSON - 0.9 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
14X (0.6)
SYMM
14X (0.3)
1
14
2X
(1.85)
12X (0.65)
15
SYMM
(4.2)
(0.69)
TYP
( 0.2) VIA
TYP
8
7
(R0.05) TYP
(0.55) TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
0.07 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223033/B 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DMT0014A
VSON - 0.9 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.47)
14X (0.6)
1
15
14
14X (0.3)
(1.18)
12X (0.65)
SYMM
(1.38)
(R0.05) TYP
METAL
TYP
8
7
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 15
77.4% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4223033/B 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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6-Nov-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLIN2022DMTRQ1
ACTIVE
VSON
DMT
14
3000
Green (RoHS
& no Sb/Br)
CU
Level-2-260C-1 YEAR
-40 to 125
TL022
TLIN2022DMTTQ1
ACTIVE
VSON
DMT
14
250
Green (RoHS
& no Sb/Br)
CU
Level-2-260C-1 YEAR
-40 to 125
TL022
TLIN2022DRQ1
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
TL022
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Nov-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLIN2022DMTRQ1
VSON
DMT
14
3000
330.0
12.4
3.2
4.7
1.15
8.0
12.0
Q1
TLIN2022DMTTQ1
VSON
DMT
14
250
180.0
12.4
3.2
4.7
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2020
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLIN2022DMTRQ1
VSON
DMT
14
3000
370.0
355.0
55.0
TLIN2022DMTTQ1
VSON
DMT
14
250
195.0
200.0
45.0
Pack Materials-Page 2
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