Texas Instruments | SN55HVD233-SEP 3.3-V Radiation Hardened CAN Transceiver in Space Enhanced Plastic | Datasheet | Texas Instruments SN55HVD233-SEP 3.3-V Radiation Hardened CAN Transceiver in Space Enhanced Plastic Datasheet

Texas Instruments SN55HVD233-SEP 3.3-V Radiation Hardened CAN Transceiver in Space Enhanced Plastic Datasheet
Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
SN55HVD233-SEP
SLLSF98 – DECEMBER 2018
SN55HVD233-SEP 3.3-V Radiation Hardened CAN Transceiver in Space Enhanced Plastic
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
VID V62/18617
Radiation Hardened
– Single Event Latch-up (SEL) Immune to 43
MeV-cm2/mg at 125°C
– ELDRS Free to 30 krad(Si)
– Total Ionizing Dose (TID) RLAT for Every
Wafer Lot up to 20 krad(Si)
Space Enhanced Plastic
– Controlled Baseline
– Gold Wire
– NiPdAu Lead Finish
– One Assembly and Test Site
– One Fabrication Site
– Available in Military (–55°C to 125°C)
Temperature Range
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
– Enhanced Mold Compound for Low
Outgassing
Compatible With ISO 11898-2
Bus Pins Fault Protection Exceeds ±16 V
Bus Pins ESD Protection Exceeds ±14-kV HBM
Data Rates up to 1 Mbps
Extended –7-V to 12-V Common Mode Range
High-Input Impedance Allows for 120 Nodes
LVTTL I/Os are 5-V Tolerant
Adjustable Driver Transition Times for Improved
Signal Quality
Unpowered Node Does Not Disturb the Bus
Low-Current Standby Mode, 200-µA Typical
Loopback for Diagnostic Functions
Thermal Shutdown Protection
Power Up and Power Down With Glitch-Free Bus
Inputs and Outputs
– High-Input Impedance With Low VCC
– Monolithic Output During Power Cycling
•
Supports Low Earth Orbit Space Applications
Space Data Bus Communication and Control
Satellite Telemetry and Telecommand for Onboard Data Handling
CAN Bus Standards Such as CANopen,
DeviceNet, CAN Kingdom, ISO 11783, NMEA
2000, SAE J1939
3 Description
The SN55HVD233-SEP is used in applications
employing the controller area network (CAN) serial
communication physical layer in accordance with the
ISO 11898 standard. As a CAN transceiver, the
device provides transmit and receive capability
between the differential CAN bus and a CAN
controller, with signaling rates up to 1 Mbps.
Designed for operation in especially harsh radiation
environments, the SN55HVD233-SEP features crosswire, overvoltage, loss of ground protection to ±16 V,
and overtemperature (thermal shutdown) protection.
This device operates over a wide –7-V to 12-V
common mode range. This transceiver is the interface
between the host CAN controller on the
microprocessor, FPGA, or ASIC, and the differential
CAN bus used in satellite applications.
Device Information(1)
PART NUMBER
GRADE
SN55HVD233MDPSEP
20 krad(Si)
SN55HVD233MDTPSEP RLAT
PACKAGE
8-lead SOIC [D]
6.48 mm × 6.48 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VCC
VCC
VCC
VCC
D
BIAS UNIT
1
VCC
RS
LBK / EN /AB
SLOPE CONTROL
and MODE
LOGIC
R
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN55HVD233-SEP
SLLSF98 – DECEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
5
5
5
6
7
7
8
8
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Driver Electrical Characteristics ................................
Receiver Electrical Characteristics ...........................
Driver Switching Characteristics ...............................
Receiver Switching Characteristics...........................
Device Switching Characteristics..............................
Typical Characteristics ............................................
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
15
18
10 Application and Implementation........................ 19
10.1 Application Information.......................................... 19
10.2 Typical Application ................................................ 21
11 Power Supply Recommendations ..................... 23
12 Layout................................................................... 23
12.1 Layout Guidelines ................................................. 23
12.2 Layout Example .................................................... 25
13 Device and Documentation Support ................. 26
13.1
13.2
13.3
13.4
13.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
14 Mechanical, Packaging, and Orderable
Information ........................................................... 27
Parameter Measurement Information ................ 11
Detailed Description ............................................ 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2018
*
Initial release.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
SN55HVD233-SEP
www.ti.com
SLLSF98 – DECEMBER 2018
5 Description (continued)
Modes: The RS, pin 8 of the SN55HVD233-SEP, provides for three modes of operation: high-speed, slope
control, or low-power standby mode. The user selects the high-speed mode of operation by connecting pin 8
directly to ground, allowing the driver output transistors to switch on and off as fast as possible with no limitation
on the rise and fall slope. The user can adjust the rise and fall slope by connecting a resistor to ground at pin 8,
because the slope is proportional to the pin's output current. Slope control is implemented with a resistor value of
0 Ω to achieve a single ended slew rate of approximately 38 V/µs, and up to a value of 50 kΩ to achieve
approximately 4-V/µs slew rate. For more information about slope control, refer to the Application and
Implementation section.
The SN55HVD233-SEP enters a low-current standby (listen-only) mode during which the driver is switched off
and the receiver remains active if a high logic level is applied to pin 8. The local protocol controller reverses this
low-current standby mode when it needs to transmit to the bus. For more information on the loopback mode,
refer to the Application Information section.
Loopback: A logic high on the loopback LBK pin 5 of the SN55HVD233-SEP places the bus output and bus input
in a high-impedance state. The remaining circuit remains active and available for driver-to-receiver loopback,
self-diagnostic node functions without disturbing the bus.
CAN bus states: The CAN bus has two states during powered operation of the device: dominant and recessive.
A dominant bus state is when the bus is driven differentially, corresponding to a logic low on the D and R pin. A
recessive bus state is when the bus is biased to VCC / 2 through the high-resistance internal input resistors RIN of
the receiver, corresponding to a logic high on the D and R pins (see Bus States (Physical Bit Representation)
and Simplified Recessive Common Mode Bias and Receiver).
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
3
SN55HVD233-SEP
SLLSF98 – DECEMBER 2018
www.ti.com
6 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
D
GND
VCC
R
1
8
2
7
3
6
4
5
RS
CANH
CANL
LBK
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
I
CAN transmit data input (LOW for dominant and HIGH for recessive bus states), also called TXD, driver input.
D
1
GND
2
GND
VCC
3
Supply
R
4
O
CAN receive data output (LOW for dominant and HIGH for recessive bus states), also called RXD, receiver
output.
LBK
5
I
Loopback mode input pin.
CANL
6
I/O
Low-level CAN bus line.
CANH
7
I/O
High-level CAN bus line.
RS
8
I
4
Ground connection.
Transceiver 3.3-V supply voltage.
Mode select pin:
Tie to GND = high-speed mode,
Strong pullup to VCC = low power mode,
0-Ω to 50-kΩ pulldown to GND = slope control mode.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
SN55HVD233-SEP
www.ti.com
SLLSF98 – DECEMBER 2018
7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature unless otherwise noted (1) (2)
VCC
Supply voltage
MIN
MAX
UNIT
–0.3
7
V
Voltage at any bus pin (CANH or CANL)
–16
16
V
Voltage input, transient pulse, CANH and CANL, through 100 Ω (see Figure 18)
–100
100
V
VI
Input voltage, (D, RS, LBK)
–0.5
7
V
VO
Output voltage, (R)
–0.5
7
V
IO
Receiver output current
–10
10
mA
TJ
Operating junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground pin.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
CANH, CANL, and GND
±14000
Other pins
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
UNIT
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
VCC
Supply voltage
Voltage at any bus pin (separately or common mode)
NOM
MAX
UNIT
3
3.6
V
–7
12
V
VIH
High-level input voltage
D, LBK
2
5.5
V
VIL
Low-level input voltage
D, LBK
0
0.8
V
VID
Differential input voltage
–6
6
V
0
50
kΩ
0.75 VCC
5.5
V
Resistance from RS to ground for slope control
VI(RS)
Input voltage at RS for standby
IOH
High-level output current
IOL
Low-level output current
TJ
Operating junction temperature (1)
(1)
Driver
–50
Receiver
–10
mA
Driver
50
Receiver
10
–55
125
mA
°C
Maximum junction temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
5
SN55HVD233-SEP
SLLSF98 – DECEMBER 2018
www.ti.com
7.4 Thermal Information
SN55HVD233-SEP
THERMAL METRIC (1) (2)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
112.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
47.1
°C/W
RθJB
Junction-to-board thermal resistance
57.2
°C/W
ψJT
Junction-to-top characterization parameter
7.4
°C/W
ψJB
Junction-to-board characterization parameter
56.2
°C/W
(1)
(2)
6
All values except RθJC were taken on a JEDEC-51 standard High-K PCB using a nominal lead form. Differences in lead form,
component density, or PCB design can affect these values.
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
SN55HVD233-SEP
www.ti.com
SLLSF98 – DECEMBER 2018
7.5 Driver Electrical Characteristics
At TA = –55°C to 125°C, unless otherwise noted.
PARAMETER
MIN TYP (1)
TEST CONDITIONS
MAX
VO(D)
Bus output voltage
(dominant)
CANH
VO
Bus output voltage
(recessive)
CANH
VOD(D)
Differential output voltage
(dominant)
V(D) = 0 V, V(RS) = 0 V, see Figure 12 and Figure 13
1.5
2
3
V(D) = 0 V, V(RS) = 0 V, see Figure 13 and Figure 14
1.2
2
3
VOD
Differential output voltage
(recessive)
V(D) = 3 V, V(RS) = 0 V, see Figure 12 and Figure 13
–120
12
V(D) = 3 V, V(RS) = 0 V, no load
–0.5
0.05
VOC(pp)
Peak-to-peak common-mode output
See Figure 20
voltage
IIH
High-level input current D, LBK
V(D) = 2 V
IIL
Low-level input current
V(D) = 0.8 V
CANL
CANL
D, LBK
V(D) = 0 V, V(RS) = 0 V, see Figure 12 and Figure 13
Short-circuit output current
CO
Output capacitance
IIRS(s)
RS input current for standby
VCC
0.5
1.25
2.3
V(D) = 3 V, V(RS) = 0 V, see Figure 12 and Figure 13
(1)
Supply current
mV
V
V
30
µA
–30
30
µA
–250
1
–1
V(CANL) = 12 V, CANH open, see Figure 23
ICC
V
–30
V(CANH) = 12 V, CANL open, see Figure 23
V(CANL) = –7 V, CANH open, see Figure 23
V
V
2.3
1
V(CANH) = –7 V, CANL open, see Figure 23
IOS
2.4
UNIT
mA
250
See receiver input capacitance
V(RS) = 0.75 VCC
–10
µA
Standby
V(RS) = VCC, V(D) = VCC, V(LBK) = 0 V
200
700
Dominant
V(D) = 0 V, no load, V(LBK) = 0 V, RS = 0 V
6
Recessive
V(D) = VCC, no load, V(LBK) = 0 V, V(RS) = 0 V
6
µA
mA
All typical values are at 25°C and with a 3.3-V supply.
7.6 Receiver Electrical Characteristics
At TA = –55°C to 125°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Hysteresis voltage (VIT+ – VIT–)
VOH
High-level output voltage
IO = –4 mA, see Figure 17
VOL
Low-level output voltage
IO = 4 mA, see Figure 17
V(LBK) = 0 V, see Table 1
500
II
Bus input current
CANH or CANL = –7 V
CANH or CANL = –7 V,
VCC = 0 V
TYP (1)
MAX
UNIT
750
900
mV
650
mV
100
mV
2.4
V
0.4
V(CANH) or V(CANL) = 12 V
V(CANH) or V(CANL) = 12 V,
VCC = 0 V
MIN
Other bus pin = 0 V,
V(D) = 3 V,
V(LBK) = 0 V,
V(RS) = 0 V
150
500
150
600
–610
–100
–450
–100
V
µA
CI
Input capacitance (CANH or CANL)
Pin-to-ground, VI = 0.4 sin(4E6πt) + 0.5 V,
V(D) = 3 V, V(LBK) = 0 V
40
pF
CID
Differential input capacitance
Pin-to-pin, VI = 0.4 sin(4E6πt) + 0.5 V,
V(D) = 3 V, V(LBK) = 0 V
20
pF
RID
Differential input resistance
RIN
Input resistance (CANH or CANL)
ICC
(1)
Supply current
V(D) = 3 V, V(LBK) = 0 V
40
105
kΩ
20
55
kΩ
700
µA
Standby
V(RS) = VCC, V(D) = VCC, V(LBK) = 0 V
200
Dominant
V(D) = 0 V, no load, V(RS) = 0 V, V(LBK) = 0 V
6
mA
Recessive
V(D) = VCC, no load, V(RS) = 0 V, V(LBK) = 0 V
6
mA
All typical values are at 25°C and with a 3.3-V supply.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
7
SN55HVD233-SEP
SLLSF98 – DECEMBER 2018
www.ti.com
7.7 Driver Switching Characteristics
At TA = –55°C to 125°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Propagation delay time,
low-to-high-level output
tPLH
MIN
tPHL
35
85
RS with 10 kΩ to ground, see Figure 15
70
125
RS with 50 kΩ to ground, see Figure 15
500
870
70
120
RS with 10 kΩ to ground, see Figure 15
130
180
RS with 50 kΩ to ground, see Figure 15
870
1200
V(RS) = 0 V, see Figure 15
tsk(p)
Pulse skew (|tPHL – tPLH|)
tr
Differential output signal rise time
tf
Differential output signal fall time
tr
Differential output signal rise time
tf
Differential output signal fall time
tr
Differential output signal rise time
tf
Differential output signal fall time
ten(s)
Enable time from standby to dominant
(1)
MAX
V(RS) = 0 V, see Figure 15
V(RS) = 0 V, see Figure 15
Propagation delay time,
high-to-low-level output
TYP (1)
UNIT
ns
ns
35
RS with 10 kΩ to ground, see Figure 15
60
RS with 50 kΩ to ground, see Figure 15
370
ns
20
V(RS) = 0 V, see Figure 15
RS with 10 kΩ to ground, see Figure 15
RS with 50 kΩ to ground, see Figure 15
70
ns
20
70
ns
30
135
ns
30
135
ns
350
1400
ns
350
See Figure 19
1400
ns
0.6
1.5
µs
TYP (1)
MAX
UNIT
All typical values are at 25°C and with a 3.3-V supply.
7.8 Receiver Switching Characteristics
At TA = –55°C to 125°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
tPLH
Propagation delay time, low-to-high-level output
35
105
ns
tPHL
Propagation delay time, high-to-low-level output
35
105
ns
tsk(p)
Pulse skew (|tPHL – tPLH|)
tr
tf
(1)
See Figure 17
7
ns
Output signal rise time
2
ns
Output signal fall time
2
ns
All typical values are at 25°C and with a 3.3-V supply.
7.9 Device Switching Characteristics
At TA = –55°C to 125°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
t(LBK)
Loopback delay, driver input to receiver
output
t(loop1)
Total loop delay, driver input to receiver
output, recessive to dominant
MIN
See Figure 22
(1)
8
UNIT
ns
70
215
V(RS) with 10 kΩ to ground, see Figure 21
105
225
V(RS) with 50 kΩ to ground, see Figure 21
500
800
70
215
V(RS) with 10 kΩ to ground, see Figure 21
105
225
V(RS) with 50 kΩ to ground, see Figure 21
500
800
V(RS) at 0 V, see Figure 21
Total loop delay, driver input to receiver
output, dominant to recessive
MAX
7.5
V(RS) at 0 V, see Figure 21
t(loop2)
TYP (1)
ns
ns
All typical values are at 25°C and with a 3.3-V supply.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
SN55HVD233-SEP
www.ti.com
SLLSF98 – DECEMBER 2018
100
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
95
90
85
80
75
70
65
60
-55 -40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95 110 125
t(LOOPL2)- Dominant to Recessive Loop Time (ns)
t(LOOPL1)- Recessive to Dominant Loop Time (ns)
7.10 Typical Characteristics
100
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
95
90
85
80
75
-55 -40 -25 -10
5
D005
V(RS), V(LBK) = 0 V
20 35 50 65
Temperature (qC)
80
95 110 125
D002
V(RS), V(LBK) = 0 V
Figure 1. Recessive-To-Dominant Loop Time vs
Temperature
Figure 2. Dominant-To-Recessive Loop Time vs
Temperature
20
160
Driver Output Current (mA)
140
Supply Current (mA)
19
18
17
16
120
100
80
60
40
20
15
0
200
400
600
800
1000
Frequency (kbps)
VCC = 3.3 V
60-Ω load
0
V(RS), V(LBK) = 0 V
2
3
4
Low-Level Output Voltage (V)
TA = 25°C
VCC = 3.3 V
Figure 3. Supply Current vs Frequency
V(RS), V(LBK) = 0 V
C004
TA = 25°C
Figure 4. Driver Low-Level Output Current vs
Low-Level Output Voltage
2.2
VOD - Differential Output Voltage (V)
0.12
Driver High-Level Output Current (mA)
1
C003
0.10
0.08
0.06
0.04
0.02
0.00
0.0
0.5
1.0
1.5
2.0
2.5
3.0
High-Level Output Voltage (V)
VCC = 3.3 V
V(RS), V(LBK) = 0 V
3.5
2
1.8
1.6
1.4
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
1.2
1
-55 -40 -25 -10
C005
TA = 25°C
Figure 5. Driver High-Level Output Current vs
High-Level Output Voltage
RL = 60 Ω
5
20 35 50 65
Temperature (°C)
80
95 110 125
D001
V(RS), V(LBK) = 0 V
Figure 6. Differential Output Voltage vs
Temperature
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
9
SN55HVD233-SEP
SLLSF98 – DECEMBER 2018
www.ti.com
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
-55 -40 -25 -10
tPHL - Receiver High to Low Propagation Delay
tPLH - Receiver Low to High Propagation Delay
Typical Characteristics (continued)
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
5
V(RS), V(LBK) = 0 V
20 35 50 65
Temperature (qC)
80
95 110 125
See Figure 17
tPHL- Driver High to Low Propagation Delay (ns)
tPLH - Driver Low to High Propagation Delay (ns)
45
44
43
42
41
40
39
38
37
-55 -40 -25 -10
5
20 35 50 65
Temperature (qC)
45
40
35
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
30
20 35 50 65
Temperature (°C)
80
80
95 110 125
D006
See Figure 17
Figure 8. Receiver High-To-Low Propagation Delay vs
Temperature
50
V(RS), V(LBK) = 0 V
46
V(RS), V(LBK) = 0 V
55
5
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
47
D007
Figure 7. Receiver Low-To-High Propagation Delay vs
Temperature
25
-55 -40 -25 -10
48
95 110 125
60
55
50
45
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
40
-55 -40 -25 -10
5
D004
20 35 50 65
Temperature (qC)
V(RS), V(LBK) = 0 V
See Figure 15
80
95 110 125
D003
See Figure 15
Figure 10. Driver High-To-Low Propagation Delay vs
Temperature
Figure 9. Driver Low-To-High Propagation Delay vs
Temperature
35
Driver Output Current (mA)
30
25
20
15
10
5
0
±5
0.0
0.6
1.2
1.8
2.4
3.0
3.6
Supply Voltage (V)
V(RS), V(LBK) = 0 V
TA = 25°C
C011
RL = 60 Ω
Figure 11. Driver Output Current vs Supply Voltage
10
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
SN55HVD233-SEP
www.ti.com
SLLSF98 – DECEMBER 2018
8 Parameter Measurement Information
IO(CANH)
II
D
60 Ω ±1%
VO(CANH)
VOD
VI
VO(CANH) + VO(CANL)
IIRs
RS
2
VOC
IO(CANL)
+
VO(CANL)
VI(Rs)
-
Figure 12. Driver Voltage, Current, and Test Definition
Dominant
Recessive
≈3V
VO(CANH)
≈ 2.3 V
≈1V
VO(CANL)
Figure 13. Bus Logic State Voltage Definitions
VI
D
CANH
330 Ω ±1%
VOD
60 Ω ±1%
+
_
RS
CANL
-7 V ≤ VTEST ≤ 12 V
330 Ω ±1%
Figure 14. Driver VOD
CANH
CL = 50 pF ±20%
(see Note B)
D
RL = 60 Ω ±1%
VI
B.
VO
VI(Rs)
-
VCC
VCC/2
0V
tPLH
tPHL
RS +
(see Note A)
A.
VCC/2
VI
VO
VO(D)
90%
0.9 V
0.5 V
10%
CANL
tr
VO(R)
tf
The input pulse is supplied by a generator having the following characteristics:
•
Pulse repetition rate (PRR) ≤ 125 kHz, 50% duty cycle
•
tr ≤ 6 ns
•
tf ≤ 6 ns
•
ZO = 50 Ω
CL includes fixture and instrumentation capacitance.
Figure 15. Driver Test Circuit and Voltage Waveforms
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
11
SN55HVD233-SEP
SLLSF98 – DECEMBER 2018
www.ti.com
Parameter Measurement Information (continued)
CANH
R
VIC =
VI(CANH)
VI(CANH + VI(CANL)
IO
VID
2
VO
CANL
VI(CANL)
Figure 16. Receiver Voltage and Current Definitions
2.9 V
CANH
2.2 V
VI
R
1.5 V
IO
VI
(see Note A)
1.5 V
tPLH
CL = 15 pF ±20%
(see Note B)
CANL
2.2 V
tPHL
VO
50%
10%
VO
90%
90%
tr
A.
B.
VOH
50%
10%
VOL
tf
The input pulse is supplied by a generator having the following characteristics:
•
PRR ≤ 125 kHz, 50% duty cycle
•
tr ≤ 6 ns
•
tf ≤ 6 ns
•
ZO = 50 Ω
CL includes fixture and instrumentation capacitance.
Figure 17. Receiver Test Circuit and Voltage Waveforms
Table 1. Differential Input Voltage Threshold Test
INPUT
VCANH
VCANL
–6.1 V
–7 V
L
12 V
11.1 V
L
–1 V
–7 V
L
OUTPUT
MEASURED
R
|VID|
900 mV
900 mV
VOL
6V
12 V
6V
L
6V
–6.5 V
–7 V
H
500 mV
12 V
11.5 V
H
500 mV
–7 V
–1 V
H
6V
12 V
H
6V
Open
Open
H
X
VOH
6V
CANH
R
100 Ω
Pulse Generator
15 µs Duration
1% Duty Cycle
tr, tf ≤ 100 ns
CANL
D at 0 V or VCC
Rs, LBK, at 0 V or VCC
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 18. Test Circuit, Transient Overvoltage Test
12
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
SN55HVD233-SEP
www.ti.com
SLLSF98 – DECEMBER 2018
HVD233
RS
VI
CANH
D
0V
60 Ω ±1%
LBK
CANL
R
VO
+
15 pF ±20%
-
VCC
50%
VI
0V
VOH
50%
VO
VOL
ten(s)
Copyright © 2017, Texas Instruments Incorporated
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
•
tr or tf ≤ 6 ns
•
PRR = 125 kHz, 50% duty cycle
Figure 19. Ten(s) Test Circuit and Voltage Waveforms
CANH
27 Ω ±1%
VOC(PP)
D
VI
VOC
RS
CANL
27 Ω ±1%
VOC
50 pF ±20%
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
•
tr or tf ≤ 6 ns
•
PRR = 125 kHz, 50% duty cycle
Figure 20. VOC(pp) Test Circuit and Voltage Waveforms
0Ω, 10 kΩ,
or 100 kΩ ±5%
RS
DUT
CANH
D
VI
60 Ω ±1%
VCC
VI
50%
0V
LBK
t(loop2)
CANL
VCC
50%
VO
t(loop1)
50%
VOL
R
VO
+
-
VOH
50%
15 pF ±20%
Figure 21. T(loop) Test Circuit and Voltage Waveforms
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
13
SN55HVD233-SEP
SLLSF98 – DECEMBER 2018
RS
HVD233
VCC
CANH
+
VOD
-
D
VI
VCC
www.ti.com
LBK
50%
VI
50%
0V
60 W±1%
t(LBK1)
CANL
t(LBK2)
50%
VO
R
VO
+
VOH
50%
VOL
t(LBK) = t(LBK1) = t(LBK2)
VOD
≈ 2.3 V
15 pF ±20%
Copyright © 2017, Texas Instruments Incorporated
Figure 22. T(LBK) Test Circuit and Voltage Waveforms
 IOS 
IOS
D
0 V or VCC
15 s
CANH
+
_
IOS
0V
VI
12 V
CANL
VI
0V
0V
10 µs
and
VI
-7 V
Figure 23. IOS Test Circuit and Waveforms
3.3 V
R2 ± 1%
CANH
R
CANL
R1 ± 1%
TA = 25°C
VCC = 3.3 V
+
VID
-
R2 ± 1%
Vac
R1 ± 1%
VI
The R Output State Does Not Change During
Application of the Input Waveform.
VID
500 mV
900 mV
R1
50 Ω
50 Ω
R2
280 Ω
130 Ω
12 V
VI
-7 V
NOTE: All input pulses are supplied by a generator with ƒ ≤ 1.5 MHz.
Figure 24. Common-Mode Voltage Rejection
14
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
SN55HVD233-SEP
www.ti.com
SLLSF98 – DECEMBER 2018
9 Detailed Description
9.1 Overview
The SN55HVD233-SEP is used in applications employing the CAN serial communication physical layer in
accordance with the ISO 11898 standard. As a CAN transceiver, the device provides transmit and receive
capability between the differential CAN bus and a CAN controller, with signaling rates up to 1 Mbps.
Designed for operation in especially harsh environments, the SN55HVD233-SEP features cross-wire,
overvoltage, and loss of ground protection to ±16 V, overtemperature (thermal shutdown) protection, and
common-mode transient protection of ±100 V. This device operates over a wide –7-V to 12-V common mode
range. This transceiver is the interface between the host CAN controller on the microprocessor, FPGA, or ASIC;
and the differential CAN bus used in satellite applications.
9.2 Functional Block Diagram
8
Rs
7
CANH
D
1
6
CANL
4
R
5
LBK
Copyright © 2017, Texas Instruments Incorporated
9.3 Feature Description
9.3.1 Modes
The RS, pin 8 of the SN55HVD233-SEP, provides for three modes of operation: high-speed, slope control, or
low-power standby mode. The user selects the high-speed mode of operation by connecting pin 8 directly to
ground, allowing the driver output transistors to switch on and off as fast as possible with no limitation on the rise
and fall slope. The user can adjust the rise and fall slope by connecting a resistor to ground at pin 8, because the
slope is proportional to the pin's output current. Slope control is implemented with a resistor value of 0 Ω to
achieve a single ended slew rate of approximately 38-V/µs, and up to a value of 50 kΩ to achieve approximately
4-V/µs slew rate. For more information about slope control, refer to Application and Implementation section.
The SN55HVD233-SEP enters a low-current standby (listen-only) mode during which the driver is switched off
and the receiver remains active if a high logic level is applied to pin 8. The local protocol controller reverses this
low-current standby mode when it needs to transmit to the bus.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
15
SN55HVD233-SEP
SLLSF98 – DECEMBER 2018
www.ti.com
Feature Description (continued)
9.3.2 Loopback
A logic high on the loopback LBK pin 5 of the SN55HVD233-SEP places the bus output and bus input in a highimpedance state. The remaining circuit remains active and available for driver-to-receiver loopback, selfdiagnostic node functions without disturbing the bus. For more information on the loopback mode, refer to the
Application Information section.
9.3.3 CAN Bus States
Typical Bus Voltage (V)
1
2
3
4
The CAN bus has two states during powered operation of the device: dominant and recessive. A dominant bus
state is when the bus is driven differentially, corresponding to a logic low on the D and R pin. A recessive bus
state is when the bus is biased to VCC / 2 through the high-resistance internal input resistors RIN of the receiver,
corresponding to a logic high on the D and R pins (see Figure 25 and Figure 26).
CANH
Vdiff(D)
Vdiff(R)
CANL
Recessive
Logic H
Dominant
Logic L
Recessive
Logic H
Time, t
Figure 25. Bus States (Physical Bit Representation)
CANH
VCC/2
RXD
CANL
Figure 26. Simplified Recessive Common Mode Bias and Receiver
9.3.4 ISO 11898 Compliance of SN55HVD233-SEP
9.3.4.1 Introduction
Many users value the low-power consumption of operating their CAN transceivers from a 3.3-V supply. However,
some users are concerned about the interoperability with 5-V supplied transceivers on the same bus. This report
analyzes this situation to address those concerns.
16
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
SN55HVD233-SEP
www.ti.com
SLLSF98 – DECEMBER 2018
Feature Description (continued)
9.3.4.2 Differential Signal
CAN is a differential bus where complementary signals are sent over two wires and the voltage difference
between the two wires defines the logical state of the bus. The differential CAN receiver monitors this voltage
difference and outputs the bus state with a single-ended output signal.
NOISE MARGIN
900 mV Threshold
RECEIVER DETECTION WINDOW
75% SAMPLE POINT
500 mV Threshold
NOISE MARGIN
Figure 27. Typical SN55HVD233-SEP Differential Output Voltage Waveform
The CAN driver creates the difference in voltage between CANH and CANL in the dominant state. The dominant
differential output of the SN55HVD233-SEP is greater than 1.5 V and less than 3 V across a 60-Ω load. The
minimum required by ISO 11898 is 1.5 V and maximum is 3 V. These are the same limiting values for 5-V
supplied CAN transceivers. The bus termination resistors drive the recessive bus state and not the CAN driver.
A CAN receiver is required to output a recessive state with less than 500 mV and a dominant state with more
than 900-mV difference voltage on its bus inputs. The CAN receiver must do this with common-mode input
voltages from –2 V to 7 V. The SN55HVD233-SEP receiver meets these same input specifications as 5-V
supplied receivers.
9.3.4.2.1 Common-Mode Signal
A common-mode signal is an average voltage of the two signal wires that the differential receiver rejects. The
common-mode signal comes from the CAN driver, ground noise, and coupled bus noise. The supply voltage of
the CAN transceiver has nothing to do with noise. The SN55HVD233-SEP driver lowers the common-mode
output in a dominant bit by a couple hundred millivolts from that of most 5-V drivers. While this does not fully
comply with ISO 11898, this small variation in the driver common-mode output is rejected by differential receivers
and does not effect data, signal noise margins, or error rates.
9.3.4.3 Interoperability of 3.3-V CAN in 5-V CAN Systems
The 3.3-V supplied CAN transceivers are electrically interchangeable with 5-V CAN transceivers. The differential
output is the same. The recessive common mode output is the same. The dominant common mode output
voltage is a couple hundred millivolts lower than 5-V supplied drivers, while the receivers exhibit identical
specifications as 5-V devices.
To help ensure the widest interoperability possible, the SN55HVD233-SEP successfully passed the
internationally recognized GIFT ICT conformance and interoperability testing for CAN transceivers. Electrical
interoperability does not always assure interchangeability, however. Most implementers of CAN buses recognize
that ISO 11898 does not sufficiently specify the electrical layer and that strict standard compliance alone does
not ensure full interchangeability. Interchangeability is ensured with thorough equipment testing.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
17
SN55HVD233-SEP
SLLSF98 – DECEMBER 2018
www.ti.com
Feature Description (continued)
9.3.5 Thermal Shutdown
If the junction temperature of the device exceeds the thermal shutdown threshold, the device turns off the CAN
driver circuits thus blocking the D pin to bus transmission path. The shutdown condition is cleared when the
junction temperature drops below the thermal shutdown temperature of the device. The CAN bus pins are highimpedance biased to recessive level during a thermal shutdown, and the receiver-to-R pin path remains
operational.
9.4 Device Functional Modes
Table 2. Driver I/O
DRIVER (1)
INPUTS
(1)
OUTPUTS
D
LBK
RS
CANH
CANL
BUS STATE
X
X
> 0.75 VCC
Z
Z
Recessive
L
L or open
H
L
Dominant
H or open
X
Z
Z
Recessive
X
H
Z
Z
Recessive
≤ 0.33 VCC
≤ 0.33 VCC
H = High level; L = Low level; Z = High impedance; X = Irrelevant
Table 3. Receiver I/O
RECEIVER (1)
INPUTS
(1)
18
OUTPUT
BUS STATE
VID = V(CANH) – V(CANL)
D
R
Dominant
VID ≥ 0.9 V
X
L
Recessive
VID ≤ 0.5 V or open
H or open
H
?
0.5 V < VID < 0.9 V
H or open
?
Dominant
VID ≥ 0.9 V
X
L
Recessive
VID ≤ 0.5 V or open
H
H
Recessive
VID ≤ 0.5 V or open
L
L
?
0.5 V < VID < 0.9 V
L
L
H = High level; L = Low level; Z = High impedance; X = Irrelevant; ? = Indeterminate
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
SN55HVD233-SEP
www.ti.com
SLLSF98 – DECEMBER 2018
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Diagnostic Loopback
The diagnostic loopback or internal loopback function of the SN55HVD233-SEP is enabled with a high-level input
on pin 7, LBK. This mode disables the driver output while keeping the bus pins biased to the recessive state.
This mode also redirects the D data input (transmit data) through logic to the received data output (R), thus
creating an internal loopback of the transmit-to-receive data path. This mimics the loopback that occurs normally
with a CAN transceiver because the receiver loops back the driven output to the R (receive data) pin. This mode
allows the host microprocessor to input and read back a bit sequence or CAN messages to perform diagnostic
routines without disturbing the CAN bus. Figure 33 shows a typical CAN bus application.
If the LBK pin is not used, it may be tied to ground (GND). However, it is pulled low internally (defaults to a lowlevel input) and may be left open if not in use.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
19
SN55HVD233-SEP
SLLSF98 – DECEMBER 2018
www.ti.com
Application Information (continued)
RS INPUT
D INPUT
CANH INPUT
VCC
VCC
VCC
110 kW
100 kW
INPUT
1 kW
45 kW
INPUT
9V
9 kW
INPUT
CANH AND CANL OUTPUTS
VCC
VCC
110 kW
40 V
+
_
CANL INPUT
R OUTPUT
VCC
9 kW
5W
45 kW
OUTPUT
INPUT
40 V
9 kW
OUTPUT
9 kW
9V
40 V
LBK INPUT
VCC
INPUT
1 kW
9V
100 kW
Copyright © 2017, Texas Instruments Incorporated
Figure 28. Equivalent Input and Output Schematic Diagrams
20
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
SN55HVD233-SEP
www.ti.com
SLLSF98 – DECEMBER 2018
10.2 Typical Application
CANH
Bus Lines -- 40 m max
120 :
120 :
Stub Lines -- 0.3 m max
CANL
3.3 V
Vcc
Rs
0.1 PF
SN55HVD233-SP
3.3 V
Vcc
Rs
LBK
GPIO
D
CANTX
0.1 PF
SN55HVD233-SP
GND
3.3 V
Vcc
Rs
R
LBK
CANRX
GPIO
FPGA/MCU
Sensor, Actuator, or Control
Equipment
D
CANTX
0.1 P F
SN55HVD233-SP
GND
GND
R
D
LBK
CANRX
GPIO
CANTX
R
CANRX
FPGA/MCU
FPGA/MCU
Sensor, Actuator, or Control
Equipment
Sensor, Actuator, or Control
Equipment
Copyright © 2017, Texas Instruments Incorporated
Figure 29. Typical Application Schematic
10.2.1 Design Requirements
The High-Speed ISO 11898 Standard specifications are given for a maximum signaling rate of 1 Mbps with a bus
length of 40 m and a maximum of 30 nodes. It also recommends a maximum unterminated stub length of 0.3 m.
The cable is specified to be a shielded or unshielded twisted-pair with a 120-Ω characteristic impedance (ZO).
The standard defines a single line of twisted-pair cable with the network topology as shown in Figure 29. It is
terminated at both ends with 120-Ω resistors, which match the characteristic impedance of the line to prevent
signal reflections. According to ISO 11898, placing RL on a node should be avoided because the bus lines lose
termination if the node is disconnected from the bus.
10.2.2 Detailed Design Procedure
Table 4. Suggested Cable Length vs Signaling Rate
BUS LENGTH (m)
SIGNALING RATE (Mbps)
40
1
100
0.5
200
0.25
500
0.1
1000
0.05
Basically, the maximum bus length is determined by, or rather is a trade-off with the selected signaling rate as
listed in Table 4.
A signaling rate decreases as transmission distance increases. While steady-state losses may become a factor
at the longest transmission distances, the major factors limiting signaling rate as distance is increased are time
varying. Cable bandwidth limitations, which degrade the signal transition time and introduce inter-symbol
interference (ISI), are primary factors reducing the achievable signaling rate when transmission distance is
increased.
For a CAN bus, the signaling rate is also determined from the total system delay – down and back between the
two most distant nodes of a system and the sum of the delays into and out of the nodes on a bus with the typical
5-ns/m prop delay of a twisted-pair cable. Also, consideration must be given the signal amplitude loss due to
resistance of the cable and the input resistance of the transceivers. Under strict analysis, skin effects, proximity
to other circuitry, dielectric loss, and radiation loss effects all act to influence the primary line parameters and
degrade the signal.
A conservative rule of thumb for bus lengths over 100 m is derived from the product of the signaling rate in Mbps
and the bus length in m, which should be less than or equal to 50.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
21
SN55HVD233-SEP
SLLSF98 – DECEMBER 2018
www.ti.com
Signaling Rate (Mbps) × Bus Length (m) ≤ 50. Operation at extreme temperatures should employ additional
conservatism.
10.2.2.1 Slope Control
Adjust the rise and fall slope of the SN55HVD233-SEP driver output by connecting a resistor from the RS (pin 8)
to ground (GND), or to a low-level input voltage as shown in Figure 30.
The slope of the driver output signal is proportional to the pin's output current. This slope control is implemented
with an external resistor value ranging from 0 Ω to achieve a ≈38-V/µs single ended slew rate, and up to 50 kΩ to
achieve a ≈4-V/µs slew rate as displayed in Figure 31. Figure 32 shows typical driver output waveforms with
slope control.
RS
D
GND
VCC
R
N/C
1
10
2
9
3
8
4
7
5
6
0 kΩ to
50 kΩ
GPIO
MCU/DSP
CANH
CANL
LBK
N/C
Figure 30. Slope Control/Standby Connection to a DSP
10.2.2.2 Standby
If a high-level input (> 0.75 VCC) is applied to RS (pin 8), the circuit enters a low-current, listen-only standby
mode during which the driver is switched off and the receiver remains active. The local controller can reverse this
low-power standby mode when the rising edge of a dominant state (bus differential voltage > 900-mV typical)
occurs on the bus.
10.2.3 Application Curves
40
35
Slope (V/Ps)
30
25
20
15
10
5
0
0
10000
20000
30000
40000
50000
Slope Control Resistance (k:)
60000
D008
Figure 31. HVD233 Driver Output Signal Slope vs Slope
Control Resistance Value
22
Figure 32. Typical SN55HVD233-SEP 250-Kbps Output
Pulse Waveforms With Slope Control
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
SN55HVD233-SEP
www.ti.com
SLLSF98 – DECEMBER 2018
11 Power Supply Recommendations
TI recommends to have localized capacitive decoupling near device VCC pin to GND. Values of 4.7 µF at VCC
pin and 10 µF, 1 µF, and 0.1 µF at supply have tested well on evaluation modules.
12 Layout
12.1 Layout Guidelines
Minimize stub length from node insertion to bus.
12.1.1 Bus Loading, Length, and Number of Nodes
The ISO11898 standard specifies up to 1-Mbps data rate, maximum bus length of 40 m, maximum drop line
(stub) length of 0.3 m, and a maximum of 30 nodes. However, with careful network design, the system may have
longer cables, longer stub lengths, and many more nodes to a bus. Many CAN organizations and standards have
scaled the use of CAN for applications outside the original ISO11898 standard. They made system level tradeoffs for data rate, cable length, and parasitic loading of the bus. Examples of some of these specifications are
ARINC825, CANopen, CAN Kingdom, DeviceNet, and NMEA200.
A high number of nodes requires a transceiver with high input impedance and wide common mode range such
as the SN55HVD233-SEP CAN. ISO11898-2 specifies the driver differential output with a 60-Ω load (two 120-Ω
termination resistors in parallel), and the differential output must be greater than 1.5 V. The SN55HVD233-SEP is
specified to meet the 1.5-V requirement with a 60-Ω load, and additionally specified with a differential output
voltage minimum of 1.2 V across a common mode range of –2 V to 7 V through a 330-Ω coupling network. This
network represents the bus loading of 120 SN55HVD233-SEP transceivers based on their minimum differential
input resistance of 40 kΩ. Therefore, the SN55HVD233-SEP supports up to 120 transceivers on a single bus
segment with margin to the 1.2-V minimum differential input voltage requirement at each node. For CAN network
design, margin must be given for signal loss across the system and cabling, parasitic loadings, network
imbalances, ground offsets, and signal integrity; thus, a practical maximum number of nodes may be lower. Bus
length may also be extended beyond the original ISO11898 standard of 40 m by careful system design and data
rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1 km with
changes in the termination resistance, cabling, less than 64 nodes, and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO11898 CAN standard. Using this flexibility requires good
network design.
12.1.2 CAN Termination
The ISO11898 standard specifies the interconnect to be a twisted pair cable (shielded or unshielded) with 120-Ω
characteristic impedance (ZO). Use resistors equal to the characteristic impedance of the line to terminate both
ends of the cable to prevent signal reflections. Keep unterminated drop lines (stubs) connecting nodes to the bus
as short as possible to minimize signal reflections. The termination may be on the cable or in a node, but if
nodes may be removed from the bus, the termination must be carefully placed so that it is not removed from the
bus.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
23
SN55HVD233-SEP
SLLSF98 – DECEMBER 2018
www.ti.com
Layout Guidelines (continued)
Node n
(with termination)
Node 1
Node 2
Node 3
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
MCU or DSP
CAN
Controller
CAN
Transceiver
RTERM
RTERM
Figure 33. Typical CAN Bus
Termination is typically a 120-Ω resistor at each end of the bus. If filtering and stabilization of the common mode
voltage of the bus is desired, then the user may use split termination (see Figure 34). Split termination uses two
60-Ω resistors with a capacitor in the middle of these resistors to ground. Split termination improves the
electromagnetic emissions behavior of the network by eliminating fluctuations in the bus common mode voltages
at the start and end of message transmissions.
Take care with the power ratings of the termination resistors used, especially for the worst-case condition (if a
system power supply is shorted across the termination resistance to ground). In most cases, under the worstcase condition, much higher current passes through the termination resistance than the CAN transceiver's
current limit.
Standard Termination
CANH
Split Termination
CANH
RTERM/2
CAN
CAN
Transceiver
RTERM
Transceiver
CSPLIT
RTERM/2
CANL
CANL
Figure 34. CAN Bus Termination Concepts
24
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
SN55HVD233-SEP
www.ti.com
SLLSF98 – DECEMBER 2018
12.2 Layout Example
R3
RS
C4
R1
C1
D
GND
C8
R5
GND
GND
J1
C7
C3
R6
C9
R
C2
VCC
D1
U1
GND
R2
R4
LBK
Figure 35. Board Layout Example
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
25
SN55HVD233-SEP
SLLSF98 – DECEMBER 2018
www.ti.com
13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
26
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
SN55HVD233-SEP
www.ti.com
SLLSF98 – DECEMBER 2018
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN55HVD233-SEP
27
PACKAGE OPTION ADDENDUM
www.ti.com
7-Mar-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN55HVD233MDPSEP
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
33PSEP
SN55HVD233MDTPSEP
ACTIVE
SOIC
D
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
33PSEP
V62/18617-01XE
ACTIVE
SOIC
D
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
33PSEP
V62/18617-01XE-T
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
33PSEP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Mar-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN55HVD233-SEP :
• Space: SN55HVD233-SP
NOTE: Qualified Version Definitions:
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN55HVD233MDTPSEP
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN55HVD233MDTPSEP
SOIC
D
8
250
340.5
338.1
20.6
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising