Texas Instruments | AM26LS31x Quadruple Differential Line Driver (Rev. L) | Datasheet | Texas Instruments AM26LS31x Quadruple Differential Line Driver (Rev. L) Datasheet

Texas Instruments AM26LS31x Quadruple Differential Line Driver (Rev. L) Datasheet
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AM26LS31, AM26LS31C, AM26LS31I, AM26LS31M
SLLS114L – JANUARY 1979 – REVISED OCTOBER 2018
AM26LS31x Quadruple Differential Line Driver
1 Features
3 Description
•
The AM26LS31 family of devices is a quadruple
complementary-output line driver designed to meet
the requirements of ANSI TIA/EIA-422-B and ITU
(formerly CCITT) Recommendation V.11. The 3-state
outputs have high-current capability for driving
balanced lines such as twisted-pair or parallel-wire
transmission lines, and they are in the highimpedance state in the power-off condition. The
enable function is common to all four drivers and
offers the choice of an active-high or active-low
enable (G, G) input. Low-power Schottky circuitry
reduces power consumption without sacrificing
speed.
1
•
•
•
•
•
•
Meets or Exceeds the Requirements of ANSI
TIA/EIA-422-B and ITU
Operates From a Single 5-V Supply
TTL-Compatible
Complementary Outputs
High Output Impedance in Power-Off Conditions
Complementary Output-Enable Inputs
Available MIL-PRF-38535-Qualified Options (M):
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
PART NUMBER
2 Applications
•
•
•
•
Device Information(1)
Motor Encoders
Field Transmitters: Pressure Sensors and
Temperature Sensors
Military and Avionics Imaging
Temperature Sensors or Controllers Using
Modbus
PACKAGE
BODY SIZE (NOM)
AM26LS31MFK
LCCC (20)
8.89 mm × 8.89 mm
AM26LS31MJ
CDIP (16)
19.60 mm × 6.92 mm
AM26LS31MW
CFP (16)
10.30 mm × 6.73 mm
AM26LS31CD
SOIC (16)
9.90 mm × 3.91 mm
AM26LS31CDB
SSOP (16)
6.20 mm × 5.30 mm
AM26LS31CN
PDIP (16)
19.30 mm × 6.35 mm
AM26LS31xNS
SO (16)
10.30 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Schematic (Each Driver)
Input A
V
22 kΩ
9Ω
9Ω
Output Z
Output Y
Common to All Four Drivers
VCC
V
22 kΩ
22 kΩ
To Three Other Drivers
Enable G
Enable G
GND
All resistor values are nominal.
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AM26LS31, AM26LS31C, AM26LS31I, AM26LS31M
SLLS114L – JANUARY 1979 – REVISED OCTOBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
5
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Switching Characteristics – AM26LS31 ....................
Switching Characteristics – AM26LS31M .................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (July 2016) to Revision L
Page
•
Changed VCC pin number From: 8 To: 16 in the Pin Functions table .................................................................................. 3
•
Changed GND pin number From: 16 To: 8 in the Pin Functions table ................................................................................. 3
Changes from Revision J (January 2014) to Revision K
Page
•
Added Applications section, the Device Information table, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1
•
Split up Switching Characteristics table into two tables specified for each part..................................................................... 5
Changes from Revision I (February 2006) to Revision J
Page
•
Updated document to new TI data sheet format - no specification changes. ........................................................................ 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Updated Features. .................................................................................................................................................................. 1
•
Added Device and Documentation Support section............................................................................................................. 14
2
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SLLS114L – JANUARY 1979 – REVISED OCTOBER 2018
5 Pin Configuration and Functions
D, DB, N , NS, J, or W Package
SOIC, SSOP, PDIP, SO, CDIP, or CFP
Top View
6
11
7
10
8
9
1
20 19
4A
12
2
1Z
4
18 4Y
G
5
17 4Z
NC
6
16 NC
2Z
7
15 G
2Y
8
14 3Z
2A
9
10 11 12 13
3Y
5
3
V CC
13
3A
14
4
1A
3
VCC
4A
4Y
4Z
G
3Z
3Y
3A
NC
15
NC
16
2
GND
1
1Y
1A
1Y
1Z
G
2Z
2Y
2A
GND
FK Package
20-Pin LCCC
Top View
Pin Functions
PIN
SOIC, SSOP,
PDIP, SO, CDIP,
or CFP
LCCC
1A
1
2
I
Logic Data Input to RS422 Driver number 1
1Y
2
3
O
RS-422 Data Line (Driver 1)
1Z
3
4
O
RS-422 Data Line (Driver 1)
G
4
5
I
Driver Enable (active high)
G
12
15
I
Driver Enable (active Low)
2A
7
9
I
Logic Data Input to RS422 Driver number 2
2Y
6
8
O
RS-422 Data Line (Driver 2)
2Z
5
7
O
RS-422 Data Line (Driver 2)
3A
9
12
I
Logic Data Input to RS422 Driver number 3
3Y
10
13
O
RS-422 Data Line (Driver 3)
3Z
11
14
O
RS-422 Data Line (Driver 3)
4A
15
19
I
Logic Data Input to RS422 Driver number 4
4Y
14
18
O
RS-422 Data Line (Driver 4)
4Z
13
17
O
RS-422 Data Line (Driver 4)
VCC
16
20
–
Power Input. Connect to 5-V Power Source.
GND
8
10
–
Device Ground Pin
NAME
I/O
DESCRIPTION
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VCC
Supply voltage (2)
VI
Input voltage
(1)
(2)
UNIT
7
V
7
V
Output off-state voltage
5.5
V
Lead temperature 1,6 mm (1/16 in) from case for 10 s
260
°C
300
°C
150
°C
Lead temperature 1,6 mm (1/16 in) from case for 60 s J package
Tstg
MAX
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential output voltage VOD, are with respect to network GND.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
AM26LS31C
4.75
5
5.25
AM26LS31M
4.5
5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
V
IOH
High-level output current
–20
mA
IOL
Low-level output current
20
mA
TA
Operating free-air temperature
2
AM26LS31C
V
V
0
70
AM26LS31I
–40
85
AM26LS31M
–55
125
°C
6.4 Thermal Information
AM26LS31x
THERMAL METRIC (1)
D (SOIC)
DB (SSOP)
N (PDIP)
NS (SO)
16 PINS
UNIT
16 PINS
16 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance (2)
73
82
67
64
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
38.1
–
–
32.6
°C/W
RθJB
Junction-to-board thermal resistance
34.7
–
–
36.8
°C/W
ψJT
Junction-to-top characterization parameter
7.1
–
–
4.2
°C/W
ψJB
Junction-to-board characterization parameter
34.4
–
–
36.5
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The package thermal impedance is calculated in accordance with JESD 51-7.
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SLLS114L – JANUARY 1979 – REVISED OCTOBER 2018
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VIK
Input clamp voltage
VCC = MIN, II = –18 mA
VOH
High-level output voltage
VCC = MIN, IOH = –20 mA
VOL
Low-level output voltage
VCC = MIN, IOL = 20 mA
TYP (2)
MIN
MAX
UNIT
–1.5
V
2.5
V
0.5
VO = 0.5 V
–20
VO = 2.5 V
20
V
IOZ
Off-state (high-impedance-state)
output current
VCC = MIN,
II
Input current at maximum input voltage
VCC = MAX, VI = 7 V
0.1
mA
IIH
High-level input current
VCC = MAX, VI = 2.7 V
20
μA
IIL
Low-level input current
VCC = MAX, VI = 0.4 V
–0.36
mA
IOS
Short-circuit output current (3)
VCC = MAX
–150
mA
ICC
Supply current
VCC = MAX, all outputs disabled
80
mA
(1)
(2)
(3)
–30
32
μA
For C-suffix devices, VCC min = 4.75 V and VCC max = 5.25 V. For M-suffix devices, VCC min = 4.5 V and VCC max = 5.5 V.
All typical values are at VCC = 5 V and TA = 25°C.
Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
6.6 Switching Characteristics – AM26LS31
TA = 25°C, VCC = 5 V (see Figure 11)
PARAMETER
tPLH
TEST CONDITIONS
Propagation delay time, low- to
high-level output
MIN
TYP
MAX
14
20
14
20
RL = 75 Ω
25
40
RL = 180 Ω
37
45
21
30
23
35
1
6
UNIT
CL = 30 pF, S1 and S2 open
tPHL
Propagation delay time, high- to
low-level output
tPZH
Output enable time to high level
tPZL
Output enable time to low level
tPHZ
Output disable time from high level
tPLZ
Output disable time from low level
tSKEW
Output-to-output skew
CL = 30 pF
ns
CL = 10 pF, S1 and S2 closed
CL = 30 pF, S1 and S2 open
ns
ns
ns
6.7 Switching Characteristics – AM26LS31M
TA = 25°C, VCC = 5 V (see Figure 11)
PARAMETER
tPLH
TEST CONDITIONS
Propagation delay time, low- to highlevel output
tPHL
Propagation delay time, high- to lowlevel output
tPZH
Output enable time to high level
tPZL
Output enable time to low level
tPHZ
Output disable time from high level
tPLZ
Output disable time from low level
tSKEW
Output-to-output skew
MIN
MAX
UNIT
30
CL = 30 pF, S1 and S2 open
ns
30
CL = 30 pF
RL = 75 Ω
60
RL = 180 Ω
68
CL = 10 pF, S1 and S2 closed
CL = 30 pF, S1 and S2 open
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53
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ns
ns
ns
5
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6.8 Typical Characteristics
4
4
VCC = 5 V
Load = 470 Ω to GND
See Note A
VCC = 5.25 V
VCC = 5 V
3
VO − Y Output Voltage − V
VO − Y Output Voltage − V
Load = 470 Ω to GND
TA = 25°C
See Note A
VCC = 4.75 V
2
1
TA = 70°C
3
TA = 0°C
TA = 25°C
2
1
0
0
0
1
2
0
3
1
2
3
VI − Enable G Input Voltage − V
VI − Enable G Input Voltage − V
A. The A input is connected to VCC during testing of the Y outputs
and to ground during testing of the Z outputs.
Figure 1. Output Voltage vs Enable G Input Voltage
A. The A input is connected to VCC during testing of the Y outputs
and to ground during testing of the Z outputs.
Figure 2. Output Voltage vs Enable G Input Voltage
6
6
VCC = 5.25 V
5
VCC = 5 V
VCC = 4.75 V
4
VO − Output Voltage − V
VO − Output Voltage − V
5
3
2
1
0
1
TA = 70°C
3
TA = 25°C
VCC = 5 V
Load = 470 Ω to VCC
See Note B
0
2
3
0
1
2
3
VI − Enable G Input Voltage − V
VI − Enable G Input Voltage − V
B. The A input is connected to ground during testing of the Y
outputs and to VCC during testing of the Z outputs.
Figure 3. Output Voltage vs Enable G Input Voltage
B. The A input is connected to ground during testing of the Y
outputs and to VCC during testing of the Z outputs.
Figure 4. Output Voltage vs Enable G Input Voltage
4
5
VCC = 5 V
See Note A
VCC = 5.25 V
VOH − High-Level Output Voltage − V
VOH − High-Level Output Voltage − V
TA = 0°C
2
1
Load = 470 Ω to VCC
TA = 25°C
See Note B
0
4
4
IOH = −20 mA
3
IOH = −40 mA
2
1
VCC = 5 V
3
VCC = 4.75 V
2
1
TA = 25°C
See Note A
0
0
0
25
50
75
0
−20
TA − Free-Air Temperature − °C
A. The A input is connected to VCC during testing of the Y outputs
and to ground during testing of the Z outputs.
Figure 5. High-Level Output Voltage vs Free-Air
Temperature
6
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−40
−60
−80
−100
IOH − High-Level Output Current − mA
A. The A input is connected to VCC during testing of the Y outputs
and to ground during testing of the Z outputs.
Figure 6. High-Level Output Voltage vs High-Level Output
Current
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Typical Characteristics (continued)
0.5
1
TA = 25°C
See Note B
0.9
VOL− Low-Level Output Voltage − V
VOL− Low-Level Output Voltage − V
VCC = 5 V
IOL = 40 mA
See Note B
0.4
0.3
0.2
0.1
0.8
0.7
0.6
0.5
VCC = 4.75 V
0.4
VCC = 5.25 V
0.3
0.2
0.1
0
0
0
25
50
0
75
20
TA − Free-Air Temperature − °C
B. The A input is connected to ground during testing of the Y
outputs and to VCC during testing of the Z outputs.
Figure 7. Low-Level Output Voltage vs Free-Air Temperature
60
80
100
120
B. The A input is connected to ground during testing of the Y
outputs and to VCC during testing of the Z outputs.
Figure 8. Low-Level Output Voltage vs Low-Level Output
Current
5
5
No Load
No Load
TA = 25°C
4
4
VCC = 5.25 V
VO − Y Output Voltage − V
VO − Y Output Voltage − V
40
IOL − Low-Level Output Current − mA
VCC = 5 V
VCC = 4.75 V
3
2
1
TA = 70°C
TA = 0°C
3
TA = 25°C
2
1
0
0
0
1
2
3
0
1
2
3
VI − Data Input Voltage − V
VI − Data Input Voltage − V
Figure 9. Y Output Voltage vs Data Input Voltage
Figure 10. Y Output Voltage vs Data Input Voltage
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7 Parameter Measurement Information
Input A
(see Notes B
and C)
Test Point
3V
1.3 V
1.3 V
0V
VCC
tPHL
tPLH
180 Ω
VOH
1.5 V
Output Y
S1
From Output
Under Test
VOL
Skew
75 Ω
CL
(see Note A)
Skew
tPLH
tPHL
S2
VOH
1.5 V
Output Z
VOL
PROPAGATION DELAY TIMES AND SKEW
Enable G
(see Note D)
Enable G
TEST CIRCUIT
3V
1.5 V
1.5 V
See Note D
0V
tPLZ
tPZL
S1 Closed
S2 Closed
≈4.5 V
Waveform 1
(see Note E)
S1 Closed
S2 Open
≈1.5 V
1.5 V
VOL
0.5 V
tPZH
tPHZ
0.5 V
S1 Open
S2 Closed
Waveform 2
(see Note E)
1.5 V
VOH
≈1.5 V
≈0 V
S1 Closed
S2 Closed
ENABLE AND DISABLE TIME WAVEFORMS
NOTES: A.
B.
C.
D.
E.
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 15 ns, tf ≤ 6 ns.
When measuring propagation delay times and skew, switches S1 and S2 are open.
Each enable is tested separately.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
Figure 11. Test Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The AM26LS31x differential bus transmitter is a monolithic integrated circuit designed for unidirectional data
communication on transmission lines. It is designed for balanced transmission lines and meets ANSI Standard
EIA/TIA-422-B and ITU Recommendation V.11.
The AM26LS31x has a four 3-state differential line drivers that operate from a single 5-V power supply. The
driver also integrates active-high and active-low enables for precise device control.
The driver is designed to handle loads of a minimum of ±30 mA of sink or source current. The driver features
positive- and negative-current limiting for protection from line fault conditions.
8.2 Functional Block Diagram
4
G
G
12
2
1
1A
1Y
3
1Z
6
2Y
7
5
2A
2Z
10
3Y
9
11
3A
3Z
14
4Y
15
4A
13
4Z
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Complementary Output-Enable Inputs
The AM26LS31x can be configured using the G and G logic inputs to control transmitter outputs. Setting either G
to a logic HIGH or G to an logic LOW enables the transmitter outputs. If G is set to logic LOW and G is set to
logic HIGH, the transmitter outputs are disabled. See Table 1 for a complete truth table.
8.3.2 High Output Impedance in Power-Off Conditions
When the AM26LS31x transmitter outputs are disabled using G and G, the outputs are set to a high impedance
state.
8.3.3 Complementary Outputs
The AM26LS31x is the driver half of a pair of devices, with the AM26LS32 being the complementary receiver. TI
recommends using these devices together for optimal performance, but any RS-422 compliant receive must
ensure proper RS-422 communication and logic level translation.
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8.4 Device Functional Modes
Table 1 lists the functional modes of the AM26LS31.
Table 1. Function Table (1)
(Each Driver)
(1)
10
ENABLES
OUTPUTS
INPUT
A
G
G
Y
H
H
X
H
L
L
H
X
L
H
H
X
L
H
L
L
X
L
L
H
X
L
H
Z
Z
Z
H = high level, L = low level,
X = irrelevant,
Z = high impedance (off)
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
x
x
x
x
x
x
x
x
xxxxxxxxxxxxxx
x
x
When designing a system that uses drivers, receivers, and transceivers that comply with RS-422 or RS-485,
proper cable termination is essential for highly reliable applications with reduced reflections in the transmission
line. Because RS-422 allows only one driver on the bus, if termination is used, it is placed only at the end of the
cable near the last receiver. In general, RS-485 requires termination at both ends of the cable. Factors to
consider when determining the type of termination usually are performance requirements of the application and
the ever-present factor, cost. The different types of termination techniques discussed are unterminated lines,
parallel termination, AC termination, and multipoint termination. Laboratory waveforms for each termination
technique (except multipoint termination) illustrate the usefulness and robustness of RS-422 (and, indirectly, RS485). Similar results can be obtained if 485-compliant devices and termination techniques are used. For
laboratory experiments, 100 feet of 100-Ω, 24-AWG, twisted-pair cable (Bertek) was used. A single driver and
receiver, TI AM26LS31 and AM26LS32C, respectively, were tested at room temperature with a 5-V supply
voltage. Two plots per termination technique are shown. In each plot, the top waveform is the driver input and the
bottom waveform is the receiver output. To show voltage waveforms related to transmission-line reflections, the
first plot shows output waveforms from the driver at the start of the cable; the second plot shows input waveforms
to the receiver at the far end of the cable.
x
x
x xx
x xx
x
9.2 Typical Application
Servo Drive
Encoder
Interpolation
Electronics
A
Motion Controller
D
R
Encoder Phase A
D
R
Encoder Phase B
D
R
Encoder Index
D
R
Status
B
Z
Status
AM26LS31
AM26LS32
Copyright © 2016, Texas Instruments Incorporated
Figure 12. Encoder Application
Copyright © 1979–2018, Texas Instruments Incorporated
Product Folder Links: AM26LS31 AM26LS31M
Submit Documentation Feedback
11
AM26LS31, AM26LS31C, AM26LS31I, AM26LS31M
SLLS114L – JANUARY 1979 – REVISED OCTOBER 2018
www.ti.com
Typical Application (continued)
9.2.1 Design Requirements
This example requires the following:
• 5-V power source
• RS-485 bus operating at 10 Mbps or less
• Connector that ensures the correct polarity for port pins
9.2.2 Detailed Design Procedure
Place the device close to bus connector to keep traces (stub) short to prevent adding reflections to the bus line.
If desired, add external fail-safe biasing to ensure 200 mV on the A-B port, if the drive is in high impedance state
(see Failsafe in RS-485 data buses).
9.2.3 Application Curve
5
4
Voltage (V)
3
2
1
0
±1
±2
Y
A/B
±3
0
0.1
0.2
0.3
0.4
Time ( s)
0.5
C001
Figure 13. Differential 120-Ω Terminated Output Waveforms (Cat 5E Cable)
12
Submit Documentation Feedback
Copyright © 1979–2018, Texas Instruments Incorporated
Product Folder Links: AM26LS31 AM26LS31M
AM26LS31, AM26LS31C, AM26LS31I, AM26LS31M
www.ti.com
SLLS114L – JANUARY 1979 – REVISED OCTOBER 2018
10 Power Supply Recommendations
Place a 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can often propagate into analog circuitry through the power supply of the circuit. Bypass capacitors are
used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
11.2 Layout Example
VCC
Reduce logic
signal trace
where possible
16 VCC
1A 1
2
15
3
14
4
13
0.1uF
AM26LS31
GND
5
12
6
11
7
10
8
9
Figure 14. Layout Recommendation
Copyright © 1979–2018, Texas Instruments Incorporated
Product Folder Links: AM26LS31 AM26LS31M
Submit Documentation Feedback
13
AM26LS31, AM26LS31C, AM26LS31I, AM26LS31M
SLLS114L – JANUARY 1979 – REVISED OCTOBER 2018
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Failsafe in RS-485 data buses (SLYT080)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
AM26LS31
Click here
Click here
Click here
Click here
Click here
AM26LS31C
Click here
Click here
Click here
Click here
Click here
AM26LS31I
Click here
Click here
Click here
Click here
Click here
AM26LS31M
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
14
Submit Documentation Feedback
Copyright © 1979–2018, Texas Instruments Incorporated
Product Folder Links: AM26LS31 AM26LS31M
PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-7802301M2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59627802301M2A
AM26LS31
MFKB
5962-7802301MEA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-7802301ME
A
AM26LS31MJB
5962-7802301MFA
ACTIVE
CFP
W
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-7802301MF
A
AM26LS31MWB
5962-7802301Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
AM26LS31CD
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
AM26LS31C
AM26LS31CDBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
SA31C
AM26LS31CDBRE4
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
SA31C
AM26LS31CDE4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
AM26LS31C
AM26LS31CDG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
AM26LS31C
AM26LS31CDR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
AM26LS31C
AM26LS31CDRE4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
AM26LS31C
AM26LS31CDRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
AM26LS31C
AM26LS31CN
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
AM26LS31CN
AM26LS31CNSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
26LS31
AM26LS31INSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
26LS31
Addendum-Page 1
59627802301Q2A
AM26LS31M
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
22-Oct-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
AM26LS31MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59627802301M2A
AM26LS31
MFKB
AM26LS31MJB
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-7802301ME
A
AM26LS31MJB
AM26LS31MWB
ACTIVE
CFP
W
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-7802301MF
A
AM26LS31MWB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF AM26LS31, AM26LS31M :
• Catalog: AM26LS31
• Military: AM26LS31M
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
AM26LS31CDR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
AM26LS31CDR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
AM26LS31CDRG4
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
AM26LS31CDRG4
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
AM26LS31INSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
AM26LS31CDR
SOIC
D
16
2500
367.0
367.0
38.0
AM26LS31CDR
SOIC
D
16
2500
333.2
345.9
28.6
AM26LS31CDRG4
SOIC
D
16
2500
367.0
367.0
38.0
AM26LS31CDRG4
SOIC
D
16
2500
333.2
345.9
28.6
AM26LS31INSR
SO
NS
16
2000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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