Texas Instruments | TUSB1044 USB TYPE-C™ 10 Gbps Multi-Protocol Bi-Directional Linear Redriver (Rev. C) | Datasheet | Texas Instruments TUSB1044 USB TYPE-C™ 10 Gbps Multi-Protocol Bi-Directional Linear Redriver (Rev. C) Datasheet

Texas Instruments TUSB1044 USB TYPE-C™ 10 Gbps Multi-Protocol Bi-Directional Linear Redriver (Rev. C) Datasheet
Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
TUSB1044 USB TYPE-C™ 10 Gbps Multi-Protocol Bi-Directional Linear Redriver
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
Protocol Agnostic Reversible 4 Channel Linear
Redriver Supporting up to 10 Gbps
– USB Type-C with USB 3.1 Gen 2 and
DisplayPort 1.4 as Alternate Mode.
Supports Processors with USB 3.1 and
DisplayPort Mux Integrated for Type-C
Applications
Supports Signal Conditioning Inside Type-C Cable
Cross-Point Mux for SBU Signals
Linear Equalization up to 11 dB at 4.05 GHz
GPIO and I2C Control for Channel Direction and
Equalization
Advanced Power Management by Monitoring USB
Power States and Snooping DP Link Training
Configuration through GPIO or I2C
Hot-Plug Capable
Single 3.3 V Supply
Industrial Temperature: –40ºC to 85ºC
(TUSB1044I)
Commercial Temperature: 0ºC to 70ºC
(TUSB1044)
4 mm × 6 mm, 0.4 mm Pitch, 40-pin QFN
Package
Tablets
Notebooks
Desktops
Docking Stations
3 Description
The TUSB1044 is a USB Type-C Alt Mode redriver
switch supporting data rates up to 10 Gbps. This
protocol-agnostic linear redriver is capable of
supporting USB Type-C Alt Mode interfaces including
DisplayPort.
The TUSB1044 provides several levels of receive
linear equalization to compensate for inter-symbol
interference (ISI) due to cable and board trace loss.
Operates on a single 3.3 V supply and comes in a
commercial and industrial temperature range.
All four lanes of the TUSB1044 are reversible making
it a versatile signal conditioner that can be used in
many applications.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TUSB1044
WQFN (40)
4.00 mm x 6.00 mm
TUSB1044I
WQFN (40)
4.00 mm x 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
D+/-
TUSB1044
DRX2
UTX2
DTX2
UTX1
DTX1
URX1
DRX1
AUXp
SBU1
AUXn
SBU2
TUSB1044
Type-C Receptacle
USB/DP/
Custom
Source
URX2
FLIP 0 1 CTL
HPD
Control
CC1
USB PD
Controller
CC2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
1
1
1
2
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Switching Characteristics ........................................ 10
Timing Requirements .............................................. 11
Typical Characteristics ............................................ 15
Detailed Description ............................................ 18
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
19
20
21
7.5 Programming .......................................................... 34
7.6 Register Maps ........................................................ 36
8
Application and Implementation ........................ 45
8.1 Application Information............................................ 45
8.2 Typical Application ................................................. 45
8.3 System Examples .................................................. 49
9 Power Supply Recommendations...................... 56
10 Layout................................................................... 57
10.1 Layout Guidelines ................................................. 57
10.2 Layout Example .................................................... 58
11 Device and Documentation Support ................. 59
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
59
59
59
59
59
59
12 Mechanical, Packaging, and Orderable
Information ........................................................... 59
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2018) to Revision C
Page
•
Added pull-down indicator (PD) in the I/O column on SWAP, SLP_S0#, DIR0, DIR1, FLIP. CTL0 pins. ............................ 3
•
Added junction temperature of 105℃ for TUSB1044. ........................................................................................................... 6
•
Changed junction temperature from 105℃ to 125℃ for TUSB1044I ................................................................................... 6
•
Changed RPD_CTL1 From: Internal pull-down resistance for CTL1 To: Internal pull-down resistance for CTL1, CTL0,
DIR0, DIR1, FLIP, and SLP_S0#. .......................................................................................................................................... 7
•
Added RPD_SWAP parameter of 200kΩ..................................................................................................................................... 7
Changes from Revision A (February 2018) to Revision B
•
Page
Changed the Simplified Schematic......................................................................................................................................... 1
Changes from Original (February 2018) to Revision A
Page
•
Changed text in the Detailed Design Procedure From: "This AC-coupling capacitor should be no more than 220 nF."
To: This AC-coupling capacitor should be no smaller than 297 nF. A value of 330 nF is recommended." ......................... 46
•
Changed 220 nF to 330 nF on DRX2P, DRX2N and DRX1P, DRX1N in Figure 36 ........................................................... 47
2
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
5 Pin Configuration and Functions
DRX2p
DRX2n
DEQ0
DTX2p
DTX2n
UEQ0/A0
DTX1n
DTX1p
HPDIN
DRX1n
DRX1p
DEQ1
40
39
38
37
36
35
34
33
32
31
30
29
RNQ Package
40-Pin (WQFN)
Top View
VCC
1
28
VCC
UEQ1/A1
2
27
SBU1
CFG0
3
26
SBU2
CFG1
4
25
AUXn
24
AUXp
Thermal
Pad
21
FLIP/SCL
VCC
URX1p
URX1n
I2C_EN
UTX1p
UTX1n
VIO_SEL
UTX2n
UTX2p
DIR1
URX2n
URX2p
20
8
19
DIR0
18
CTL0/SDA
17
22
16
7
15
SLP_S0#
14
CTL1
13
23
12
6
11
VCC
10
5
9
SWAP
Not to scale
Pin Functions
PIN
NO.
NAME
I/O
P
DESCRIPTION
1
VCC
2
UEQ1/A1
4 Level I
This pin along with UEQ0 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1,
UTX2 receivers. In I2C Mode, this pin will also set TUSB1044 I2C address. Refer to Table 9.
3
CFG0
4 Level I
CFG0. This pin along with CFG1 will select VOD linearity range and DC gain for all the downstream and
upstream channels. Refer to Table 8 for VOD linearity range and DC gain options.
4
CFG1
4 Level I
CFG1. This pin along with CFG0 will set VOD linearity range and DC gain for all the downstream and
upstream channels. Refer to Table 8 for VOD linearity range and DC gain options.
5
SWAP
2 Level I
(PD)
This pin swaps all the channel directions and EQ settings of downstream facing and upstream facing data
path inputs.
0 – Do not swap channel directions and EQ settings (Default)
1. – Swap channel directions and EQ settings.
6
VCC
P
3.3 V Power Supply
3.3V Power Supply
7
SLP_S0#
2 Level I
(PD)
This pin when asserted low will disable Receiver Detect functionality. While this pin is low and TUSB1044
is in U2/U3, TUSB1044 will disable LOS and LFPS detection circuitry and RX termination for both
channels will remain enabled. If this pin is low and TTUSB1044 is in Disconnect state, the RX detect
functionality will be disabled and RX termination for both channels will be disabled.
0 – RX Detect disabled
1 – RX Detect enabled (Default)
8
DIR0
2 Level I
(PD)
This pin along with DIR1 sets the data path signal direction format. Refer to Table 4 for signal direction
formats.
0 - Source Side (DFP) Alt Mode format
1 - Sink Side (UFP) Alt Mode format
9
URX2p
Diff I/O
Differential positive input/output for upstream facing RX2 port.
10
URX2n
Diff I/O
Differential negative input/output for upstream facing RX2 port.
11
DIR1
2 Level I/O
(PD)
This pin along with DIR0 sets the data path signal direction format. Refer to Table 4 for signal direction
formats.
0 - DisplayPort Alt Mode format
1 - Custom Alt Mode format
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
3
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
Pin Functions (continued)
PIN
DESCRIPTION
NAME
12
UTX2p
Diff I/O
Differential positive input/output for upstream facing TX2 port.
13
UTX2n
Diff I/O
Differential negative input/output for upstream facing TX2 port.
4 Level I/O
This pin selects I/O voltage levels for the 2-level GPIO configuration pins and the I2C interface:
0 = 3.3-V configuration I/O voltage, 3.3-V I2C interface (Default)
R = 3.3-V configuration I/O voltage, 1.8-V I2C interface
F = 1.8-V configuration I/O voltage, 3.3-V I2C interface
1 = 1.8-V configuration I/O voltage, 1.8-V I2C interface.
14
VIO_SEL
15
UTX1n
Diff I/O
Differential negative input/output for upstream facing TX1 port.
16
UTX1p
Diff I/O
Differential positive input/output for upstream facing TX1 port.
I2C Programming or Pin Strap Programming Select.
0 = GPIO Mode, AUX Snoop Enabled (I2C disabled)
R = TI Test Mode (I2C enabled)
F = GPIO Mode, AUX Snoop Disabled (I2C disabled)
1 = I2C enabled.
17
I2C_EN
4 Level I
18
URX1n
Diff I/O
Differential negative input/output for upstream facing RX1 port.
19
URX1p
Diff I/O
Differential positive input/output for upstream facing RX1 port.
20
VCC
P
3.3V Power Supply
21
FLIP/SCL
2 Level I
(PD)
(Failsafe)
22
CTL0/SDA
2 Level I
(PD)
(Failsafe)
In GPIO mode, this is a USB3.1 Switch control pin, otherwise this pin is I2C data.
CTL1
2 Level I
(PD)
DP Alt mode Switch Control Pin. In GPIO mode, this pin will enable or disable DisplayPort functionality.
Otherwise DisplayPort functionality is enabled and disabled through I2C registers.
L = DisplayPort Disabled.
H = DisplayPort Enabled.
In I2C Mode, this pin is not used by TUSB1044.
23
24
4
I/O
NO.
AUXp
In GPIO mode, this is Flip control pin, otherwise this pin is I2C clock.
I/O,
CMOS
AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source or sink through an AC coupling
capacitor. In addition to AC coupling capacitor, this pin also requires a 100-kΩ resistor to GND between
the AC coupling capacitor and the AUXp pin if the TUSB1044 is used on the DisplayPort source side, or a
1-MΩ resistor to DP_PWR (3.3V) between the AC coupling capacitor and the AUXp pin if TUSB1044 is
used on the DisplayPort sink side. This pin along with AUXn is used by the TUSB1044 for AUX snooping
and is routed to SBU1/2 based on the orientation of the Type-C plug.
25
AUXn
I/O,
CMOS
AUXn. DisplayPort AUX I/O connected to the DisplayPort source or sink through an AC coupling
capacitor. In addition to AC coupling capacitor, this pin also requires a 100-kΩ resistor to DP_PWR (3.3V)
between the AC coupling capacitor and the AUXn pin if the TUSB1044 is used on the DisplayPort source
side, or a 1-MΩ resistor to GND between the AC coupling capacitor and the AUXn pin if TUSB1044 is
used on the DisplayPort sink side. This pin along with AUXp is used by the TUSB1044 for AUX snooping
and is routed to SBU1/2 based on the orientation of the Type-C plug.
26
SBU2
I/O,
CMOS
SBU2. When the TUSB1044 is used on the DisplayPort source side, this pin should be DC coupled to the
SBU2 pin of the Type-C receptacle. When the TUSB1044 is used on the DisplayPort sink side, this pin
should be DC coupled to the SBU1 pin of the Type-C receptacle. A 2-MΩ resistor to GND is also
recommended.
27
SBU1
I/O,
CMOS
SBU1. When the TTUSB1044 is used on the DisplayPort source side, this pin should be DC coupled to
the SBU1 pin of the Type-C receptacle. When the TUSB1044 is used on the DisplayPort sink side, this pin
should be DC coupled to the SBU2 pin of the Type-C receptacle. A 2-MΩ resistor to GND is also
recommended.
28
VCC
P
29
DEQ1
4 Level I
30
DRX1p
Diff I/O
Differential positive input/output for downstream facing RX1 port.
31
DRX1n
Diff I/O
Differential negative input/output for downstream facing RX1 port.
32
HPDIN
2 Level I
(PD)
33
DTX1p
Diff I/O
Differential positive input/output for downstream facing TX1 port.
34
DTX1n
Diff I/O
Differential negative input/output for downstream facing TX1 port.
35
UEQ0/A0
36
DTX2n
Diff I/O
Differential negative input/output for downstream facing TX2 port.
37
DTX2p
Diff I/O
Differential positive input/output for downstream facing TX2 port.
4 Level I
3.3V Power Supply
This pin along with DEQ0 sets the high-frequency equalizer gain for downstream facing DRX1, DRX2,
DTX1, DTX2 receivers.
This pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is low for greater
than 2ms, all DisplayPort lanes are disabled and AUX to SBU switch will remain closed. When HPDIN is
high, the enabled DisplayPort lanes from AUX snoop or registers will be active.
This pin along with UEQ1 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1,
UTX2 receivers. In I2C mode, this pin will also set TUSB1044 I2C address. Refer to Table 9.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
NAME
38
DEQ0
4 Level I
39
DRX2n
Diff I/O
Differential negative input/output for downstream facing RX2 port.
40
DRX2p
Diff I/O
Differential positive input/output for downstream facing RX2 port.
Thermal Pad
GND
This pin along with DEQ1 sets the high-frequency equalizer gain for downstream facing URX1, URX2,
UTX1, UTX2 receivers.
Ground
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
5
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
-0.3
4
V
±2.5
V
4
V
-0.3
4
V
-65
150
°C
VCC
Supply voltage range
VIN_DIFF
Differential voltage at differential input pins.
VIN_SE
Single-ended input voltage at differential input pins.
-0.5
VIN_CMOS
Input voltage at CMOS inputs
Tstg
Storage temperature
(1)
UNIT
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±5000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
VI2C
Supply that external resistors on SDA and SCL are pulled up to.
VPSN
Power supply noise on VCC
TA
TUSB1044 Ambient temperature
TA
TUSB1044i Ambient temperature
TJ
MIN
NOM
MAX
3
3.3
3.6
1.7
UNIT
V
3.6
V
100
mV
0
70
°C
-40
85
°C
TUSB1044 Junction temperature
105
°C
TUSB1044I Junction temperature
125
°C
6.4 Thermal Information
TUSB1044
THERMAL METRIC (1)
RNQ (WQFN)
UNIT
40 PINS
RθJA
Junction-to-ambient thermal resistance
37.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
20.7
°C/W
RθJB
Junction-to-board thermal resistance
9.5
°C/W
ΨJT
Junction-to-top characterization parameter
0.2
°C/W
ΨJB
Junction-to-board characterization parameter
9.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.3
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
6.5 Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power
Link in U0 with GEN2 data transmission;
EQ control pins = NC; K28.5 pattern at
Average power when configured for USB
10 Gbps; VID = 1000mVp-p; VOD
3.1 only mode.
Linearity = 900mVp-p; CTL1 = L; CTL0 =
H
297
mW
Link in U0 with GEN2 data transmission
and DP active; EQ control pins = NC;
Average power when configured for USB
K28.5 pattern at 10 Gbps; VID =
3.1 and 2 lane DP.
1000mVp-p; VOD Linearity = 900mVp-p;
CTL1 = H; CTL0 = H
578
mW
Link in U0 with GEN2 data transmission
and custom alt mode active; EQ control
Average power when configured for USB
pins = NC; K28.5 pattern at 10 Gbps; VID
3.1 and 2 channel custom alt mode.
= 1000mVp-p; VOD Linearity = 900mVpp; CTL1 = H; CTL0 = H
578
mW
Four active DP lanes; EQ control pins =
Average power when configured for Four NC; K28.5 pattern at 10 Gbps; VID =
DP lanes
1000mVp-p; VOD Linearity = 900mVp-p;
CTL1 = H; CTL0 = L
564
mW
PUSB-NC
Average power when configured for
USB3.1 only and nothing connected to
TXP/N pins.
No USB device connected; CTL1 = L;
CTL0 = H
2.5
mW
PUSB-
Average power when configured for
USB3.1 only and link in U2 or U3 state.
Link in U2 or U3 state; CTL1 = L; CTL0
=H
2
mW
Average power when device in
Shutdown
CTL1 = L; CTL0 = L; I2C_EN = 0;
0.65
mW
PUSBACTIVE
PUSB-DPACTIVE
PCUSTOMACTIVE
P4DPACTIVE
U2U3
PSHUTDO
WN
4-State CMOS Inputs(UEQ[1:0];DEQ[1:0], CFG[1:0], A[1:0], I2C_EN, VIO_SEL)
IIH
High-level input current
VCC = 3.6 V; VIN = 3.6 V
IIL
Low-level input current
VCC = 3.6 V; VIN = 0 V
Threshold 0 / R
VCC = 3.3 V
0.55
V
Threshold R/ Float
VCC = 3.3 V
1.65
V
Threshold Float / 1
VCC = 3.3 V
2.7
V
4-Level
VTH
20
80
µA
-160
-40
µA
RPU
Internal pull up resistance
35
kΩ
RPD
Internal pull-down resistance
95
kΩ
2-State CMOS Input (CTL0, CTL1, FLIP, HPDIN, SLP_S0#, SWAP, DIR[1:0]).
VIH-3.3V
High-level input voltage
VCC = 3.3V; VIO_SEL = "0" or "R";
2
3.6
V
VIL-3.3V
Low-level input voltage
VIH-1.8V
High-level input voltage
VCC = 3.3V; VIO_SEL = "0" or "R";
0
0.8
V
VCC = 3.3V; VIO_SEL = "F" or "1";
1.2
3.6
VIL-1.8V
Low-level input voltage
V
VCC = 3.3V; VIO_SEL = "F" or "1";
0
0.4
V
RPD_CTL1
Internal pull-down resistance for CTL1,
CTL0, DIR0, DIR1, FLIP, SLP_S0#.
500
kΩ
RPD_HPDI
Internal pull-down resistance for HPDIN
500
kΩ
Internal pull-down resistance for SWAP.
200
kΩ
N
RPD_SWA
P
IIH
High-level input current
VIN = 3.6 V
-25
25
µA
IIL
Low-level input current
VIN = GND, VCC = 3.6 V
-25
25
µA
I2C Control Pins SCL, SDA
VIH-3.3V
High-level input voltage
VCC = 3.3V; VIO_SEL = "0" or "R"; I2C
Mode Enabled;
2
3.6
V
VIL-3.3V
Low-level input voltage
VCC = 3.3V; VIO_SEL = "0" or "R"; I2C
Mode Enabled;
0
0.8
V
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
7
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH-1.8V
High-level input voltage
VCC = 3.3V; VIO_SEL = "F" or "1"; I2C
Mode Enabled;
1.2
3.6
V
VIL-1.8V
Low-level input voltage
VCC = 3.3V; VIO_SEL = "F" or "1"; I2C
Mode Enabled;
0
0.4
V
VOL
Low-level output voltage
I2C_EN ! = 0; IOL = 3 mA
0
0.4
IOL
Low-level output current
I2C_EN ! = 0; VOL = 0.4 V
20
II_I2C
Input current on SDA pin
0.1*VI2C < Input voltage < 3.3 V
Ci_I2C
Input capacitance
V
mA
-10
10
µA
0.5
5
pF
USB Gen 2 Differential Receiver (UTX1P/N, UTX2P/N, DRX1P/N, DRX2P/N)
VRX-DIFFPP
VRX-DC-
Input differential peak-peak voltage
swing dynamic range
AC-coupled differential peak-to-peak
signal measured post CTLE through a
reference channel
2000
Common-mode voltage bias in the
receiver (DC)
CM
RRX-DIFF-
IMP-DCPOS
VSIGNALDET-DIFFPP
VRX-IDLEDET-DIFFPP
VRX-LFPSDET-DIFFPP
V
Present after a GEN 2 device is detected
on TXP/TXN
72
120
Ω
Receiver DC Common Mode impedance
Present after a GEN 2 device is detected
on TXP/TXN
18
30
Ω
Common-mode input impedance with
termination disabled (DC)
Present when no GEN 2 device is
detected on TXP/TXN. Measured over
the range of 0-500 mV with respect to
GND.
25
Input Differential peak-to-peak Signal
Detect Assert Level
10 Gbps PRBS7 pattern; low loss input
channel;
80
mV
Input Differential peak-to-peak Signal
Detect De-assert Level
10 Gbps PRBS7 pattern; low loss input
channel;
60
mV
DC
ZRX-HIGH-
0
Differential input impedance (DC)
DC
RRX-CM-
mVpp
Low-frequency Periodic Signaling (LFPS)
Below the minimum is squelched.
Detect Threshold
kΩ
100
300
mV
0.3
pF
CRX
RX input capacitance to GND
At 5 GHz
RLRX-
Differential Return Loss
50 MHz – 2.5 GHz at 90 Ω
-13
dB
5 GHz at 90 Ω
-12
dB
-10.5
dB
10
dB
DIFF
RLRXDIFF
RLRX-CM
Common Mode Return Loss
50 MHz – 5 GHz at 90 Ω
EQSSP
Receiver equalization at maximum
setting
UEQ[1:0] and DEQ[1:0]. at 5 GHz.
USB Gen 2 Differential Transmitter (DTX1P/N, DTX2P/N, URX1P/N, URX2P/N)
VTX-DIFFPP
VTX-RCVDETECT
VTX-CMIDLEDELTA
VTX-DC-
Transmitter dynamic differential voltage
swing range.
Amount of voltage change allowed
during Receiver Detection
At 3.3 V
Transmitter idle common-mode voltage
change while in U2/U3 and not actively
transmitting LFPS
measured at the connector side of the
AC coupling caps with 50 ohm load
VTX-CMAC-PPACTIVE
VTX-IDLE-
8
-600
Common-mode voltage bias in the
transmitter (DC)
CM
DIFF-ACPP
1500
1.75
Tx AC Common-mode voltage active
Rx EQ setting matches input channel
loss; Max mismatch from Txp + Txn for
both time and amplitude; -40℃ to 85℃;
AC Electrical idle differential peak-topeak output voltage
At package pins
Submit Documentation Feedback
0
mVpp
600
mV
600
mV
2.3
V
100
mVpp
10
mV
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
VTX-IDLEDIFF-DC
DC Electrical idle differential output
voltage
RTX-DIFF
CAC-
TEST CONDITIONS
At package pins after low-pass filter to
remove AC component
MIN
TYP
MAX
UNIT
0
14
mV
Differential impedance of the driver
75
120
Ω
AC Coupling capacitor
75
265
nF
18
30
Ω
74
mA
COUPLING
RTX-CM
Common-mode impedance of the driver
Measured with respect to AC ground
over 0-500 mV
ITX-SHORT TX short circuit current
TX + /- shorted to GND
RLTX-DIFF Differential Return Loss
50 MHz – 2.5 GHz at 90 Ω
RLTX-DIFF Differential Return Loss
5 GHz at 90 Ω
RLTX-CM
Common Mode Return Loss
-13
dB
-10.5
dB
50 MHz – 5 GHz at 90 Ω
-10
dB
-30
dB
AC Characteristics
Crosstalk
Differential Cross Talk between TX and
RX signal Pairs
At 5 GHz
GLF
Low-frequency voltage gain for 0dB
setting.
At 100 MHz; 200 mVpp < VID < 2000
mVpp; 0 dB DC Gain;
CP1 dB-
Low-frequency 1-dB compression point
At 100 MHz; 200 mVpp < VID < 2000
mVpp; 1100mVpp linearity setting;
1100
mVpp
High-frequency 1-dB compression point
At 5 GHz; 200 mVpp < VID < 2000
mVpp; 1100mVpp linearity setting;
1200
mVpp
fLF
Low-frequency cutoff
200 mVpp < VID < 2000 mVpp
DJ
TX output deterministic jitter
200 mVpp < VID < 2000 mVpp, PRBS7,
10 Gbps
0.07
UIpp
DJ
TX output deterministic jitter
200 mVpp < VID < 2000 mVpp, PRBS7,
8.1 Gbps
0.07
UIpp
TJ
TX output total jitter
200 mVpp < VID < 2000 mVpp, PRBS7,
10 Gbps
0.11
UIpp
TJ
TX output total jitter
200 mVpp < VID < 2000 mVpp, PRBS7,
8.1 Gbps
0.11
UIpp
1500
V
LF-1100
CP1 dBHF-1100
-1
0
22
1
dB
50
kHz
DisplayPort Receiver (UTX1P/N, UTX2P/N, URX1P/N, URX2P/N)
VID_PP
Peak-to-peak input differential dynamic
voltage range
VIC
Input Common Mode Voltage
CAC
AC coupling capacitance
EQDP
Receiver Equalizer
DPEQ1, DPEQ0 at 4.05 GHz
dR
Data rate
HBR3
Rti
Input Termination resistance
0
75
V
265
9.5
80
100
nF
dB
8.1
Gbps
120
Ω
DisplayPort Transmitter (DTX1P/N, DTX2P/N, DRX1P/N, DRX2P/N)
VTX-
VOD dynamic range
1500
mV
DIFFPP
AUXP/N and SBU1/2
RON
Output ON resistance
VCC = 3.3 V; VI = 0 to 0.4 V for AUXP; VI
= 2.7 V to 3.6 V for AUXN
ΔRON
ON resistance mismatch within pair
ON resistance flatness (RON max –
RON_FLAT RON min) measured at identical VCC
and temperature
VAUXP_D
C_CM
VAUXN_D
C_CM
5
12
Ω
VCC = 3.3 V; VI = 0 to 0.4 V for AUXP; VI
= 2.7 V to 3.6 V for AUXN
1.3
Ω
VCC = 3.3 V; VI = 0 to 0.4 V for AUXP; VI
= 2.7 V to 3.6 V for AUXN
2
Ω
AUX Channel DC common mode voltage
VCC = 3.3 V
for AUXP and SBU1.
0
0.4
V
AUX Channel DC common mode voltage
VCC = 3.3 V
for AUXN and SBU2
2.7
3.6
V
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
9
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USB 3.1
tIDLEEntry
Delay from U0 to electrical idle
tIDLEExit_U U1 exist time: break in electrical idle to
the transmission of LFPS
1
Refer to Figure 4
0.16
ns
Refer to Figure 4
0.16
ns
5
µs
tIDLEExit_U U2/U3 exit time: break in electrical idle to
transmission of LFPS
2U3
tRXDET_IN
RX detect interval while in Disconnect
12
ms
TVL
tIDLEExit_D
Disconnect Exit Time
12
ms
0.5
ms
ISC
tExit_SHTD
Shutdown Exit Time
CTL0 = Vcc/2 to U2U3
Differential Propagation Delay
Refer to Figure 3
N
tDIFF_DLY
tPWRUPAC Time when Vcc reaches 70% to device
active
TIVE
tR/F
Output Rise/Fall Time
20%-80% of differential voltage
measured 1.7 inch from the output pin;
Input signal rise/fall faster than 35ps;
Refer to Figure 5
tRF-MM
Output Rise/Fall time mismatch
20%-80% of differential voltage
measured 1.7 inch from the output pin
300
ps
1
ms
35
ps
2.6
ps
AUXP/N and SBU1/2
tAUX_PD
Switch propagation delay
Refer to Figure 3
1050
ps
tAUX_SW_
Switching time CTL1 to switch OFF.
Refer to Figure 7
500
ns
Switching time CTL1 to switch ON
Refer to Figure 6
500
ns
100
ps
OFF
tAUX_SW_
ON
tAUX_INTR
Intra-pair output skew
A
10
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
6.7 Timing Requirements
MIN
NOM
MAX
UNIT
1
MHz
I2C Timing
fSCL
I2C clock frequency
tBUF
Bus free time between START and STOP conditions
tHDSTA
Hold time after repeated START condition. After this period, the first clock
pulse is generated
tLOW
0.5
µs
0.26
µs
Low period of the I2C clock
0.5
µs
tHIGH
High period of the I2C clock
0.26
µs
tSUSTA
Setup time for a repeated START condition
0.26
µs
tHDDAT
Data hold time
0
µs
tSUDAT
Data setup time
50
tR
Rise time of both SDA and SCL signals
tF
Fall time of both SDA and SCL signals
tSUSTO
Setup time for STOP condition
CBUS
Capacitive load for each bus line
ns
20 ×
(VI2C/5.5
V)
120
ns
120
ns
100
pF
0.26
µs
HPDIN and CTL1
tCTL1_DEBO
UNCE
CTL1 and HPDIN debounce time when transitioning from H to L. DP lanes
will be disabled if low is greater than min value.
2.5
ms
4
µs
USB3.1 and DisplayPort mode transition requirement GPIO mode
tGP_USB_4D Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode
to 4-Lane DisplayPort mode or vice versa. Refer to Figure 2
P
Power-on timings
td_pg
VCC(MIN) to Internal power good asserted high. Refer to Figure 8
tcfg_su
CFG pins setup. Refer to Figure 8
tcfg_hd
CFG pin hold. Refer to Figure 8
tctl_db
CTL[1:0] and FLIP pin debounce. Refer to Figure 8
tVCC_RAMP
VCC supply ramp requirement. Refer to Figure 8
500
µs
350
µs
10
µs
0.1
16
ms
100
ms
70%
SDA
30%
tLOW
tBUF
tR
tHIGH
tHDSTA
tF
70%
SCL
P
30%
S
S
tHDDAT
tHDSTA
tSUDAT
P
tSUSTA
tSUSTO
Figure 1. I2C Timing Diagram Definitions
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
11
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
4us
(min)
CTL1 pin
CTL0 pin
Figure 2. USB3.1 to 4-Lane DisplayPort in GPIO Mode
IN
TDIFF_DLY
TDIFF_DLY
OUT
Figure 3. Propagation Delay
IN+
VRX-LFPS-DET-DIFF-PP
Vcm
INTIDLEExit
TIDLEEntry
OUT+
Vcm
OUT-
Figure 4. Electrical Idle Mode Exit and Entry Delay
12
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
80%
20%
tr
tf
Figure 5. Output Rise and Fall Times
CTL1
VIH(min)
tAUX-SW-ON
SBU2
Copyright © 2017, Texas Instruments Incorporated
Figure 6. AUX to SBU Switch ON Timing Diagram
tAUX-SW-OFF
CTL1
VIL(max)
SBU2
Copyright © 2017, Texas Instruments Incorporated
Figure 7. AUX to SBU Switch OFF Timing Diagram
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
13
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
Tctl_db
In I2C mode
DISABLED
In GPIO mode
DISABLED
Mode of operation
determined by value of
FLIPSEL bit and CTLSEL[1:0]
bits at offset 0x0A. Default
is USB3.1-only no Flip.
USB3.1-only
FLIP = 0
USB3.1-only
FLIP = 0
If ((CTL[1:0] == 2'b00 | CTL[1:0] == 2'b01) & FLIP == 0 ) {
USB3.1-only no FLIP;
} ELSEIF ((CTL[1:0] == 2'b00 | CTL[1:0] == 2'b01) & FLIP == 1 ) {
USB3.1-only with FLIP;
} ELSEIF (CTL[1:0] == 2'b10 & FLIP == 0) {
4-Lane DP no FLIP;
} ELSEIF (CTL[1:0] == 2'b10 & FLIP == 1) {
4-Lane DP with FLIP;
} ELSEIF (CTL[1:0] == 2'b11 & FLIP == 0) {
2-Lane DP USB3.1 no FLIP;
}ELSE {
2-lane DP USB3.1 with FLIP;
};
CTL[1:0] pins
FLIP pin
VCC (min)
VCC
Td_pg
Internal
Power
Good
Tcfg_su
Tcfg_hd
CFG pins
Figure 8. Power-Up Timing Diagram
14
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
6.8 Typical Characteristics
0
0
-5
-5
-10
-10
SDD22 (dB)
SDD11 (dB)
-15
-20
-25
-30
-15
-20
-25
-35
-30
-40
-35
-45
0
5
10
Frequency (GHz)
15
0
20
Figure 9. Input Return Loss Performance of the Downstream
Ports
15
20
D002
0
-5
-5
-10
-10
-15
-15
SDD22 (dB)
SDD11 (dB)
10
Frequency (GHz)
Figure 10. Output Return Loss Performance of the
Downstream Ports
0
-20
-25
-20
-25
-30
-30
-35
-35
-40
-40
-45
-45
0
5
10
Frequency (GHz)
15
20
0
1400
1600
Differential Output Voltage (mVpp)
1800
1200
1000
EQ0
EQ2
EQ4
EQ6
EQ8
EQ10
EQ12
EQ15
600
400
200
500
1000
1500
Differential Input Voltage (mVpp)
15
20
D004
1400
1200
1000
EQ 0
EQ 2
EQ 4
EQ 6
EQ 8
EQ 10
EQ 12
EQ 15
800
600
400
200
0
0
0
10
Frequency (GHz)
Figure 12. Output Return Loss Performance of the Upstream
Ports
1600
800
5
D003
Figure 11. Input Return Loss Performance of the Upstream
Ports
Differential Output Voltage (mVpp)
5
D001
2000
D001
5 GHz
Figure 13. Downstream-to-Upstream Linearity Performance
at 5 GHz
0
200
400
600 800 1000 1200 1400 1600 1800 2000
Differential Input Voltage (mVpp)
D008
4.05 GHz
Figure 14. Downstream-to-Upstream Linearity Performance
at 4.05 GHz
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
15
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
1600
1600
1400
1400
Differential Output Voltage (mVpp)
Differential Output Voltage (mVpp)
Typical Characteristics (continued)
1200
1000
800
600
400
200
EQ 0
1200
1000
800
EQ0
EQ2
EQ4
EQ6
EQ8
EQ10
EQ12
EQ15
600
400
200
0
0
200
400
0
600 800 1000 1200 1400 1600 1800 2000
Differential Input Voltage (mVpp)
D009
0
500
1000
1500
Differential Input Voltage (mVpp)
100 MHz
2000
D002
5 GHz
Figure 15. Downstream-to-Upstream Linearity Performance
at 100 MHz
Figure 16. Upstream-to-Downstream Linearity Performance
at 5 GHz
1600
Differential Output Voltage (mVpp)
1600
1400
Y Axis Title (Unit)
1200
1000
800
EQ 0
EQ 2
EQ 4
EQ 6
EQ 8
EQ 10
EQ 12
EQ 15
600
400
200
1400
1200
1000
800
600
400
200
EQ 0
0
0
0
200
400
600
0
800 1000 1200 1400 1600 1800 2000
200
400
D011
4.05 GHz
100 MHz
Figure 17. Upstream-to-Downstream Linearity Performance
at 4.05 GHz
Source:
Channel:
Settings:
Data Rate: 10 Gbps; Data Pattern: PRBS7;
Swing: 1 Vpp
Upstream-to-Downstream, 12 in 6 mil Input
PCB Channel
EQ Setting: TBD; DC Gain Setting: 0 dB;
Linear Range Setting: 1100 mVpp
Figure 19. Output Eye-Pattern Performance at 10 Gbps
16
600 800 1000 1200 1400 1600 1800 2000
Differential Input Voltage (mVpp)
D012
Figure 18. Upstream-to-Downstream Linearity Performance
at 100 MHz
Source:
Channel:
Settings:
Data Rate: 8.1 Gbps; Data Pattern: PRBS7;
Swing: 1 Vpp
Upstream-to-Downstream, 12 in 6 mil Input
PCB Channel
EQ Setting: 7; DC Gain Setting: 0 dB;
Linear Range Setting: 1100 mVpp
Figure 20. Output Eye-Pattern Performance at 8.1 Gbps
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
Typical Characteristics (continued)
15
SDD21 (dB)
10
EQ0
EQ1
EQ2
EQ3
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
5
0
-5
-10
0.01
0.1
1
10
Frequency (GHz)
20
D005
Figure 21. Upstream-to-Downstream EQ Settings Curves
15
SDD21 (dB)
10
EQ0
EQ1
EQ2
EQ3
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
5
0
-5
-10
0.01
0.1
1
10
Frequency (GHz)
20
D006
Figure 22. Downstream-to-Upstream EQ Settings Curves
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
17
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
7 Detailed Description
7.1 Overview
The TUSB1044 is a USB Type-C Alt Mode redriver switch supporting data rates up to 8.1 Gbps. This device
implements 5th generation USB redriver technology. The device is used for configurations C, D, E, and F from
the VESA DisplayPort Alt Mode on USB Type-C Standard. It can also be configured to support custom USB
Type-C alternate modes.
The TUSB1044 provides several levels of receive equalization to compensate for cable and board trace loss due
to inter-symbol interference (ISI) when USB 3.1 Gen 2 or DisplayPort (or other Alt modes) signals travel across a
PCB or cable. This device requires a 3.3V power supply. It comes for both commercial temperature range and
industrial temperature range operation.
For host (source) or device (sink) applications, the TUSB1044 enables the system to pass both transmitter
compliance and receiver jitter tolerance tests for USB 3.1 Gen 2 and DisplayPort version 1.4 HBR3. The re-driver
recovers incoming data by applying equalization that compensates for channel loss, and drives out signals with a
high differential voltage. Each channel has a receiver equalizer with selectable gain settings. Equalization control
for upstream and downstream facing ports can be set using UEQ[1:0], and DEQ[1:0] pins respectively or through
the I2C interface.
Moreover, the CFG[1:0] or the equivalent I2C registers provide the ability to control the EQ DC gain and the
voltage linearity range for all the channels (Refer to Table 8). This flexible control makes it easy to set up the
device to pass various standard compliance requirements.
The TUSB1044 advanced state machine makes it transparent to hosts and devices. After power up, the
TUSB1044. periodically performs receiver detection on the TX pairs. If it detects a USB 3.1 receiver, the RX
termination is enabled, and the TUSB1044 is ready to re-drive.
The TUSB1044 provides extremely flexible data path signal direction control using the CTL[1:0], FLIP, DIR[1:0],
and SWAP pins or through the I2C interface. Refer to Table 4 for detailed information on the input to output
signal pin mapping.
The device ultra-low-power architecture operates at a 3.3 V power supply and achieves enhanced performance.
The automatic LFPS De-Emphasis control further enables the system to be USB 3.1 compliant.
18
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
7.2 Functional Block Diagram
EQ
Driver
Term
Detect
Term
DRX2EQ_SEL
URX2EQ_SEL
Driver
EQ
EQ
DRX2p
Term
Detect
Term
URX2p
CHANNEL 0
URX2n
DRX2n
CHANNEL 0
EQ
Driver
Term
Detect
Term
DTX2EQ_SEL
UTX2EQ_SEL
Driver
EQ
EQ
DTX2p
Term
Detect
CHANNEL 1
Term
UTX2p
UTX2n
DTX2n
CHANNEL 1
EQ
Driver
Term
Detect
Term
DTX1EQ_SEL
UTX1EQ_SEL
UTX1p
Driver
EQ
EQ
DTX1n
Term
Detect
Term
UTX1n
CHANNEL 2
DTX1p
CHANNEL 2
EQ
Driver
Term
Detect
Term
DRX1EQ_SEL
URX1EQ_SEL
Driver
EQ
EQ
URX1p
DRX1n
Term
Detect
Term
CHANNEL 3
URX1n
UTX[2:1]EQ_SEL
DTX[2:1]EQ_SEL
URX[2:1]EQ_SEL
DRX[2:1]EQ_SEL
UEQ1/A1
UEQ0/A0
I2C_EN
FLIP/SCL
CTL0/SDA
CTL1
CHANNEL 3
DRX1p
DEQ[1:0]
SWAP
I2C
Slave
FSM, Control Logic &
Registers
DIR[1:0]
SLP_S0#
VIO_SEL
CFG[1:0]
AUX
RX
M
U
X
AUXp
AUXn
VCC
SBU1
SBU2
VREG
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
19
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
7.3 Feature Description
7.3.1 USB 3.1
The TUSB1044 supports USB 3.1 data rates up to 10 Gbps. The TUSB1044 supports all the USB defined power
states (U0, U1, U2, and U3). Because the TUSB1044 is a linear redriver, it can’t decode USB3.1 physical layer
traffic. The TUSB1044 monitors the actual physical layer conditions like receiver termination, electrical idle,
LFPS, and SuperSpeed signaling rate to determine the USB power state of the USB3.1 interface.
The TUSB1044 features an intelligent low frequency periodic signaling (LFPS) detector. The LFPS detector
automatically senses the low frequency signals and disables receiver equalization functionality. When not
receiving LFPS, the TUSB1044 enables receiver equalization based on the UEQ[1:0] and DEQ[1:0] pins or
values programmed into UEQ[3:0]_SEL, and DEQ[3:0]_SEL registers.
7.3.2 DisplayPort
The TUSB1044 supports up to 4 DisplayPort lanes at data rates up to 8.1 Gbps (HBR3). The TUSB1044, when
configured in DisplayPort mode, monitors the native AUX traffic as it traverses between DisplayPort source and
DisplayPort sink. For the purposes of reducing power, the TUSB1044 manages the number of active DisplayPort
lanes based on the content of the AUX transactions. The TUSB1044 snoops native AUX writes to DisplayPort
sink’s DPCD registers 00101h (LANE_COUNT_SET) and 00600h (SET_POWER_STATE). TUSB1044 disable or
enable lanes based on value written to LANE_COUNT_SET. The TUSB1044 disables all lanes when
SET_POWER_STATE is in the D3. Otherwise, active lanes are based on value of LANE_COUNT_SET.
DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE
register. Once AUX snoop is disabled, management of TUSB1044 DisplayPort lanes are controlled through
various configuration registers.
7.3.3 4-level Inputs
The TUSB1044 has (I2C_EN, UEQ[1:0], DEQ[1:0], CFG[1:0], and A[1:0]) 4-level inputs pins that are used to
control the equalization gain, voltage linearity range, and place TUSB1044 into different modes of operation.
These 4-level inputs utilize a resistor divider to help set the 4 valid levels and provide a wider range of control
settings. There is an internal pull-up and a pull-down resistors. These resistors, together with the external resistor
connection combine to achieve the desired voltage level.
Table 1. 4-Level Control Pin Settings
LEVEL
SETTINGS
0
Option 1: Tie 1 KΩ 5% to GND.
Option 2: Tie directly to GND.
R
Tie 20 KΩ 5% to GND.
F
Float (leave pin open)
1
Option 1: Tie 1 KΩ 5%to VCC.
Option 2: Tie directly to VCC.
NOTE
All four-level inputs are latched on rising edge of internal reset. After Tcfg_hd, the internal
pull-up and pull-down resistors will be isolated in order to save power.
7.3.4 Receiver Linear Equalization
The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in
the system. The receiver overcomes these losses by attenuating the low frequency components of the signals
with respect to the high frequency components. The proper gain setting should be selected to match the channel
insertion loss. Two 4-level input pins enable up to 16 possible equalization settings. The upstream path, and the
downstream path each have their own two 4-level inputs for equalization settings; UEQ[1:0] and DEQ[1:0]
respectively. The TUSB1044 also provides the flexibility of adjusting equalization settings through I2C registers
URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL for each individual channel and
for each direction (upstream or downstream) .
20
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
7.4 Device Functional Modes
7.4.1 Device Configuration in GPIO mode
The TUSB1044 is in GPIO configuration when I2C_EN = “0” or I2C_EN = "F". The TUSB1044 supports
operational combinations with USB and two different Type-C Alternate Modes. One combination includes USB
and Alternate Mode DisplayPort, and the other combination includes USB and custom Alternate Mode. For each
operational combination the data path directions can be further set using the DIR[1:0] pins or through I2C to
enable the device to operate in the source or sink sides. Please refer to Table 2 for all the configuration of all the
operational modes.
When the device is set to operate in a USB and Alternate Mode DisplayPort the following configurations can be
further set: USB3.1 only, 2 DisplayPort lanes + USB3.1, or 4 DisplayPort lanes (no USB3.1). The CTL1 pin
controls whether DisplayPort mode is enabled. The combination of CTL1 and CTL0 selects between USB3.1
only, 2 lanes of DisplayPort, or 4-lanes of DisplayPort as detailed in Table 2. The AUXP/N to SBU1/2 mapping is
controlled based on Table 3..
When the device is set to operate in a USB and custom Alternate Mode, the following configurations can be
further set: USB3.1 only, 2 Channels of custom Alternate Mode + USB3.1, or 4 Channels of custom Alternate
Mode (no USB3.1). The CTL1 pin controls whether custom Alternate Mode is enabled. The combination of CTL1
and CTL0 selects between USB3.1 only, 2 channels of custom Alternate Mode, or 4 channels of custom
Alternate Mode as detailed in Table 2. The AUXP/N to SBU1/2 mapping is controlled based on Table 3.
Further data path direction control can be achieved using the SWAP pin. When set high, the SWAP pin reverses
the data path direction on all the channels and swaps the equalization settings of the upstream and downstream
facing input ports. This pin may be found useful in active cable application with TUSB1044 installed on only one
end. The SWAP pin can be set based on which cable end is plugged to the source or sink side receptacle
After power-up (VCC from 0 V to 3.3 V), the TUSB1044 will default to USB3.1 mode. The USB PD controller,
upon detecting no device attached to Type-C port or USB3.1 operation not required by attached device, must
take TUSB1044 out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.
Table 2. GPIO Configuration Control
DIR1
PIN
DIR0
PIN
CTL1
PIN
CTL0
PIN
FLIP
PIN
TUSB1044 CONFIGURATION
VESA DisplayPort ALT
MODE
DFP_D Configuration
USB + DisplayPort Alternate Mode (Source Side)
L
L
L
L
L
Power Down
—
L
L
L
L
H
Power Down
—
L
L
L
H
L
One Port USB 3.1 - No Flip
—
L
L
L
H
H
One Port USB 3.1 – With Flip
—
L
L
H
L
L
4 Lane DP - No Flip
C and E
L
L
H
L
H
4 Lane DP – with Flip
C and E
L
L
H
H
L
One Port USB 3.1 + 2 Lane DP- No
Flip
D and F
L
L
H
H
H
One Port USB 3.1 + 2 Lane DP– with
Flip
D and F
USB + DisplayPort Alternate Mode (Sink Side)
L
H
L
L
L
Power Down
–
L
H
L
L
H
Power Down
–
L
H
L
H
L
One Port USB 3.1 - No Flip
–
L
H
L
H
H
One Port USB 3.1 – With Flip
–
L
H
H
L
L
4 Lane DP - No Flip
C and E
L
H
H
L
H
4 Lane DP – With Flip
C and E
D and F
D and F
L
H
H
H
L
One Port USB 3.1 + 2 Lane DP- No
Flip
L
H
H
H
H
One Port USB 3.1 + 2 Lane DP– With
Flip
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
21
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
Device Functional Modes (continued)
Table 2. GPIO Configuration Control (continued)
DIR1
PIN
DIR0
PIN
CTL1
PIN
CTL0
PIN
FLIP
PIN
TUSB1044 CONFIGURATION
VESA DisplayPort ALT
MODE
DFP_D Configuration
USB + Custom Alternate Mode (Source Side)
H
L
L
L
L
Power Down
–
H
L
L
L
H
Power Down
–
H
L
L
H
L
One Port USB 3.1 - No Flip
–
H
L
L
H
H
One Port USB 3.1 – With Flip
–
H
L
H
L
L
4 Channel Custom Alt Mode - No Flip
–
H
L
H
L
H
4 Channel Custom Alt Mode– With
Flip
–
H
L
H
H
L
One Port USB 3.1 + 2 Channel
Custom Alt Mode- No Flip
–
H
L
H
H
H
One Port USB 3.1 + 2 Channel
Custom Alt Mode – With Flip
–
L
L
Power Down
-
USB + Custom Alternate Mode (Sink Side)
H
H
L
H
H
L
L
H
Power Down
-
H
H
L
H
L
One Port USB 3.1 - No Flip
-
H
H
L
H
H
One Port USB 3.1 – With Flip
-
H
H
H
L
L
4 Channel Custom Alt Mode - No Flip
-
H
H
H
L
H
4 Channel Custom Alt Mode– With
Flip
H
H
H
H
L
One Port USB 3.1 + 2 Channel
Custom Alt Mode- No Flip
-
H
H
H
H
H
One Port USB 3.1 + 2 Channel
Custom Alt Mode – With Flip
-
Table 3. GPIO AUXP/N to SBU1/2 Mapping
CTL1 pin
22
FLIP pin
Mapping
H
L
AUXP -> SBU1
AUXN -> SBU2
H
H
AUXP -> SBU2
AUXN -> SBU1
L > 2ms
X
Open
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
Table 4 details the TUSB1044 mux routing. This table is valid for GPIO Mode. This table is also valid for I2C
mode if CH_SWAP_SEL = 4'b0000 or 4'b1111.
Table 4. INPUT to OUTPUT Mapping
SWAP = L
From
DIR1
PIN
DIR0
PIN
CTL1
PIN
CTL0
PIN
FLIP
PIN
Rx EQ
Control
PINS
From
SWAP = H
To
From
From
To
Input
PIN
Output
PIN
Rx EQ
Control
PINS
Input
PIN
Output
PIN
USB + DisplayPort Alternate Mode (Source Side)
L
L
L
L
L
NA
NA
NA
NA
NA
NA
L
L
L
L
H
NA
NA
NA
NA
NA
NA
DEQ[1:0]
DRX1P
URX1P
(SSRXP)
DEQ[1:0]
URX1P
(SSTXP)
DRX1P
DEQ[1:0]
DRX1N
URX1N
(SSRXN)
DEQ[1:0]
URX1N
(SSTXN)
DRX1N
UEQ[1:0]
UTX1P
(SSTXP)
DTX1P
UEQ[1:0]
DTX1P
UTX1P
(SSRXP)
UEQ[1:0]
UTX1N
(SSTXN)
DTX1N
UEQ[1:0]
DTX1N
UTX1N
(SSRXN)
DEQ[1:0]
DRX2P
URX2P
(SSRXP)
DEQ[1:0]
URX2P
(SSTXP)
DRX2P
DEQ[1:0]
DRX2N
URX2N
(SSRXN)
DEQ[1:0]
URX2N
(SSTXN)
DRX2N
UEQ[1:0]
UTX2P
(SSTXP)
DTX2P
UEQ[1:0]
DTX2P
UTX2P
(SSRXP)
UEQ[1:0]
UTX2N
(SSTXN)
DTX2N
UEQ[1:0]
DTX2N
UTX2N
(SSRXN)
UEQ[1:0]
URX2P
(DP0P)
DRX2P
UEQ[1:0]
DRX2P
URX2P
(DP0P)
UEQ[1:0]
URX2N
(DP0N)
DRX2N
UEQ[1:0]
DRX2N
URX2N
(DP0N)
UEQ[1:0]
UTX2P
(DP1P)
DTX2P
UEQ[1:0]
DTX2P
UTX2P (DP1P)
UEQ[1:0]
UTX2N
(DP1N)
DTX2N
UEQ[1:0]
DTX2N
UTX2N
(DP1N)
UEQ[1:0]
UTX1P
(DP2P)
DTX1P
UEQ[1:0]
DTX1P
UTX1P (DP2P)
UEQ[1:0]
UTX1N
(DP2N)
DTX1N
UEQ[1:0]
DTX1N
UTX1N
(DP2N)
UEQ[1:0]
URX1P
(DP3P)
DRX1P
UEQ[1:0]
DRX1P
URX1P
(DP3P)
UEQ[1:0]
URX1N
(DP3N)
DRX1N
UEQ[1:0]
DRX1N
URX1N
(DP3N)
L
L
L
L
L
L
L
L
H
H
H
L
L
H
L
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
23
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
Table 4. INPUT to OUTPUT Mapping (continued)
SWAP = L
DIR1
PIN
L
L
L
DIR0
PIN
L
L
L
CTL1
PIN
H
H
H
CTL0
PIN
L
H
H
FLIP
PIN
SWAP = H
From
From
To
From
From
To
Rx EQ
Control
PINS
Input
PIN
Output
PIN
Rx EQ
Control
PINS
Input
PIN
Output
PIN
UEQ[1:0]
URX1P
(DP0P)
DRX1P
UEQ[1:0]
DRX1P
URX1P
(DP0P)
UEQ[1:0]
URX1N
(DP0N)
DRX1N
UEQ[1:0]
DRX1N
URX1N
(DP0N)
UEQ[1:0]
UTX1P
(DP1P)
DTX1P
UEQ[1:0]
DTX1P
UTX1P (DP1P)
UEQ[1:0]
UTX1N
(DP1N)
DTX1N
UEQ[1:0]
DTX1N
UTX1N
(DP1N)
UEQ[1:0]
UTX2P
(DP2P)
DTX2P
UEQ[1:0]
DTX2P
UTX2P (DP2P)
UEQ[1:0]
UTX2N
(DP2N)
DTX2N
UEQ[1:0]
DTX2N
UTX2N
(DP2N)
UEQ[1:0]
URX2P
(DP3P)
DRX2P
UEQ[1:0]
DRX2P
URX2P
(DP3P)
UEQ[1:0]
URX2N
(DP3N)
DRX2N
UEQ[1:0]
DRX2N
URX2N
(DP3N)
DEQ[1:0]
DRX1P
URX1P
(SSRXP)
DEQ[1:0]
URX1P
(SSTXP)
DRX1P
DEQ[1:0]
DRX1N
URX1N
(SSRXN)
DEQ[1:0]
URX1N
(SSTXN)
DRX1N
UEQ[1:0]
UTX1P
(SSTXP)
DTX1P
UEQ[1:0]
DTX1P
UTX1P
(SSRXP)
UEQ[1:0]
UTX1N
(SSTXN)
DTX1N
UEQ[1:0]
DTX1N
UTX1N
(SSRXN)
UEQ[1:0]
URX2P
(DP0P)
DRX2P
UEQ[1:0]
DRX2P
URX2P
(DP0P)
UEQ[1:0]
URX2N
(DP0N)
DRX2N
UEQ[1:0]
DRX2N
URX2N
(DP0N)
UEQ[1:0]
UTX2P
(DP1P)
DTX2P
UEQ[1:0]
DTX2P
UTX2P (DP1P)
UEQ[1:0]
UTX2N
(DP1N)
DTX2N
UEQ[1:0]
DTX2N
UTX2N
(DP1N)
DEQ[1:0]
DRX2P
URX2P
(SSRXP)
DEQ[1:0]
URX2P
(SSTXP)
DRX2P
DEQ[1:0]
DRX2N
URX2N
(SSRXN)
DEQ[1:0]
URX2N
(SSTXN)
DRX2N
UEQ[1:0]
UTX2P
(SSTXP)
DTX2P
UEQ[1:0]
DTX2P
UTX2P
(SSRXP)
UEQ[1:0]
UTX2N
(SSTXN)
DTX2N
UEQ[1:0]
DTX2N
UTX2N
(SSRXN)
UEQ[1:0]
URX1P
(DP0P)
DRX1P
UEQ[1:0]
DRX1P
URX1P
(DP0P)
UEQ[1:0]
URX1N
(DP0N)
DRX1N
UEQ[1:0]
DRX1N
URX1N
(DP0N)
UEQ[1:0]
UTX1P
(DP1P)
DTX1P
UEQ[1:0]
DTX1P
UTX1P (DP1P)
UEQ[1:0]
UTX1N
(DP1N)
DTX1N
UEQ[1:0]
DTX1N
UTX1N
(DP1N)
H
L
H
USB + DisplayPort Alternate Mode (Sink Side)
24
L
H
L
L
L
NA
NA
NA
NA
NA
NA
L
H
L
L
H
NA
NA
NA
NA
NA
NA
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
Table 4. INPUT to OUTPUT Mapping (continued)
SWAP = L
DIR1
PIN
L
L
L
L
DIR0
PIN
H
H
H
H
CTL1
PIN
L
L
H
H
CTL0
PIN
H
H
L
L
FLIP
PIN
SWAP = H
From
From
To
From
From
To
Rx EQ
Control
PINS
Input
PIN
Output
PIN
Rx EQ
Control
PINS
Input
PIN
Output
PIN
UEQ[1:0]
UTX2P
DTX2P
(SSRXP)
UEQ[1:0]
DTX2P
(SSTXP)
UTX2P
UEQ[1:0]
UTX2N
DTX2N
(SSRXN)
UEQ[1:0]
DTX2N
(SSTXN)
UTX2N
DEQ[1:0]
DRX2P
(SSTXP)
URX2P
DEQ[1:0]
URX2P
DRX2P
(SSRXP)
DEQ[1:0]
DRX2N
(SSTXN)
URX2N
DEQ[1:0]
URX2N
DRX2N
(SSRXN)
UEQ[1:0]
UTX1P
DTX1P
(SSRXP)
UEQ[1:0]
DTX1P
(SSTXP)
UTX1P
UEQ[1:0]
UTX1N
DTX1N
(SSRXN)
UEQ[1:0]
DTX1N
(SSTXN)
UTX1N
DEQ[1:0]
DRX1P
(SSTXP)
URX1P
DEQ[1:0]
URX1P
DRX1P
(SSRXP)
DEQ[1:0]
DRX1N
(SSTXN)
URX1N
DEQ[1:0]
URX1N
DRX1N
(SSRXN)
UEQ[1:0]
URX2P
DRX2P
(DP3P)
UEQ[1:0]
DRX2P
(DP3P)
URX2P
UEQ[1:0]
URX2N
DRX2N
(DP3N)
UEQ[1:0]
DRX2N
(DP3N)
URX2N
UEQ[1:0]
UTX2P
DTX2P
(DP2P)
UEQ[1:0]
DTX2P
(DP2P)
UTX2P
UEQ[1:0]
UTX2N
DTX2N
(DP2N)
UEQ[1:0]
DTX2N
(DP2N)
UTX2N
UEQ[1:0]
UTX1P
DTX1P
(DP1P)
UEQ[1:0]
DTX1P
(DP1P)
UTX1P
UEQ[1:0]
UTX1N
DTX1N
(DP1N)
UEQ[1:0]
DTX1N
(DP1N)
UTX1N
UEQ[1:0]
URX1P
DRX1P
(DP0P)
UEQ[1:0]
DRX1P
(DP0P)
URX1P
UEQ[1:0]
URX1P
DRX1N
(DP0P)
UEQ[1:0]
DRX1N
(DP0N)
URX1N
UEQ[1:0]
URX1P
DRX1P
(DP3P)
UEQ[1:0]
DRX1P
(DP3P)
URX1P
UEQ[1:0]
URX1N
DRX1N
(DP3N)
UEQ[1:0]
DRX1N
(DP3N)
URX1N
UEQ[1:0]
UTX1P
DTX1P
(DP2P)
UEQ[1:0]
DTX1P
(DP2P)
UTX1P
UEQ[1:0]
UTX1N
DTX1N
(DP2N)
UEQ[1:0]
DTX1N
(DP2N)
UTX1N
UEQ[1:0]
UTX2P
DTX2P
(DP1P)
UEQ[1:0]
DTX2P
(DP1P)
UTX2P
UEQ[1:0]
UTX2N
DTX2N
(DP1N)
UEQ[1:0]
DTX2N
(DP1N)
UTX2N
UEQ[1:0]
URX2P
DRX2P
(DP0P)
UEQ[1:0]
DRX2P
(DP0P)
URX2P
UEQ[1:0]
URX2N
DRX2N
(DP0N)
UEQ[1:0]
DRX2N
(DP0N)
URX2N
L
H
L
H
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
25
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
Table 4. INPUT to OUTPUT Mapping (continued)
SWAP = L
DIR1
PIN
L
L
DIR0
PIN
H
H
CTL1
PIN
H
H
CTL0
PIN
H
H
FLIP
PIN
SWAP = H
From
From
To
From
From
To
Rx EQ
Control
PINS
Input
PIN
Output
PIN
Rx EQ
Control
PINS
Input
PIN
Output
PIN
DEQ[1:0]
DRX2P
(SSRXP)
URX2P
DEQ[1:0]
URX2P
DRX2P
(SSRXP)
DEQ[1:0]
DRX2N
(SSRXN)
URX2N
DEQ[1:0]
URX2N
DRX2N
(SSRXN)
UEQ[1:0]
UTX2P
DTX2P
(SSTXP)
UEQ[1:0]
DTX2P
(SSTXP)
UTX2P
UEQ[1:0]
UTX2N
DTX2N
(SSTXN)
UEQ[1:0]
DTX2N
(SSTXN)
UTX2N
UEQ[1:0]
URX1P
DRX1P
(DP0P)
UEQ[1:0]
DRX1P
(DP0P)
URX1P
UEQ[1:0]
URX1N
DRX1N
(DP0N)
UEQ[1:0]
DRX1N
(DP0N)
URX1N
UEQ[1:0]
UTX1P
DTX1P
(DP1P)
UEQ[1:0]
DTX1P
(DP1P)
UTX1P
UEQ[1:0]
UTX1N
DTX1N
(DP1N)
UEQ[1:0]
DTX1N
(DP1N)
UTX1N
DEQ[1:0]
DRX1P
(SSRXP)
URX1P
DEQ[1:0]
URX1P
DRX1P
(SSRXP)
DEQ[1:0]
DRX1N
(SSRXN)
URX1N
DEQ[1:0]
URX1N
DRX1N
(SSRXN)
UEQ[1:0]
UTX1P
DTX1P
(SSTXP)
UEQ[1:0]
DTX1P
(SSTXP)
UTX1P
UEQ[1:0]
UTX1N
DTX1N
(SSTXN)
UEQ[1:0]
DTX1N
(SSTXN)
UTX1N
UEQ[1:0]
URX2P
DRX2P
(DP0P)
UEQ[1:0]
DRX2P
(DP0P)
URX2P
UEQ[1:0]
URX2N
DRX2N
(DP0N)
UEQ[1:0]
DRX2N
(DP0N)
URX2N
UEQ[1:0]
UTX2P
DTX2P
(DP1P)
UEQ[1:0]
DTX2P
(DP1P)
UTX2P
UEQ[1:0]
UTX2N
DTX2N
(DP1N)
UEQ[1:0]
DTX2N
(DP1N)
UTX2N
L
H
USB + Custom Alternate Mode (Source Side)
H
L
L
L
L
NA
NA
NA
NA
NA
NA
H
L
L
L
H
NA
NA
NA
NA
NA
NA
DEQ[1:0]
DRX1P
URX1P
(SSRXP)
DEQ[1:0]
URX1P
(SSTXP)
DRX1P
DEQ[1:0]
DRX1N
URX1N
(SSRXN)
DEQ[1:0]
URX1N
(SSTXN)
DRX1N
UEQ[1:0]
UTX1P
(SSTXP)
DTX1P
UEQ[1:0]
DTX1P
UTX1P
(SSRXP)
UEQ[1:0]
UTX1N
(SSTXN)
DTX1N
UEQ[1:0]
DTX1N
UTX1N
(SSRXN)
DEQ[1:0]
DRX2P
URX2P
(SSRXP)
DEQ[1:0]
URX2P
(SSTXP)
DRX2P
DEQ[1:0]
DRX2N
URX2N
(SSRXN)
DEQ[1:0]
URX2N
(SSTXN)
DRX2N
UEQ[1:0]
UTX2P
(SSTXP)
DTX2P
UEQ[1:0]
DTX2P
UTX2P
(SSRXP)
UEQ[1:0]
UTX2N
(SSTXN)
DTX2N
UEQ[1:0]
DTX2N
UTX2N
(SSRXN)
H
H
26
L
L
L
L
H
H
L
H
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
Table 4. INPUT to OUTPUT Mapping (continued)
SWAP = L
DIR1
PIN
H
H
H
DIR0
PIN
L
L
L
CTL1
PIN
H
H
H
CTL0
PIN
L
L
H
FLIP
PIN
SWAP = H
From
From
To
From
From
To
Rx EQ
Control
PINS
Input
PIN
Output
PIN
Rx EQ
Control
PINS
Input
PIN
Output
PIN
DEQ[1:0]
DRX2P
URX2P
(LN1RXP)
DEQ[1:0]
URX2P
(LN1RXP)
DRX2P
DEQ[1:0]
DRX2N
URX2N
(LN1RXN)
DEQ[1:0]
URX2N
(LN1RXN)
DRX2N
UEQ[1:0]
UTX2P
(LN1TXP)
DTX2P
UEQ[1:0]
DTX2P
UTX2P
(LN1TXP)
UEQ[1:0]
UTX2N
(LN1TXN)
DTX2N
UEQ[1:0]
DTX2N
UTX2N
(LN1TXN)
UEQ[1:0]
UTX1P
(LN0TXP)
DTX1P
UEQ[1:0]
DTX1P
UTX1P
(LN0TXP)
UEQ[1:0]
UTX1N
(LN0TXN)
DTX1N
UEQ[1:0]
DTX1N
UTX1N
(LN0TXN)
DEQ[1:0]
DRX1P
URX1P
(LN0RXP)
DEQ[1:0]
URX1P
(LN0RXP)
DRX1P
DEQ[1:0]
DRX1N
URX1N
(LN0RXN)
DEQ[1:0]
URX1N
(LN0RXN)
DRX1N
DEQ[1:0]
DRX1P
URX1P
(LN1RXP)
DEQ[1:0]
URX1P
(LN1RXP)
DRX1P
DEQ[1:0]
DRX1N
URX1N
(LN1RXN)
DEQ[1:0]
URX1N
(LN1RXN)
DRX1N
UEQ[1:0]
UTX1P
(LN1TXP)
DTX1P
UEQ[1:0]
DTX1P
UTX1P
(LN1TXP)
UEQ[1:0]
UTX1N
(LN1TXN)
DTX1N
UEQ[1:0]
DTX1N
UTX1N
(LN1TXN)
UEQ[1:0]
UTX2P
(LN0TXP)
DTX2P
UEQ[1:0]
DTX2P
UTX2P
(LN0TXP)
UEQ[1:0]
UTX2N
(LN0TXN)
DTX2N
UEQ[1:0]
DTX2N
UTX2N
(LN0TXN)
DEQ[1:0]
DRX2P
URX2P
(LN0RXP)
DEQ[1:0]
URX2P
(LN0RXP)
DRX2P
DEQ[1:0]
DRX2N
URX2N
(LN0RXN)
DEQ[1:0]
URX2N
(LN0RXN)
DRX2N
DEQ[1:0]
DRX1P
URX1P
(SSRXP)
DEQ[1:0]
URX1P
(SSTXP)
DRX1P
DEQ[1:0]
DRX1N
URX1N
(SSRXN)
DEQ[1:0]
URX1N
(SSTXN)
DRX1N
UEQ[1:0]
UTX1P
(SSTXP)
DTX1P
UEQ[1:0]
DTX1P
UTX1P
(SSRXP)
UEQ[1:0]
UTX1N
(SSTXN)
DTX1N
UEQ[1:0]
DTX1N
UTX1N
(SSRXN)
UEQ[1:0]
UTX2P
(LN0TXP)
DTX2P
UEQ[1:0]
DTX2P
UTX2P
(LN0TXP)
UEQ[1:0]
UTX2N
(LN0TXN)
DTX2N
UEQ[1:0]
DTX2N
UTX2N
(LN0TXN)
DEQ[1:0]
DRX2P
URX2P
(LN0RXP)
DEQ[1:0]
URX2P
(LN0RXP)
DRX2P
DEQ[1:0]
DRX2N
URX2N
(LN0RXN)
DEQ[1:0]
URX2N
(LN0RXN)
DRX2N
L
H
L
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
27
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
Table 4. INPUT to OUTPUT Mapping (continued)
SWAP = L
DIR1
PIN
H
DIR0
PIN
L
CTL1
PIN
H
CTL0
PIN
H
FLIP
PIN
SWAP = H
From
From
To
From
From
To
Rx EQ
Control
PINS
Input
PIN
Output
PIN
Rx EQ
Control
PINS
Input
PIN
Output
PIN
DEQ[1:0]
DRX2P
URX2P
(SSRXP)
DEQ[1:0]
URX2P
(SSTXP)
DRX2P
DEQ[1:0]
DRX2N
URX2N
(SSRXN)
DEQ[1:0]
URX2N
(SSTXN)
DRX2N
UEQ[1:0]
UTX2P
(SSTXP)
DTX2P
UEQ[1:0]
DTX2P
UTX2P
(SSRXP)
UEQ[1:0]
UTX2N
(SSTXN)
DTX2N
UEQ[1:0]
DTX2N
UTX2N
(SSRXN)
UEQ[1:0]
UTX1P
(LN0TXP)
DTX1P
UEQ[1:0]
DTX1P
UTX1P
(LN0TXP)
UEQ[1:0]
UTX1N
(LN0TXN)
DTX1N
UEQ[1:0]
DTX1N
UTX1N
(LN0TXN)
DEQ[1:0]
DRX1P
URX1P
(LN0RXP)
DEQ[1:0]
URX1P
(LN0RXP)
DRX1P
DEQ[1:0]
DRX1N
URX1N
(LN0RXN)
DEQ[1:0]
URX1N
(LN0RXN)
DRX1N
NA
NA
NA
NA
H
USB + Custom Alternate Mode (Sink Side)
H
H
L
L
L
NA
NA
H
H
L
L
H
NA
NA
NA
NA
NA
NA
UEQ[1:0]
UTX2P
DTX2P
(SSRXP)
UEQ[1:0]
DTX2P
(SSTXP)
UTX2P
UEQ[1:0]
UTX2N
DTX2N
(SSRXN)
UEQ[1:0]
DTX2N
(SSTXN)
UTX2N
DEQ[1:0]
DRX2P
(SSTXP)
URX2P
DEQ[1:0]
URX2P
DRX2P
(SSRXP)
DEQ[1:0]
DRX2N
(SSTXN)
URX2N
DEQ[1:0]
URX2N
DRX2N
(SSRXN)
UEQ[1:0]
UTX1P
DTX1P
(SSRXP)
UEQ[1:0]
DTX1P
(SSTXP)
UTX1P
UEQ[1:0]
UTX1N
DTX1N
(SSRXN)
UEQ[1:0]
DTX1N
(SSTXN)
UTX1N
DEQ[1:0]
DRX1P
(SSTXP)
URX1P
DEQ[1:0]
URX1P
DRX1P
(SSRXP)
DEQ[1:0]
DRX1N
(SSTXN)
URX1N
DEQ[1:0]
URX1N
DRX1N
(SSRXN)
DEQ[1:0]
DRX2P
URX2P
(LN1TXP)
DEQ[1:0]
URX2P
(LN1TXP)
DRX2P
DEQ[1:0]
DRX2N
URX2N
(LN1TXN)
DEQ[1:0]
URX2N
(LN1TXN)
DRX2N
UEQ[1:0]
UTX2P
(LN1RXP)
DTX2P
UEQ[1:0]
DTX2P
UTX2P
(LN1RXP)
UEQ[1:0]
UTX2N
(LN1RXN)
DTX2N
UEQ[1:0]
DTX2N
UTX2N
(LN1RXN)
UEQ[1:0]
UTX1P
(LN0RXP)
DTX1P
UEQ[1:0]
DTX1P
UTX1P
(LN0RXP)
UEQ[1:0]
UTX1N
(LN0RXN)
DTX1N
UEQ[1:0]
DTX1N
UTX1N
(LN0RXN)
DEQ[1:0]
DRX1P
URX1P
(LN0RXP)
DEQ[1:0]
URX1P
(LN0RXP)
DRX1P
DEQ[1:0]
DRX1N
URX1N
(LN0RXN)
DEQ[1:0]
URX1N
(LN0RXN)
DRX1N
H
H
H
28
H
H
H
L
L
H
H
H
L
L
H
L
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
Table 4. INPUT to OUTPUT Mapping (continued)
SWAP = L
DIR1
PIN
H
H
H
DIR0
PIN
H
H
H
CTL1
PIN
H
H
H
CTL0
PIN
L
H
H
FLIP
PIN
SWAP = H
From
From
To
From
From
To
Rx EQ
Control
PINS
Input
PIN
Output
PIN
Rx EQ
Control
PINS
Input
PIN
Output
PIN
DEQ[1:0]
DRX2P
URX2P
(LN0RXP)
DEQ[1:0]
URX2P
(LN0RXP)
DRX2P
DEQ[1:0]
DRX2N
URX2N
(LN0RXN)
DEQ[1:0]
URX2N
(LN0RXN)
DRX2N
UEQ[1:0]
UTX2P
(LN0RXP)
DTX2P
UEQ[1:0]
DTX2P
UTX2P
(LN0RXP)
UEQ[1:0]
UTX2N
(LN0RXN)
DTX2N
UEQ[1:0]
DTX2N
UTX2N
(LN0RXN)
UEQ[1:0]
UTX1P
(LN0RXP)
DTX1P
UEQ[1:0]
DTX1P
UTX1P
(LN0RXP)
UEQ[1:0]
UTX1N
(LN0RXN)
DTX1N
UEQ[1:0]
DTX1N
UTX1N
(LN0RXN)
DEQ[1:0]
DRX1P
URX1P
(LN0TXP)
DEQ[1:0]
URX1P
(LN0TXP)
DRX1P
DEQ[1:0]
DRX1N
URX1N
(LN0TXN)
DEQ[1:0]
URX1N
(LN0TXN)
DRX1N
UEQ[1:0]
UTX2P
DTX2P
(SSRXP)
UEQ[1:0]
DTX2P
(SSTXP)
UTX2P
UEQ[1:0]
UTX2N
DTX2N
(SSRXN)
UEQ[1:0]
DTX2N
(SSTXN)
UTX2N
DEQ[1:0]
DRX2P
(SSTXP)
URX2P
DEQ[1:0]
URX2P
DRX2P
(SSRXP)
DEQ[1:0]
DRX2N
(SSTXN)
URX2N
DEQ[1:0]
URX2N
DRX2N
(SSRXN)
UEQ[1:0]
UTX1P
DTX1P
(LN0RXP)
UEQ[1:0]
DTX1P
(LN0RXP)
UTX1P
UEQ[1:0]
UTX1N
DTX1N(LN0R
XN)
UEQ[1:0]
DTX1N(LN0R
XN)
UTX1N
DEQ[1:0]
DRX1P
(LN0TXP)
URX1P
DEQ[1:0]
URX1P
DRX1P
(LN0TXP)
DEQ[1:0]
DRX1N
(LN0TXN)
URX1N
DEQ[1:0]
URX1N
DRX1N
(LN0TXN)
UEQ[1:0]
UTX1P
DTX1P
(SSRXP)
UEQ[1:0]
DTX1P
(SSSXP)
UTX1P
UEQ[1:0]
UTX1N
DTX1N
(SSRXN)
UEQ[1:0]
DTX1N
(SSSXN)
UTX1N
DEQ[1:0]
DRX1P
(SSTXP)
URX1P
DEQ[1:0]
URX1P
DRX1P
(SSRXP)
DEQ[1:0]
DRX1N
(SSTXN)
URX1N
DEQ[1:0]
URX1N
DRX1N
(SSRXN)
DEQ[1:0]
DRX2P
URX2P
(LN0TXP)
DEQ[1:0]
URX2P
(LN0TXP)
DRX2P
DEQ[1:0]
DRX2N
URX2N
(LN0TXN)
DEQ[1:0]
URX2N
(LN0TXN)
DRX2N
UEQ[1:0]
UTX2P
(LN0RXP)
DTX2P
UEQ[1:0]
DTX2P
UTX2P
(LN0RXP)
UEQ[1:0]
UTX2N
(LN0RXN)
DTX2N
UEQ[1:0]
DTX2N
UTX2N
(LN0RXN)
H
L
H
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
29
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
7.4.2 Device Configuration in I2C Mode
The TUSB1044 is in I2C mode when I2C_EN is equal to “1”. The same configurations defined in GPIO mode are
also available in I2C mode. The TUSB1044 USB3.1, DisplayPort, and custom Alternate Mode configuration is
controlled based on Table 5. The AUXP/N to SBU1/2 mapping control is based on Table 5.
Table 5. I2C Configuration Control
Registers
DIRSEL1
DIRSEL0
CTLSEL1
CTLSEL0
FLIPSEL
TUSB1044 Configuration
VESA DisplayPort Alt Mode
DFP_D Configuration
USB + DisplayPort Alternate Mode (Source Side)
L
L
L
L
L
Power Down
–
L
L
L
L
H
Power Down
–
L
L
L
H
L
One Port USB 3.1 - No Flip
–
L
L
L
H
H
One Port USB 3.1 – With Flip
L
L
H
L
L
4 Lane DP - No Flip
C and E
L
L
H
L
H
4 Lane DP – With Flip
C and E
D and F
D and F
–
L
L
H
H
L
One Port USB 3.1 + 2 Lane
DP- No Flip
L
L
H
H
H
One Port USB 3.1 + 2 Lane
DP– With Flip
L
L
Power Down
–
USB + DisplayPort Alternate Mode (Sink Side)
L
H
L
L
H
L
L
H
Power Down
–
L
H
L
H
L
One Port USB 3.1 - No Flip
–
L
H
L
H
H
One Port USB 3.1 – With Flip
L
H
H
L
L
4 Lane DP - No Flip
C and E
L
H
H
L
H
4 Lane DP – With Flip
C and E
D and F
D and F
L
H
H
H
L
One Port USB 3.1 + 2 Lane
DP- No Flip
L
H
H
H
H
One Port USB 3.1 + 2 Lane
DP– With Flip
–
USB + Custom Alternate Mode (Source Side)
H
L
L
L
L
Power Down
–
H
L
L
L
H
Power Down
–
H
L
L
H
L
One Port USB 3.1 - No Flip
–
H
L
L
H
H
One Port USB 3.1 – With Flip
–
H
L
H
L
L
4 Channel Custom Alt Mode No Flip
–
H
L
H
L
H
4 Channel Custom Alt Mode–
With Flip
–
H
L
H
H
L
One Port USB 3.1 + 2
Channel Custom Alt ModeNo Flip
–
H
L
H
H
H
One Port USB 3.1 + 2
Channel Custom Alt Mode –
With Flip
–
USB + Custom Alternate Mode (Sink Side)
H
H
L
L
L
Power Down
–
H
H
L
L
H
Power Down
–
H
H
L
H
L
One Port USB 3.1 - No Flip
–
H
H
L
H
H
One Port USB 3.1 – With Flip
–
L
4 Channel Custom Alt Mode No Flip
–
H
30
H
H
L
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
Table 5. I2C Configuration Control (continued)
Registers
TUSB1044 Configuration
VESA DisplayPort Alt Mode
DFP_D Configuration
H
4 Channel Custom Alt Mode–
With Flip
–
H
L
One Port USB 3.1 + 2
Channel Custom Alt ModeNo Flip
–
H
H
One Port USB 3.1 + 2
Channel Custom Alt Mode –
With Flip
–
DIRSEL1
DIRSEL0
CTLSEL1
CTLSEL0
FLIPSEL
H
H
H
L
H
H
H
H
H
H
Table 6. I2C AUXP/N to SBU1/2 Mapping
Registers
AUX_SBU_OVR
CTLSEL1
FLIPSEL
Mapping
00
H
L
AUXp -> SBU1
AUXn -> SBU2
00
H
H
AUXp -> SBU2
AUXn -> SBU1
00
L
X
Open
01
X
X
AUXp -> SBU1
AUXn -> SBU2
10
X
X
AUXp -> SBU2
AUXn -> SBU1
11
X
X
Open
7.4.3 DisplayPort Mode
The TUSB1044 supports up to four DisplayPort lanes at datarates up to 8.1Gbps. TUSB1044 can be enabled for
DisplayPort through GPIO control or through I2C register control. When in GPIO mode, DisplayPort is controlled
based on Table 2. When not in GPIO mode, enable of DisplayPort functionality is controlled through I2C
registers.
7.4.4 Custom Alternate Mode
The TUSB1044 supports up to two lanes (or 4 channels) of custom Alternate Mode at datarates up to 10 Gbps.
TUSB1044 can be enabled for custom Alternate Mode through GPIO control or through I2C register control.
Custom Alternate mode is not supported for GPIO mode which has AUX snoop disabled. When in GPIO mode,
custom Alternate Mode is controlled based on Table 2. When not in GPIO mode, enable of custom Alternate
Mode functionality is controlled through I2C registers. In I2C mode, the operation of this mode requires leaving
AUX_SNOOP_DISABLE register 13h bit 7 at 0.
7.4.5 Linear EQ Configuration
TUSB1044 receiver lanes have controls for receiver equalization for upstream and downstream facing ports. The
receiver equalization gain value can be controlled either through I2C registers or through GPIOs. Table 7 details
the gain value for each available combination when TUSB1044 is in GPIO mode. These same options are also
available per channel and for upstream and downstream facing ports in I2C mode by updating registers
URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL.
Table 7. TUSB1044 Receiver Equalization GPIO Control
Downstream Facing Ports using 1100mV linearity
setting
EQ
Setting
#
DEQ1
pin
Level
0
1
Upstream Facing Port using 1100mV linearity setting
DEQ0
pin
Level
EQ GAIN
5GHz
(dB)
EQ GAIN
4.05GHz
(dB)
UEQ1
pin
Level
UEQ0
pin
Level
EQ GAIN
5GHz
(dB)
EQ GAIN
4.05GHz
(dB)
0
0
-2.1
-1.4
0
R
0
0.4
0
0
-4.4
-3.3
0
R
-2.2
-1.5
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
31
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
Table 7. TUSB1044 Receiver Equalization GPIO Control (continued)
Downstream Facing Ports using 1100mV linearity
setting
Upstream Facing Port using 1100mV linearity setting
2
0
F
1.5
1.7
0
F
0.7
0.0
3
0
1
3.0
3.2
0
1
0.9
1.4
4
R
0
4.0
4.1
R
0
1.9
2.4
5
R
R
5.0
5.2
R
R
3.0
3.5
6
R
F
5.9
6.1
R
F
3.8
4.3
7
R
1
6.7
6.9
R
1
4.7
5.2
8
F
0
7.4
7.7
F
0
5.4
6.0
9
F
R
8.0
8.3
F
R
6.0
6.6
10
F
F
8.5
8.8
F
F
6.5
7.2
11
F
1
9.0
9.4
F
1
7.1
7.7
12
1
0
9.4
9.8
1
0
7.5
8.1
13
1
R
9.8
10.3
1
R
7.9
8.6
14
1
F
10.1
10.6
1
F
8.3
9.0
15
1
1
10.5
11.0
1
1
8.6
9.4
7.4.6 Adjustable VOD Linear Range and DC Gain
The CFG0 and CFG1 pins can be used to adjust the TUSB1044 differential output voltage (VOD) swing linear
range and receiver equalization DC gain for both downstream and upstream data path directions. Table 8 details
the available options.
Table 8. VOD Linear Range and DC Gain
32
CFG0 pin
Level
Downstream
DC Gain
(dB)
Upstream
DC Gain (dB)
Downstream
VOD Linear
Range
(mVpp)
Upstream
VOD Linear
Range
(mVpp)
0
0
1
0
900
900
0
R
0
1
900
900
2
0
F
0
0
900
900
3
0
1
1
1
900
900
4
R
0
0
0
1100
1100
5
R
R
1
0
1100
1100
6
R
F
0
1
1100
1100
7
R
1
2
2
1100
1100
8
F
0
Reserved
Reserved
Reserved
Reserved
9
F
R
Reserved
Reserved
Reserved
Reserved
10
F
F
0
0
1300
1300
11
F
1
Reserved
Reserved
Reserved
Reserved
12
1
0
Reserved
Reserved
Reserved
Reserved
13
1
R
Reserved
Reserved
Reserved
Reserved
14
1
F
Reserved
Reserved
Reserved
Reserved
15
1
1
Reserved
Reserved
Reserved
Reserved
Setting
#
CFG1 pin
Level
0
1
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
7.4.7 USB3.1 Modes
The TUSB1044 monitors the physical layer conditions like receiver termination, electrical idle, LFPS, and
SuperSpeed signaling rate to determine the state of the USB3.1 interface. Depending on the state of the USB
3.1 interface, the TUSB1044 can be in one of four primary modes of operation when USB 3.1 is enabled (CTL0 =
H or CTLSEL0 = 1b1): Disconnect, U2/U3, U1, and U0.
The Disconnect mode is the state in which TUSB1044 has not detected far-end termination on both upstream
facing port (UFP) or downstream facing port (DFP). The disconnect mode is the lowest power mode of each of
the four modes. The TUSB1044 remains in this mode until far-end receiver termination has been detected on
both UFP and DFP. The TUSB1044 immediately exits this mode and enter U0 once far-end termination is
detected.
Once in U0 mode, the TUSB1044 redrives all traffic received on UFP and DFP. U0 is the highest power mode of
all USB3.1 modes. The TUSB1044 remains in U0 mode until electrical idle occurs on both UFP and DFP. Upon
detecting electrical idle, the TUSB1044 immediately transitions to U1.
The U1 mode is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB1044 UFP
and DFP receiver termination remain enabled. The UFP and DFP transmitter DC common mode is maintained.
The power consumption in U1 is similar to power consumption of U0.
Next to the disconnect mode, the U2 and U3 mode is next lowest power state. While in this mode, the
TUSB1044 periodically performs far-end receiver detection. Anytime the far-end receiver termination is not
detected on either UFP or DFP, the TUSB1044 leaves the U2 and U3 mode and transition to the Disconnect
mode. It also monitors for a valid LFPS. Upon detection of a valid LFPS, the TUSB1044 immediately transitions
to the U0 mode. In U2 and U3 mode, the TUSB1044 receiver terminations remains enabled, but the TX DC
common mode voltage is not maintained.
When SLP_S0# is asserted low, it disables Receiver Detect functionality. While SLP_S0# is low and TUSB1044
is in U2 and U3, TUSB1044 disables LOS and LFPS detection circuitry and RX termination for both channels
remains enabled. This allows even lower TUSB1044 power consumption while in the U2 and U3 mode. Once
SLP_S0# is asserted high, the TUSB1044 will again start performing far-end receiver detection as well as
monitor LFPS so it can know when to exit the U2 and U3 mode.
When SLP_S0# is asserted low and the TUSB1044 is in Disconnect mode, the TUSB1044 will remain in
Disconnect mode and never perform far-end receiver detection. This allows even lower TUSB1044 power
consumption while in the Disconnect mode. Once SLP_S0# is asserted high, the TUSB1044 will again start
performing far-end receiver detection so it can know when to exit the Disconnect mode.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
33
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
7.5 Programming
For further programmability, the TUSB1044 can be controlled using I2C. The SCL and SDA terminals are used
for I2C clock and I2C data respectively.
Table 9. I2C Slave Address
TUSB1044 I2C Slave Address
UEQ1/A1
Pin Level
UEQ0/A0
Pin Level
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(W/R)
0
0
1
0
0
0
1
0
0
0/1
0
R
1
0
0
0
1
0
1
0/1
0
F
1
0
0
0
1
1
0
0/1
0
1
1
0
0
0
1
1
1
0/1
R
0
0
1
0
0
0
0
0
0/1
R
R
0
1
0
0
0
0
1
0/1
R
F
0
1
0
0
0
1
0
0/1
R
1
0
1
0
0
0
1
1
0/1
F
0
0
0
1
0
0
0
0
0/1
F
R
0
0
1
0
0
0
1
0/1
F
F
0
0
1
0
0
1
0
0/1
F
1
0
0
1
0
0
1
1
0/1
1
0
0
0
0
1
1
0
0
0/1
1
R
0
0
0
1
1
0
1
0/1
1
F
0
0
0
1
1
1
0
0/1
1
1
0
0
0
1
1
1
1
0/1
7.5.1 Use The Following Procedure to Write to TUSB1044 I2C Registers:
1. The master initiates a write operation by generating a start condition (S), followed by the TUSB1044 7-bit
address and a zero-value “W/R” bit to indicate a write cycle .
2. The TUSB1044 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TUSB10444) to be written, consisting of one byte of
data, MSB-first.
4. The TUSB1044 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The TUSB1044 acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the TUSB1044.
8. The master terminates the write operation by generating a stop condition (P).
7.5.2 Use The Following Procedure to Read the TUSB1044 I2C Registers:
1. The master initiates a read operation by generating a start condition (S), followed by the TUSB1044 7-bit
address and a one-value “W/R” bit to indicate a read cycle
2. The TUSB1044 acknowledges the address cycle.
3. The TUSB1044 transmit the contents of the memory registers MSB-first starting at register 00h or last read
sub-address+1. If a write to the T I2C register occurred prior to the read, then the TUSB1044 shall start at
the sub-address specified in the write.
4. The TUSB1044 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master
after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the TUSB1044 transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
34
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
7.5.3 Use The Following Procedure for Setting a Starting Sub-Address for I2C Reads:
1. The master initiates a write operation by generating a start condition (S), followed by the TUSB1044 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB1044 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TUSB1044) to be written, consisting of one byte of
data, MSB-first.
4. The TUSB1044 acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).
NOTE
If no sub-addressing is included for the read procedure, and reads start at register offset
00h and continue byte by byte through the registers until the I2C master terminates the
read operation. If a I2C address write occurred prior to the read, then the reads start at the
sub-address specified by the address write.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
35
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
7.6 Register Maps
7.6.1 TUSB1044 Registers
Table 10 lists the memory-mapped registers for the TUSB1044. All register offset addresses not listed in
Table 10 should be considered as reserved locations and the register contents should not be modified.
Table 10. TUSB1044 Registers
Offset
Acronym
Register Name
Ah
General_1
General Registers 1
Section
Go
Bh
General_2
General Registers 2
Go
Ch
General_3
General Registers 3
Go
10h
UFP2_EQ
UFP2 EQ Control
Go
11h
UFP1_EQ
UFP1 EQ Control
Go
12h
DisplayPort_1
AUX Snoop Status
Go
13h
DisplayPort_2
DP Lane Enable/Disable Control
Go
1Bh
SOFT_RESET
I2C and DPCD Soft Resets
Go
20h
DFP2_EQ
DFP2 EQ Control
Go
21h
DFP1_EQ
DFP1 EQ Control
Go
22h
USB3_MISC
Misc USB3 Controls
Go
23h
USB3_LOS
USB3 LOS Threshold Controls
Go
Complex bit access types are encoded to fit into small table cells. Table 11 shows the codes that are used for
access types in this section.
Table 11. TUSB1044 Access Type Codes
Access Type
Code
Description
R
R
Read
RH
H
R
Set or cleared by hardware
Read
H
H
Set or cleared by hardware
W
W
Write
WSH
H
W
WS
Set or cleared by hardware
Write
Read Type
Write Type
Reset or Default Value
-n
Value after reset or the default value
Register Array Variables
36
i,j,k,l,m,n
When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y
When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
7.6.1.1 General_1 Register (Offset = Ah) [reset = 1h]
General_1 is shown in Figure 23 and described in Table 12.
Return to Summary Table.
Figure 23. General_1 Register
7
RESERVED
6
RESERVED
5
SWAP_SEL
R-0h
R/W-0h
R/W-0h
4
EQ_OVERRID
E
R/W-0h
3
HPDIN_OVER
RIDE
R/W-0h
2
FLIP_SEL
R/W-0h
1
0
CTLSEL[1:0]
R/W-1h
Table 12. General_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
0h
Reserved
6
RESERVED
R/W
0h
Reserved
5
SWAP_SEL
R/W
0h
Setting this field performs a global direction swap on all the
channels.
0h = Channel directions and EQ settings are in normal mode
1h = Reverse all channel directions and EQ settings for the input
ports.
4
EQ_OVERRIDE
R/W
0h
Setting this field will allow software to use EQ settings from registers
instead of value sampled from pins.
0h = EQ settings based on sampled state of EQ pins.
1h = EQ settings based on programmed value of each of the EQ
registers.
3
HPDIN_OVERRIDE
R/W
0h
Overrides HPDIN pin state.
0h = HPD_IN based on HPD_IN pin.
1h = HPD_IN high.
2
FLIP_SEL
R/W
0h
FLIPSEL
0h = Normal Orientation
1h = Flip orientation.
1-0
CTLSEL[1:0]
R/W
1h
Controls the DP and USB modes.
0h = Disabled. All RX and TX for USB3 and DisplayPort are
disabled.
1h = USB3.1 only enabled.
2h = Four Lanes of DisplayPort enabled.
3h = USB3.1 and Two DisplayPort Lanes.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
37
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
7.6.1.2 General_2 Register (Offset = Bh) [reset = 0h]
General_2 is shown in Figure 24 and described in Table 13.
Return to Summary Table.
Figure 24. General_2 Register
7
6
5
4
3
RESERVED
R-0h
2
1
CH_SWAP_SEL
R/W-0h
0
Table 13. General_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0h
Reserved
3-0
CH_SWAP_SEL
R/W
0h
Swaps direction (TX to Rx and Rx to Tx) and EQ settings of
individual channels. Channels are numbered from 0 to 3. 1 bit per
lane.
0h = Channel and EQ settings normal.
1h = Reverse channel direction and EQ setting.
7.6.1.3 General_3 Register (Offset = Ch) [reset = 0h]
General_3 is shown in Figure 25 and described in Table 14.
Return to Summary Table.
Figure 25. General_3 Register
7
RESERVED
R-0h
6
VOD_DCGAIN
_OVERRIDE
R/W-0h
5
4
3
VOD_DCGAIN_SEL
2
1
0
DIR_SEL
R/W-0h
R/W-0h
Table 14. General_3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
0h
Reserved
6
VOD_DCGAIN_OVERRID R/W
E
0h
Setting of this field will allow software to use VOD linearity range and
DC gain settings from registers instead of value sampled from pins
0h = VOD linearity and DC gain settings based on sampled CFG[2:1]
pins.
1h = EQ settings based on programmed value of each VOD linearity
and DC Gain registers.
5-2
VOD_DCGAIN_SEL
R/W
0h
Field selects VOD linearity range and DC gain for all the channels
and in all directions. When VOD_DCGAIN_OVERRIDE = 0b, this
field reflects the sampled state of CFG[1:0] pins. When
VOD_DCGAIN_OVERRIDE = 1b software can change the VOD
linearity range and DC gain for all the channels and in all directions
based on value written to this field. Each CFG is a 2-bit value. The
register-to-CFG1/0 mapping is: [5:2] = {CFG1[1:0], CFG0[1:0]} where
CFGx[1:0] mapping is:
0h = 0
1h = R
2h = F
3h = 1
38
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
Table 14. General_3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
DIR_SEL
R/W
0h
Sets the operation mode.
0h = USB + DP Alt Mode Source
1h = USB + DP Alt Mode Sink.
2h = USB + Custom Alt Mode Source
3h = USB + Custom Alt Mode Sink.
7.6.1.4 UFP2_EQ Register (Offset = 10h) [reset = 0h]
UFP2_EQ is shown in Figure 26 and described in Table 15.
Return to Summary Table.
Figure 26. UFP2_EQ Register
7
6
5
4
3
2
UTX2EQ_SEL
R/W-0h
1
0
URX2EQ_SEL
R/W-0h
Table 15. UFP2_EQ Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
UTX2EQ_SEL
R/W
0h
Field selects EQ for UTX2P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of UEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
UTX2P/N pins based on value written to this field.
3-0
URX2EQ_SEL
R/W
0h
Field selects EQ for URX2P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of UEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
URX2P/N pins based on value written to this field.
7.6.1.5 UFP1_EQ Register (Offset = 11h) [reset = 0h]
UFP1_EQ is shown in Figure 27 and described in Table 16.
Return to Summary Table.
Figure 27. UFP1_EQ Register
7
6
5
4
3
UTX1EQ_SEL
R/W-0h
2
1
0
URX1EQ_SEL
R/W-0h
Table 16. UFP1_EQ Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
UTX1EQ_SEL
R/W
0h
Field selects EQ for UTX1P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of UEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
UTX1P/N pins based on value written to this field.
3-0
URX1EQ_SEL
R/W
0h
Field selects EQ for URX1P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of UEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
URX1P/N pins based on value written to this field.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
39
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
7.6.1.6 DisplayPort_1 Register (Offset = 12h) [reset = 0h]
DisplayPort_1 is shown in Figure 28 and described in Table 17.
Return to Summary Table.
Figure 28. DisplayPort_1 Register
7
RESERVED
R-0h
6
5
SET_POWER_STATE
RH-0h
4
3
2
LANE_COUNT_SET
RH-0h
1
0
Table 17. DisplayPort_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
6-5
SET_POWER_STATE
RH
0h
This field represents the snooped value of the AUX write to DPCD
address 0x00600. When AUX_SNOOP_DISABLE = 0b, the
enable/disable of DP lanes based on the snooped value. When
AUX_SNOOP_DISABLE = 1b, then DP lane enable/disable are
determined by state of DPx_DISABLE registers, where x = 0, 1, 2, or
3. This field is reset to 0h by hardware when CTLSEL1 changes
from a 1b to a 0b.
4-0
LANE_COUNT_SET
RH
0h
This field represents the snooped value of AUX write to DPCD
address 0x00101 register. When AUX_SNOOP_DISABLE = 0b, DP
lanes enabled specified by the snoop value. Unused DP lanes will
be disabled to save power. When AUX_SNOOP_DISABLE = 1b,
then DP lanes enable/disable are determined by DPx_DISABLE
registers, where x = 0, 1, 2, or 3. This field is reset to 0h by
hardware when CTLSEL1 changes from a 1b to a 0b.
7
40
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
7.6.1.7 DisplayPort_2 Register (Offset = 13h) [reset = 0h]
DisplayPort_2 is shown in Figure 29 and described in Table 18.
Return to Summary Table.
Figure 29. DisplayPort_2 Register
7
AUX_SNOOP_
DISABLE
R/W-0h
6
RESERVED
5
4
AUX_SBU_OVR
3
DP3_DISABLE
2
DP2_DISABLE
1
DP1_DISABLE
0
DP0_DISABLE
R-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 18. DisplayPort_2 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
AUX_SNOOP_DISABLE
R/W
0h
Controls whether DP lanes are enabled based on AUX snooped
value or registers.
0h = AUX snoop enabled.
1h = AUX snoop disabled. DP lanes are controlled by registers.
6
5-4
RESERVED
R
0h
Reserved
AUX_SBU_OVR
R/W
0h
This field overrides the AUXP/N to SBU1/2 connect and disconnect
based on CTL1 and FLIP. Changing this field to 1b will allow traffic
to pass through AUX to SBU regardless of the state of CTLSEL1
and FLIPSEL register.
0h = AUX to SBU connection determined by CTLSEL1 and FLIPSEL
1h = AUXP -> SBU1 and AUXN -> SBU2
2h = AUXP -> SBU2 and AUXN -> SBU1
3h = AUX to SBU open.
3
DP3_DISABLE
R/W
0h
When AUX_SNOOP_DISABLE = 1b, this field can be used to enable
or disable DP lane 3. When AUX_SNOOP_DISABLE = 0b, changes
to this field will have no effect on lane 3 functionality.
0h = DP Lane 3 enabled.
1h = DP Lane 3 disabled.
2
DP2_DISABLE
R/W
0h
When AUX_SNOOP_DISABLE = 1b, this field can be used to enable
or disable DP lane 2. When AUX_SNOOP_DISABLE = 0b, changes
to this field will have no effect on lane 2 functionality.
0h = DP Lane 2 enabled.
1h = DP Lane 2 disabled.
1
DP1_DISABLE
R/W
0h
When AUX_SNOOP_DISABLE = 1b, this field can be used to enable
or disable DP lane 1. When AUX_SNOOP_DISABLE = 0b, changes
to this field will have no effect on lane 1 functionality.
0h = DP Lane 1 enabled.
1h = DP Lane 1 disabled.
0
DP0_DISABLE
R/W
0h
When AUX_SNOOP_DISABLE = 1b, this field can be used to enable
or disable DP lane 0. When AUX_SNOOP_DISABLE = 0b, changes
to this field will have no effect on lane 0 functionality.
0h = DP Lane 0 enabled.
1h = DP Lane 0 disabled.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
41
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
7.6.1.8 SOFT_RESET Register (Offset = 1Bh) [reset = 0h]
SOFT_RESET is shown in Figure 30 and described in Table 19.
Return to Summary Table.
Figure 30. SOFT_RESET Register
7
I2C_RST
RH/WS-0h
6
DPCD_RST
RH/WS-0h
5
4
3
2
1
0
RESERVED
R-0h
Table 19. SOFT_RESET Register Field Descriptions
Bit
Field
Type
Reset
Description
7
I2C_RST
RH/WS
0h
Resets I2C registers to default values. This field is self-clearing.
6
DPCD_RST
RH/WS
0h
Resets DPCD registers to default values. This field is self-clearing.
5-0
RESERVED
R
0h
Reserved
7.6.1.9 DFP2_EQ Register (Offset = 20h) [reset = 0h]
DFP2_EQ is shown in Figure 31 and described in Table 20.
Return to Summary Table.
Figure 31. DFP2_EQ Register
7
6
5
4
3
DTX2EQ_SEL
R/W-0h
2
1
0
DRX2EQ_SEL
R/W-0h
Table 20. DFP2_EQ Register Field Descriptions
42
Bit
Field
Type
Reset
Description
7-4
DTX2EQ_SEL
R/W
0h
Field selects EQ for DTX2P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of DEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
DTX2P/N pins based on value written to this field.
3-0
DRX2EQ_SEL
R/W
0h
Field selects EQ for DRX2P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of DEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
DRX2P/N pins based on value written to this field.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
7.6.1.10 DFP1_EQ Register (Offset = 21h) [reset = 0h]
DFP1_EQ is shown in Figure 32 and described in Table 21.
Return to Summary Table.
Figure 32. DFP1_EQ Register
7
6
5
4
3
2
DTX1EQ_SEL
R/W-0h
1
0
DRX1EQ_SEL
R/W-0h
Table 21. DFP1_EQ Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DTX1EQ_SEL
R/W
0h
Field selects EQ for DTX1P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of DEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
DTX1P/N pins based on value written to this field.
3-0
DRX1EQ_SEL
R/W
0h
Field selects EQ for DRX1P/N pins. When EQ_OVERRIDE = 0b, this
field reflects the sampled state of DEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for
DRX1P/N pins based on value written to this field.
7.6.1.11 USB3_MISC Register (Offset = 22h) [reset = 4h]
USB3_MISC is shown in Figure 33 and described in Table 22.
Return to Summary Table.
Figure 33. USB3_MISC Register
7
CM_ACTIVE
6
LFPS_EQ
RH-0h
R/W-0h
5
U2U3_LFPS_D
EBOUNCE
R/W-0h
4
DISABLE_U2U
3_RXDET
R/W-0h
3
2
DFP_RXDET_INTERVAL
1
0
USB_COMPLIANCE_CTRL
R/W-1h
R/W-0h
Table 22. USB3_MISC Register Field Descriptions
Bit
7
Field
Type
Reset
Description
CM_ACTIVE
RH
0h
Compliance mode status.
0h = Not in USB3.1 compliance mode.
1h = In USB3.1 compliance mode.
6
LFPS_EQ
R/W
0h
Controls whether settings of EQ based on URX[2:1]EQ_SEL,
UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL applies
to received LFPS signal.
0h = EQ set to zero when receiving LFPS
1h = EQ set by the related registers when receiving LFPS.
5
U2U3_LFPS_DEBOUNCE R/W
0h
Controls whether or not incoming LFPS is debounced or not.
0h = No debounce of LFPS before U2/U3 exit.
1h = 200us debounce of LFPS before U2/U3 exit.
4
DISABLE_U2U3_RXDET
R/W
0h
Controls whether or not Rx.Detect is performed in U2/U3 state.
0h = Rx.Detect in U2/U3 enabled.
1h = Rx.Detect in U2/U3 disabled.
3-2
DFP_RXDET_INTERVAL
R/W
1h
This field controls the Rx.Detect interval for the downstream facing
port (DTX1P/N and DTX2P/N).
0h = 8ms
1h = 12ms
2h = Reserved
3h = Reserved.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
43
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
Table 22. USB3_MISC Register Field Descriptions (continued)
Bit
Field
1-0
USB_COMPLIANCE_CTR R/W
L
Type
Reset
Description
0h
Controls whether compliance mode is determined by FSM or
register.
0h = Compliance mode determined by FSM.
1h = Compliance mode enabled in DFP direction.
2h = Compliance mode enabled in UFP direction.
3h = Compliance mode disabled.
7.6.1.12 USB3_LOS Register (Offset = 23h) [reset = 23h]
USB3_LOS is shown in Figure 34 and described in Table 23.
Return to Summary Table.
Figure 34. USB3_LOS Register
7
6
5
RESERVED
R-0h
4
CFG_LOS_HYST
R/W-4h
3
2
1
CFG_LOS_VTH
R/W-3h
0
Table 23. USB3_LOS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R
0h
Reserved
5-3
CFG_LOS_HYST
R/W
4h
Controls LOS hysteresis defined as 20 log (LOS de-assert
threshold/LOS assert threshold).
0h = 0.15 dB
1h = 0.85 dB
2h = 1.45 dB
3h = 2.00 dB
4h = 2.70 dB
5h = 3.00 dB
6h = 3.40 dB
7h = 3.80 dB
2-0
CFG_LOS_VTH
R/W
3h
Controls LOS assert threshold voltage
0h = 67 mV
1h = 72 mV
2h = 79 mV
3h = 85 mV
4h = 91 mV
5h = 97 mV
6h = 105 mV
7h = 112 mV
44
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TUSB1044 is a linear redriver designed specifically to compensate for intersymbol interference (ISI) jitter
caused by signal attenuation through a passive medium like PCB traces and cables. Because the TUSB1044
has four independent inputs, it can be optimized to correct ISI on all those seven inputs through 16 different
equalization choices. Placing the TUSB1044 between a USB3.1 Host/DisplayPort 1.4 GPU and a USB3.1 TypeC receptacle can correct signal integrity issues resulting in a more robust system.
8.2 Typical Application
A
B
F
E
PCB Trace of Length XAB
PCB Trace of Length XEF
RX2P
URX2P
RX2N
URX2N
TX2P
UTX2P
TX2N
UTX2N
DRX2P
DRX2N
DTX2P
USB3.1/
DP1.4
Host
Type-C
Receptacle
DTX2N
TUSB1044
DTX1N
DTX1P
TX1N
UTX1N
TX1P
UTX1P
RX1N
URX1N
RX1P
URX1P
DRX1N
DRX1P
PCB Trace of Length XCD
C
PCB Trace of Length XGH
D
G
H
Figure 35. TUSB1044 in a Host Application
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
45
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters shown in Table 24.
Table 24. Design Parameters
PARAMETER
VALUE
A to B PCB trace length, XAB
8 inches (assuming 1 dB/inch at 5GHz).
C to D PCB trace length, XCD
8 inches (assuming 1 dB/inch at 5GHz).
E to F PCB trace length, XEF
1.5 inches (assuming 1 dB/inch at 5GHz).
G to H PCB trace length, XGH
1.5 inches (assuming 1 dB/inch at 5GHz).
PCB trace width
4 mils
AC-coupling capacitor (75 nF to 265 nF)
220 nF
VCC supply (3 V to 3.6 V)
3.3 V
I2C Mode or GPIO Mode
I2C Mode.
1.8V or 3.3V I2C Interface
3.3V I2C. Pull-up the I2C_EN pin to 3.3V with a 1K
ohm resistor.
8.2.2 Detailed Design Procedure
A typical usage of the TUSB1044 device is shown in Figure 36. The device can be controlled either through its
GPIO pins or through its I2C interface. In Figure 36, a Type-C PD controller is used to configure the device
through the I2C interface. In I2C mode, the equalization settings for each receiver can be independently
controlled through I2C registers. For this reason, all of the equalization pins (UEQ[1:0] and DEQ[1:0]) can be left
unconnected. If these pins are left unconnected, the TUSB1044 7-bit I2C slave address is 12h because both
UEQ1/A1 and UEQ0/A0 are at pin level "F". If a different I2C slave address is desired, UEQ1/A1 and UEQ0/A0
pins should be set to a level which produces the desired I2C slave address.
Recent ECN (Engineering Change Notice) to the USB3.1 specification allows for AC-coupling capacitors
between USB receptacle and the USB3.1 receiver pins of a device/host/hub. The TUSB1044 does support the
additional AC-capacitor as depicted in Figure 36 on pins DRX2P/N and DRX1P/N. This AC-coupling capacitor
should be no smaller than 297 nF. A value of 330 nF is recommended.
46
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
3.3 V
100nF
VCC
VCC
220 nF
RX2P
VCC
VCC
10uF
URX2P
DRX2P
URX2N
DRX2N
100nF
100nF
330 nF
330 nF
220 nF
RX2N
USB Type-C
Receptacle
220 nF
220 nF
TX2P
UTX2P
DTX2P
UTX2N
DTX2N
220 nF
220 nF
TX2N
100K
AUXP
100 nF
AUXN
100 nF
A12
GND
A11
URXP2
A10
URXN2
AUXP
A9
VBUS
A8
SBU1
AUXN
DP_PWR (3.3V)
SBU1
100K
TUSB1044
USB 3.1/DP1.4
Host
SBU2
2M
UTX1P
DTX1P
DP1
A5
CC1
A4
VBUS
A3
TXN1
A2
TXP1
A1
GND
DRX1N
URX1N
330 nF
220 nF
DRX1P
URX1P
RX1P
A6
330 nF
220 nF
RX1N
DN1
B1
GND
B2
TXP2
B3
TXN2
B4
VBUS
B5
CC2
B6
DP2
B7
DN2
B8
SBU2
B9
VBUS
B10
URXN1
B11
URXP1
B12
GND
220 nF
220 nF
TX1P
A7
DTX1N
UTX1N
TX1N
2M
220 nF
220 nF
3.3V
3.3V
SWAP
I2C_EN
3.3V
100nF
3.3V
UEQ0/A0
VI2C
UEQ1/A1
3.3V
R
R
VIO_SEL
FLIP/SCL
3.3V
3.3V
3.3V
3.3V
CFG0
CTL0/SDA
CFG1
CTL1
DEQ0
SLP_S0#
DEQ1
HPDIN
3.3V
Type-C
PD
Controller
3.3V
DIR0
TP
DIR1
GPIO Mode Only Connections
GPIO/I2C Mode Connections
Figure 36. Typical Application Circuit
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
47
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
8.2.3 Application Curve
0
-5
-10
Insertion Loss (dB)
-15
-20
-25
-30
-35
Length=12in, Width=6mil
Length=16in, Width=6mil
Length=20in, Width=6mil
Length=24in, Width=6mil
Length=4in, Width=4mil
Length=8in, Width=10mil
Length=8in, Width=6mil
-40
-45
-50
-55
-60
0
2
4
6
8
10
Frequency (GHz)
12
14
16
D009
Figure 37. Insertion Loss of FR4 PCB Traces
48
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
8.3 System Examples
8.3.1 USB 3.1 only (USB/DP Alternate Mode)
The TUSB1044 is in USB3.1 only when the CTL1 pin is low and CTL0 pin is high.
USB/DP Source (USB
Only ± No Flip)
USB/DP Sink
(USB Only ± No Flip)
D+/-
D+/-
TUSB1044
UTX2
DTX2
TX1
UTX1
DTX1
TX1
RX1
URX1
DRX1
RX1
AUXp
SBU1
AUXn
SBU2
Type t C Receptacle
DRX2
Type t C Receptacle
USB/DP
Source
TUSB1044
Type-C Cable
URX2
TX1
URX2
DRX2
TX1
RX1
UTX2
DTX2
RX1
UTX1
DTX1
URX1
DRX1
SBU2
AUXn
SBU1
AUXp
HPDIN
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
PD Controller
Control
USB/DP
Sink
CC1
CC1
CC2
CC2
HPD
PD Controller
DIR1/DIR0/CTL1/CTL0/FLIP = L/L/L/H/L
Control
DIR1/DIR0/CTL1/CTL0/FLIP = L/H/L/H/L
Figure 38. USB3.1 Only – No Flip
USB/DP Source (USB
Only ± Flip)
USB/DP Sink
(USB Only ± Flip)
D+/-
D+/-
TUSB1044
TUSB1044
DRX2
RX2
TX2
UTX2
DTX2
TX2
UTX1
DTX1
TX1
URX1
DRX1
AUXp
SBU1
AUXn
SBU2
USB/DP
Source
Type-C Cable
Type t C Receptacle
URX2
Type t C Receptacle
RX2
URX2
DRX2
UTX2
DTX2
RX2
UTX1
DTX1
RX2
TX2
URX1
DRX1
TX2
SBU2
AUXn
SBU1
AUXp
HPDIN
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
CC1
Control
DP/USB
Sink
PD Controller
CC2
HPD
CC1
CC2
DIR1/DIR0/CTL1/CTL0/FLIP = L/L/L/H/H
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = L/H/L/H/H
Figure 39. USB3.1 Only – With Flip
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
49
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
System Examples (continued)
8.3.2 USB3.1 and 2 lanes of DisplayPort
USB/DP Source
(USB + 2 Lane DP ± No Flip)
D+/-
D+/-
TUSB1044
TUSB1044
URX2
DRX2
ML1
UTX2
DTX2
TX2
TX1
UTX1
DTX1
TX1
RX1
URX1
DRX1
AUXp
AUXp
SBU1
SBU1
AUXn
AUXn
SBU2
SBU2
Type-C Cable
RX2
RX1
Type t C Receptacle
ML0
Type t C Receptacle
USB/DP
Source
USB/DP Sink
(USB + 2 Lane DP ± No Flip)
TX1
URX2
DRX2
RX1
UTX2
DTX2
RX2
UTX1
DTX1
TX2
URX1
DRX1
SBU1
SBU2
AUXn
SBU2
SBU1
AUXp
HPDIN
TX1
RX1
ML1
ML0
AUXn
AUXp
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
CC1
PD Controller
Control
USB/DP
Sink
HPD
CC1
PD Controller
CC2
CC2
Control
DIR1/DIR0/CTL1/CTL0/FLIP = L/H/H/H/L
DIR1/DIR0/CTL1/CTL0/FLIP = L/L/H/H/L
Figure 40. USB3.1 + 2 Lane DP – No Flip
USB/DP Source
(USB + 2 Lane DP ± Flip)
D+/-
D+/-
TUSB1044
TUSB1044
RX2
URX2
DRX2
RX2
TX2
UTX2
DTX2
TX2
ML1
UTX1
DTX1
TX1
ML0
URX1
DRX1
RX1
AUXp
AUXp
SBU1
AUXn
AUXn
SBU2
Type-C Cable
URX2
DRX2
RX1
UTX2
DTX2
RX2
UTX1
DTX1
TX2
URX1
DRX1
SBU1
SBU1
SBU2
AUXn
SBU2
SBU2
SBU1
AUXp
Type t C Receptacle
TX1
Type t C Receptacle
USB/DP
Source
USB/DP Sink
(USB + 2 Lane DP ± Flip)
ML0
ML1
RX2
TX2
AUXn
HPDIN
AUXp
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
Control
USB/DP
Sink
PD Controller
CC1
CC1
CC2
CC2
DIR1/DIR0/CTL1/CTL0/FLIP = L/L/H/H/H
HPD
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = L/H/H/H/H
Figure 41. USB 3.1 + 2 Lane DP – Flip
50
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
System Examples (continued)
8.3.3 DisplayPort Only
USB/DP Source
(4 Lane DP ± No Flip)
D+/-
D+/-
TUSB1044
TUSB1044
ML0
URX2
DRX2
RX2
ML1
UTX2
DTX2
ML2
UTX1
ML3
URX1
AUXp
AUXp
SBU1
SBU1
AUXn
AUXn
SBU2
SBU2
Type-C Cable
URX2
DRX2
TX2
RX1
UTX2
DTX2
DTX1
TX1
RX2
UTX1
DTX1
DRX1
RX1
TX2
URX1
DRX1
SBU1
SBU2
AUXn
SBU2
SBU1
AUXp
Type t C Receptacle
TX1
Type t C Receptacle
USB/DP
Source
USB/DP Sink
(4 Lane DP ± No Flip)
HPDIN
ML3
ML2
ML1
ML0
AUXn
AUXp
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
CC1
Control
USB/DP
Sink
PD Controller
HPD
CC1
PD Controller
CC2
CC2
Control
DIR1/DIR0/CTL1/CTL0/FLIP = L/H/H/L/L
DIR1/DIR0/CTL1/CTL0/FLIP = L/L/H/L/L
Figure 42. Four Lane DP – No Flip
USB/DP Source
(4 Lane DP ± Flip)
D+/-
D+/-
TUSB1044
TUSB1044
URX2
DRX2
ML2
UTX2
DTX2
TX2
TX1
Type-C Cable
RX2
ML1
UTX1
DTX1
ML0
URX1
DRX1
AUXp
AUXp
SBU1
SBU1
AUXn
AUXn
SBU2
SBU2
RX1
Type t C Receptacle
ML3
Type t C Receptacle
USB/DP
Source
USB/DP Sink
(4 Lane DP ± Flip)
TX1
URX2
DRX2
RX1
UTX2
DTX2
ML0
RX2
UTX1
DTX1
TX2
URX1
DRX1
SBU1
SBU2
AUXn
SBU2
SBU1
AUXp
ML1
ML2
ML3
HPDIN
AUXn
HPDIN
CC1
PD Controller
AUXp
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
Control
USB/DP
Sink
CC2
HPD
CC1
CC2
DIR1/DIR0/CTL1/CTL0/FLIP = L/L/H/
L/H
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = L/H/H/L/H
Figure 43. Four Lane DP – With Flip
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
51
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
System Examples (continued)
8.3.4 USB 3.1 only (USB/Custom Alternate Mode)
USB/Custom Source
(USB Only ± No Flip)
D+/-
D+/-
TUSB1044
TUSB1044
Type-C Cable
DRX2
UTX2
DTX2
TX1
UTX1
DTX1
TX1
RX1
URX1
DRX1
RX1
AUXp
SBU1
AUXn
SBU2
TX1
URX2
DRX2
TX1
RX1
UTX2
DTX2
RX1
UTX1
DTX1
URX1
DRX1
SBU2
AUXn
SBU1
AUXp
Type t C Receptacle
URX2
Type t C Receptacle
USB/Custom
Source
USB/Custom Sink
(USB Only ± No Flip)
HPDIN
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
PD Controller
Control
USB/Custom
Sink
CC1
CC1
CC2
CC2
HPD
PD Controller
DIR1/DIR0/CTL1/CTL0/FLIP = H/L/L/H/L
Control
DIR1/DIR0/CTL1/CTL0/FLIP = H/H/L/H/L
Figure 44. USB3.1 Only – No Flip
USB/Custom Source
(USB Only ± Flip)
USB/Custom Sink
(USB Only ± Flip)
D+/-
D+/-
TUSB1044
TUSB1044
RX2
URX2
DRX2
RX2
TX2
UTX2
DTX2
TX2
UTX1
DTX1
TX1
URX1
DRX1
AUXp
AUXn
DRX2
UTX2
DTX2
RX2
UTX1
DTX1
RX2
TX2
URX1
DRX1
TX2
SBU1
SBU2
AUXn
SBU2
SBU1
AUXp
Type t C Receptacle
URX2
Type t C Receptacle
USB/Custom
Source
Type-C Cable
HPDIN
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
Control
Custom/USB
Sink
PD Controller
CC1
CC1
CC2
CC2
DIR1/DIR0/CTL1/CTL0/FLIP = H/L/L/H/H
HPD
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = H/H/L/H/H
Figure 45. USB3.1 Only – With Flip
52
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
System Examples (continued)
8.3.5 USB3.1 and 1 Lane of Custom Alt Mode
USB/Custom Sink
(USB + 1 Lane Custom ± No Flip)
USB/Custom Source
(USB + 1 Lane Custom ± No Flip)
D+/-
TUSB1044
TUSB1044
URX2
DRX2
RX2
TX2
UTX2
DTX2
TX2
TX1
UTX1
DTX1
TX1
RX1
URX1
DRX1
RX1
AUXp
AUXp
SBU1
AUXn
AUXn
SBU2
Type-C Cable
Type t C Receptacle
RX2
Type t C Receptacle
USB/Custom
Source
D+/-
TX1
URX2
DRX2
RX1
UTX2
DTX2
RX2
UTX1
DTX1
TX2
URX1
DRX1
SBU2
AUXn
SBU1
AUXp
SBU1
SBU1
SBU2
SBU2
HPDIN
TX1
RX1
RX2
TX2
AUXn
AUXp
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
CC1
Control
USB/Custom
Sink
PD Controller
HPD
CC1
PD Controller
CC2
CC2
DIR1/DIR0/CTL1/0/FLIP = H/L/H/H/L
Control
DIR1/DIR0/CTL1/0/FLIP = H/H/H/H/L
Figure 46. USB3.1 + 1 Lane Custom Alt Mode – No Flip
USB/Custom Source
(USB + 1 Lane Custom ± Flip)
D+/-
D+/-
TUSB1044
TUSB1044
URX2
DRX2
TX2
UTX2
DTX2
TX2
Type-C Cable
RX2
Type t C Receptacle
RX2
Type t C Receptacle
USB/Custom
Source
USB/Custom Sink
(USB + 1 Lane Custom ± Flip)
TX1
URX2
DRX2
RX1
UTX2
DTX2
RX2
UTX1
DTX1
TX2
URX1
DRX1
TX1
UTX1
DTX1
TX1
RX1
URX1
DRX1
RX1
AUXp
AUXp
SBU1
SBU1
SBU1
SBU2
AUXn
AUXn
AUXn
SBU2
SBU2
SBU2
SBU1
AUXp
TX1
RX1
RX2
TX2
AUXn
HPDIN
AUXp
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
CC1
HPD
Control
USB/Custom
Sink
PD Controller
CC2
HPD
CC1
CC2
DIR1/DIR0/CTL1/0/FLIP = H/L/H/H/H
PD Controller
Control
DIR1/DIR0/CTL1/0/FLIP = H/H/H/H/H
Figure 47. USB 3.1 + 1 Lane Custom Alt. Mode – Flip
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
53
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
System Examples (continued)
8.3.6 USB3.1 and 2 Lane of Custom Alt Mode
USB/Custom Source
(USB + 2 Lane Custom ± No Flip)
D+/-
D+/-
TUSB1044
TUSB1044
URX2
DRX2
LN1
UTX2
DTX2
TX2
TX1
UTX1
DTX1
TX1
RX1
URX1
DRX1
RX1
AUXp
AUXp
SBU1
SBU1
AUXn
AUXn
SBU2
SBU2
Type-C Cable
RX2
Type t C Receptacle
LN0
Type t C Receptacle
USB/Custom
Source
USB/Custom Sink
(USB + 2 Lane Custom ± No Flip)
TX1
URX2
DRX2
RX1
UTX2
DTX2
RX2
UTX1
DTX1
TX2
URX1
DRX1
SBU1
SBU2
AUXn
SBU2
SBU1
AUXp
HPDIN
TX1
RX1
LN1
LN0
AUXn
AUXp
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
CC1
Control
USB/Custom
Sink
PD Controller
HPD
CC1
PD Controller
CC2
CC2
DIR1/DIR0/CTL1/CTL0/FLIP = H/L/H/H/L
Control
DIR1/DIR0/CTL1/CTL0/FLIP = H/H/H/H/L
Figure 48. Two Lane Custom Alternate Mode – No Flip
USB/Custom Source
(USB + 2 Lane Custom ± Flip)
D+/-
D+/-
TUSB1044
TUSB1044
RX2
URX2
DRX2
RX2
TX2
UTX2
DTX2
TX2
LN1
UTX1
DTX1
TX1
LN0
URX1
DRX1
RX1
AUXp
AUXp
SBU1
AUXn
AUXn
SBU2
Type-C Cable
URX2
DRX2
RX1
UTX2
DTX2
RX2
UTX1
DTX1
TX2
URX1
DRX1
SBU1
SBU1
SBU2
AUXn
SBU2
SBU2
SBU1
AUXp
Type t C Receptacle
TX1
Type t C Receptacle
USB/Custom
Source
USB/Custom Sink
(USB + 2 Lane Custom ± Flip)
LN0
LN1
RX2
TX2
AUXn
HPDIN
AUXp
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
CC1
Control
USB/Custom
Sink
PD Controller
CC2
HPD
CC1
CC2
DIR1/DIR0/CTL1/CTL0/FLIP = H/L/H/H/H
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = H/H/H/H/H
Figure 49. Two Lane Custom Alternate Mode – With Flip
54
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
System Examples (continued)
8.3.7 USB3.1 and 4 Lane of Custom Alt Mode
USB/Custom Source
(4 Lane Custom ± No Flip)
D+/-
D+/-
TUSB1044
TUSB1044
LN0
URX2
DRX2
RX2
LN1
UTX2
DTX2
TX2
LN2
UTX1
DTX1
TX1
LN3
URX1
DRX1
RX1
AUXp
AUXp
SBU1
AUXn
AUXn
SBU2
Type-C Cable
URX2
DRX2
RX1
UTX2
DTX2
RX2
UTX1
DTX1
TX2
URX1
DRX1
SBU1
SBU1
SBU2
AUXn
SBU2
SBU2
SBU1
AUXp
Type t C Receptacle
TX1
Type t C Receptacle
USB/Custom
Source
USB/Custom Sink
(4 Lane Custom ± No Flip)
HPDIN
LN3
LN2
LN1
LN0
AUXn
AUXp
HPDIN
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
Control
USB/Custom
Sink
PD Controller
CC1
CC1
CC2
CC2
HPD
PD Controller
DIR1/DIR0/CTL1/CTL0/FLIP = H/L/H/L/L
Control
DIR1/DIR0/CTL1/CTL0/FLIP = H/H/H/L/L
Figure 50. Four Lane Custom Alternate Mode – No Flip
USB/Custom Source
(4 Lane Custom ± Flip)
D+/-
D+/-
TUSB1044
TUSB1044
LN3
URX2
DRX2
RX2
LN2
UTX2
DTX2
TX2
LN1
UTX1
DTX1
TX1
LN0
URX1
DRX1
RX1
AUXp
AUXp
SBU1
AUXn
AUXn
SBU2
Type-C Cable
URX2
DRX2
RX1
UTX2
DTX2
RX2
UTX1
DTX1
TX2
URX1
DRX1
SBU1
SBU1
SBU2
AUXn
SBU2
SBU2
SBU1
AUXp
Type t C Receptacle
TX1
Type t C Receptacle
USB/Custom
Source
USB/Custom Sink
(4 Lane Custom ± Flip)
LN0
LN1
LN2
LN3
HPDIN
AUXn
HPDIN
PD Controller
AUXp
FLIP 0 1 CTL
FLIP 0 1 CTL
HPD
Control
USB/Custom
Sink
CC1
CC1
CC2
CC2
DIR1/DIR0/CTL1/CTL0/FLIP = H/L/H/L/H
HPD
PD Controller
Control
DIR1/DIR0/CTL1/CTL0/FLIP = H/H/H/L/H
Figure 51. Four Lane Custom Alternate Mode – With Flip
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
55
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
9 Power Supply Recommendations
The TUSB1044 is designed to operate with a 3.3-V power supply. Levels above those listed in the table should
not be used. If using a higher voltage system power supply, a voltage regulator can be used to step down to 3.3
V. Decoupling capacitors should be used to reduce noise and improve power supply integrity. A 0.1-µF capacitor
should be used on each power pin.
56
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
10 Layout
10.1 Layout Guidelines
1.
2.
3.
4.
5.
6.
RXP/N and TXP/N pairs should be routed with controlled 90-Ω differential impedance (± 15%).
Keep away from other high speed signals.
Intra-pair routing should be kept to within 2 mils.
Length matching should be near the location of mismatch.
Each pair should be separated at least by 3 times the signal trace width.
The use of bends in differential traces should be kept to a minimum. When bends are used, the number of
left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This
will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on
EMI.
7. Route all differential pairs on the same of layer.
8. The number of VIAS should be kept to a minimum. It is recommended to have no more than 1 VIA between
TUSB1044 and Type-C connector and no more than 1 VIA between TUSB1044 and USB3.1 Device/Host.
9. Keep traces on layers adjacent to ground plane.
10. Do NOT route differential pairs over any plane split.
11. Adding Test points will cause impedance discontinuity; and therefore, negatively impacts signal
performance. If test points are used, the test points should be placed in series and symmetrically. The test
points must not be placed in a manner that causes a stub on the differential pair.
12. Assuming 1 dB/inch loss at 5 GHz, the trace length between TUSB1044 and Type-C connector should be
no more than 1.5 inches.
13. Assuming 1 dB/inch loss at 5 GHz, the trace length between TUSB1044 and the USB 3.1 Host/Device
should be no more than 8 inches.
14. ESD protection devices and EMI suppression devices need to be carefully selected and have to have
excellent transient performance at 10 Gbps with flat shunt capacitance characteristics over ±650 mV voltage
range. Note small-signal insertion loss characteristics are insufficient to determine suitability of non-linear
devices (ESD devices) for 10Gbps operation
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
57
TUSB1044
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
www.ti.com
10.2 Layout Example
DRX2
UTX2
DTX2
GND
DTX1
URX1
DRX1
SBU
UTX1
To USB Type-C
Receptacle
URX2
AUX
To USB Host/GPU
AC Coupling
capacitors
Figure 52. Example Layout
58
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
TUSB1044
www.ti.com
SLLSF47C – FEBRUARY 2018 – REVISED OCTOBER 2018
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
The documents identified in this section are referenced within this specification. Most references with the text will
use a document tag, identified as [Document Tag], instead of the complete document title to simplify the text.
For related documentation see the following:
• [USB31] Universal Serial Bus 3.1 Specification.
• [TYPEC] Universal Serial Bus Type C Cable and Connector Specification
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TUSB1044
59
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TUSB1044IRNQR
ACTIVE
WQFN
RNQ
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TUSB44
TUSB1044IRNQT
ACTIVE
WQFN
RNQ
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TUSB44
TUSB1044RNQR
ACTIVE
WQFN
RNQ
40
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
TUSB44
TUSB1044RNQT
ACTIVE
WQFN
RNQ
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
TUSB44
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Oct-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TUSB1044IRNQR
WQFN
RNQ
40
TUSB1044IRNQT
WQFN
RNQ
TUSB1044RNQR
WQFN
RNQ
TUSB1044RNQT
WQFN
RNQ
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
4.3
6.3
1.1
8.0
12.0
Q2
40
250
180.0
12.4
4.3
6.3
1.1
8.0
12.0
Q2
40
3000
330.0
12.4
4.3
6.3
1.1
8.0
12.0
Q2
40
250
180.0
12.4
4.3
6.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Oct-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TUSB1044IRNQR
WQFN
RNQ
40
3000
367.0
367.0
35.0
TUSB1044IRNQT
WQFN
RNQ
40
250
210.0
185.0
35.0
TUSB1044RNQR
WQFN
RNQ
40
3000
367.0
367.0
35.0
TUSB1044RNQT
WQFN
RNQ
40
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RNQ0040A
WQFN - 0.8 mm max height
SCALE 2.500
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
A
B
PIN 1 INDEX AREA
4.1
3.9
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08
4.7±0.1
2X 4.4
(0.2) TYP
9
36X 0.4
20
8
EXPOSED
THERMAL PAD
21
2X
2.8
2.7±0.1
1
PIN 1 ID
(OPTIONAL)
28
29
40
40X
0.5
0.3
0.25
0.15
0.1
C A
0.05
40X
B
4222125/B 01/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.7)
2X (2.1)
6X (0.75)
40
29
40X (0.6)
1
28
40X (0.2)
4X
(1.1)
SYMM
(3.8)
(2.7)
36X (0.4)
8
21
(R0.05) TYP
9
20
SYMM
( 0.2) TYP
VIA
(5.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222125/B 01/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (1.5)
40
29
40X (0.6)
1
28
40X (0.2)
6X
(0.695)
SYMM
(3.8)
6X
(1.19)
36X (0.4)
8
21
(R0.05) TYP
METAL
TYP
9
6X (1.3)
20
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
73% PRINTED SOLDER COVERAGE BY AREA
SCALE:18X
4222125/B 01/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising