Texas Instruments | DS90C187 Low Power, 1.8-V Dual Pixel FPD-Link (LVDS) Serializer (Rev. C) | Datasheet | Texas Instruments DS90C187 Low Power, 1.8-V Dual Pixel FPD-Link (LVDS) Serializer (Rev. C) Datasheet

Texas Instruments DS90C187 Low Power, 1.8-V Dual Pixel FPD-Link (LVDS) Serializer (Rev. C) Datasheet
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DS90C187
SNLS401C – FEBRUARY 2012 – REVISED SEPTEMBER 2018
DS90C187 Low Power, 1.8-V Dual Pixel FPD-Link (LVDS) Serializer
1 Features
3 Description
•
The DS90C187 is a low power Serializer for portable
battery powered that reduces the size of the RGB
interface between the host GPU and the Display.
1
•
•
•
•
•
•
•
•
•
•
•
100 mW Typical Power Consumption at 185 MHz
(SIDO Mode)
Drives QXGA and WQXGA Class Displays
Three Operating Modes:
– Single Pixel In, Single Pixel Out (SISO): 105
MHz Maximum
– Single Pixel In, Dual Pixel Out (SIDO): 185
MHz Maximum
– Dual Pixel In, Dual Pixel Out (DIDO): 105MHz
Supports 24-Bit RGB, 48-Bit RGB
Optional low Power Mode Supports 18-Bit RGB,
36-Bit RGB
Supports 3D+C, 4D+C, 6D+C, 6D+2C, 8D+C, and
8D+2C LVDS Configurations
Compatible With FPD-Link Deserializers
Operates Off a Single 1.8-V Supply
Interfaces Directly With 1.8-V LVCMOS
Less Than 1 mW Power Consumption in Sleep
Mode
Spread Spectrum Clock Compatible
Small 7-mm × 7-mm × 0.9-mm 92-Pin Dual Row
VQFN Package
2 Applications
•
•
•
•
Camera Monitor Systems (CMS)
Automotive Head Units
Smart Mirrors
Cluster
The DS90C187 Serializer is designed to support dual
pixel data transmission between a Host and a Flat
Panel Display at resolutions of up to QXGA
(2048x1536) at 60 Hz. The transmitter converts up to
48 bits (Dual Pixel 24-bit color) of 1.8-V LVCMOS
data into two channels of 4 data + clock (4D+C)
reduced width interface LVDS compatible data
streams.
DS90C187 supports 3 modes of operation.
• In single pixel mode in/out mode, the device can
drive up to SXGA+ (1400x1050) at 60 Hz. In this
mode, the device converts one bank of 24-bit
RGB data to a one channel 4D+C LVDS data
stream.
• In single pixel in / dual pixel out mode, the device
can drive up to WUXGA+ (1920x1440) at 60 Hz.
In this configuration, the device provides single-todual pixel conversion and converts one bank of
24-bit RGB data into two channels of 4D+C LVDS
streams at half the pixel clock rate.
In dual pixel in / dual pixel out mode, the device can
drive up to QXGA 2048x1536 at 60Hz or up to
QSXGA 2560x2048 at 30Hz. In this mode, the device
converts 2 channels of 24 bit RGB data into 2
channels of 4D+C LVDS streams. For all the modes,
the device supports 18bpp and 24bpp color.
Device Information(1)
PART NUMBER
PACKAGE
DS90C187
BODY SIZE (NOM)
VQFN-MR (92)
7.00 mm × 7.00 mm
(1) For all available packages, see the order addendum at the
end of the data sheet.
Typical Application
1.8 V LVCMOS
(24 bit RGB + HS/VS/DE)
Typical Application
1.8 V LVCMOS
(24 bit RGB + HS/VS/DE)
2 Channels FPD-Link (LVDS)
(4 Data + Clock)
1.8 V
GPU
DS90C187
Single Pixel
R[7:0] G[7:0]
B[7:0]
GPU ± Jacinto 6
Single Pixel
R[7:0] G[7:0]
B[7:0]
DS90C187
L
A
T
C
H
&
LVDS
4D+C
(even pixel)
&
P
2
S
HS
VS
DE
GPO/CNTL (L/R)
PCLK
Display (TCON)
LVDS
4D+C
(odd pixel)
L
A
T
C
H
2 Channels OLDI (LVDS)
(4 Data + Clock)
2 Lanes FPD-Link III
1.8 V
DS90UB947
-Q1 SER
Display (TCON)
DOUT0+
DOUT0-
RIN0+
RIN0-
DOUT1+
DOUT1-
RIN1+
RIN1-
FPD-Link III
Interface
P
2
S
HS
VS
DE
GPO/CNTL (L/R)
PCLK
PLL
PDB
PLL
PDB
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90C187
SNLS401C – FEBRUARY 2012 – REVISED SEPTEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
Recommended Input Characteristics........................ 7
Switching Characteristics .......................................... 7
AC Timing Diagrams................................................. 8
Typical Characteristics ............................................ 11
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagrams ..................................... 12
8.3 Device Functional Modes........................................ 15
8.4 Programming........................................................... 17
9
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application ................................................. 24
10 Power Supply Recommendations ..................... 26
10.1 Power Up Sequence ............................................. 26
10.2 Power Supply Filtering .......................................... 26
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 28
12 Device and Documentation Support ................. 29
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2013) to Revision C
Page
•
Added Device Information table, Device Comparison table, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1
•
Added Start Up / Phase Lock Loop Set Time timing diagram ............................................................................................... 9
•
Added content to the Power Up Sequence section ............................................................................................................. 26
Changes from Revision A (April 2013) to Revision B
•
2
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 1
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SNLS401C – FEBRUARY 2012 – REVISED SEPTEMBER 2018
5 Description (continued)
The DS90C187 is offered in a small 92 pin dual row VQFN package and features single 1.8 V supply for minimal
power dissipation.
6 Pin Configuration and Functions
A39
OA_0 INA_0
INA_1
INA_2
INA_3
INA_4
INA_5
INA_6
INA_9
INA_7
INA_8
INB_9
A1
INB_10
OA_1 -
OA_2 -
INB_11
OA_2 +
INA_11
INB_12
OA_C INA_12
OA_C +
INA_13
OA_3 +
INB_13
OA_3 -
DS90C187
TOP VIEW
(not to scale)
IN_CLK
INA_14
INB_14
OB_0 OB_0 +
OB_1 OB_1 +
INA_15
DAP = GND
INB_15
OB_2 OB_2 +
INA_16
OB_C -
INB_16
OB_C +
INA_17
INB_17
18B
VDDTX
HS
OB_3 -
RSVD
OB_3 +
B20
B21
GND
MODE0
VDD
MODE1
A27
RFB
INA_27
INB_27
INB_26
INA_26
INA_25
INB_25
INB_24
INA_24
INA_23
INB_23
INB_22
INB_21
GND
B12
VDD
VDDP
A12
RSVD
DE
INA_21
RSVD
INA_22
VS
A13
B31
OA_1 +
INA_10
B11
A38
OA_0 +
A26
B1
N/C
PDB
VODSEL
B32
INB_0
INB_1
INB_2
INB_3
INB_4
INB_5
INB_6
INB_7
B40
INB_8
VDD
GND
A52
NLA Package
92-Pin VQFN-MR
Top View
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DS90C187 Pin Descriptions — Serializer
NAME
PIN NO.
I/O
DESCRIPTION
1.8-V LVCMOS VIDEO INPUTS
INA_[27:21]
INA_[17:9]
NA_[8:0]
B19-B13,
B9-B1,
B40-B32
I
Channel A Data Inputs
Typically consists of 8 Red, 8 Green, 8 Blue and a general purpose or L/R control
bit.
Includes pull down.
INB_[27:21]
INB_[17:14],
INB_[13:9]
INB_[8:0
A23-A17,
A10-A7,
A5-A1,
A50-A42
I
Channel B Data Inputs
Typically consists of 8 Red, 8 Green, 8 Blue and a general purpose or L/R control
bit.
Includes pull down.
HS (INA_18),
VS (INA_19),
DE (INA_20)
B10,
B11
B12
I
Video Control Signal Inputs HS = Horizontal Sync, VS = Vertical SYNC, and DE = Data Enable
A6
I
Pixel Input Clock
Includes pull down.
IN_CLK
1.8-V LVCMOS CONTROL INPUTS
MODE0,
MODE1
B20,
A25
I
Mode Control Input (MODE0)
00 = Single In / Single Out
01 = Single In / Dual Out
10 = Dual In / Dual Out
11 = Reserved
Includes pull down.
RFB
A24
I
Rising / Falling Clock Edge Select Input 0 = Falling Edge, 1 = Rising Edge
Includes pull down.
PDB
A40
I
Power Down (Sleep) Control Input 0 = Sleep (Power Down mode), 1 = device active (enabled)
Includes pull down.
18B
A29
I
18 bit / 24 bit Control Input 0 = 24 bit mode,
1 = 18 bit mode
Includes pull down.
VODSEL
A41
I
VOD Level Select Input 0 = Low swing, 1 = Normal swing
Includes pull down.
N/C
RSVD
A39
I
no connect pin — leave open
A11, A12, A16
I
Reserved - Tie to Ground.
B28,
A35
O
Channel A LVDS Output Clock —
Expects 100 Ω DC load.
B27, B29-B31
A34, A36-A38
O
Channel A LVDS Output Data —
Expects 100 Ω DC load.
B23,
A30
O
Channel B LVDS Output Clock —
Expects 100 Ω DC load.
B21, B24-B26
A28, A16-A33
O
Channel B LVDS Output Data —
Expects 100 Ω DC load.
B22
P
Power supply for LVDS Drivers, 1.8V.
A14, A26, A51
P
Power supply pin for core, 1.8V.
LVDS OUTPUTS
OA_C+
OA_COA_[3:0]+,
OA_[3:0]OB_C+,
OB_COB_[3:0]+,
OB_[3:0]-
POWER AND GROUND
VDDTX
VDD
VDDP
A13
P
Power supply pin for PLL, 1.8V.
GND
A15, A27, A52
G
Ground pins.
DAP
DAP
G
Connect DAP to Ground plane.
4
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SNLS401C – FEBRUARY 2012 – REVISED SEPTEMBER 2018
7 Specifications
7.1 Absolute Maximum Ratings
(1)
See
MIN
MAX
UNIT
Supply Voltage (VCC)
−0.3
2.5
V
LVCMOS Input Voltage
−0.3
VDD + 0.3
V
LVDS Driver Output Voltage
−0.3
3.6
V
150
°C
150
°C
LVDS Output Short-Circuit
Duration
Continuous
Junction Temperature
−65
Storage Temperature (Tstg)
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±8000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1250
Machine model
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. [Following
sentence optional; see the wiki.] Manufacturing with less than 500-V HBM is possible with the necessary precautions. [Following
sentence optional; see the wiki.] Pins listed as ±XXX V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. [Following
sentence optional; see the wiki.] Manufacturing with less than 250-V CDM is possible with the necessary precautions. [Following
sentence optional; see the wiki.] Pins listed as ±YYY V may actually have higher performance.
7.3 Recommended Operating Conditions
Supply Voltage
Operating Free Air
Temperature (TA)
MIN
NOM
MAX
1.71
1.80
1.89
V
−10
+25
+70
°C
80
100
Differential Load Impedance
Supply Noise Voltage
UNIT
120
Ω
<90
mVp-p
7.4 Thermal Information
DS90C187
THERMAL METRIC
(1)
NLA (VQFN-MR)
UNIT
92 PINS
RθJA
Junction-to-ambient thermal resistance (2)
RθJC(top)
Junction-to-case (top) thermal resistance
°C/W
RθJB
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
°C/W
ψJB
Junction-to-board characterization parameter
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
°C/W
(1)
(2)
35.1
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Above +22°C
7.5 Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS DC SPECIFICATIONS
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIH
High Level Input Voltage
0.65VDD
VDD
VIL
Low Level Input Voltage
GND
0.35VDD
V
IIN
Input Current
µA
VIN = 0V or VDD = 1.71 V to 1.89 V
–10
±1
+10
VODSEL = VIH
160
(320)
300
(600)
450
(900)
mV
(mVP-P)
VODSEL = VIL
110
(220)
180
(360)
300
(600)
mV
(mVP-P)
LVDS DRIVER DC SPECIFICATIONS
VOD
Differential Output Voltage
RL = 100Ω
Figure 3
ΔVOD
Change in VOD between
Complimentary Output States
RL = 100Ω
Figure 3
VOS
Offset Voltage
RL = 100Ω
Figure 3
ΔVOS
Change in VOS between
Complimentary Output States
RL = 100Ω
Figure 3
IOS
Output Short Circuit Current
VOUT = GND, VODSEL = VDD
50
mV
1.0
V
50
mV
−35
−25
mA
f = 105 MHz,
MODE[1:0] = 00
(SISO)
60
85
mA
f = 185 MHz,
MODE[1:0] = 01
(SIDO)
95
140
mA
f = 105 MHz,
MODE[1:0] = 10
(DIDO)
100
150
mA
18B = VIL,
VODSEL = VIL,
VDD = 1.8
55
mA
18B = VIL,
VODSEL = VIH,
VDD = 1.8
75
mA
18B = VIH,
VODSEL = VIL,
VDD = 1.8
49
mA
18B = VIH,
VODSEL = VIH,
VDD = 1.8
65
mA
18B = VIL,
VODSEL = VIL,
VDD = 1.8
53
mA
18B = VIL,
VODSEL = VIH,
VDD = 1.8
71
mA
18B = VIH,
VODSEL = VIL,
VDD = 1.8
48
mA
18B = VIH,
VODSEL = VIH,
VDD = 1.8
63
mA
0.8
-45
0.9
SUPPLY CURRENT
IDDT1
IDDT2
Serializer Worst Case Supply
Current (includes load current)
IDDT3
IDDTP
IDDTG
IDDZ
6
Serializer Supply Current PRBS-7
Serializer Supply Current 16
Grayscale
Power Down Supply Current
Checkerboard
pattern,
RL = 100 Ω,
18B = VIL,
VODSEL = VIH,
VDD = 1.89 V,
Figure 1
MODE[1:0] = 01
(SIDO),
f = 150 MHz,
RL = 100 Ω,
PRBS-7 Pattern
Figure 12
MODE[1:0] = 01
(SIDO),
f = 150 MHz,
RL = 100 Ω,
16 Grayscale
Pattern
PDB = GND
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18
200
µA
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7.6 Recommended Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
MIN
TYP
MAX
UNIT
T
4
ns
2
ns
IN_CLK Transition Time
Figure 5
MODE[1:0] = 00 or 10
1
MODE[1:0] = 01
1
TCIP
IN_CLK Period
Figure 6
MODE[1:0] = 00 or 10
9.53
T
40
ns
MODE[1:0] = 01
5.40
T
20
ns
TCIH
IN_CLK High Time
See Figure 6
0.35T
0.5T
0.65T
ns
TCIL
IN_CLK Low Time
See Figure 6
0.35T
0.5T
0.65T
ns
TXIT
INA_x & INB_x Transition Time
See Figure 5
1.5
0.3T
ns
MAX
UNIT
TCIT
7.7 Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
MIN
TYP
TSTC
INn_x Setup to IN_CLK
See Figure 6
0
ns
THTC
INn_x Hold from IN_CLK
See Figure 6
2.5
ns
LLHT
LVDS Low-to-High Transition Time
Figure 4 (1)
0.18
LHLT
LVDS High-to-Low Transition Time
Figure 4 (1)
0.18
TBIT
LVDS Output Bit Width
TPPOS0
Transmitter Output Pulse Positions Normalized
for Bit 0
TPPOS1
0.5
0.5
ns
ns
MODE[1:0] = 00, or 10
1/7 TCIP
ns
MODE[1:0] = 01
2/7 TCIP
ns
See Figure 9
1
UI
Transmitter Output Pulse Positions Normalized
for Bit 1
See Figure 9
2
UI
TPPOS2
Transmitter Output Pulse Positions Normalized
for Bit 2
See Figure 9
3
UI
TPPOS3
Transmitter Output Pulse Positions Normalized
for Bit 3
See Figure 9
4
UI
TPPOS4
Transmitter Output Pulse Positions Normalized
for Bit 4
See Figure 9
5
UI
TPPOS5
Transmitter Output Pulse Positions Normalized
for Bit 5
See Figure 9
6
UI
TPPOS6
Transmitter Output Pulse Positions Normalized
for Bit 6
See Figure 9
7
UI
ΔTPPOS
Variation in Transmitter Pulse Position (Bit 6 —
Bit 0)
See Figure 9
±0.06
UI
TCCS
LVDS Channel to Channel Skew
110
ps
TJCC
Jitter Cycle-to-Cycle
MODE0, MODE1 = 0,
f = 105 MHz,
TPLLS
Phase Lock Loop Set (Enable Time)
Figure 7
TPDD
Powerdown Delay
TSD
Latency Delay
(1)
Figure 8
(2)
MODE0 = 0,
MODE1 = 1 or 0
Figure 10
(1)
TLAT
MODE0 = 1,
Latency Delay for Single Pixel In / Dual Pixel Out MODE1 = 0
Mode
Figure 10
(1)
(1)
(2)
0.028
0.035
UI
1
ms
100
ns
ns
2*TCIP +
10.54
2*TCIP +
13.96
9*TCIP +
4.19
9*TCIP +
6.36
ns
Parameter is ensured by characterization and is not tested at final test.
Parameter is ensured by design and is not tested at final test.
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7.8 AC Timing Diagrams
T
IN_CLK
INn_x,
n = A or B,
x = ODD
INn_x,
n = A or B,
x = EVEN
Falling Edge CLK (RFB = GND) shown
A.
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/ I/O.
B.
Figure 1 and Figure 2 show a falling edge data strobe (IN_CLK).
Figure 1. Checker Board Test Pattern
Signal
Signal Pattern
Signal Frequency
f
PCLK
R0
f / 16
R1
f/8
R2
f/4
R3
f/2
R4
Steady State, Low
R5
Steady State, Low
G0
f / 16
G1
f/8
G2
f/4
G3
f/2
G4
Steady State, Low
G5
Steady State, Low
B0
f / 16
B1
f/8
B2
f/4
B3
f/2
B4
Steady State, Low
B5
Steady State, Low
HS
Steady State, High
VS
Steady State, High
DE
Steady State, High
A.
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/ I/O.
B.
Recommended pin to signal mapping for 18 bits per pixel, customer may choose to define differently. The 16
grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
C.
Figure 2 shows a falling edge data strobe (IN_CLK).
Figure 2. “16 Gray Scale” Test Pattern (Falling Edge Clock shown)
8
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AC Timing Diagrams (continued)
OA/B_C+, OA/B_[3:0]+
100:
OA/B_C-, OA/B_[3:0]-
Figure 3. DS90C187 (Transmitter) LVDS Output Load
+VOD
80%
80%
VSS = 2|VOD|
0V
20%
20%
-VOD
LLHT
LHLT
Figure 4. LVDS Output Transition Times
VDD
80%
80%
50%
20%
20%
GND
TCIT, or
TXIT
TCIT, or
TXIT
Figure 5. LVCMOS Input Transition Times
TCIP
TCIH
TCIL
VDD
50%
GND
VDD
VIHmin
TSTC
VILmax
50%
THTC
GND
Falling Edge CLK shown (RFB = GND)
Figure 6. LVCMOS Input Setup/Hold and Clock High/Low Times (Falling Edge Strobe)
1.8V
VDD
GND
VDD
IN_CLK
GND
VDD
PDB
GND
OCA/B
(Diff.)
TPLLS
(LVDS)
Figure 7. Start Up / Phase Lock Loop Set Time
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AC Timing Diagrams (continued)
GND
VDD
IN_CLK
GND
VDD
PDB
50%
GND
TPDD
OCA/B
(Diff.)
(LVDS)
Figure 8. Sleep Mode / Power Down Delay
Cycle N
OA_C+/-,
or OB_C+/-
OA[3:0]+/-, or
OB[3:0]+/-
bit 1
n-1
bit 0
n-1
bit 6
n
bit 5
n
bit 4
n
bit 3
n
bit 2
n
bit 1
n
bit 0
n
1UI
2UI
3UI
4UI
5UI
6UI
7UI
Figure 9. LVDS Serial Bit Positions
IN_CLK
INA/Bn
Pixel 1
Pixel 2
Pixel 3
Pixel 4
DE
TLAT
OA/B_C+/OA_n+/-
Pixel 1
Pixel 3
OB_n+/-
Pixel 2
Pixel 4
Figure 10. Single In Dual Out Mode Timing and Latency
IN_CLK
INA/B
Pixel n-1
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
TSD
OA/B_C+/Pixel n
OA/B_n+/-
Pixel n+1
Figure 11. Single In Single Out / Dual In Dual Out Latency
10
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7.9 Typical Characteristics
110
VODSEL = L
VODSEL = H
55
90
50
80
45
IDD (mA)
IDD (mA)
100
60
VODSEL = L
VODSEL = H
70
60
40
35
50
30
40
25
30
20
40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
Figure 12. Typ Current Draw — Single In/Dual Out Mode —
PRBS-7 Data Pattern
20
40
60
80
100
FREQUENCY (MHz)
120
Figure 13. Typ Current Draw — Single In/Single Out Mode —
PRBS-7 Data Pattern
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8 Detailed Description
8.1 Overview
DS90C187 converts a wide parallel LVCMOS input bus into banks of FPD-Link LVDS data. The device can be
configured to support RGB-888 (24-bit color) or RGB-666 (18 bit color) in three main configurations: single pixel
in / single pixel out; single pixel in / dual pixel out; dual pixel in / dual pixel out. The DS90C187 has several
power saving features including: selectable VOD, 18 bit / 24 bit mode select, and a power down pin control.
8.2 Functional Block Diagrams
RED
INA[27:21],
INA[17:0]
GREEN
BLUE
CNTRL (L/R)
HS
VS
DE
IN_CLK
LVCMOS PARALLEL TO LVDS
LVCMOS INPUTS
PLL
DATA (LVDS)
CLOCK (LVDS)
PDB
18B
VODSEL
RFB
MODE0
MODE1
DS90C187 ± SERIALIZER
Single Pixel In / Single Pixel Out
(SISO)
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Functional Block Diagrams (continued)
LVCMOS INPUTS
RED
INA[27:21],
INA[17:0]
GREEN
HS
VS
DE
IN_CLK
LVCMOS PARALLEL TO LVDS
BLUE
CNTRL (L/R)
PLL
DATA (LVDS)
CLOCK (LVDS)
PDB
18B
VODSEL
RFB
MODE0
MODE1
DS90C187 ± SERIALIZER
Single Pixel In / Dual Pixel Out (SIDO)
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Functional Block Diagrams (continued)
LVCMOS INPUTS
ODD_RED
INA[27:21],
INA[17:0]
ODD_GREEN
EVEN_RED
INB[27:21],
INB[17:0]
EVEN_GREEN
EVEN_BLUE
EVEN_CNTRL (L/R)
LVCMOS PARALLEL TO LVDS
ODD_BLUE
ODD_CNTRL (L/R)
DATA (LVDS)
HS
VS
DE
IN_CLK
PLL
CLOCK (LVDS)
PDB
18B
VODSEL
RFB
MODE0
MODE1
DS90C187 ± SERIALIZER
Dual Pixel In / Dual Pixel Out (SIDO)
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8.3 Device Functional Modes
8.3.1 Device Configuration
The MODE0 and MODE1 pins are used to configure the DS90C187 into the three main operation modes as
shown in the table below.
Table 1. Mode Configurations
MODE1
MODE0
0
0
CONFIGURATION
Single Pixel Input, Single Pixel Output (SISO)
0
1
Single Pixel Input, Dual Pixel Output (SIDO)
1
0
Dual Pixel Input, Dual Pixel Output (DIDO)
1
1
RESERVED
8.3.2 Single Pixel Input / Single Pixel Output
When MODE0 and MODE1 are both set to low, data from INA_[27:0], HS, VS and DE is serialized and driven
out on OA_[3:0]+/- with OA_C+/-. If 18B_MODE is LOW, then OA_3+/- is powered down and the corresponding
LVCMOS input signals are ignored.
In this configuration IN_CLK can range from 25 MHz to 105 MHz, resulting in a total maximum payload of 700
Mbps (28 bits * 25MHz) to 2.94 Gbps (28 bits * 105 MHz). Each LVDS driver will operate at a speed of 7 bits per
input clock cycle, resulting in a serial line rate of 175 Mbps to 735 Mbps. OA_C+/- will operate at the same rate
as IN_CLK with a duty cycle ratio of 57:43.
8.3.3 Single Pixel Input / Dual Pixel Output
When MODE0 is HIGH and MODE1 is LOW, data from INA_[27:0], HS, VS and DE is serialized and driven out
on OA_[3:0]+/- and OB_[3:0]+/- with OA_C+/- and OB_C+/-. If 18B_MODE is LOW, then OA_3+/- and OB_3+/are powered down and the corresponding LVCMOS input signals are ignored. The input LVCMOS data is split
into odd and even pixels starting with the odd (first) pixel outputs OA_[3:0]+/- and then the even (second) pixel
outputs OB_[3:0]+/-. The splitting of the data signals starts with DE (data enable) transitioning from logic LOW to
HIGH indicating active data (see Figure 10). The number of clock cycles during blanking must be an EVEN
number. This configuration will allow the user to interface with two FPD-Link receivers or other dual pixel inputs.
In this configuration IN_CLK can range from 50 MHz to 185 MHz, resulting in a total maximum payload of 1.4
Gbps (28 bits * 50 MHz) to 5.18 Gbps (28 bits * 185 MHz). Each LVDS driver will operate at a speed of 7 bits per
2 input clock cycles, resulting in a serial line rate of 175 Mbps to 647.5 Mbps. OA_C+/- and OA_B+/- will operate
at ½ the rate as IN_CLK with a duty cycle ratio of 57:43.
1. Disable the clock and data.
2. Toggle PDB to Low and then High.
3. After PDB settles reset the data pattern and enable the clock and data.
8.3.4 Dual Pixel Input / Dual Pixel Output
When MODE0 is LOW and MODE1 is set to HIGH, data from INA_[27:0], HS, VS and DE is serialized and
driven out on OA_[3:0]+/- with OA_C+/-, while data from INB_[27:0], HS, VS and DE is serializer and driven out
on OB_[3:0]+/- with OB_C+/-. If 18B_MODE is LOW, then OA_3+/- and OB_3+/- is powered down and the
corresponding LVCMOS input signals are ignored.
In this configuration IN_CLK can range from 25 MHz to 105 MHz, resulting in a total maximum payload of 1.325
Gbps (53 bits * 25 MHz) to 5.565 Gbps (53 bits * 105 MHz). Each LVDS driver will operate at a speed of 7 bits
per input clock cycle, resulting in a serial line rate of 175 Mbps to 735 Mbps. OA_C+/- and OB_C+/- will operate
at the same rate as IN_CLK with a duty cycle ratio of 57:43.
8.3.5 Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the input LVCMOS data is latched on. If RFB is HIGH, input data is
latched on the RISING EDGE of the pixel clock (IN_CLK). If RFB is LOW, the input data is latched on the
FALLING EDGE of the pixel clock. Note: This can be set independently of receiver’s output clock strobe.
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Table 2. Pixel Clock Edge
RFB
Result
0
FALLING edge
1
RISING edge
8.3.6 Power Management
The DS90C187 has several features to assist with managing power consumption. The device can be configured
through the MODE0 and MODE1 control pins to enable only the required number of LVDS drivers for each
application. The 18B_MODE pin allows the DS90C187 to power down the unused LVDS driver(s) for RGB-666
(18 bit color) applications for an additional level of power management. If no clock is applied to the IN_CLK pin,
the DS90C187 will enter a low power state. To place the DS90C187 in its lowest power state, the device can be
powered down by driving the PDB pin to LOW.
16
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8.3.7 Sleep Mode (PDB)
The DS90C187 provides a power down feature. When the device has been powered down, current draw through
the supply pins is minimized and the PLL is shut down. The LVDS drivers are also powered down with their
outputs pulled to GND through 100-Ω resistors (not tri-stated).
Table 3. Power Down Select
PDB
Result
0
SLEEP Mode (default)
1
ACTIVE (enabled)
8.3.8 LVDS Outputs
The DS90C187's LVDS drivers are compatible with ANSI/TIA/EIA-644-A LVDS receivers. The LVDS drivers can
output a power saving low VOD, or a high VOD to enable longer trace and cable lengths by configuring the
VODSEL pin.
Table 4. VOD Select
VODSEL
Result
0
±220 mV (440 mVpp)
1
±340 mV (680 mVpp)
Any unused LVDS outputs that are not powered down or put into TRI-STATE® due to the MODE0, MODE1, or
18B pins should be externally terminated differentially with a 100 ohm resistor. For example, when driving a
timing controller (TCON) that only requires an 8D + C LVDS interface, rather than 8D + 2C, the unused clock line
should be terminated near the package of the DS90C187. For more information regarding the output state of
unused LVDS drivers, refer to the next section, 18 bit / 24 bit Color Mode (18B). For more information regarding
the electrical characteristics of the LVDS outputs, refer to the LVDS DC Characteristics and LVDS Switching
Specifications.
8.3.9 18 bit / 24 bit Color Mode (18B)
The 18B pin can be used to further save power by powering down the 4th LVDS driver in each used bank when
the application requires only 18 bit color or 3D+C LVDS. Set the 18B pin to logic HIGH to TRI-STATE® OA_3+/and OB_3+/- (if the device is configured for dual pixel output). For 24 bit color applications this pin should be set
to logic LOW. Note that the power down function takes priority over the TRI-STATE® function. So if the device is
configured for 18 bit color Single Pixel In/Single Pixel Out, LVDS channel OB_3+/- will be powered down and not
TRI-STATE®. If an LVDS driver is powered down, each output terminal is pulled low by a 100 ohm resistor to
ground.
Table 5. Color DepthConfigurations
18B
Result
0
24bpp, LVDS 4D+C or 8D+2C
1
18bpp, LVDS 3D+C or 6D+2C
8.3.10 LVCMOS Inputs
The DS90C187 has two banks of 24 data inputs, one set of video control signal (HS, VS and DE) inputs and
several device configuration LVCMOS pins. All LVCMOS input pins are designed for 1.8 V LVCMOS logic. All
LVCMOS inputs, including clock, data and configuration pins, have an internal pull down resistor to set a default
state. If any inputs are unused, they can be left as no connect (NC) or connected to ground.
8.4 Programming
8.4.1 LVDS Interface / TFT Color Data Recommended Mapping
Different color mapping options exist. Check with the color mapping of the Deserializer / TCON device that is
used to ensure compatible mapping for the application. The DS90C187 supports three modes of operation for
single and dual pixel applications supporting either 24bpp or 18bpp color depths.
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Programming (continued)
In the Dual Pixel / 24bpp mode, eight LVDS data lines are provided along with two LVDS clock lines (8D+2C).
The Deserializer may utilize one or two clock lines. The 53 bit interface typically assigns 24 bits to RGB for the
odd pixel, 24 bits to RGB for the even pixel, 3 bits for the video control signals (HS, VS and DE), 1 bit for odd
pixel and 1 bit for even pixel which can be ignored or used for general purpose data, control or L/R signaling.
A reduced width input interface is also supported with a Single-to-Dual Pixel conversion where the data is
presented at double rate (same clock edge, 2X speed, see ) and the DE transition is used to flag the first pixel.
Also note in both 8D+2C configurations, the three video control signals are sent over both the A and B outputs.
The DES / TCON may recover one set, or both depending upon its implementation. The Dual Pixel / 24bpp
8D+2C LVDS Interface Mapping is shown in .
A Dual Pixel / 18bpp mode is also supported. In this configuration OA3 and OB3 LVDS output channels are
placed in TRI-STATE® to save power. Their respective inputs are ignored. (Figure 15)
In the Single Pixel / 24bpp mode, four LVDS data lines are provided along with a LVDS clock line (4D+C). The
28 bit interface typically assigns 24 bits to RGB color data, 3 bits to video control (HS, VS and DE) and one
spare bit can be ignored, used for L/R signaling or function as a general purpose bit. The Single Pixel / 24bpp
4D+C LVDS Interface Mapping is shown in .
A Single Pixel / 18bpp mode is also supported. In this configuration the OA3 LVDS output channel is placed in
TRI-STATE® to save power. Its respective inputs are ignored. (Figure 17)
OA_C+/(Diff)
Current Cycle
OA_3+/(SE)
OA_2+/(SE)
INA27 INA26 INA25 INA24 INA23 INA22 INA21
DE
VS
HS
INA17 INA16 INA15 INA14
OA_1+/(SE)
INA13 INA12 INA11 INA10
INA9
INA8
INA7
OA_0+/(SE)
INA6
INA2
INA1
INA0
OB_3+/(SE)
INB27 INB26 INB25 INB24 INB23 INB22 INB21
OB_2+/(SE)
DE
INA5
VS
INA4
HS
INA3
INB17 INB16 INB15 INB14
OB_1+/(SE)
INB13 INB12 INB11 INB10
INB9
INB8
INB7
OB_0+/(SE)
INB6
INB2
INB1
INB0
INB5
INB4
INB3
OB_C+/(Diff)
Figure 14. Dual Pixel / 24bpp LVDS Mapping
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Programming (continued)
OA_C+/(Diff)
Current Cycle
OA_3+/(SE)
OA_2+/(SE)
TRI-STATE
DE
VS
HS
INA17 INA16 INA15 INA14
OA_1+/(SE)
INA13 INA12 INA11 INA10
INA9
INA8
INA7
OA_0+/(SE)
INA6
INA2
INA1
INA0
OB_3+/(SE)
OB_2+/(SE)
INA5
INA4
INA3
TRI-STATE
DE
VS
HS
INB17 INB16 INB15 INB14
OB_1+/(SE)
INB13 INB12 INB11 INB10
INB9
INB8
INB7
OB_0+/(SE)
INB6
INB2
INB1
INB0
INB5
INB4
INB3
OB_C+/(Diff)
Figure 15. Dual Pixel / 18bpp LVDS Mapping
OA_C+/(Diff)
Current Cycle
OA_3+/(SE)
OA_2+/(SE)
INA27 INA26 INA25 INA24 INA23 INA22 INA21
DE
VS
HS
INA17 INA16 INA15 INA14
OA_1+/(SE)
INA13 INA12 INA11 INA10
INA9
INA8
INA7
OA_0+/(SE)
INA6
INA2
INA1
INA0
INA5
INA4
INA3
Figure 16. Single Pixel / 24bpp LVDS Mapping
OA_C+/(Diff)
Current Cycle
OA_3+/(SE)
OA_2+/(SE)
TRI-STATE
DE
VS
HS
INA17 INA16 INA15 INA14
OA_1+/(SE)
INA13 INA12 INA11 INA10
INA9
INA8
INA7
OA_0+/(SE)
INA6
INA2
INA1
INA0
INA5
INA4
INA3
Figure 17. Single Pixel / 18bpp LVDS Mapping
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Programming (continued)
8.4.1.1 Color Mapping Information
A defacto color mapping is shown next. Different color mapping options exist. Check with the color mapping of
the Deserializer / TCON device that is used to ensure compatible mapping for the application.
Table 6. Single Pixel Input / 24bpp / MSB on CH3
DS90C187 Input
Color Mapping
Note
INA_22
R7
MSB
INA_21
R6
INA_5
R5
INA_4
R4
INA_3
R3
INA_2
R2
INA_1
R1
INA_0
R0
LSB
INA_24
G7
MSB
INA_23
G6
INA_11
G5
INA_10
G4
INA_9
G3
INA_8
G2
INA_7
G1
INA_6
G0
LSB
INA_26
B7
MSB
INA_25
B6
INA_17
B5
INA_16
B4
INA_15
B3
INA_14
B2
INA_13
B1
INA_12
B0
DE
DE
Data Enable*
VS
VS
Vertical Sync
HS
HS
Horizontal Sync
INA_27
GP
General Purpose
Table 7. Single Pixel Input / 24bpp / LSB on CH3
20
DS90C187 Input
Color Mapping
Note
INA_5
R7
MSB
INA_4
R6
INA_3
R5
INA_2
R4
INA_1
R3
INA_0
R2
INA_22
R1
INA_21
R0
LSB
INA_11
G7
MSB
INA_10
G6
INA_9
G5
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Table 7. Single Pixel Input / 24bpp / LSB on
CH3 (continued)
DS90C187 Input
Color Mapping
INA_8
G4
Note
INA_7
G3
INA_6
G2
INA_24
G1
INA_23
G0
LSB
INA_17
B7
MSB
INA_16
B6
INA_15
B5
INA_14
B4
INA_13
B3
INA_12
B2
INA_26
B1
INA_25
B0
DE
DE
Data Enable*
VS
VS
Vertical Sync
HS
HS
Horizontal Sync
INA_27
GP
General Purpose
Table 8. Single Pixel Input / 18bpp
DS90C187 Input
Color Mapping
Note
INA_5
R5
MSB
INA_4
R4
INA_3
R3
INA_2
R2
INA_1
R1
INA_0
R0
LSB
INA_11
G5
MSB
INA_10
G4
INA_9
G3
INA_8
G2
INA_7
G1
INA_6
G0
LSB
INA_17
B5
MSB
INA_16
B4
INA_15
B3
INA_14
B2
INA_13
B1
INA_12
B0
DE
DE
Data Enable*
VS
VS
Vertical Sync
HS
HS
Horizontal Sync
Table 9. Dual Pixel Input / 24bpp
DS90C187 Input
Color Mapping
Note
INA_22
O_R7
MSB
INA_21
O_R6
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Table 9. Dual Pixel Input / 24bpp (continued)
22
DS90C187 Input
Color Mapping
INA_5
O_R5
Note
INA_4
O_R4
INA_3
O_R3
INA_2
O_R2
INA_1
O_R1
INA_0
O_R0
LSB
INA_24
O_G7
MSB
INA_23
O_G6
INA_11
O_G5
INA_10
O_G4
INA_9
O_G3
INA_8
O_G2
INA_7
O_G1
INA_6
O_G0
LSB
INA_26
O_B7
MSB
INA_25
O_B6
INA_17
O_B5
INA_16
O_B4
INA_15
O_B3
INA_14
O_B2
INA_13
O_B1
INA_12
O_B0
INB_22
E_R7
INB_21
E_R6
INB_5
E_R5
INB_4
E_R4
INB_3
E_R3
INB_2
E_R2
INB_1
E_R1
INB_0
E_R0
INB_24
E_G7
INB_23
E_G6
INB_11
E_G5
INB_10
E_G4
INB_9
E_G3
INB_8
E_G2
INB_7
E_G1
INB_6
E_G0
INB_26
E_B7
INB_25
E_B6
INB_17
E_B5
INB_16
E_B4
INB_15
E_B3
INB_14
E_B2
INB_13
E_B1
INB_12
E_B0
DE
DE
Data Enable*
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Table 9. Dual Pixel Input / 24bpp (continued)
DS90C187 Input
Color Mapping
Note
VS
VS
Vertical Sync
HS
HS
Horizontal Sync
INA_27
GP
General Purpose
INB_27
GP
General Purpose
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS90C187 is a Low Power Bridge for automotive application that reduces the size of the RGB interface
between the host GPU and the Display. It is designed to support single pixel data transmission between Host
and Flat Panel Display up to QXGA (2048x1536) at 60 Hz resolutions. The transmitter converts up to 24 bits
(Single Pixel 24 bit color) of 1.8-V LVCMOS data into two channels of 4 data + clock (4D+C) reduced width
interface LVDS compatible data streams.
9.2 Typical Application
1.8 V LVCMOS
(24 bit RGB + HS/VS/DE)
2 Channels FPD-Link (LVDS)
(4 Data + Clock)
1.8 V
GPU
Display (TCON)
DS90C187
LVDS
4D+C
(odd pixel)
L
A
T
C
H
Single Pixel
R[7:0] G[7:0]
B[7:0]
LVDS
4D+C
(even pixel)
&
P
2
S
HS
VS
DE
GPO/CNTL (L/R)
PCLK
PLL
PDB
Figure 18. Single Pixel In Dual Pixel Out (SIDO) Mode
9.2.1 Design Requirements
The DS90C187 is used to convert 24-bit color to two channels of LVDS datastreams.
Table 10. Design Parameters
DESIGN PARAMETER
24
VALUE
Supply
1.8V
Display Driven
SXGA+, WUXGA+
Pixel Depth
24 bits
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9.2.2 Detailed Design Procedure
9.2.2.1 LVDS Interconnect Guidelines
Refer to the AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and Transmission
Line RAPIDESIGNER Operation and Applications Guide (SNLA035) for full details.
• Use 100-Ω coupled differential pairs
• Use differential connectors when above 500 Mbps
• Minimize skew within the pair
• Use the S/2S/3S rule in spacings
– S = space between the pairs
– 2S = space between pairs
– 3S = space to LVCMOS signals
• Place ground vias next to signal vias when changing between layers
• When a signal changes reference planes, place a bypass cap and vias between the new and old reference
plane
For more tips and detailed suggestions regarding high speed board layout principles, see the LVDS Owner's
Manual at http://www.ti.com/lvds
9.2.3 Application Curves
110
60
VODSEL = L
VODSEL = H
VODSEL = L
VODSEL = H
55
90
50
80
45
IDD (mA)
IDD (mA)
100
70
60
40
35
50
30
40
25
30
20
40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
Figure 19. Typical Current Draw - Single In/Dual Out Mode
- PRBS-7 Data Pattern
20
40
60
80
100
FREQUENCY (MHz)
120
Figure 20. Typical Current Draw - Single In/Single Out
Mode - PRBS-7 Data Pattern
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10 Power Supply Recommendations
10.1 Power Up Sequence
The VDD power supply pins do not require a specific power on sequence and can be powered on in any order.
However, the PDB pin should only be set to logic HIGH once the power sent to all supply pins is stable. Active
data inputs should not be applied to the DS90C187 until all of the input power pins have been powered on,
settled to the recommended operating voltage and the PDB pin has be set to logic HIGH.
The user experience can be impacted by the way a system powers up and powers down an LCD screen. The
following sequence is recommended:
Power up sequence (DS90C187 PDB input initially LOW):
1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off.
2. Toggle DS90C187 power down pin to PDB = VDD.
3. Enable clock and wait for additional 0-200ms to ensure display noise won’t occur.
4. Enable video source output; start sending black video data.
5. Send >1ms of black video data; this allows the DS90C187 to be phase locked, and the display to show black
data first.
6. Start sending true image data.
7. Enable backlight.
Power Down sequence (DS90C187 PDB input initially HIGH):
1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive
this for >2 frame times.
3. Set DS90C187 power down pin to PDB = GND.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system power.
The DS90C187 is highly sensitive to the VDD input. Even small levels on the VDD pin prior to full power up
should be avoided. The user should additionally take care to not drive or pull up the CMOS inputs to the device
prior to device power up so as to ensure proper power on behavior.
10.2 Power Supply Filtering
The DS90C187 has several power supply pins at 1.8 V. It is important that these pins all be connected and
properly bypassed. Bypassing should consist of at least one 0.1μF capacitor placed on each pin, with an
additional 4.7 μF - 22 μF capacitor placed on the PLL supply pin (VDDP). 0.01 μF capacitors are typically
recommended for each pin. Additional filtering including ferrite beads may be necessary for noisy systems. It is
recommended to place a 0 ohm resistor at the bypass capacitors that connect to each power pin to allow for
additional filtering if needed. A large bulk capacitor is recommended at the point of power entry. This is typically
in the 50 μF — 100 μF range.
26
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SNLS401C – FEBRUARY 2012 – REVISED SEPTEMBER 2018
11 Layout
11.1 Layout Guidelines
Circuit board layout and stack-up for the LVDS devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. This practice is
easier to implement in dense pcbs with many layers and may not be practical in simpler boards. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. It is recommended to connect power and ground pins
directly to the power and ground planes with bypass capacitors connected to the plane with vias on both ends of
the capacitor.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency. Some devices provide separate power and ground pins for different portions of
the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate
planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean
power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
For more information on the VQFN package, refer to the AN-1187 Leadless Leadframe Package (LLP)
application note (SNOA401).
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DS90C187
SNLS401C – FEBRUARY 2012 – REVISED SEPTEMBER 2018
www.ti.com
11.2 Layout Example
Figure 21. Layout Example
28
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SNLS401C – FEBRUARY 2012 – REVISED SEPTEMBER 2018
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see:
• LVDS Owner's Manual (SNLA187)
• AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008)
• Transmission Line RAPIDESIGNER Operation and Applications Guide (SNLA035)
• AN-1187 Leadless Leadframe Package (LLP) (SNOA401)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: DS90C187
29
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS90C187LF/NOPB
ACTIVE
VQFN-MR
NLA
92
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-10 to 70
90C187LF
DS90C187LFE/NOPB
ACTIVE
VQFN-MR
NLA
92
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-10 to 70
90C187LF
DS90C187LFX/NOPB
ACTIVE
VQFN-MR
NLA
92
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-10 to 70
90C187LF
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DS90C187LF/NOPB
VQFNMR
NLA
92
1000
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
DS90C187LFE/NOPB
VQFNMR
NLA
92
250
178.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
DS90C187LFX/NOPB
VQFNMR
NLA
92
2500
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90C187LF/NOPB
VQFN-MR
NLA
92
1000
367.0
367.0
38.0
DS90C187LFE/NOPB
VQFN-MR
NLA
92
250
210.0
185.0
35.0
DS90C187LFX/NOPB
VQFN-MR
NLA
92
2500
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
NLA0092A
BOTTOM SIDE OF PACKAGE
TOP SIDE OF PACKAGE
LFA92A (Rev B)
www.ti.com
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