Texas Instruments | ESDS302, ESDS304 Data-Line Surge and ESD Protection Devices (Rev. A) | Datasheet | Texas Instruments ESDS302, ESDS304 Data-Line Surge and ESD Protection Devices (Rev. A) Datasheet

Texas Instruments ESDS302, ESDS304 Data-Line Surge and ESD Protection Devices (Rev. A) Datasheet
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ESDS302, ESDS304
SLVSEG8A – MAY 2018 – REVISED SEPTEMBER 2018
ESDS302, ESDS304 Data-Line Surge and ESD Protection Devices for High Speed
Interfaces
1 Features
3 Description
•
The ESDS302, ESDS304 devices are bidirectional
TVS ESD protection diode array in two and four
channel configurations respectively, for Ethernet and
USB surge protection up to 12 A (8/20 μs). The
ESDS302, ESDS304 devices are rated to dissipate
ESD strikes up to 30 kV per the IEC 61000-4-2
international standard (> Level 4).
1
•
•
•
•
•
•
•
•
IEC 61000-4-2 Level 4 ESD Protection
– ±30-kV Contact Discharge
– ±30-kV Air Gap Discharge
IEC 61000-4-4 EFT Protection
– 80 A (5/50 ns)
IEC 61000-4-5 Surge Protection
– 12 A (8/20 μs)
– Low Surge Clamping Voltage 6 V at 12 A Ipp
IO Capacitance:
– 2.3 pF (Typical)
DC Breakdown Voltage: 4.5 V (Minimum)
Ultra Low Leakage Current: 3 nA (Typical)
Supports High Speed Interfaces up to 1 Gbps
Industrial Temperature Range: –40°C to +125°C
Easy Flow-Through Routing Package (ESDS302)
The devices features a 2.3-pF IO capacitance per
channel making it ideal for protecting high-speed
interfaces such as Ethernet 1G and USB 2.0. The low
dynamic resistance and low clamping voltage ensure
system level protection against transient events.
The ESDS302, ESDS304 devices are offered in the
industry standard 5-Pin SOT23 packages.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ESDS302
SOT23 (5);
2 NC pins
2.90 mm × 1.6 mm x 1.25 mm
2 Applications
ESDS304
SOT23 (5)
2.90 mm × 1.6 mm x 1.25 mm
•
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
End Equipment
– Ethernet Switches
– Access Points
– Gateways
– Printers
– DVR and NVR
Interfaces
– Ethernet 10/100/1000 Mbps
– USB 2.0
– GPIO
Typical Application Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ESDS302, ESDS304
SLVSEG8A – MAY 2018 – REVISED SEPTEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings -JEDEC Specifications ........................
ESD Ratings - IEC Specifications .............................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 8
8
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application ................................................... 9
9 Power Supply Recommendations...................... 11
10 Layout................................................................... 11
10.1 Layout Guidelines ................................................. 11
10.2 Layout Examples................................................... 11
11 Device and Documentation Support ................. 12
11.1
11.2
11.3
11.4
11.5
11.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
12
12
12 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
Changes from Original (May 2018) to Revision A
Page
•
Changed data sheet status from Product Preview to Production Data .................................................................................. 1
•
Changed ESDS03802 and ESDS03804 part numbers to ESDS302 and ESDS304 ............................................................ 1
2
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5 Pin Configuration and Functions
ESDS302 DBV Package
5-Pin SOT23
Top View
ESDS304 DBV Package
5-Pin SOT23
Top View
2.8
2.8
1.6
1.6
1
5
NC
1
I/O2
2
2.9
5
I/O1
I/O4
2
2.9
GND
3
GND
4
3
I/O1
NC
4
I/O3
I/O2
Pin Functions for ESDS302
PIN
NAME
NO.
I/O1
4
I/O2
5
GND
2
NC
1
NC
3
TYPE
I/O
GND
NC
DESCRIPTION
Surge/ESD protected channels. Connect to the lines being protected.
Ground. Connect to ground
Not connected; Used for optional straight-through routing. Can be left floating or
grounded
Pin Functions for ESDS304
PIN
NAME
NO.
I/O1
1
I/O2
3
I/O3
4
I/O4
5
GND
2
TYPE
I/O
GND
DESCRIPTION
Surge/ESD protected channels. Connect to the lines being protected.
Ground. Connect to ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
IEC 61000-4-4
Electrical Fast
Transient
MAX
UNIT
Peak Power at 25 °C
80
A
IEC 61000-4-5
Surge (tp 8/20
µs
Peak Power at 25 °C
85
W
Peak Current at 25 °C
12
A
TA
Operating free-air temperature
–40
125
°C
Tstg
Storage temperature
–65
155
°C
(1)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings -JEDEC Specifications
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, allpins (1)
±2500
Charged device model (CDM), per JEDEC
specificationJESD22-C101, all pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. [Following sentence
optional; see the wiki.] Manufacturing with less than 500-V HBM is possible with the necessary precautions. [Following sentence
optional; see the wiki.] Pins listed as ±WWW V and/or ±XXX V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. [Following sentence
optional; see the wiki.] Manufacturing with less than 250-V CDM is possible with the necessary precautions. [Following sentence
optional; see the wiki.] Pins listed as ±YYY V and/or ±ZZZ V may actually have higher performance.
6.3 ESD Ratings - IEC Specifications
VALUE
V(ESD)
Electrostatic discharge
IEC 61000-4-2 Contact Discharge, all pins
±30000
IEC 61000-4-2 Air Discharge, all pins
±30000
UNIT
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage
TA
Operating Free Air Temperature
NOM
MAX
UNIT
0
3.6
V
–40
125
°C
6.5 Thermal Information
THERMAL METRIC
(1)
ESDS302
ESDS304
DBV (SOT-23)
DBV (SOT-23)
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
176.2
133.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
125.7
85.1
°C/W
RθJB
Junction-to-board thermal resistance
88.4
49.4
°C/W
ΨJT
Junction-to-top characterization parameter
71.4
30.1
°C/W
ΨJB
Junction-to-board characterization parameter
88.2
49.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics
At TA = 25°C unless otherwise noted
PARAMETER
TEST CONDITIONS
VRWM
Reverse stand-off voltage
IIO < 500 nA, across operating
temperature range
ILEAKAGE
Leakage current at 3.6 V
VIO = 3.6 V, Any IO pin to GND
VBRF
Breakdown voltage, Any IO pin to
GND (1)
IIO = 1 mA
VFWD
Diode forward voltage, GND to IO pin
VHOLD
Holding voltage, Any IO pin to GND
(2)
VCLAMP
TLP Clamping Voltage, tp = 100 ns
TYP
3
4.5
MAX
UNIT
3.6
V
50
nA
7.5
V
IIO = 1 mA
0.8
V
IIO = 1 mA
5
V
5.1
V
6
V
1.2
V
IPP = 12 A, GND to any IO pin
3
V
IPP = 16 A, any IO to GND pin
5.8
V
IPP = 16 A, GND to any IO pin
3.1
IPP = 1 A, Any IO pin to GND
Surge Clamping voltage, tp = 8/20 µs
MIN
IPP = 12 A, Any IO pin to GND
IPP = 1 A, GND to any IO pin
V
CLINE
Line capacitance, any IO to GND
VIO = 0 V, Vp-p = 30 mV, f = 1 MHz
2.3
2.8
pF
ΔCLINE
Variation of line capacitance
CLINE1 - CLINE2, VIO = 0 V, Vp-p = 30
mV, f = 1 MHz
0.05
0.1
pF
CCROSS
Line-to-line capacitance
VIO = 0V, Vrms = 30 mV, f = 1 MHz
1.25
1.5
pF
(1)
(2)
VBRF is defined as the max voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback state
VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.
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8
5
7.5
4.5
7
4
6.5
3.5
Voltage (V)
Voltage (V)
6.7 Typical Characteristics
6
5.5
5
4.5
3
2.5
2
1.5
4
1
3.5
0.5
3
0
0
1
2
3
4
5
6
7
8
Peak Current (A)
9
10 11 12 13
0
1
2
3
4
5 6 7 8 9
Peak Current (A)
D001
10 11 12 13 14
D001_Vclamp_Pos.grf
Figure 1. Surge Clamping Voltage vs. Peak Pulse Current
(IEC 61000-4-5, tp = 8/20 µs), Any IO Pin to GND
12.5
Current (A), Voltage (V)
Figure 2. Surge Clamping Voltage vs. Peak Pulse Current
(IEC 61000-4-5, tp = 8/20 µs), GND to IO Pin
100
Voltage (V)
Current (A)
Power (W) 80
10
D002
D002_Vclamp_Neg.grf
0.001
0.0008
0.0006
5
40
2.5
20
Current (A)
60
Power (W)
0.0004
7.5
0.0002
0
-0.0002
-0.0004
-0.0006
0
0
-2.5
-20
-20
180
-0.0008
-0.001
0
20
40
60
80 100
Time (µs)
120
140
160
-0.0012
-1
0
1
D003
2
3
Voltage (V)
4
5
D004
D003_Surge_IV.grf
D004_DC_Plot.grf
Figure 3. Surge Current, Clamping Voltage and Power
Waveform (IEC-61000-4-5, tp = 8/20 µs), Any IO Pin to GND
Figure 4. DC I-V Curve
32
4
28
0
24
-4
-8
Current (A)
Current (A)
20
16
12
-12
-16
8
-20
4
-24
0
-28
-4
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
Voltage (V)
D005
-32
-4.5
D005_TLP_Pos.grf
Figure 5. TLP I-V Curve, IO to GND, tp = 100 ns
6
6
-4
-3.5
-3
-2.5
-2
Voltage (V)
-1.5
-1
-0.5
0
D006
D006_TLP_Neg.grf
Figure 6. TLP I-V Curve, IO to GND Negative, tp = 100 ns
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80
40
60
20
40
0
Voltage (V)
Voltage (V)
Typical Characteristics (continued)
20
-20
0
-40
-20
-60
-40
-10
0
10
20
30
40
50
Time (ns)
60
70
80
-80
-10
90
0
10
20
D007
30
40
50
Time (ns)
60
70
90
D008
D007_IEC_Pos.grf
Figure 7. +8 kV IEC 61000-4-2 Clamping Voltage Waveform,
IO Pin to GND
80
D008_IEC_Neg.grf
Figure 8. -8 kV IEC 61000-4-2 Clamping Voltage Waveform,
IO Pin to GND
100
4
90
3.5
80
3
Capacitance (pF)
Current (nA)
70
60
50
40
30
2.5
2
1.5
1
20
0.5
10
0
-40
0
-20
0
20
40
60
80
Temperature (qC)
100
120
0
140
0.5
1
D009
1.5
2
2.5
Bias Voltage (V)
Differential Insertion Loss (dB)
Percentage of Rated Power (%)
95
90
85
80
75
70
0
25
50
75
Temperature (qC)
100
125
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
-5
-5.5
-6
-6.5
-7
-7.5
-8
0.1
D011
D010
0.2
0.3 0.4 0.5 0.60.7
Frequency (GHz)
1
2
D012
D012_S21.grf
D011_Sureg_Derating.grf
Figure 11. Surge Power Derating with Respect to Ambient
Temperature
4
Figure 10. Capacitance vs. Bias Voltage at 25°C
105
100
3.5
D010_Capacitance.grf
D009_Leakage.grf
Figure 9. DC Leakage Current vs. Ambient Temperature,
Bias Voltage = 3.6 V
3
Figure 12. Differential Insertion Loss vs. Frequency
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7 Detailed Description
7.1 Overview
The ESDS304, ESDS302 devices are uni-directional ESD Protection Diode with ultra-low capacitance. This
device can dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 International
Standard. The ultra-low capacitance makes this device ideal for protecting any super high-speed signal pins.
7.2 Functional Block Diagram
7.3 Feature Description
The I/O pins of ESDS304 and ESDS302 can withstand surge events (IEC 61000-4-5, 8/20 μs waveform) up to
12 A and 85 W. These devices also provide ESD protection up to ±30-kV contact and ±30-kV air gap per IEC
61000-4-2 standard. The I/O pins can withstand an electrical fast transient burst of up to 80 A (IEC 61000-4-4
5/50 ns waveform, 4 kV with 50-Ω impedance). The capacitance between each I/O pin to ground is 2.3 pF
(typical) and 2.8 pF (maximum). This device supports data rates up to 1 Gbps. The reverse DC breakdown
voltage of each I/O pin is a minimum of 4.5 V. This ensures that sensitive equipment is protected from surges
above the reverse standoff voltage of 3.6 V. The I/O pins feature an ultra-low leakage current of 50 nA
(maximum) with a bias of 3.6 V. This device features an industrial operating range of –40°C to +125°C.
7.4 Device Functional Modes
The ESDS304, ESDS302 devices are a passive integrated circuit that triggers when voltages are above VBRF or
below 0.7 V. During ESD events, voltages as high as ±30 kV (air) can be directed to ground via the internal
diode network. When the voltages on the protected line fall below the trigger levels of ESDS304, ESDS302
(usually within a few nano-seconds) the devices reverts to passive.
8
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The ESDS304, ESDS302 devices are diode type TVS which is used to provide a path to ground for dissipating
ESD events on high-speed signal lines between a human interface connector and a system. As the current from
ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage
presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for
the protected IC.
8.2 Typical Application
Figure 13. ESDS304 Protecting the Ethernet 1G Interface
8.2.1 Design Requirements
A typical operation for the ESDS304 would be protecting a high speed dataline similar to one shown in Figure 13.
In this example, the ESDS304 is protecting an Ethernet PHY's data lines that has a nominal operating voltage of
3.6 V. Many of the Ethernet interfaces that connect to long cables require protection against ±1 kV surge test
through a 42-Ω coupling resistor and a 0.5 μF capacitor, equaling roughly 24 A of surge current. Without any
input protection, if a surge event is caused by lightning, coupling, ringing, or any other fault condition, this input
voltage will rise to hundreds of volts for multiple microseconds, harming the device. For Ethernet 1000Base-T
(1Gbps), application design parameters listed in Table 1 are known.
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
Single ended signal voltage range on
differential data line pairs
0 to 3.6 V
Operating Frequency
125 MHz
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8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The ESDS304 has 4 identical surge protection channels with each channel supporting a signal range of 0 to 3.6
V. The device will work well with any Ethernet PHY that drives the single ended voltage on the data line up to a
3.6 V.
8.2.2.2 Operating Frequency
The ESDS304 has a capacitance of 2.3 pF (typical) and can support the 125 MHz operation of Ethernet
1000Base-T application
Differential Insertion Loss (dB)
8.2.3 Application Curves
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
-5
-5.5
-6
-6.5
-7
-7.5
-8
0.1
0.2
0.3 0.4 0.5 0.60.7
Frequency (GHz)
1
2
D012
D012_S21.grf
Figure 14. Differential Insertion Loss vs. Frequency
10
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9 Power Supply Recommendations
The ESDS304, ESDS302 devices are passive ESD devices and there is no need to power them. Take care not
to violate the recommended I/O specification (0 V to 3.6 V) to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Examples
Figure 15. Layout Example for the 4-channel Device, ESDS304
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11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ESDS302
Click here
Click here
Click here
Click here
Click here
ESDS304
Click here
Click here
Click here
Click here
Click here
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
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15-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ESDS302DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1R5B
ESDS304DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1R3B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
ESDS302DBVR
SOT-23
DBV
5
3000
178.0
9.0
ESDS304DBVR
SOT-23
DBV
5
3000
178.0
9.0
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.3
3.2
1.4
4.0
8.0
Q3
3.3
3.2
1.4
4.0
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ESDS302DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
ESDS304DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2019, Texas Instruments Incorporated
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