Texas Instruments | PCF8575 Remote16-BIT I2C AND SMBus I/O Expander with Interrupt Output (Rev. G) | Datasheet | Texas Instruments PCF8575 Remote16-BIT I2C AND SMBus I/O Expander with Interrupt Output (Rev. G) Datasheet

Texas Instruments PCF8575 Remote16-BIT I2C AND SMBus I/O Expander with Interrupt Output (Rev. G) Datasheet
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PCF8575
SCPS121G – JANUARY 2005 – REVISED AUGUST 2018
PCF8575 Remote16-BIT I2C AND SMBus I/O Expander
with Interrupt Output
1 Features
•
•
•
•
•
•
1
•
•
•
•
3 Description
This 16-bit I/O expander for the two-line bidirectional
bus (I2C) is designed for 2.5-V to 5.5-V VCC
operation.
2
I C to Parallel-Port Expander
Open-Drain Interrupt Output
Low Standby-Current Consumption of 10 μA Max
Compatible With Most Microcontrollers
400-kHz Fast I2C Bus
Address by Three Hardware Address Pins for Use
of up to Eight Devices
Latched Outputs With High-Current Drive
Capability for Directly Driving LEDs
Current Source to VCC for Actively Driving a High
at the Output
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
The PCF8575 device provides general-purpose
remote I/O expansion for most microcontroller
families by way of the I2C interface [serial clock
(SCL), serial data (SDA)].
The device features a 16-bit quasi-bidirectional
input/output (I/O) port (P07–P00, P17–P10), including
latched outputs with high-current drive capability for
directly driving LEDs. Each quasi-bidirectional I/O can
be used as an input or output without the use of a
data-direction control signal. At power on, the I/Os
are high. In this mode, only a current source to VCC is
active.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
•
•
•
PCF8575
Telecom Shelters: Filter Units
Servers
Routers (Telecom Switching Equipment)
Personal Computers
Personal Electronics
Industrial Automation
Products with GPIO-Limited Processors
PACKAGE (PIN)
BODY SIZE (NOM)
SSOP (24)
8.20 mm × 5.30 mm
QSOP (24)
8.65 mm × 3.90 mm
TVSOP (24)
5.00 mm × 4.50 mm
SOIC (24)
15.40 mm × 7.50 mm
TSSOP (24)
7.80 mm × 4.40 mm
VQFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VCC
I2C or SMBus Master
(e.g. Processor)
SDA
SCL
INT
A0
A1
A2
GND
P00
P01
P02
P03
P04
P05
P06
P07
●
●
●
Peripheral Devices
RESET, ENABLE, or
control inputs
INT or status
outputs
LEDs
PCF8575
P10
P11
P12
P13
P14
P15
P16
P17
●
●
●
Peripheral Devices
RESET, ENABLE, or
control inputs
INT or status
outputs
LEDs
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCF8575
SCPS121G – JANUARY 2005 – REVISED AUGUST 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Interface Timing Requirements...........................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 16
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 18
10 Power Supply Recommendations ..................... 21
10.1 Power-On Reset.................................................... 21
10.2 System Impact ...................................................... 21
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support ....................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Revision F (May 2015) to Revision G
•
Changed the Power Supply Recommendations section ...................................................................................................... 21
Changes from Revision E (January 2015) to Revision F
•
Page
Page
Fixed naming typo in the RGE graphic, changed pin 3 From: P03 To: P02 ......................................................................... 3
Changes from Revision D (April 2007) to Revision E
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
2
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SCPS121G – JANUARY 2005 – REVISED AUGUST 2018
5 Pin Configuration and Functions
DB, DBQ, DGV, DW, or PW Package
SSOP, TVSOP, SOIC, TSSOP
(Top View)
P16
P03
7
18
P15
P04
8
17
P14
P05
9
16
P13
P06
10
15
P12
P07
11
14
P11
GND
12
13
P10
SCL
19
19
6
A0
P01
2
17
P17
P02
3
16
P16
P03
4
15
P15
P04
5
14
P14
P05
6
13
P13
Thermal
Pad
12
P02
18
P12
P17
SDA
20
20
5
1
11
P01
P00
P11
A0
VCC
21
21
4
10
P00
P10
SCL
INT
22
A1
3
22
A2
23
SDA
9
23
8
2
P07
A1
GND
VCC
A2
24
7
1
P06
INT
24
RGE Package
VQFN
(Top View)
Not to scale
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
DB, DBQ, DGV,
DW, AND PW
RGE
A0
21
18
I
Address input 0. Connect directly to VCC or ground. Pull-up resistors are not needed.
A1
2
23
I
Address input 1. Connect directly to VCC or ground. Pull-up resistors are not needed.
A2
3
24
I
Address input 2. Connect directly to VCC or ground. Pull-up resistors are not needed.
INT
1
22
O
Interrupt output. Connect to VCC through a pull-up resistor.
P00
4
1
I/O
P-port input/output. Push-pull design structure.
P01
5
2
I/O
P-port input/output. Push-pull design structure.
P02
6
3
I/O
P-port input/output. Push-pull design structure.
P03
7
4
I/O
P-port input/output. Push-pull design structure.
P04
8
5
I/O
P-port input/output. Push-pull design structure.
P05
9
6
I/O
P-port input/output. Push-pull design structure.
P06
10
7
I/O
P-port input/output. Push-pull design structure.
P07
11
8
I/O
P-port input/output. Push-pull design structure.
GND
12
9
—
Ground
P10
13
10
I/O
P-port input/output. Push-pull design structure.
P11
14
11
I/O
P-port input/output. Push-pull design structure.
P12
15
12
I/O
P-port input/output. Push-pull design structure.
P13
16
13
I/O
P-port input/output. Push-pull design structure.
P14
17
14
I/O
P-port input/output. Push-pull design structure.
P15
18
15
I/O
P-port input/output. Push-pull design structure.
P16
19
16
I/O
P-port input/output. Push-pull design structure.
P17
20
17
I/O
P-port input/output. Push-pull design structure.
SCL
22
19
I
Serial clock line. Connect to VCC through a pull-up resistor
SDA
23
20
I/O
Serial data line. Connect to VCC through a pull-up resistor.
VCC
24
21
—
Supply voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
–0.5
VCC + 0.5
V
–0.5
VCC + 0.5
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IOK
Input/output clamp current
VO < 0 or VO > VCC
–20
mA
IOL
Continuous output low current
VO = 0 to VCC
50
mA
IOH
Continuous output high current
VO = 0 to VCC
Continuous current through VCC or GND
Tstg
(1)
(2)
V
–4
mA
±100
mA
150
°C
Storage temperature range
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
2000
Charged device model (CDM), per JEDEC specification JESD22C101, all pins
1000
UNIT
V
6.3 Recommended Operating Conditions
MIN
MAX
2.5
5.5
V
High-level input voltage
0.7 × VCC
VCC + 0.5
V
VIL
Low-level input voltage
–0.5
0.3 × VCC
IOH
P-port high-level output current
–1
mA
IOHT
P-port transient pullup current
–10
mA
IOL
P-port low-level output current
25
mA
TA
Operating free-air temperature
85
°C
VCC
Supply voltage
VIH
–40
UNIT
V
6.4 Thermal Information
PCF8575
THERMAL METRIC (1)
DB
DBQ
DGV
63
61
86
DW
PW
RGE
UNIT
88
53
°C/W
24 PINS
RθJA
(1)
4
Junction-to-ambient thermal resistance
46
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
Input diode clamp voltage
TEST CONDITIONS
II = –18 mA
VPOR Power-on reset voltage (2)
VI = VCC or GND, IO = 0
IOH
P port
VO = GND
IOHT
P-port transient pullup current
High during ACK, VOH = GND
SDA
VOL = 0.4 V
IOL
P port
INT
SCL, SDA
II
A0, A1, A2
IIHL
P port
Operating mode
VCC
MIN
2.5 V to 5.5 V
–1.2
VPOR
2.5 V to 5.5 V
–30
2.5 V
–0.5
2.5 V to 5.5 V
VOL = 1 V
VOL = 0.4 V
VI = VCC or GND
2.5 V to 5.5 V
VI ≥ VCC or VI ≤ GND
2.5 V to 5.5 V
μA
–1
mA
5
15
10
25
mA
VI = VCC or GND, IO = 0,
fscl = 400 kHz
VI = VCC or GND, IO = 0, fscl = 0 kHz
±1
±400
3.6 V
30
75
2.7 V
20
50
5.5 V
2.5
10
3.6 V
2.5
10
2.7 V
2.5
10
CI
SCL
VI = VCC or GND
2.5 V to 5.5 V
VIO = VCC or GND
±5
200
2.5 V to 5.5 V
(1)
(2)
V
–300
V
100
One input at VCC – 0.6 V,
Other inputs at VCC or GND
P port
1.8
5.5 V
Supply current increase
Cio
1.2
UNIT
1.6
ΔICC
SDA
MAX
3
VOL = 0.4 V
ICC
Standby mode
TYP (1)
2.5 V to 5.5 V
μA
μA
μA
200
μA
3
7
pF
3
7
4
10
pF
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
The power-on reset circuit resets the I2C bus logic with VCC < VPOR and sets all I/Os to logic high (with current source to VCC).
6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 12)
MIN
fscl
I2C clock frequency
tsch
I2C clock high time
I C clock low time
tsp
I2C spike time
tsds
I2C serial data setup time
UNIT
400
kHz
0.6
2
tscl
MAX
μs
1.3
μs
50
100
2
ns
ns
tsdh
I C serial data hold time
ticr
I2C input rise time
20 + 0.1Cb
(1)
300
ns
ticf
I2C input fall time
20 + 0.1Cb
(1)
300
ns
300
ns
2
0
tocf
I C output fall time
tbuf
I2C bus free time between Stop and Start
1.3
μs
tsts
I2C start or repeated Start condition setup
0.6
μs
tsth
I2C start or repeated Start condition hold
0.6
μs
2
tsps
I C Stop condition setup
tvd
Valid-data time
Cb
I2C bus capacitive load
(1)
10-pF to 400-pF bus
ns
0.6
SCL low to SDA output valid
μs
1.2
μs
400
pF
Cb = total bus capacitance of one bus line in pF
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6.7 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 13 and Figure 14)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
UNIT
tiv
Interrupt valid time
P port
INT
4
μs
tir
Interrupt reset delay time
SCL
INT
4
μs
tpv
Output data valid
SCL
P port
4
μs
tsu
Input data setup time
P port
SCL
0
μs
th
Input data hold time
P port
SCL
4
μs
6.8 Typical Characteristics
TA = 25°C (unless otherwise noted)
120
SCL = VCC
VCC = 5 V
Supply Current (mA)
Supply Current (mA)
100
90
fSCL = 100 kHz
All I/Os unloaded
80
60
40
VCC = 3.3 V
20
0
25
50
75
60
50
40
VCC = 2.5 V
30
VCC = 3.3 V
20
0
−50 −25
100 125
Temperature (°C)
20
fSCL = 100 kHz
90 All I/Os unloaded
80
18
70
50
75 100 125
14
VCC = 2.5 V
TA = −40ºC
16
ISINK (mA)
Supply Current (mA)
25
Figure 2. Standby Supply Current vs Temperature
60
50
40
TA = 25ºC
12
10
8
30
6
20
4
10
2
TA = 85ºC
0
0.0
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.1
0.2
0.3
0.4
0.5
0.6
Vol (V)
Supply Voltage (V)
Figure 3. Supply Current vs Supply Voltage
6
0
Temperature (°C)
Figure 1. Supply Current vs Temperature
100
VCC = 5 V
10
VCC = 2.5 V
0
−50 −25
80 All I/Os unloaded
70
Figure 4. I/O Sink Current vs Output Low Voltage
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
15
TA = 25°C
10
TA = −40ºC
25
TA = 25ºC
20
15
10
TA = 85°C
5
0
0.0
VCC = 5 V
30
TA = −40°C
20
ISINK (mA)
35
VCC = 3.3 V
ISINK (mA)
25
TA = 85ºC
5
0.1
0.2
0.3
0.4
0.5
0
0.0
0.6
0.1
0.2
0.3
0.4
0.5
0.6
VOL (V)
VOL (V)
Figure 5. I/O Sink Current vs Output Low Voltage
Figure 6. I/O Sink Current vs Output Low Voltage
45
600
VCC = 5 V, ISINK = 10 mA
35
400
300
VCC = 2.5 V, ISINK = 10 mA
200
100
ISOURCE (mA)
VOL (mV)
500
40
VCC = 5 V,
ISINK = 1 mA
VCC = 2.5 V,
ISINK = 1mA
30
VCC = 2.5 V
TA = 25ºC
25
20
15
TA = 85°C
10
5
0
−50 −25 0
25
50
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
75 100 125
VCC − VOH (V)
Temperature (°C)
Figure 7. I/O Output Low Voltage vs Temperature
Figure 8. I/O Source Current vs Output High Voltage
45
45
ISOURCE (mA)
35
VCC = 3.3 V
TA = 25ºC
40
TA = −40ºC
35
ISOURCE (mA)
40
30
25
20
15
10
TA = −40ºC
TA = 85ºC
30
VCC = 5 V
TA = −40ºC
TA = 25ºC
25
20
15
TA = 85ºC
10
5
5
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VCC − VOH (V)
VCC − VOH (V)
Figure 9. I/O Source Current vs Output High Voltage
Figure 10. I/O Source Current vs Output High Voltage
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
VCC − VOH (V)
350
300
VCC = 5 V
250
VCC = 3.3 V
200
VCC = 2.5 V
150
100
50
0
−50 −25 0
25
50
75 100 125
Temperature (ºC)
Figure 11. I/O High Voltage vs Temperature
8
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7 Parameter Measurement Information
VCC
RL = 1 kW
DUT
SDA
CL = 50 pF
SDA LOAD CONFIGURATION
3 Bytes for Complete Device
Programming
Stop
Condition
(P)
Start
Address
Address
Condition
Bit 7
Bit 6
(S)
(MSB)
Address
Bit 1
tscl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
tsch
0.7 × VCC
SCL
0.3 × VCC
ticr
ticf
tbuf
tsts
tPHL
tPLH
tsp
0.7 × VCC
SDA
0.3 × VCC
ticf
ticr
tsth
tsdh
tsds
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2, 3
P-port data
Figure 12. I2C Interface Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VCC
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
16 Bits
(2 Data Bytes)
From Port
R/W
Slave Address (PCF8575)
S
0
1
0
0 A2 A1 A0 1
A
1
2
3
4
A
5
6
7
8
Data 1
ACK
From Slave
Data 2
Data From Port
A
Data 3
1
P
A
tir
tir
B
B
INT
A
tiv
tsps
A
Data
Into
Port
Address
Data 1
0.7 × VCC
INT
SCL
0.3 × VCC
Data 2
Data 3
0.7 × VCC
R/W
tiv
A
0.3 × VCC
tir
0.7 × VCC
Pn
0.7 × VCC
INT
0.3 × VCC
0.3 × VCC
View A−A
View B−B
Figure 13. Interrupt Load Circuit and Voltage Waveforms
10
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Parameter Measurement Information (continued)
VCC
VCC
RL = 1 kΩ
DUT
RL = 4.7 kΩ
SDA
DUT
INT
DUT
CL = 50 pF
CL = 100 pF
GND
CL = 100 pF
GND
SDA LOAD CONFIGURATION
SCL
Pn
GND
INTERRUPT LOAD CONFIGURATION
P-PORT LOAD CONFIGURATION
0.7 × VCC
P00
A
P17
0.3 × VCC
Slave
ACK
SDA
tpv
Pn
Unstable
Data
Last Stable Bit
Write-Mode Timing (R/W = 0)
SCL
0.7 × VCC
P00
A
tsu
P17
0.3 × VCC
th
0.7 × VCC
Pn
0.3 × VCC
Read-Mode Timing (R/W = 1)
Figure 14. P-Port Load Circuits and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The PCF8575 provides general-purpose remote I/O expansion for most microcontroller families via the I2C
interface serial clock (SCL) and serial data (SDA).
The device features a 16-bit quasi-bidirectional input/output (I/O) port (P07–P00, P17–P10), including latched
outputs with high-current drive capability for directly driving LEDs. Each quasi-bidirectional I/O can be used as an
input or output without the use of a data-direction control signal. At power on, the I/Os are high. In this mode,
only a current source (IOH) to VCC is active. An additional strong pullup to VCC (IOHT) allows fast-rising edges into
heavily loaded outputs. This device turns on when an output is written high and is switched off by the negative
edge of SCL. The I/Os should be high before being used as inputs. After power on, as all the I/Os are set high,
all of them can be used as inputs. Any change in setting of the I/Os as either input or outputs can be done with
the write mode. If a high is applied externally to an I/O that has been written earlier to low, a large current (IOL)
will flow to GND.
The PCF8575 provides an open-drain interrupt (INT) output, which can be connected to the interrupt input of a
microcontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After
time, tiv, the signal INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port
is changed to the original setting, or data is read from or written to the port that generated the interrupt. Resetting
occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal or in the write
mode at the ACK bit after the falling edge of the SCL signal. Interrupts that occur during the ACK clock pulse can
be lost (or be very short), due to the resetting of the interrupt during this pulse. Each change of the I/Os after
resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the
interrupt circuit. This device does not have internal configuration or status registers. Instead, read or write to the
device I/Os directly after sending the device address (see Figure 18 and Figure 19).
By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports, without having to communicate via the I2C bus. Thus, the PCF8575 can remain a simple slave
device.
Every data transmission to or from the PCF8575 must consist of an even number of bytes. The first data byte in
every pair refers to port 0 (P07–P00), and the second data byte in every pair refers to port 1 (P17–P10). To write
to the ports (output mode), the master first addresses the slave device, setting the last bit of the byte containing
the slave address to logic 0. The PCF8575 acknowledges, and the master sends the first data byte for P07–P00.
After the first data byte is acknowledged by the PCF8575, the second data byte (P17–P10) is sent by the master.
Once again, the PCF8575 acknowledges the receipt of the data, after which this 16-bit data is presented on the
port lines.
The number of data bytes that can be sent successively is not limited. After every two bytes, the previous data is
overwritten. When the PCF8575 receives the pairs of data bytes, the first byte is referred to as P07–P00 and the
second byte as P17–P10. The third byte is referred to as P07–P00, the fourth byte as P17–P10, and so on.
Before reading from the PCF8575, all ports desired as input should be set to logic 1. To read from the ports
(input mode), the master first addresses the slave device, setting the last bit of the byte containing the slave
address to logic 1. The data bytes that follow on the SDA are the values on the ports. If the data on the input port
changes faster than the master can read, this data may be lost.
When power is applied to VCC, an internal power-on reset holds the PCF8575 in a reset state until VCC has
reached VPOR. At that time, the reset condition is released, and the device I2C-bus state machine initializes the
bus to its default state.
The hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to eight
devices to share the same I2C bus or SMBus. The fixed I2C address of the PCF8575 is the same as the
PCF8575C, PCF8574, PCA9535, and PCA9555, allowing up to eight of these devices, in any combination, to
share the same I2C bus or SMBus.
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8.2 Functional Block Diagram
8.2.1 Logic Diagram (Positive Logic)
INT
A0
A1
A2
SCL
SDA
PCF8575
1
Interrupt
Logic
LP Filter
21
2
P07−P00
3
22
23
I2C Bus
Control
Input
Filter
Shift
Register
I/O
Port
16 Bits
P17−P10
Write Pulse
VCC
GND
24
12
Read Pulse
Power-On
Reset
8.2.2 Simplified Schematic Diagram of Each P-Port Input/Output
VCC
Write Pulse
IOH
100mA
Data From
Shift Register
IOHT
D
Q
FF
P07−P00
CI
IOL
S
Power-On
Reset
D
P17−P10
Q
GND
FF
Read Pulse
CI
S
To Interrupt
Logic
Data To
Shift Register
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8.3 Feature Description
8.3.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 15). After the Start condition, the device address
byte is sent, most significant bit (MSB) first, including the data direction bit (R/W). This device does not respond
to the general call address. After receiving the valid address byte, this device responds with an ACK, a low on
the SDA input/output during the high of the ACK-related clock pulse. The address inputs (A2–A0) of the slave
device must not be changed between the Start and Stop conditions.
The data byte follows the address ACK. If the R/W bit is high, the data from this device are the values read from
the P port. If the R/W bit is low, the data are from the master, to be output to the P port. The data byte is followed
by an ACK sent from this device. If other data bytes are sent from the master, following the ACK, they are
ignored by this device. Data are output only if complete bytes are received and acknowledged. The output data is
valid at time (tpv) after the low-to-high transition of SCL, during the clock cycle for the ACK.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 16).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 15).
The number of data bytes transferred between the Start and Stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the
receiver can send an ACK bit.
A slave receiver that is addressed must generate an ACK after the reception of each byte. Also, a master must
generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The device
that acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable low
during the high pulse of the ACK-related clock period (see Figure 17). Setup and hold times must be taken into
account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after
the last byte that has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 15. Definition of Start and Stop Conditions
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Feature Description (continued)
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 16. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL from
Master
1
2
89
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 17. Acknowledgment on I2C Bus
8.3.2 Interface Definition
BYTE
2
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
I C slave address
L
H
L
L
A2
A1
A0
R/W
P0x I/O data bus
P07
P06
P05
P04
P03
P02
P01
P00
P1x I/O data bus
P17
P16
P15
P14
P13
P12
P11
P10
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8.3.3 Address Reference
INPUTS
I2C BUS SLAVE 8-BIT
READ ADDRESS
I2C BUS SLAVE 8BIT WRITE
ADDRESS
A2
A1
A0
L
L
L
65 (decimal), 41
(hexadecimal)
64 (decimal), 40
(hexadecimal)
L
L
H
67 (decimal), 43
(hexadecimal)
66 (decimal), 42
(hexadecimal)
L
H
L
69 (decimal), 45
(hexadecimal)
68 (decimal), 44
(hexadecimal)
L
H
H
71 (decimal), 47
(hexadecimal)
70 (decimal), 46
(hexadecimal)
H
L
L
73 (decimal), 49
(hexadecimal)
72 (decimal), 48
(hexadecimal)
H
L
H
75 (decimal), 4B
(hexadecimal)
74 (decimal), 4A
(hexadecimal)
H
H
L
77 (decimal), 4D
(hexadecimal)
76 (decimal), 4C
(hexadecimal)
H
H
H
79 (decimal), 4F
(hexadecimal)
78 (decimal), 4E
(hexadecimal)
8.4 Device Functional Modes
Figure 18 and Figure 19 show the address and timing diagrams for the write and read modes, respectively.
Integral Multiples of Two Bytes
SCL
1
2
3
4
5
6
7
8
1
2
3
4
5
ACK
From Slave
Start
Condition
R/W
S
0
1
0
0
7
8
1
Data
A2 A1 A0
Write to
Port
0
A
P7
2
3
4
5
6
7
8
ACK
From Slave
ACK
From Slave
Slave Address
SDA
6
P6
1
Data
P0
A P7
P0
A
P5
Data A0
and B0
Valid
Data Output
Voltage
tpv
P5 Output
Voltage
IOH
P5 Pullup
Output
Current
IOHT
INT
tir
Figure 18. Write Mode (Output)
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Device Functional Modes (continued)
SCL
1
2
3
4
5
6
7
8
R/W
SDA S
0
1
0
0 A2
A1
A0 1
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
ACK
From Master
ACK
From Slave
A
1
P7 P6 P5 P4 P3 P2 P1
P0
A P7
ACK
From Master
P6 P5 P4
P3 P2
P1 P0
A P7 P6
Read From
Port
Data Into
Port
P7 to P0
P7 to P0
th
tsu
INT
tiv
tir
tir
Figure 19. Read Mode (Input)
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Figure 20 shows an application in which PCF8575 can be used.
9.2 Typical Application
VCC
(1)
VCC
10 kΩ
100 kΩ
(x 3)
VCC
23
Subsystem 1
(e.g., temperature sensor)
4
SDA
SDA
Master
Controller
2 kΩ
24
10 kΩ(1) 10 kΩ
P00
22
SCL
SCL
1
INT
5
INT
P01
INT
P02
P03
GND
PCF8575
6
7
RESET
8
Subsystem 2
(e.g., counter)
P04
9
P05
3
P06 10
A2
2
21
A
A1
P07 11
A0
P10 13
Controlled Device
(e.g., CBT device)
ENABLE
B
P11 14
ALARM
P12 15
Subsystem 3
(e.g., alarm system)
P13 16
P14 17
VCC
P15 18
P16 19
P17 20
GND
12
(1)
The SCL and SDA pins must be tied directly to VCC because if SCL and SDA are tied to an auxiliary power supply
that could be powered on while VCC is powered off, then the supply current, ICC, will increase as a result.
A.
Device address is configured as 0100000 for this example.
B.
P0, P2, and P3 are configured as outputs.
C.
P1, P4, and P5 are configured as inputs.
D.
P6 and P7 are not used and must be configured as outputs.
Figure 20. Application Schematic
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Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Minimizing ICC When I/Os Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 20. For a P-port configured as an input, ICC increases as VI becomes lower than VCC. The LED is a diode,
with threshold voltage VT, and when a P-port is configured as an input the LED will be off but VI is a VT drop
below VCC.
For battery-powered applications, it is essential that the voltage of P-ports controlling LEDs is greater than or
equal to VCC when the P-ports are configured as input to minimize current consumption. Figure 21 shows a highvalue resistor in parallel with the LED. Figure 22 shows VCC less than the LED supply voltage by at least VT.
Both of these methods maintain the I/O VI at or above VCC and prevents additional supply current consumption
when the P-port is configured as an input and the LED is off.
VCC
LED
100 kΩ
VCC
LEDx
Figure 21. High-Value Resistor in Parallel With LED
3.3 V
VCC
5V
LED
LEDx
Figure 22. Device Supplied by a Lower Voltage
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Typical Application (continued)
9.2.2 Detailed Design Procedure
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all slaves on the I2C bus. The minimum pull-up resistance is a function of
VCC, VOL,(max), and IOL:
Rp(min) =
VCC - VOL(max)
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation,
fSCL = 400 kHz) and bus capacitance, Cb:
Rp(max) =
tr
0.8473 ´ Cb
(2)
2
The maximum bus capacitance for an I C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the PCF8575, Ci for SCL or
Cio for SDA, the capacitance of wires/connections/traces, and the capacitance of additional slaves on the bus.
9.2.3 Application Curves
25
1.8
Standard-mode
Fast-mode
1.6
1.4
Rp(min) (kOhm)
Rp(max) (kOhm)
20
15
10
1.2
1
0.8
0.6
0.4
5
VCC > 2V
VCC <= 2
0.2
0
0
0
50
100
150
Standard-mode
(fSCL= 100 kHz, tr = 1 µs)
200
250
Cb (pF)
300
350
400
450
0
0.5
1
1.5
2
D008
Fast-mode
(fSCL= 400 kHz, tr= 300 ns)
Figure 23. Maximum Pull-Up Resistance (Rp(max)) vs Bus
Capacitance (Cb)
2.5
3
VCC (V)
3.5
4
4.5
5
5.5
D009
VOL = 0.2*VCC, IOL = 2 mA
when VCC ≤ 2 V
VOL = 0.4 V, IOL = 3 mA
when VCC > 2 V
Figure 24. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up
Reference Voltage (VCC)
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10 Power Supply Recommendations
The operating power-supply voltage range of the PCF8575 is 2.5 V to 5.5 V applied at the VCC pin. When the
PCF8575 is powered on for the first time or anytime the device needs to be reset by cycling the power supply,
the power-on reset requirements must be followed to ensure the I2C bus logic is initialized properly.
10.1 Power-On Reset
A power-on reset condition can be missed if the VCC ramps are outside specification listed below.
10.2 System Impact
If ramp conditions are outside timing allowances above, POR condition can be missed, causing the device to lock
up.
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11 Layout
11.1 Layout Guidelines
For printed circuit board (PCB) layout of the PCF8575 device, common PCB layout practices should be followed
but additional concerns related to high-speed data transfer such as matched impedances and differential pairs
are not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in
the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These
capacitors should be placed as close to the PCF8575 as possible. These best practices are shown in Figure 25.
For the layout example provided in Figure 25, it would be possible to fabricate a PCB with only 2 layers by using
the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND). However,
a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to
route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other
internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are
placed directly next to the surface mount component pad which needs to attach to VCC or GND and the via is
connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace
needs to be routed to the opposite side of the board, but this technique is not demonstrated in Figure 25.
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11.2 Layout Example
LEGEND
To I2C Master
To I2C Master
Power or GND Plane
VCC
VIA to Power Plane
VIA to GND Plane
INT
VCC
24
2
A1
SDA
23
3
A2
SCL
22
4
P00
A0
21
5
P01
P17
20
P16
19
P15
18
P14
17
02
7
P03
8
P04
9
P05
P13
16
10
P06
P12
15
11
P07
P11
14
12
GND
P10
13
To I/Os
To I/Os
6P
PCF8575
1
To I/Os
To I/Os
By-pass/De-coupling
capacitors
GND
Figure 25. Layout Example for PCF8575
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12 Device and Documentation Support
12.1 Device Support
12.2 Documentation Support
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PCF8575DB
ACTIVE
SSOP
DB
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF575
PCF8575DBQR
ACTIVE
SSOP
DBQ
24
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PCF8575
PCF8575DBQRG4
ACTIVE
SSOP
DBQ
24
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PCF8575
PCF8575DBR
ACTIVE
SSOP
DB
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF575
PCF8575DBRE4
ACTIVE
SSOP
DB
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF575
PCF8575DGVR
ACTIVE
TVSOP
DGV
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF575
PCF8575DGVRG4
ACTIVE
TVSOP
DGV
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF575
PCF8575DW
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCF8575
PCF8575DWR
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCF8575
PCF8575PW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF575
PCF8575PWE4
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF575
PCF8575PWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF575
PCF8575PWRE4
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PF575
PCF8575RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PF575
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
PCF8575DBQR
Package Package Pins
Type Drawing
SSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DBQ
24
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
PCF8575DBR
SSOP
DB
24
2000
330.0
16.4
8.2
8.8
2.5
12.0
16.0
Q1
PCF8575DGVR
TVSOP
DGV
24
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
PCF8575DWR
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
PCF8575PWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
PCF8575RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCF8575DBQR
SSOP
DBQ
24
2500
367.0
367.0
38.0
PCF8575DBR
SSOP
DB
24
2000
367.0
367.0
38.0
PCF8575DGVR
TVSOP
DGV
24
2000
367.0
367.0
35.0
PCF8575DWR
SOIC
DW
24
2000
350.0
350.0
43.0
PCF8575PWR
TSSOP
PW
24
2000
367.0
367.0
38.0
PCF8575RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 2.5
2.1±0.1
(0.2) TYP
12
7
20X 0.5
6
13
25
2X
2.5
SYMM
1
PIN 1 ID
(OPTIONAL)
18
24X 0.30
0.18
24
19
SYMM
24X 0.50
0.30
0.1
0.05
C A B
C
4224376 / A 07/2018
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
(3.8)
(
2.1)
19
24
24X (0.6)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.8)
2X
(0.8)
(Ø0.2) VIA
TYP
6
13
(R0.05)
12
7
2X(0.8)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224376 / A 07/2018
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
(0.19)
4X ( 0.94)
19
24
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.8)
(0.57)
TYP
6
13
(R0.05) TYP
METAL
TYP
25
7
SYMM
12
(0.57)
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 20X
4224376 / A 07/2018
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
13
B
0.30
0.19
0.1
C A B
24X
4.5
4.3
NOTE 4
1.2 MAX
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
13
12
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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• DALLAS, TEXAS 75265
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