Texas Instruments | DS90C189-Q1 Low Power, 1.8 V RGB-to-Open LDI (LVDS) Bridge (Rev. A) | Datasheet | Texas Instruments DS90C189-Q1 Low Power, 1.8 V RGB-to-Open LDI (LVDS) Bridge (Rev. A) Datasheet

Texas Instruments DS90C189-Q1 Low Power, 1.8 V RGB-to-Open LDI (LVDS) Bridge (Rev. A) Datasheet
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DS90C189-Q1
SNLS584A – JULY 2018 – REVISED AUGUST 2018
DS90C189-Q1 Low Power, 1.8 V RGB-to-Open LDI (LVDS) Bridge
1 Features
3 Description
•
The DS90C189-Q1 is a low power bridge for
automotive applications that reduces the size of the
RGB interface between the host GPU and the
Display.
1
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications
with the Following Specifications:
– Device Temperature Grade 2: –40°C to
+105°C Ambient Operating Temperature
– Device HBM ESD Classification Level ±8 kV
– Device CDM ESD Classification Level ±750 V
150 mW Typical Power Consumption at 185 MHz
(SIDO mode)
Drives QXGA and WQXGA Class Displays
Two Operating Modes:
– Single Pixel In, Single Pixel Out (SISO): 105
MHz Maximum
– Single Pixel In, Dual Pixel Out (SIDO): 185
MHz Maximum
Supports 24-Bit RGB
Supports 3D+C, 4D+C, 6D+C, 6D+2C, 8D+C, and
8D+2C LVDS Configurations
Compatible With FPD-Link Devices
Operates Off a Single 1.8 V Supply
Interfaces Directly With 1.8 V LVCMOS
Less Than 10 mW Power Consumption in Sleep
Mode
Spread Spectrum Clock Compatible
Small 9 mm × 9 mm × 0.9 mm 64-Pin VQFN
Package
DS90C189-Q1 supports 2 modes of operation.
• In single pixel mode in/out mode, the device can
drive up to SXGA+ (1400x1050) at 60 Hz. In this
mode, the device converts one bank of 24-bit
RGB data to a one channel 4D+C LVDS data
stream.
• In single pixel in / dual pixel out mode, the device
can drive up to WUXGA+ (1920x1440) at 60 Hz.
In this configuration, the device provides single-todual pixel conversion and converts one bank of
24-bit RGB data into two channels of 4D+C LVDS
streams at half the pixel clock rate.
For all the modes, the device supports 24bpp color.
The DS90C189-Q1 is offered in a small 64 pin QFN
package and features single 1.8 V supply for minimal
power dissipation.
Device Information(1)
2 Applications
•
•
•
•
The DS90C189-Q1 Bridge is designed to support
single pixel data transmission between a Host and a
Flat Panel Display at resolutions of up to QXGA
(2048x1536) at 60 Hz. The transmitter converts up to
24 bits (Single Pixel 24-bit color) of 1.8 V LVCMOS
data into two channels of 4 data + clock (4D+C)
reduced width interface LVDS compatible data
streams.
PART NUMBER
Camera Monitor Systems (CMS)
Automotive Head Unit
Smart Mirror
Cluster
PACKAGE
DS90C189-Q1
BODY SIZE (NOM)
VQFN (64)
9.00 mm × 9.00 mm
(1) For all available packages, see the order addendum at the
end of the data sheet.
4 Typical Application Diagrams
1.8 V LVCMOS
(24 bit RGB + HS/VS/DE)
1.8 V LVCMOS
(24 bit RGB + HS/VS/DE)
2 Channels FPD-Link (LVDS)
(4 Data + Clock)
1.8 V
GPU
DS90C189Q1
L
A
T
C
H
Single Pixel
R[7:0] G[7:0]
B[7:0]
GPU ± Jacinto 6
Display (TCON)
LVDS
4D+C
(odd pixel)
Single Pixel
R[7:0] G[7:0]
B[7:0]
DS90C189Q1
L
A
T
C
H
&
LVDS
4D+C
(even pixel)
&
P
2
S
HS
VS
DE
GPO/CNTL (L/R)
PCLK
2 Channels OLDI (LVDS)
(4 Data + Clock)
2 Lanes FPD-Link III
1.8 V
DS90UB947
-Q1 SER
Display (TCON)
DOUT0+
DOUT0-
RIN0+
RIN0-
DOUT1+
DOUT1-
RIN1+
RIN1-
FPD-Link III
Interface
P
2
S
HS
VS
DE
GPO/CNTL (L/R)
PCLK
PLL
PDB
PLL
Copyright © 2017, Texas Instruments Incorporated
PDB
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90C189-Q1
SNLS584A – JULY 2018 – REVISED AUGUST 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Typical Application Diagrams ..............................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
1
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Recommended Input Characteristics........................ 6
Switching Characteristics .......................................... 7
AC Timing Diagrams................................................. 7
Typical Characteristics ............................................ 11
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagrams ..................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 14
8.5 Programming........................................................... 15
9
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application ................................................. 19
10 Power Supply Recommendations ..................... 21
10.1 Power Up Sequence ............................................. 21
10.2 Power Supply Filtering .......................................... 21
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
5 Revision History
Changes from Original (May 2018) to Revision A
•
2
Page
Changed device status from Advanced Information to Production Data ............................................................................... 1
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SNLS584A – JULY 2018 – REVISED AUGUST 2018
6 Pin Configuration and Functions
OA_3+
OB_0-
OB_0+
OB_1-
OB_1+
OB_2-
OB_2+
OB_C-
OB_C+
41
40
39
38
37
36
35
34
33
44
OA_C+
OA_C-
45
OA_3-
OA_2-
46
42
OA_2+
47
43
OA_1+
OA_1-
48
RTD Package
64-Pin VQFN
Top View
OA_0-
49
32
OB_3-
OA_0+
50
31
VDDTX
NC
51
30
OB_3+
PDB
52
29
NC
IN0
53
28
VDD
VODSEL
54
27
MODE0
IN_1
55
26
RFB
IN_2
56
25
IN_27
IN_3
57
24
IN_26
IN_4
58
23
IN_25
IN_5
59
22
IN_24
DS90C189-Q1
64 VQFN
Top Down View
IN_6
60
21
IN_23
IN_7
61
20
IN_22
IN_8
62
19
IN_21
NC
63
18
VDD
64
17
DE
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IN_9
IN_10
IN_11
IN_12
IN_13
IN_CLK
IN_14
IN_15
IN_16
IN_17
RSVD
HS
VS
NC
NC
VDDP
DAP
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DS90C189 Pin Descriptions
NAME
NO.
I/O
DESCRIPTION
25-19,
10-7,
5-1,
62-55,
53
I
Data Inputs
Typically consists of 8 Red, 8 Green, 8 Blue and a general purpose or L/R control
bit.
Includes pull down.
12,
13,
18
I
Video Control Signal Inputs HS = Horizontal Sync, VS = Vertical SYNC, and DE = Data Enable
6
I
Pixel Input Clock
Includes pull down.
1.8-V LVCMOS VIDEO INPUTS
IN_[27:21],
IN_[17:14],
IN_[13:9],
IN_[8:1]
IN_[0]
HS,
VS ,
DE
IN_CLK
1.8-V LVCMOS CONTROL INPUTS
MODE0
27
I
Mode Control Input (MODE0) 0= Single In / Single Out
1= Single In / Dual Out
Includes pull down.
RFB
26
I
Rising / Falling Clock Edge Select Input 0 = Falling Edge
1 = Rising Edge
Includes pull down.
PDB
52
I
Power Down (Sleep) Control Input 0 = Sleep (Power Down mode)
1 = Device Active (enabled)
Includes pull down.
VODSEL
54
I
VOD Level Select Input 0 = Low swing
1 = Normal swing
Includes pull down.
14, 15, 17, 29, 51,
63
I
No Connect Pin – Leave Open
11
I
Reserved – Tie to Ground.
OA_C+
OA_C-
43
44
O
Channel A LVDS Output Clock –
Expects 100 Ω termination.
OA_[0]+,
OA_[0]-
50
49
O
Channel A LVDS Output Data –
Expects 100 Ω termination.
OA_[1]+,
OA_[1]-
48
47
O
Channel A LVDS Output Data –
Expects 100 Ω termination.
OA_[2]+,
OA_[2]-
46
45
O
Channel A LVDS Output Data –
Expects 100 Ω termination.
OA_[3]+,
OA_[3]-
41
42
O
Channel A LVDS Output Data –
Expects 100 Ω termination.
OB_C+,
OB_C-
33
34
O
Channel B LVDS Output Clock –
Expects 100 Ω termination.
OB_[0]+,
OB_[0]-
39
40
O
Channel B LVDS Output Data –
Expects 100 Ω termination.
OB_[1]+,
OB_[1]-
37
38
O
Channel B LVDS Output Data –
Expects 100 Ω termination.
OB_[2]+,
OB_[2]-
35
36
O
Channel B LVDS Output Data –
Expects 100 Ω termination.
OB_[3]+,
OB_[3]-
30
32
O
Channel B LVDS Output Data –
Expects 100 Ω termination.
31
P
Power supply for LVDS Drivers, 1.8 V.
28, 64
P
Power supply pin for core, 1.8 V.
N/C
RSVD
LVDS OUTPUTS
POWER AND GROUND
VDDTX
VDD
VDDP
16
P
Power supply pin for PLL, 1.8 V.
DAP
DAP
G
Connect DAP to Ground plane.
4
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7 Specifications
7.1 Absolute Maximum Ratings
(1)
See
MIN
MAX
UNIT
Supply Voltage (VDD)
−0.3
2.5
V
LVCMOS Input Voltage
−0.3
VDD + 0.3
V
LVDS Driver Output Voltage
−0.3
3.6
V
150
°C
150
°C
LVDS Output Short-Circuit Duration
Continuous
Junction Temperature
−65
Storage Temperature (Tstg)
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
±8000
Charged-device model (CDM), per JEDEC specification JESD22-C101
±750
UNIT
V
7.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Supply Voltage
1.71
1.80
1.89
V
Operating Free Air Temperature (TA)
−40
+25
+105
°C
80
100
120
Ω
<90
mVp-p
Differential Load Impedance
Supply Noise Voltage
7.4 Thermal Information
DS90C189-Q1
THERMAL METRIC
(1)
RTD (VQFN)
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance AEC-Q100 Qualified
23.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
12.5
°C/W
RθJB
Junction-to-board thermal resistance
7.9
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
7.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.0
°C/W
(1)
For more information about traditional and new thermalmetrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
0.66VDD
VDD
VIL
Low Level Input Voltage
GND
0.35VDD
V
IIN
Input Current
µA
VIN = 0V or VDD = 1.71 V to 1.89 V
- 10
±1
+10
VODSEL = VDD
160
(320)
340
(680)
500
(1000)
mV
(mVP-P)
VODSEL = VGND
110
(220)
220
(440)
400
(800)
mV
(mVP-P)
LVDS DRIVER DC SPECIFICATIONS
VOD
Differential Output Voltage
RL = 100Ω
See Figure 3
ΔVOD
Change in VOD between
Complimentary Output States
RL = 100Ω
See Figure 3
VOS
Offset Voltage
RL = 100Ω
See Figure 3
ΔVOS
Change in VOS between
Complimentary Output States
RL = 100Ω
See Figure 3
IOS
Output Short-Circuit Current
VOUT = GND, VODSEL = VDD
50
1.09
1.22
1.36
50
−15.5
mV
V
mV
mA
SUPPLY CURRENT
IDDT1
Worst Case Supply Current
(includes load current)
IDDT2
IDDTP
IDDTG
IDDZ
Supply Current PRBS-7
Supply Current 16 Grayscale
Power Down Supply Current
f = 105 MHz,
MODE0 = GND
(SISO)
50
85
mA
f = 185 MHz,
MODE0 = VDD
(SIDO)
80
140
mA
MODE0 = VDD
(SIDO),
f = 150 MHz,
RL = 100 Ω,
PRBS-7 Pattern
VODSEL = GND,
VDD = 1.8
50
mA
VODSEL = VDD,
VDD = 1.8
70
mA
MODE0 = VDD
(SIDO),
f = 150 MHz,
RL = 100 Ω,
16 Grayscale
Pattern
VODSEL = GND,
VDD = 1.8
53
mA
VODSEL = VDD,
VDD = 1.8
71
mA
Checkerboard
pattern,
RL = 100 Ω,
VODSEL = VDD,
VDD = 1.89 V,
PDB = GND
6
800
µA
7.6 Recommended Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
MIN
TYP
UNIT
TCIT
IN_CLK Transition Time
Figure 5
2
ns
TCIP
IN_CLK Period
Figure 6
MODE0 = GND
9.53
T (1)
40
ns
MODE0 = VDD
5.40
T
20
ns
TCIH
IN_CLK High Time
0.35T
0.5T
0.65T
ns
TCIL
IN_CLK Low Time
0.35T
0.5T
0.65T
ns
TXIT
IN_n Transition Time
0.3T
ns
(1)
6
MODE0 = VDD
See Figure 6
See Figure 5
1
MAX
MODE0 = GND
1
1.5
4
ns
T = Typical Period of the input Clock.
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7.7 Switching Characteristics
Over recommended operating supply and temperature ranges unlessotherwise specified.
PARAMETER
MIN
TYP
MAX
UNIT
TSTC
IN_n Setup to IN_CLK
See Figure 6
0
ns
THTC
IN_n Hold from IN_CLK
See Figure 6
2.5
ns
LLHT
LVDS Low-to-High Transition Time
See Figure 4
0.33
ns
LHLT
LVDS High-to-Low Transition Time
See Figure 4
0.33
ns
TBIT
LVDS Output Bit Width
MODE0 = GND
1/7 TCIP
ns
MODE0 = VDD
2/7 TCIP
ns
TPPOS0
Transmitter Output Pulse Positions Normalized
for Bit 0
See Figure 9
1
UI
TPPOS1
Transmitter Output Pulse Positions Normalized
for Bit 1
See Figure 9
2
UI
TPPOS2
Transmitter Output Pulse Positions Normalized
for Bit 2
See Figure 9
3
UI
TPPOS3
Transmitter Output Pulse Positions Normalized
for Bit 3
See Figure 9
4
UI
TPPOS4
Transmitter Output Pulse Positions Normalized
for Bit 4
See Figure 9
5
UI
TPPOS5
Transmitter Output Pulse Positions Normalized
for Bit 5
See Figure 9
6
UI
TPPOS6
Transmitter Output Pulse Positions Normalized
for Bit 6
See Figure 9
7
UI
Δ_TPPOS
Variation in Transmitter Pulse Position (Bit 6 —
Bit 0)
See Figure 9
±0.06
UI
TCCS
LVDS Channel to Channel Skew
110
ps
0.176
UI
TJCC
Jitter Cycle-to-Cycle
MODE0 = GND,
f = 105 MHz
TPLLS
Phase Lock Loop Set (Enable Time)
See Figure 7
TPDD
Powerdown Delay
See Figure 8
TSD
Latency Delay
MODE0 = GND
See Figure 11
TLAT
Latency Delay for Single Pixel In / Dual Pixel Out MODE0 = VDD
Mode
See Figure 10
1
2*TCIP +
10.54
ms
100
ns
2*TCIP +
19.38
ns
9*TCIP +
4.19
ns
7.8 AC Timing Diagrams
T
IN_CLK
IN_n,
n = ODD
IN_n,
n = EVEN
Falling Edge CLK (RFB = GND) shown
A.
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/ I/O.
B.
Figure 2 shows a falling edge data strobe (IN_CLK).
Figure 1. Checker Board Test Pattern
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AC Timing Diagrams (continued)
Signal Pattern
Signal
Signal Frequency
f
PCLK
R0
f / 16
R1
f/8
R2
f/4
R3
f/2
R4
Steady State, Low
R5
Steady State, Low
G0
f / 16
G1
f/8
G2
f/4
G3
f/2
G4
Steady State, Low
G5
Steady State, Low
B0
f / 16
B1
f/8
B2
f/4
B3
f/2
B4
Steady State, Low
B5
Steady State, Low
HS
Steady State, High
VS
Steady State, High
DE
Steady State, High
A.
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/ I/O.
B.
Recommended pin to signal mapping for 18 bits per pixel, customer may choose to define differently. The 16
grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
C.
Figure 2 shows a falling edge data strobe (IN_CLK).
Figure 2. “16 Gray Scale” Test Pattern (Falling Edge Clock shown)
OA/B_C+, OA/B_[3:0]+
100:
OA/B_C-, OA/B_[3:0]-
Figure 3. DS90C189-Q1 (Transmitter) LVDS Output Load
8
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AC Timing Diagrams (continued)
+VOD
80%
80%
VSS = 2|VOD|
0V
20%
20%
-VOD
LLHT
LHLT
Figure 4. LVDS Output Transition Times
VDD
80%
80%
50%
20%
20%
GND
TCIT, or
TXIT
TCIT, or
TXIT
Figure 5. LVCMOS Input Transition Times
TCIP
TCIH
TCIL
VDD
50%
GND
VDD
VIHmin
TSTC
VILmax
50%
THTC
GND
Falling Edge CLK shown (RFB = GND)
Figure 6. LVCMOS Input Setup/Hold and Clock High/Low Times (Falling Edge Strobe)
1.8V
VDD
GND
VDD
IN_CLK
GND
VDD
PDB
GND
OCA/B
(Diff.)
TPLLS
(LVDS)
Figure 7. Start Up / Phase Lock Loop Set Time
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AC Timing Diagrams (continued)
GND
VDD
IN_CLK
GND
VDD
PDB
50%
GND
TPDD
OCA/B
(Diff.)
(LVDS)
Figure 8. Sleep Mode / Power Down Delay
Cycle N
OA_C+/-,
or OB_C+/-
bit 1
n-1
OA[3:0]+/-, or
OB[3:0]+/-
bit 0
n-1
bit 6
n
bit 5
n
bit 4
n
bit 3
n
bit 2
n
bit 1
n
bit 0
n
1UI
2UI
3UI
4UI
5UI
6UI
7UI
Figure 9. LVDS Serial Bit Positions
IN_CLK
IN_n
Pixel 1
Pixel 2
Pixel 3
Pixel 4
DE
TLAT
OA/B_C+/
OA_n+/-
Pixel 1
Pixel 3
OB_n+/-
Pixel 2
Pixel 4
Figure 10. Single In, Dual Out Mode Timing and Latency
IN_CLK
IN_n
Pixel n-1
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
TSD
OA/B_C+/Pixel n
OA/B_n+/-
Pixel n+1
Figure 11. Single In, Single Out Mode Timing and Latency
10
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7.9 Typical Characteristics
110
VODSEL = L
VODSEL = H
55
90
50
80
45
IDD (mA)
IDD (mA)
100
60
VODSEL = L
VODSEL = H
70
60
40
35
50
30
40
25
30
20
40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
Figure 12. Typical Current Draw — Single In/Dual Out
Mode — PRBS-7 Data Pattern
20
40
60
80
100
FREQUENCY (MHz)
120
Figure 13. Typical Current Draw — Single In/Single Out
Mode — PRBS-7 Data Pattern
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8 Detailed Description
8.1 Overview
DS90C189-Q1 converts a wide parallel LVCMOS input bus into banks of OLDI (LVDS) data. The device can be
configured to support RGB-888 (24-bit color) in two main configurations: single pixel in / single pixel out; single
pixel in / dual pixel out. The DS90C189-Q1 has power saving features including: selectable VOD and a power
down pin control.
8.2 Functional Block Diagrams
LVCMOS INPUTS
IN_[27:21],
IN_[17:0]
DATA (LVDS)
HS
VS
DE
LVCMOS PARALLEL TO
LVDS
RED
IN_CLK
PLL
CLOCK (LVDS)
GREEN
BLUE
CNTRL (L/R)
PDB
VODSEL
RFB
MODE0
DS90C189-Q1
Single Pixel In / Single Pixel Out
(SISO)
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Functional Block Diagrams (continued)
LVCMOS INPUTS
RED
GREEN
BLUE
CNTRL (L/R)
HS
VS
DE
IN_CLK
LVCMOS PARALLEL TO LVDS
IN_[27:21],
IN_[17:0]
PLL
DATA (LVDS)
CLOCK (LVDS)
PDB
VODSEL
RFB
MODE0
DS90C189-Q1
Single Pixel In / Dual Pixel Out (SIDO)
8.3 Feature Description
8.3.1 AEC-Q100 Qualified
The DS90C189-Q1 is qualified to AEC-Q100 Grade 2 standards and operates from -40°C to +105°C.
8.3.2 ESD Protection
The DS90C189-Q1 has a HBM ESD Classification Level of ±8 kV and CDM ESD Classification Level of ±750 V.
8.3.3 Operating Modes
The DS90C189-Q1 has two operating modes: Single Pixel In, Single Pixel Out (SISO), 25 MHz – 105 MHz and
Single Pixel In, Dual Pixel Out (SIDO), 50 MHz – 185 MHz.
8.3.4 LVDS Configurations
The DS90C189-Q1 supports 3D+C, 4D+C, 6D+C, 6D+2C, 8D+C, and 8D+2C LVDS configurations.
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8.4 Device Functional Modes
8.4.1 Device Configuration
The MODE0 pin is used to configure the DS90C189-Q1 into the two main operation modes as shown in the table
below.
Table 1. Mode Configurations
MODE0
CONFIGURATION
0
Single Pixel Input, Single Pixel Output (SISO)
1
Single Pixel Input, Dual Pixel Output (SIDO)
8.4.2 Single Pixel Input / Single Pixel Output
When MODE0 is set to low, data from IN_[27:21], IN_[17:0], HS, VS and DE is serialized and driven out on
OA_[3:0]+/- with OA_C+/-.
In this configuration IN_CLK can range from 25 MHz to 105 MHz, resulting in a total maximum payload of 700
Mbps (28 bits * 25MHz) to 2.94 Gbps (28 bits * 105 MHz). Each LVDS driver will operate at a speed of 7 bits per
input clock cycle, resulting in a serial line rate of 175 Mbps to 735 Mbps. OA_C+/- will operate at the same rate
as IN_CLK with a duty cycle ratio of 57:43.
8.4.3 Single Pixel Input / Dual Pixel Output
When MODE0 is HIGH, data from IN_[27:21], IN_[17:0], HS, VS and DE is serialized and driven out on
OA_[3:0]+/- and OB_[3:0]+/- with OA_C+/- and OB_C+/-. The input LVCMOS data is split into odd and even
pixels starting with the odd (first) pixel outputs OA_[3:0]+/- and then the even (second) pixel outputs OB_[3:0]+/-.
The splitting of the data signals starts with DE (data enable) transitioning from logic LOW to HIGH indicating
active data (see Figure 10). The number of clock cycles during blanking must be an EVEN number. This
configuration will allow the user to interface with two FPD-Link receivers or other dual pixel inputs.
In this configuration IN_CLK can range from 50 MHz to 185 MHz, resulting in a total maximum payload of 1.4
Gbps (28 bits * 50 MHz) to 5.18 Gbps (28 bits * 185 MHz). Each LVDS driver will operate at a speed of 7 bits per
2 input clock cycles, resulting in a serial line rate of 175 Mbps to 647.5 Mbps. OA_C+/- and OA_B+/- will operate
at ½ the rate as IN_CLK with a duty cycle ratio of 57:43.
In the Single Pixel Input / Dual Pixel Output mode OA_x and OB_x can become misaligned if the clock or data is
interrupted or PDB is toggled. If the clock or data is interrupted or PDB is toggled to prevent misalignment the
following should be done:
1. Disable the clock and data.
2. Toggle PDB to Low and then High.
3. After PDB settles reset the data pattern and enable the clock and data.
8.4.4 Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the input LVCMOS data is latched on. If RFB is HIGH, input data is
latched on the RISING EDGE of the pixel clock (IN_CLK). If RFB is LOW, the input data is latched on the
FALLING EDGE of the pixel clock. Note: This can be set independently of receiver’s output clock strobe.
Table 2. Pixel Clock Edge
RFB
Result
0
FALLING edge
1
RISING edge
8.4.5 Power Management
The DS90C189-Q1 has several features to assist with managing power consumption. The device can be
configured through the MODE0 control pin to enable only the required number of LVDS drivers for each
application. If no clock is applied to the IN_CLK pin, the DS90C189-Q1 will enter a low power state. To place the
DS90C189-Q1 in its lowest power state, the device can be powered down by driving the PDB pin to LOW.
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8.4.6 Sleep Mode (PDB)
The DS90C189-Q1 provides a power down feature. When the device has been powered down, current draw
through the supply pins is minimized and the PLL is shut down. The LVDS drivers are also powered down with
their outputs pulled to GND through 100-Ω resistors (not tri-stated).
Table 3. Power Down Select
PDB
Result
0
SLEEP Mode (default)
1
ACTIVE (enabled)
8.4.7 LVDS Outputs
The DS90C189-Q1's LVDS drivers are compatible with ANSI/TIA/EIA-644-A LVDS receivers. The LVDS drivers
can output a power saving low VOD, or a high VOD to enable longer trace and cable lengths by configuring the
VODSEL pin.
Table 4. VOD Select
VODSEL
Result
0
±220 mV (440 mVpp)
1
±340 mV (680 mVpp)
Any unused LVDS outputs that are not powered down due to the MODE0 pin should be externally terminated
differentially with a 100 ohm resistor. For example, when driving a timing controller (TCON) that only requires an
8D + C LVDS interface, rather than 8D + 2C, the unused clock line should be terminated near the package of the
DS90C189-Q1. For more information regarding the electrical characteristics of the LVDS outputs, refer to the
LVDS DC Characteristics and LVDS Switching Specifications.
8.4.8 LVCMOS Inputs
The DS90C189-Q1 has one bank of 24 data inputs, one set of video control signal (HS, VS and DE) inputs and
several device configuration LVCMOS pins. All LVCMOS input pins are designed for 1.8 V LVCMOS logic. All
LVCMOS inputs, including clock, data and configuration pins, have an internal pull down resistor to set a default
state. If any inputs are unused, they can be left as no connect (NC) or connected to ground.
8.5 Programming
8.5.1 LVDS Interface / TFT Color Data Recommended Mapping
Different color mapping options exist. Check with the color mapping of the Deserializer / TCON device that is
used to ensure compatible mapping for the application. The DS90C189-Q1 supports two modes of operation for
single and dual pixel applications supporting 24bpp color depths.
In the Dual Pixel / 24bpp mode, eight LVDS data lines are provided along with two LVDS clock lines (8D+2C).
The Deserializer may utilize one or two clock lines. The 53 bit interface typically assigns 24 bits to RGB for the
odd pixel, 24 bits to RGB for the even pixel, 3 bits for the video control signals (HS, VS and DE), 1 bit for odd
pixel and 1 bit for even pixel which can be ignored or used for general purpose data, control or L/R signaling.
A reduced width input interface is also supported with a Single-to-Dual Pixel conversion where the data is
presented at double rate (same clock edge, 2X speed, see Figure 10) and the DE transition is used to flag the
first pixel. Also note in the 8D+2C configuration, the three video control signals are sent over both the A and B
outputs. The DES / TCON may recover one set, or both depending upon its implementation. The Dual Pixel /
24bpp 8D+2C LVDS Interface Mapping is shown in Figure 14.
In the Single Pixel / 24bpp mode, four LVDS data lines are provided along with a LVDS clock line (4D+C). The
28 bit interface typically assigns 24 bits to RGB color data, 3 bits to video control (HS, VS and DE) and one
spare bit can be ignored, used for L/R signaling or function as a general purpose bit. The Single Pixel / 24bpp
4D+C LVDS Interface Mapping is shown in Figure 15.
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Programming (continued)
OA_C+/(Diff)
Current Cycle
OA_3+/(SE)
OA_2+/(SE)
IN_27 IN_26 IN_25 IN_24 IN_23 IN_22 IN_21
DE
VS
HS
IN_17 IN_16 IN_15 IN_14
OA_1+/(SE)
IN_13 IN_12 IN_11 IN_10 IN_9
IN_8
IN_7
OA_0+/(SE)
IN_6
IN_1
IN_0
OB_3+/(SE)
IN_27 IN_26 IN_25 IN_24 IN_23 IN_22 IN_21
OB_2+/(SE)
DE
IN_5
IN_4
VS
HS
IN_3
IN_2
IN_17 IN_16 IN_15 IN_14
OB_1+/(SE)
IN_13 IN_12 IN_11 IN_10 IN_9
IN_8
IN_7
OB_0+/(SE)
IN_6
IN_1
IN_0
IN_5
IN_4
IN_3
IN_2
OB_C+/(Diff)
Figure 14. Dual Pixel / 24bpp LVDS Mapping
OA_C+/(Diff)
Current Cycle
OA_3+/(SE)
OA_2+/(SE)
IN_27 IN_26 IN_25 IN_24 IN_23 IN_22 IN_21
DE
VS
HS
IN_17 IN_16 IN_15 IN_14
OA_1+/(SE)
IN_13 IN_12 IN_11 IN_10 IN_9
IN_8
IN_7
OA_0+/(SE)
IN_6
IN_1
IN_0
IN_5
IN_4
IN_3
IN_2
Figure 15. Single Pixel / 24bpp LVDS Mapping
8.5.1.1 Color Mapping Information
A defacto color mapping is shown next. Different color mapping options exist. Check with the color mapping of
the Deserializer / TCON device that is used to ensure compatible mapping for the application.
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Table 5. Single Pixel Input / 24bpp / MSB on CH3
DS90C189-Q1 Input
Color Mapping
Note
IN_22
R7
MSB
IN_21
R6
IN_5
R5
IN_4
R4
IN_3
R3
IN_2
R2
IN_1
R1
IN_0
R0
LSB
IN_24
G7
MSB
IN_23
G6
IN_11
G5
IN_10
G4
IN_9
G3
IN_8
G2
IN_7
G1
IN_6
G0
LSB
IN_26
B7
MSB
IN_25
B6
IN_17
B5
IN_16
B4
IN_15
B3
IN_14
B2
IN_13
B1
IN_12
B0
DE
DE
Data Enable (1)
VS
VS
Vertical Sync
HS
HS
Horizontal Sync
IN_27
GP
General Purpose
(1)
See section Single Pixel Input / Dual Pixel Output.
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Table 6. Single Pixel Input / 24bpp / LSB on CH3
DS90C189-Q1 Input
Color Mapping
Note
IN_5
R7
MSB
IN_4
R6
IN_3
R5
IN_2
R4
IN_1
R3
IN_0
R2
IN_22
R1
IN_21
R0
LSB
IN_11
G7
MSB
IN_10
G6
IN_9
G5
IN_8
G4
IN_7
G3
IN_6
G2
IN_24
G1
IN_23
G0
LSB
IN_17
B7
MSB
IN_16
B6
IN_15
B5
IN_14
B4
IN_13
B3
IN_12
B2
IN_26
B1
IN_25
B0
DE
DE
Data Enable (1)
VS
VS
Vertical Sync
HS
HS
Horizontal Sync
IN_27
GP
General Purpose
(1)
18
See section Single Pixel Input / Dual Pixel Output.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS90C189-Q1 is a Low Power Bridge for automotive application that reduces the size of the RGB interface
between the host GPU and the Display. It is designed to support single pixel data transmission between Host
and Flat Panel Display up to QXGA (2048x1536) at 60 Hz resolutions. The transmitter converts up to 24 bits
(Single Pixel 24 bit color) of 1.8V LVCMOS data into two channels of 4 data + clock (4D+C) reduced width
interface LVDS compatible data streams.
9.2 Typical Application
1.8 V LVCMOS
(24 bit RGB + HS/VS/DE)
2 Channels FPD-Link (LVDS)
(4 Data + Clock)
1.8 V
GPU
Display (TCON)
DS90C189Q1
LVDS
4D+C
(odd pixel)
L
A
T
C
H
Single Pixel
R[7:0] G[7:0]
B[7:0]
LVDS
4D+C
(even pixel)
&
P
2
S
HS
VS
DE
GPO/CNTL (L/R)
PCLK
PLL
PDB
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Figure 16. Single Pixel In Dual Pixel Out (SIDO) Mode
9.2.1 Design Requirements
The DS90C189 is used to convert 24-bit color to two channels of LVDS datastreams.
Table 7. Design Parameters
DESIGN PARAMETER
VALUE
Supply
1.8V
Display Driven
SXGA+, WUXGA+
Pixel Depth
24 bits
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9.2.2 Detailed Design Procedure
9.2.2.1 LVDS Interconnect Guidelines
Refer to the AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and Transmission
Line RAPIDESIGNER Operation and Applications Guide (SNLA035) for full details.
• Use 100 Ω coupled differential pairs
• Use differential connectors when above 500 Mbps
• Minimize skew within the pair
• Use the S/2S/3S rule in spacings
– S = space between the pairs
– 2S = space between pairs
– 3S = space to LVCMOS signals
• Place ground vias next to signal vias when changing between layers
• When a signal changes reference planes, place a bypass cap and vias between the new and old reference
plane
For more tips and detailed suggestions regarding high speed board layout principles, see the LVDS Owner's
Manual at http://www.ti.com/lvds
9.2.3 Application Curves
110
60
VODSEL = L
VODSEL = H
90
50
80
45
70
60
40
35
50
30
40
25
30
20
40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
Figure 17. Typical Current Draw - Single In/Dual Out Mode
- PRBS-7 Data Pattern
20
VODSEL = L
VODSEL = H
55
IDD (mA)
IDD (mA)
100
20
40
60
80
100
FREQUENCY (MHz)
120
Figure 18. Typical Current Draw - Single In/Single Out
Mode - PRBS-7 Data Pattern
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10 Power Supply Recommendations
10.1 Power Up Sequence
The VDD power supply pins do not require a specific power on sequence and can be powered on in any order.
However, the PDB pin should only be set to logic HIGH once the power sent to all supply pins is stable. Active
data inputs should not be applied to the DS90C189-Q1 until all of the input power pins have been powered on,
settled to the recommended operating voltage and the PDB pin has be set to logic HIGH.
The user experience can be impacted by the way a system powers up and powers down an LCD screen. The
following sequence is recommended:
Power up sequence (DS90C189-Q1 PDB input initially LOW):
1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off.
2. Toggle DS90C189-Q1 power down pin to PDB = VDD.
3. Enable clock and wait for additional 0-200ms to ensure display noise won’t occur.
4. Enable video source output; start sending black video data.
5. Send >1ms of black video data; this allows the DS90C189-Q1 to be phase locked, and the display to show
black data first.
6. Start sending true image data.
7. Enable backlight.
Power Down sequence (DS90C189-Q1 PDB input initially HIGH):
1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive
this for >2 frame times.
3. Set DS90C189-Q1 power down pin to PDB = GND.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system power.
10.2 Power Supply Filtering
The DS90C189-Q1 has several power supply pins at 1.8 V. It is important that these pins all be connected and
properly bypassed. Bypassing should consist of at least one 0.1μF capacitor placed on each pin, with an
additional 4.7 μF - 22 μF capacitor placed on the PLL supply pin (VDDP). 0.01 μF capacitors are typically
recommended for each pin. Additional filtering including ferrite beads may be necessary for noisy systems. It is
recommended to place a 0 ohm resistor at the bypass capacitors that connect to each power pin to allow for
additional filtering if needed. A large bulk capacitor is recommended at the point of power entry. This is typically
in the 50 μF — 100 μF range.
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11 Layout
11.1 Layout Guidelines
Circuit board layout and stack-up for the LVDS devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. This practice is
easier to implement in dense pcbs with many layers and may not be practical in simpler boards. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. It is recommended to connect power and ground pins
directly to the power and ground planes with bypass capacitors connected to the plane with vias on both ends of
the capacitor.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency. Some devices provide separate power and ground pins for different portions of
the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate
planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean
power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
For more information on the VQFN package, refer to the AN-1187 Leadless Leadframe Package (LLP)
application note (SNOA401).
22
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11.2 Layout Example
Figure 19. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see:
• LVDS Owner's Manual (SNLA187)
• AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008)
• Transmission Line RAPIDESIGNER Operation and Applications Guide (SNLA035)
• AN-1187 Leadless Leadframe Package (LLP) (SNOA401)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS90C189TWRTDRQ1
ACTIVE
VQFN
RTD
64
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 115
DS90C189Q
DS90C189TWRTDTQ1
ACTIVE
VQFN
RTD
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 115
DS90C189Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Aug-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DS90C189TWRTDRQ1
VQFN
RTD
64
2500
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
DS90C189TWRTDTQ1
VQFN
RTD
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Aug-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90C189TWRTDRQ1
VQFN
RTD
64
2500
367.0
367.0
38.0
DS90C189TWRTDTQ1
VQFN
RTD
64
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RTD0064F
VQFN - 0.9 mm max height
SCALE 1.600
PLASTIC QUAD FLATPACK - NO LEAD
9.1
8.9
B
A
0.15
0.05
0.05
0.00
PIN 1 ID
(0.15)
DETAIL A
DETAIL A
SCALE 20.000
9.1
8.9
(
TYPICAL
8.75)
0.2
0.1
(0.15)
DETAIL B
DETAIL B
SCALE 20.000
0.9 MAX
TYPICAL
SEE DETAIL A
C
0.08 C
(0.2)
SEE DETAIL B
4X (45 X0.42)
32
17
16
4X
7.5
33
SYMM
65
5.75 0.1
1
64X 0.5
SEATING PLANE
48
64
PIN 1 ID
(R0.2)
SYMM
49
64X
0.5
0.3
64X
0.3
0.2
0.1
0.05
C B
C
A
4223128/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTD0064F
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
5.75)
(1.36) TYP
64X (0.6)
3X (1.265)
64
64X (0.25)
49
1
48
3X
(1.265)
60X (0.5)
SYMM
(1.36) TYP
65
( 0.2) TYP
VIA
16
(8.8)
33
17
32
SYMM
(8.8)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223128/A 08/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTD0064F
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.36)
TYP
64X (0.6)
64
64X (0.25)
1
49
48
16X ( 1.16)
(1.36)
TYP
60X (0.5)
SYMM
65
(8.8)
METAL
TYP
33
16
17
SYMM
32
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 65:
65% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:8X
4223128/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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