Texas Instruments | HD3SS3412 4-Channel High-Performance Differential Switch (Rev. F) | Datasheet | Texas Instruments HD3SS3412 4-Channel High-Performance Differential Switch (Rev. F) Datasheet

Texas Instruments HD3SS3412 4-Channel High-Performance Differential Switch (Rev. F) Datasheet
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HD3SS3412
SLAS828F – FEBRUARY 2012 – REVISED JULY 2018
HD3SS3412 4-Channel High-Performance Differential Switch
1 Features
3 Description
•
The HD3SS3412 device is a high-speed passive
switch capable of switching four differential channels,
including applications such as two full PCI Express x1
lanes from one source to one of two target locations
in a PC/server application. With its bidirectional
capability the HD3SS3412 also supports applications
that allow connections between one target and two
source devices, such as a shared peripheral between
two platforms. The HD3SS3412 has a single control
line (SEL pin) which can be used to control the signal
path between Port A and either Port B or Port C.
1
•
•
•
•
•
•
•
Compatible With Multiple Interface Standards
Operating up to 12 Gbps Including PCI Express
Gen III and USB 3.0
Wide –3dB Differential BW of over 8 GHz
Excellent Dynamic Characteristics (at 4 GHz)
– Crosstalk = –35 dB
– Off Isolation = –19 dB
– Insertion Loss = –1.5 dB
– Return Loss = –11 dB
Bidirectional "MUX/De-MUX" Type Differential
Switch
VDD Operating Range 3.3 V ±10%
Small 3.5-mm × 9.0-mm, 42-Pin WQFN Package
Common Industry Standard Pinout
Supports XAUI and SGMII
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
The HD3SS3412 is offered in an industry standard
42-pin WQFN package available in a common
footprint shared by several other vendors. The device
is specified to operate from a single supply voltage of
3.3 V over the full temperature range of -40°C to
85ºC.
HD3SS3412
Desktop and Notebook PCs
Server and Storage Area Networks
PCI Express Backplanes
Shared I/O Ports
WQFN (42)
9.00 mm × 3.50 mm
HD3SS3412 Switch Flow Through Routing
GND
VDD
GND
BODY SIZE (NOM)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
HD3SS3412 Pinout
NC
PACKAGE
39
40
B0±
41
B0+
37
42
38
2
A0±
3
36
B1+
GND
4
35
B1±
VDD
5
34
C0+
A1+
6
33
C0±
A1±
7
32
C1+
31
C1±
30
VDD
NC
8
SEL
9
GND
10
29
B2+
A2+
11
28
B2±
A2±
12
27
B3+
Thermal
Pad
A3±
16
23
C3+
GND
17
22
C3±
GND
VDD
NC
GND
21
C2±
20
24
19
15
18
C2+
A3+
21
B3±
25
22
26
14
18
13
17
VDD
GND
1
1
A0+
38
39
42
GND
Not to scale
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
HD3SS3412
SLAS828F – FEBRUARY 2012 – REVISED JULY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
9
1
1
1
2
4
5
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Dissipation Ratings ................................................... 8
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 11
Detailed Description ............................................ 13
9.1 Overview ................................................................. 13
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Description................................................. 14
9.4 Device Functional Modes........................................ 14
10 Application and Implementation........................ 15
10.1 Application Information.......................................... 15
10.2 Typical Application ................................................ 16
11 Power Supply Recommendations ..................... 18
12 Layout................................................................... 18
12.1 Layout Guidelines ................................................. 18
12.2 Layout Example .................................................... 18
13 Device and Documentation Support ................. 19
13.1
13.2
13.3
13.4
13.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
14 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (January 2015) to Revision F
Page
•
Changed temperature range to –40°C to 85ºC from 0°C to 70ºC. ........................................................................................ 1
•
Changed TA To: –40°C MIN and 85°C MAX From: 0°C MIN and 70°C MAX in the Recommended Operating
Conditions table ...................................................................................................................................................................... 7
•
Changed the PD values From: MIN = 15.5, MAX = 21.6 To: MIN = 2.8, MAX = 4.4 in the Dissipation Ratings table ........... 8
Changes from Revision D (December 2015) to Revision E
•
Changed "over the full industrial temperature range of –40°C to 70°C" To: "over the commercial temperature range
of 0°C to 70°C" in the Overview section............................................................................................................................... 13
Changes from Revision C (July 2015) to Revision D
•
Page
Page
Changed "full industrial temperature range of –40°C to 85°C" To: "full industrial temperature range of 0°C to 70°C"
in the Overview section ........................................................................................................................................................ 13
Changes from Revision B (November 2013) to Revision C
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Removed Ordering Information table ..................................................................................................................................... 1
Changes from Revision A (February 2012 ) to Revision B
Page
•
Added additional feature: bidirectional "MUX/de-MUX" type differential switch ..................................................................... 1
•
Added that the device supports XAUI and SGMII .................................................................................................................. 1
•
Changed temperature range from –40°C to 85ºC to 0°C to 70ºC and deleted "industrial" in Description section. ............... 1
2
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SLAS828F – FEBRUARY 2012 – REVISED JULY 2018
•
Changed pin description of NC From: Electrically not connected. To: Electrically not connected. May connect to
VDD or GND, or leave unconnected ...................................................................................................................................... 6
•
Added the Application Information section ........................................................................................................................... 15
Changes from Original (January 2012 ) to Revision A
Page
•
Changed Differential BW Feature bullet from "7.5GHZ" to "8GHz"........................................................................................ 1
•
Changed Dynamic Characteristics Feature sub-bullet from "Isolation" to "Off Isolation" ....................................................... 1
•
Changed Dynamic Characteristics sub-bullet Return Loss from "–9 dB" to "–11 dB" ........................................................... 1
•
Deleted Dynamic Characteristics sub-bullet "Max Intra-Pair (Bit-Bit) Skew".......................................................................... 1
•
Changed ESD, Human body model, MAX voltage from "±2000" to "±4,000" in Absolute Maximum Ratings table .............. 7
•
Changed ILK spec (Diff I/O pins) MAX value from "4 µA" to "130 µA" and added [Ports B and C] and [Port A] to
Conditions statements. ........................................................................................................................................................... 8
•
Changed tPD spec MAX delay from "50" ps to "85" ps in Device Parameters table............................................................... 8
•
Changed SEL-to-switch Ton and Toff spec TYP values from "175" ns to "70" ns; in the Device Parameters table................ 8
•
Changed TSKEW_Inter and TSKEW_Intra spec MAX values from "5 ps" and "4 ps" respectively, to "20 ps" and "8 ps"
respectively, in Electrical Characteristics table....................................................................................................................... 8
•
Changed RL spec TYP value from "–25" and "–9" dB to "–28" and "–11" dB for f=0.3 MHz and f=4000 MHz,
respectively, in Electrical Characteristics table. .................................................................................................................... 8
•
Changed OIRR spec TYP value from "–70" to "–75" dB for f=0.3 MHz, in Electrical Characteristics table. .......................... 8
•
Changed BW spec TYP value from "7.5" GHz to "8" GHz in Electrical Characteristics table. .............................................. 8
•
Changed graphic image for Figure 3.................................................................................................................................... 10
•
Changed graphic image for Figure 4.................................................................................................................................... 10
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SLAS828F – FEBRUARY 2012 – REVISED JULY 2018
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5 Description (continued)
The HD3SS3412 is a generic 4-CH high-speed MUX/de-MUX type of switch that can be used for routing highspeed signals between two different locations on a circuit board. Although it was designed specifically to address
PCI Express Gen III applications, the HD3SS3412 will also support several other high-speed data protocols with
a differential amplitude of <1800 mVpp and a common-mode voltage of < 2 V, as with USB 3.0 and DisplayPort
1.2. The device’s one select input (SEL) pin can easily be controlled by an available GPIO pin within a system or
from a microcontroller.
4
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SLAS828F – FEBRUARY 2012 – REVISED JULY 2018
6 Pin Configuration and Functions
GND
VDD
B0±
A0±
3
36
B1+
GND
4
35
B1±
VDD
5
34
C0+
A1+
6
33
C0±
A1±
7
32
C1+
NC
8
31
C1±
SEL
9
30
VDD
GND
10
29
B2+
A2+
11
28
B2±
A2±
12
27
B3+
VDD
13
26
B3±
GND
14
25
C2+
A3+
15
24
C2±
A3±
16
23
C3+
GND
17
22
C3±
39
37
40
2
Thermal
21
GND
20
VDD
19
Pad
GND
A0+
41
B0+
42
38
18
1
NC
GND
GND
NC
RUA Package
42-Pin WQFN
Top View
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
SWITCH PORT A
A0+
2
I/O
Port A, Channel 0, High-Speed Positive Signal
A0–
3
I/O
Port A, Channel 0, High-Speed Negative Signal
A1+
6
I/O
Port A, Channel 1, High-Speed Positive Signal
A1–
7
I/O
Port A, Channel 1, High-Speed Negative Signal
A2+
11
I/O
Port A, Channel 2, High-Speed Positive Signal
A2–
12
I/O
Port A, Channel 2, High-Speed Negative Signal
A3+
15
I/O
Port A, Channel 3, High-Speed Positive Signal
A3–
16
I/O
Port A, Channel 3, High-Speed Negative Signal
B0+
38
I/O
Port B, Channel 0, High-Speed Positive Signal
B0–
37
I/O
lPort B, Channel 0, High-Speed Negative Signal
SWITCH PORT B
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
B1+
36
I/O
Port B, Channel 1, High-Speed Positive Signal
B1–
35
I/O
Port B, Channel 1, High-Speed Negative Signal
B2+
29
I/O
Port B, Channel 2, High-Speed Positive Signal
B2–
28
I/O
Port B, Channel 2, High-Speed Negative Signal
B3+
27
I/O
Port B, Channel 3, High-Speed Positive Signal
B3–
26
I/O
Port B, Channel 3, High-Speed Negative Signal
C0+
34
I/O
Port C, Channel 0, High-Speed Positive Signal
C0–
33
I/O
Port C, Channel 0, High-Speed Negative Signal
C1+
32
I/O
Port C, Channel 1, High-Speed Positive Signal
C1–
31
I/O
Port C, Channel 1, High-Speed Negative Signal
C2+
25
I/O
Port C, Channel 2, High-Speed Positive Signal
C2–
24
I/O
Port C, Channel 2, High-Speed Negative Signal
C3+
23
I/O
Port C, Channel 3, High-Speed Positive Signal
C3–
22
I/O
Port C, Channel 3, High-Speed Negative Signal
—
Electrically not connected. May connect to VDD or GND, or leave unconnected.
SWITCH PORT C
CONTROL, SUPPLY, AND NO CONNECT
8
NC
18
42
1
4
10
14
GND
17
19
Supply
Negative power supply voltage
21
39
41
Center Pad
SEL
9
I
Select between port B or port C. Internally tied to GND through a 100-kΩ resistor
5
13
VDD
20
Supply
Positive power supply voltage
30
40
6
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SLAS828F – FEBRUARY 2012 – REVISED JULY 2018
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1) (2)
Supply voltage (VDD)
Voltage
MIN
MAX
UNIT
Absolute minimum/maximum supply voltage
–0.5
4
V
Differential I/O
–0.5
4
Control pin (SEL)
–0.5
VDD + 0.5
–65
150
Storage temperature, Tstg
(1)
(2)
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Typical values for all parameters are at VDD = 3.3 V and TA = 25°C. (Temperature limits are specified by design)
MIN
NOM
3.3
MAX
UNIT
VDD
Supply voltage
3
3.6
V
VIH
Input high voltage (SEL pin)
2
VDD
V
VIL
Input low voltage (SEL pin)
–0.1
0.8
V
VI/O_Diff
Differential voltage (differential pins)
Switch I/O diff voltage
0
1.8
VPP
VI/O_CM
Common voltage (differential pins)
Switch I/O common-mode voltage
TA
Operating free-air temperature
Ambient temperature
0
2
V
-40
85
°C
7.4 Thermal Information
HD3SS3412
THERMAL METRIC (1)
RUA (WQFN)
UNIT
42 PINS
RθJA
Junction-to-ambient thermal resistance
53.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
38.2
°C/W
RθJB
Junction-to-board thermal resistance
21.9
°C/W
ψJT
Junction-to-top characterization parameter
27.4
°C/W
ψJB
Junction-to-board characterization parameter
5.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
27.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEVICE PARAMETERS
IIH
Input High Voltage (SEL)
VDD = 3.6 V; VIN = VDD
95
µA
IIL
Input Low Voltage (SEL)
VDD = 3.6 V; VIN = GND
1
µA
Leakage Current (Differential
I/O pins)
ILK
VDD = 3.6 V; VIN = 0 V; VOUT = 2 V
(ILK On OPEN outputs) [Ports B and C]
130
µA
VDD = 3.6 V, VIN = 2 V; VOUT = 0 V
(ILK On OPEN outputs) [Port A]
4
IDD
Supply Current
VDD = 3.6 V; SEL = VDD/GND; Outputs Floating
4.7
CON
Outputs ON Capacitance
VIN = 0 V; Outputs Open; Switch ON
1.5
COFF
Outputs OFF Capacitance
VIN = 0 V; Outputs Open, Switch OFF
1
RON
Output ON resistance
VDD = 3.3 V; VCM = 0.5 V to 1.5 V ; IO = –8 mA
5
ON-resistance flatness
(RON(MAX) – RON(MAIN)
VDD = 3.3 V; –0.35 V ≤ VIN ≤ 1.2 V
tPD
Switch propagation delay
Rsc and RLOAD = 50 Ω
SEL-to-switch TON
SEL-to-switch TOFF
TSKEW_Inter
Inter-pair output skew
(CH-CH)
TSKEW_Intra Intra-pair output skew (bit-bit)
Rsc and RLOAD = 50 Ω
2
Ω
0.7
Ω
1.15
Ω
85
ps
250
70
250
Rsc and RLOAD = 50 Ω
Rsc and RLOAD = 50 Ω
f = 0.3 MHz
–28
f = 2500 MHz
–12
f = 4000 MHz
–11
Differential Crosstalk
(VCM = 0 V)
Also see Typical
Characteristics
f = 0.3 MHz
–90
f = 2500 MHz
–39
f = 4000 MHz
–35
Differential Off-Isolation
(VCM = 0 V)
Also see Typical
Characteristics
f = 0.3 MHz
–75
OIRR
f = 2500 MHz
–22
f = 4000 MHz
–19
f = 0.3 MHz
–0.5
IL
Differential Insertion Loss
(VCM = 0 V)
Also see Typical
Characteristics
f = 2500 MHz
–1.1
f = 4000 MHz
–1.5
Bandwidth
At –3 dB
BW
Ω
70
Differential return loss
(VCM = 0 V)
Also see Typical
Characteristics
XTALK
pF
8
ON-resistance match between
VDD = 3.3 V; –0.35 V ≤ VIN ≤ 1.2 V; IO = –8 mA
pairs of the same channel
RFLAT_ON
mA
pF
ON-resistance match between
VDD = 3.3 V ; –0.35 V ≤ VIN ≤ 1.2 V; IO = –8 mA
channels
ΔRON
RL
6
ns
20
ps
8
ps
dB
dB
dB
dB
8
GHz
7.6 Dissipation Ratings
PD
8
Power Dissipation
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MIN
MAX
UNIT
2.8
4.4
mW
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50%
SEL
90%
VOUT
10%
Toff
Ton
Figure 1. Switch ON and OFF Timing Diagram
VDD
RSC = 50W
An+
RSC = 50W
HD3SS3412
Bn+/Cn+
RL = 50W
An-
Bn-/CnRL = 50W
SEL
VDD
VIN+
50%
50%
50%
50%
0V
VDD
VIN-
0V
VDD
VOUT+
50%
50%
50%
50%
0V
VDD
VOUT+
0V
tP1
tP1
TSKEWInter = Difference between tPD for any two pairs of outputs
TSKEWIntra = Difference between tP1 and tP2 of same pair
Figure 2. Propagation Delay Timing Diagram and Test Setup
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7.7 Typical Characteristics
m1
5
m2 m3
m1
freq=300.0kHz
freq=300.0kHz
dB(SDD21)=-0.491
m4
-2
dB (SDD21)
-4
m2
freq= 2.514GHz
dB(SDD21)=-1.221
-6
-8
m3
freq= 3.985GHz
dB(SDD21)=-1.536
-10
-12
-14
m5
freq= 329.0kHz
dB(SDD11)=-28.545
0
dB (SDD11)
0
-5
-15
m7
freq= 3.985GHz
dB(SDD11)=-11.177
-20
-25
m5
-30
freq, Hz
Figure 3. Differential Insertion Loss
-20
Figure 4. Differential Return Loss
0
m1
freq=300.0kHz
dB(SDD21)=-97.081
-40
m2
freq=2.514GHz
dB(SDD21)=-39.567
-60
-80
m3
freq=3.985GHz
dB(SDD21)=-34.786
m1
-100
m1
freq=300.0kHz
dB(SDD21)=-74.449
m2 m3
-20
dB (SDD21)
m3
m2
dB (SDD21)
2E10
1E10
1E9
1E8
1E7
1E6
2E10
1E10
1E9
1E8
1E7
1E6
m4
freq= 8.331GHz
dB(SDD21)=-2.998
freq, Hz
m2
freq=2.514GHz
dB(SDD21)=-22.000
-40
-60
m1
m3
freq=3.985GHz
dB(SDD21)=-18.935
-80
-100
2E10
1E10
1E9
1E8
1E7
2E10
1E10
1E9
1E8
1E7
1E6
1E6
-120
freq, Hz
freq, Hz
Figure 5. Differential Crosstalk
10
m6
freq= 2.514GHz
dB(SDD11)=-13.842
m7
m6
-10
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Figure 6. Differential Off Isolation
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8 Parameter Measurement Information
Network
Analyzer
P2
P1
VDD
B0+
A0+
100 W
A0B0HD3SS3412
SEL
B1+
A1+
100 W
A1B1-
Figure 7. Cross Talk Measurement Setup
Network
Analyzer
P2
P1
VDD
A0+
B0+
A0-
100 W
B0-
HD3SS3412
SEL
B1+
B1-
Figure 8. Off Isolation Measurement Setup
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Parameter Measurement Information (continued)
A
3.1 Inches Rogers
Microstrip
Oscilloscope
10Gbps PRBS 2 7- 1
Vi=0.8Vpp ; Vcm =0V
Figure 9. Source Eye Diagram Test Setup
A
1.4 Inches
Rogers
Microstrip
1.7 Inches
Rogers
Microstrip
7
10Gbps PRBS 2 - 1
Vi=0.8Vpp ; Vcm =0V
Oscilloscope
Figure 10. Output Eye Diagram Test Setup
12
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9 Detailed Description
9.1 Overview
The HD3SS3412 is a high-speed passive switch offered in an industry standard 42-pin WQFN package available
in a common footprint shared by several other vendors. The device is specified to operate from a single supply
voltage of 3.3 V over the commercial temperature range of 0°C to 70°C. The HD3SS3412 is a generic 4-CH
high-speed mux/demux type of switch that can be used for routing high-speed signals between two different
locations on a circuit board. Although it was designed specifically to address PCI Express Gen III applications,
the HD3SS3412 will also support several other high-speed data protocols with a differential amplitude of < 1800
mVpp and a common-mode voltage of < 2.0 V, as with USB 3.0 and DisplayPort 1.2. The device’s one select
input (SEL) pin can easily be controlled by an available GPIO pin within a system or from a microcontroller.
9.2 Functional Block Diagram
VDD
MUX 0
B0+
B0C0+
C0-
A0+
A0SEL
SEL
100kO
C1+
C1-
SEL
MUX 1
B1+
B1-
A1+
A1-
SEL
C2+
C2-
MUX 2
B2+
B2A2+
A2-
C3+
C3-
MUX 3
SEL
B3+
B3-
A3+
A3-
GND
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9.3 Feature Description
The HD3SS3412 has a single control line (SEL Pin) which can be used to control the signal path between Port A
and either Port B or Port C. The one select input (SEL) pin of the device can easily be controlled by an available
GPIO pin within a system or from a microcontroller. The input signal is selected using the SEL pin.
Table 1. Mux Pin Connections (1)
PORT B OR PORT C CHANNEL
CONNECTED TO PORT A CHANNEL
PORT A CHANNEL
SEL = L
SEL = H
B0+
C0+
A0+
(1)
A0–
B0–
C0–
A1+
B1+
C1+
A1–
B1–
C1–
A2+
B2+
C2+
A2–
B2–
C2–
A3+
B3+
C3+
A3–
B3–
C3–
The HD3SS3412 can tolerate polarity inversions for all differential signals on Ports A, B, and C. Take care to ensure the same polarity is
maintained on Port A versus Port B/C.
9.4 Device Functional Modes
Table 2 lists the functional modes for the HD3SS3412.
Table 2. HD3SS3412 Control Logic
PORT A TO PORT B
CONNECTION STATUS
PORT A TO PORT C
CONNECTION STATUS
L (Default State)
Connected
Disconnected
H
Disconnected
Connected
CONTROL PIN (SEL)
14
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 AC Coupling Caps
Many interfaces require AC coupling between the transmitter and receiver. The 0402 capacitors are the preferred
option to provide AC coupling, and the 0603 size capacitors also work. The 0805 size capacitors and C-packs
should be avoided. When placing AC coupling capacitors symmetric placement is best. A capacitor value of 0.1
µF is best and the value should be match for the ± signal pair. The placement should be along the TX pairs on
the system board, which are usually routed on the top layer of the board.
There are several placement options for the AC coupling capacitors. Because the switch requires a bias voltage,
the capacitors must only be placed on one side of the switch. If they are placed on both sides of the switch, a
biasing voltage should be provided. A few placement options are shown below. In Figure 11, the coupling
capacitors are placed between the switch and endpoint. In this situation, the switch is biased by the system/host
controller.
Figure 11. AC Coupling Capacitors Between Switch Tx and Endpoint Tx
In Figure 12, the coupling capacitors are placed on the host transmit pair and endpoint transmit pair. In this
situation, the switch on the top is biased by the endpoint and the lower switch is biased by the host controller.
Figure 12. AC Coupling Capacitors on Host Tx and Endpoint Tx
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Application Information (continued)
If the common-mode voltage in the system is higher than 2 V, the coupling capacitors are placed on both sides
of the switch (shown in Figure 13). A biasing voltage of less than 2 V is required in this case.
Figure 13. AC Coupling Capacitors on Both Sides of Switch
HD3SS3412
Chipset
Memory/GPU
Hub
Port B
x2
Port C
x2
Port B
x2
Port C
x2
x8
x16
HD3SS3412
Chipset
I/O Hub
HD3SS3412
iGPU
GPIO
Port B
x2
Port C
x2
x8 Graphics Card Slot
Port A
x2
x16 Graphics Card Slot
Microprocessor
HD3SS3412
10.2 Typical Application
Port B
x2
Port C
x2
SEL Pins
Figure 14. Typical Application Block Diagram
16
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Typical Application (continued)
10.2.1 Design Requirements
Table 3 lists the design parameters of this example.
Table 3. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
Input voltage range
3.3 V
Decoupling capacitors
0.1 µF
AC capacitors
75 nF – 200 nF (100 nF shown) USBAA TX p and
n lines require AC capacitors. Alternate mode
signals may or may not require AC capacitors
10.2.2 Detailed Design Procedure
• Connect VDD and GND pins to the power and ground planes of the printed circuit board, with 0.1-uF bypass
capacitor
• Use +3.3-V TTL/CMOS logic level at SEL
• Use controlled-impedance transmission media for all the differential signals
• Ensure the received complimentary signals are with a differential amplitude of <1800 mVpp and a commonmode voltage of <2 V
10.2.3 Application Curves
Figure 15. 10-gbps Source Eye Diagram at a: VID = 800
Mvpp; 27–1 Prbs; VCM= 0 V
Figure 16. 10-gbps Output Eye Diagram at a: VID = 800
Mvpp; 27–1 Prbs; VCM= 0v; VDD= 3.3 V; Sel= 0 V
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11 Power Supply Recommendations
The HD3SS3412 requires +3.3-V digital power sources. VDD 3.3 supply must have 0.1-μF bypass capacitors to
VSS (ground) in order for proper operation. The recommendation is one capacitor for each power terminal. Place
the capacitor as close as possible to the terminal on the device and keep trace length to a minimum. Smaller
value capacitors like 0.01-μF are also recommended on the digital supply terminals.
12 Layout
12.1 Layout Guidelines
•
Decoupling caps should be placed next to each power terminal on the HD3SS3412. Take care to minimize
the stub length of the race connecting the capacitor to the power pin.
Avoid sharing vias between multiple decoupling caps
Place vias as close as possible to the decoupling cop solder pad
Widen VDD/GND planes to reduce effect if static and dynamic IR drop
The VBUS traces/planes must be wide enough to carry maximum of 2-A current
•
•
•
•
12.2 Layout Example
Use controlled-impedance
Transmission media for all
Differential signals
VIA to SW Cooper Pour
VDD3P3
VDD3P3
AX+
AXBX+
BXCX+
CXVSS
SEL
VBUS
GND
Exposed Thermal
Pad Are
3.3V Logic level
VBUS traces wide
enough to carry 2A
current
Figure 17. Layout Example
18
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13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
HD3SS3412RUAR
ACTIVE
WQFN
RUA
42
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
HD3SS3412
HD3SS3412RUAT
ACTIVE
WQFN
RUA
42
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
XHD3SS3412
HD3SS3412
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jul-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jul-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
HD3SS3412RUAR
WQFN
RUA
42
3000
330.0
16.4
3.8
9.3
1.0
8.0
16.0
Q1
HD3SS3412RUAT
WQFN
RUA
42
250
180.0
16.4
3.8
9.3
1.0
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jul-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
HD3SS3412RUAR
WQFN
RUA
42
3000
367.0
367.0
38.0
HD3SS3412RUAT
WQFN
RUA
42
250
210.0
185.0
35.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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