Texas Instruments | ESD224 Low Clamping 4-Channel ESD Protection Device for HDMI Interface (Rev. A) | Datasheet | Texas Instruments ESD224 Low Clamping 4-Channel ESD Protection Device for HDMI Interface (Rev. A) Datasheet

Texas Instruments ESD224 Low Clamping 4-Channel ESD Protection Device for HDMI Interface (Rev. A) Datasheet
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ESD224
SLVSEB4A – FEBRUARY 2018 – REVISED MARCH 2018
ESD224 Low Clamping 4-Channel ESD Protection Device for HDMI Interface
1 Features
3 Description
•
The ESD224 is a bidirectional TVS ESD protection
diode array for high speed applications such as USB
3.0 and HDMI 2.0. The ESD224 is rated to dissipate
ESD strikes at the maximum level specified in the
IEC 61000-4-2 international standard (Level 4). The
ESD224 employs on-chip differentially matched
series elements to enhance down-stream ESD
clamping performance while maintaining the signal
compliance for high speed interfaces. The ultra-low
clamping performance and high differential bandwidth
provided by the ESD224 on-chip ESD protection
network enables the device to be HDMI 2.0 compliant
while providing robust protection to downstream
HDMI devices.
1
•
•
•
•
•
•
•
•
•
IEC 61000-4-2 Level 4 ESD Protection
– ±12-kV Contact Discharge
– ±15-kV Air Gap Discharge
IEC 61000-4-4 EFT Protection
– 80 A (5/50 ns)
IEC 61000-4-5 Surge Protection
– 2 A (8/20 µs)
IO Capacitance:
– 0.5 pF (Typical)
HDMI 2.0 Compliant
Ultra-Low Leakage Current: 0.1 nA (Typical)
Ultra-Low ESD Clamping Voltage: 8 V at 16-A
TLP (System Side)
Supports High Speed Interfaces up to 6 Gbps
Industrial Temperature Range: –40°C to +125°C
Industry Standard DQA Package
The ESD224 is offered in the industry standard
USON-10 (DQA) package. The package features 0.5mm pin pitch easing implementation and reducing
design time.
Device Information(1)
PART NUMBER
2 Applications
•
•
PACKAGE
BODY SIZE (NOM)
USON (10)
2.50 mm × 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
ESD224
TMDS D2+
TMDS D2-
TMDS D1+
TMDS D1-
To System
ESD224
TMDS D0+
TMDS D0TMDS CLK+
TMDS CLK-
TPD4E05U06
CEC
UTILITY
HDMI 2.0 Connector
End Equipment
– Set-Top Boxes
– TV and Monitors
– Laptops and Desktops
– DVD, Blue-ray, Multimedia Players
Interfaces
– HDMI 2.0/1.4
– Ethernet 10/100/1000 Mbps
– USB 3.0
ESD224
DDC_CLK
DDC_DAT
GND
P 5V0
HOTPLUG
TPD1E05U06
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ESD224
SLVSEB4A – FEBRUARY 2018 – REVISED MARCH 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings -JEDEC Specifications ........................
ESD Ratings - IEC Specifications .............................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Parameter Measurement Setup ............................ 8
7.1 IEC 61000-4-2 System Level ESD Test Setup with
HDMI Driver for Clamping Voltage Measurement ..... 8
8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Examples ................................................. 14
12 Device and Documentation Support ................. 15
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
Changes from Original (February 2018) to Revision A
•
2
Page
Changed product status from Advance Information to Production Data ............................................................................... 1
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5 Pin Configuration and Functions
DQA Package
10-Pin USON
Top View
Pin Functions
PIN
NAME
NO.
TYPE
GND
3
GND
8
IO1_C
1
IO2_C
2
IO3_C
4
IO4_C
5
IO4_S
6
System Side I/O Pin
corresponding to
IO4_C
IO3_S
7
System Side I/O Pin
corresponding to
IO3_C
IO2_S
9
System Side I/O Pin
corresponding to
IO2_C
IO1_S
10
System Side I/O Pin
corresponding to
IO1_C
Ground
Connector Side I/O
DESCRIPTION
Ground. Connect to ground. These pins are shorted internally.
ESD protected channel to be connected to the connector
To be connected to the system side
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Electrical Fast
Transient
Peak Pulse
MAX
UNIT
IEC 61000-4-4 Peak Current at 25°C
80
A
IEC 61000-4-5 Surge (tp 8/20 µs) Peak Power at 25°C
17
W
IEC 61000-4-5 Surge (tp 8/20 µs) Peak Current at 25°C
2
A
TA
Operating free-air temperature
-40
125
°C
Tstg
Storage temperature
-65
155
°C
(1)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings -JEDEC Specifications
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2500
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings - IEC Specifications
VALUE
V(ESD)
Electrostatic discharge
IEC 61000-4-2 Contact Discharge, all pins
±12000
IEC 61000-4-2 Air Discharge, all pins
±15000
UNIT
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input voltage
-3.6
3.6
V
TA
Operating Free Air Temperature
-40
125
°C
6.5 Thermal Information
ESD224
THERMAL METRIC (1)
DQA (USON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
173.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
109.6
°C/W
RθJB
Junction-to-board thermal resistance
77.6
°C/W
ΨJT
Junction-to-top characterization parameter
14.3
°C/W
ΨJB
Junction-to-board characterization parameter
77.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics
At TA = 25°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VRWM
Reverse stand-off voltage
IIO < 10 nA, across operating
temperature range
VBRF
Breakdown voltage, Pin 1, 2, 4, 5 to 3
(GND) (1)
IIO = 1 mA
VBRR
Reverse breakdown voltage, pin 1, 2,
4, 5 to 3 (GND) (1)
IIO = -1 mA
VHOLD
Holding voltage, pin1, 2, 4, 5 to 3
(GND) and 3 (GND) to pin 1, 2, 4, 5
IIO = 1 mA
6.3
V
VHOLD-NEG
Breakdown voltage, pin1, 2, 4, 5 to 3
(GND) (2)
IIO = -1 mA
-6.3
V
IPP = 1 A, pin 1, 2, 4, 5 to 3 or
8(GND), GND to pin 1, 2, 4, 5
7
V
IPP = 5 A, pin 1, 2, 4, 5 to 3 or
8(GND), GND to pin 1, 2, 4, 5
9
V
IPP = 16 A, pin 1, 2, 4, 5 to 3 or
8(GND), GND to pin 1, 2, 4, 5
14
V
8
V
-5
V
VCLAMP
VCLAMP-IECSYS
(2)
TLP Clamping voltage (Intrinsic)
8-kV Contact discharge on pin 1, 2, 4,
5 with pin3 grounded. Voltage
waveform measured at pin 6, 7, 9, 10
with respect to GND
IEC 61000-4-2 30 ns Clamping
voltage (system side) assuming
system draws at least 3 A of current at -8-kV Contact discharge on pin 1, 2, 4,
8 V. See measurement setup.
5 with pin3 grounded. Voltage
waveform measured at pin 6, 7, 9, 10
with respect to GND
-3.6
3.6
V
5
7.9
V
-7.9
-5
V
Pin 1, 2, 4, 5 to GND, 100 ns TLP
0.5
GND to Pin 1, 2, 4, 5 , 100 ns TLP
0.5
Line capacitance, any IO to GND
VIO = 0 V, Vp-p = 30 mV, f = 1 MHz
0.5
0.6
pF
ΔCLINE
Variation of line capacitance
CLINE1 - CLINE2, VIO = 0 V, Vp-p = 30
mV, f = 1 MHz
0.02
0.07
pF
CCROSS
Line-to-line capacitnace between one
differential pair to another differnetial
pair
VIO = 0 V, Vrms = 30 mV, f = 1 MHz
0.28
pF
S21DC
DC Insertion Loss
DC insertion loss at Ch1, Ch2, Ch3,
Ch4
0.3
dB
Ileakage
Leakage Current
VIO=±3.6 V, Pin 1,2,4,5 to Pin 3
0.1
RDYN
Dynamic resistance
CLINE
(1)
(2)
Ω
10
nA
VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the
snapback state
VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.
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32
32
28
28
24
24
20
20
Current (A)
Current (A)
6.7 Typical Characteristics
16
12
12
8
8
4
4
0
0
-4
-4
0
2
4
6
8
10 12 14
Voltage (V)
16
18
20
0
22
2
4
6
8
D001
Figure 1. Positive TLP Curve, Connector side IO Pin to GND
(tp=100ns)
10 12 14
Voltage (V)
16
18
20
22
D002
Figure 2. Negative TLP Curve, Connector side IO Pin to GND
(Plotted as positive TLP from GND to IO, tp=100ns )
30
150
Voltage on Connector Side (V)
Voltage on System Side (V)
120
0
-30
Voltage (V)
90
Voltage (V)
16
60
-60
30
-90
0
-120
Voltage on Connector Side (V)
Voltage on System Side (V)
0
10
20
30 40 50
Time (ns)
60
70
80
-150
-10
90 100
Figure 3. Clamping voltage waveform for +8kV IEC 61000-42 stress. See Figure 11 for details.
1.8
17.5
Current (A)
Power (W) 15
1.5
12.5
1.2
10
0.9
7.5
0.6
5
0.3
2.5
0
0
0
20
40
60
80 100
Time (Ps)
120
140
160
-2.5
180
20
30
40 50
Time (ns)
60
70
80
90
100
D004
Figure 4. Clamping voltage waveform for -8kV IEC 61000-4-2
stress. See Figure 11 for details.
0.5
0.4
0.3
0.2
0.1
0
0
ESD2
D005
Figure 5. IEC 61000-4-5 Surge Waveform (tp=8/20 µs)
6
10
0.6
Power (W)
Current (A)
2.1
-0.3
-20
0
D003
Capacitance (pF)
-30
-20 -10
0.5
1
1.5
2
2.5
Bias Voltage (V)
3
3.5
4
D009
Figure 6. Capacitance vs. Bias Voltage at 25 degree Celsius
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Typical Characteristics (continued)
2.2
0.00125
2
0.001
Current (A)
1.8
0.00075
1.6
0.0005
1.4
1.2
0.00025
1
0
0.8
0.6
-0.00025
0.4
-0.0005
0.2
-0.00075
0
-0.001
-8
-6
-4
-2
0
2
Voltage (V)
4
6
8
-0.2
-40
0
20
40
60
Temperature qC
80
100
120
D008
Figure 7. DC Voltage Sweep I-V Curve, IO Pin to GND
Figure 8. Leakage Current vs Temperature, IO Pin to GND,
at 2.5 V Bias
0
0.7
-1
0.6
-2
-3
Capacitance (pF)
Differential Insertion Loss (dB)
-20
D007
-4
-5
-6
-7
0.5
0.4
0.3
0.2
-8
0.1
-9
-10
0.01
0
0.1
1
Frequency (GHz)
10
1
1.5
D011
Figure 9. Differential Insertion Loss
2
2.5
3
3.5 4 4.5 5
Frequency (GHz)
5.5
6
6.5
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D010
Figure 10. Capacitance vs Frequency
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7 Parameter Measurement Setup
7.1 IEC 61000-4-2 System Level ESD Test Setup with HDMI Driver for Clamping Voltage
Measurement
Figure 11 shows the setup used to perform System Level ESD test to evaluate the clamping performance of
ESD224 in real-world applications where the device is protecting a downstream HDMI driver System-on-Chip.
IEC 61000-4-2 8kV Contact stress was applied at the connector pin and the voltage waveform on the systemside pin was captured to look at the clamping voltage presented by ESD224 to the down stream HDMI driver.
SMA
Connector
ESD Strike Point
0Ÿ
IO1_C
IO1_S
IO2_C
IO2_S
GND
ESD224
GND
IO3_C
IO3_S
IO4_C
IO4_S
HDMI Driver
Figure 11. System Level IEC 61000-4-2 ESD Test Setup with ESD224 protecting an HDMI driver chip
8
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8 Detailed Description
8.1 Overview
The ESD224 is a bidirectional ESD Protection Diode with ultra-low capacitance. This device can dissipate ESD
strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultra-low
capacitance makes this device ideal for protecting any super high-speed signal pins.
8.2 Functional Block Diagram
IO1_C
IO1_S
IO2_C
IO2_S
IO3_C
IO3_S
IO4_C
IO4_S
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8.3 Feature Description
8.3.1 IEC 61000-4-2 ESD Protection
The I/O pins can withstand ESD events up to ±12-kV contact and ±15-kV air gap. The ESD-surge clamp diverts
the current to ground.
8.3.2 IEC 61000-4-4 EFT Protection
The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω
impedance). The ESD-surge clamp diverts the current to ground.
8.3.3 IEC 61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 2 A and 17 W (8/20 µs waveform). The ESD-surge clamp diverts
this current to ground.
8.3.4 IO Capacitance
The capacitance between each I/O pin to ground is 0.5 pF (typical). This device supports data rates up to 6
Gbps.
8.3.5 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is a minimum of ±5.5 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of ±3.6 V.
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Feature Description (continued)
8.3.6 Ultra Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (maximum) with a bias of ±2.5 V.
8.3.7 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 8 V (IPP = 16 A TLP) on the system
side pins when the system draws at least 3 A.
8.3.8 Supports High Speed Interfaces
This device is capable of supporting high speed interfaces up to 6 Gbps, because of the extremely low IO
capacitance.
8.3.9 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
8.4 Device Functional Modes
The ESD224 is a passive integrated circuit that triggers when voltages are above VBRF or below VBRR. During
ESD events, voltages as high as ±15 kV (air) can be directed to ground via the internal diode network. When the
voltages on the protected line fall below the trigger levels of ESD224 (usually within 100s of nano-seconds) the
device reverts to passive.
10
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ESD224 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on highspeed signal lines between a human interface connector and a system. As the current from ESD passes through
the TVS, only a small voltage drop is present across the diode. Part of this voltage drop across the diode drops
across the series element between the connector side pin and the system-side pin. Therefore, the effective
voltage drop across the protected IC is smaller than the voltage drop across the diode. It is recommended to
avoid through-routing for this ESD diode (single trace connecting both the connector side pin and the system
side pin) for the best ESD performance.
9.2 Typical Application
ESD224
TMDS D2+
TMDS D2-
TMDS D1+
TMDS D1-
ESD224
TMDS CLK+
TMDS CLKTPD4E05U06
CEC
UTILITY
HDMI 2.0 Connector
To System
TMDS D0+
TMDS D0-
DDC_CLK
DDC_DAT
GND
P 5V0
HOTPLUG
TPD1E05U06
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Figure 12. ESD224 Protecting the HDMI Interface
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Typical Application (continued)
9.2.1 Design Requirements
In this design example, two ESD224 devices, one TPD4E05U06 and one TPD1E05U06 device are used to
protect an HDMI 2.0 interface. For HDMI 2.0 application design parameters listed in Table 1 are known.
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
Signal range on high speed differential data lines
0 to 3.6 V
Operating frequency of high speed data lines
3 GHz (First Harmonic)
Signal range on control lines (CEC, UTILITY, DDC_CLK and
DDC_DAT)
0 to 5 V
9.2.2 Detailed Design Procedure
9.2.2.1 Signal Range
ESD224 supports signal ranges between –3.6 V and 3.6 V, which supports the high-speed lines on the HDMI 2.0
application. The TPD4E05U06 and TPD1E05U06 support signal ranges between 0 V and 5.5 V, which supports
the HDMI control lines.
9.2.2.2 Operating Frequency
The ESD224 has a 0.5 pF (typical) capacitance, which supports the HDMI 2.0 rate of 6 Gbps. The TPD4E05U06
and TPD1E05U06 have a typical capacitance of 0.5 pF and 0.42 pF respectively, which easily support the control
lines. The ESD224 has 4 identical protection channels for the differential HDMI high-speed signal lines. The
symmetrical pin out of the device with a ground pin between the two differential signal pins makes it suitable for
this application.
9.2.3 Application Curves
Figure 13. HDMI 2.0 6 Gbps Eye Diagram (Bare Board)
12
Figure 14. HDMI 2.0 6 Gbps Eye Diagram with ESD224
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10 Power Supply Recommendations
This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended
I/O specification (–3.6 V to 3.6 V) to ensure the device functions properly.
11 Layout
11.1 Layout Guidelines
•
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
For the best ESD performance, do not use through-routing for the data channels. Connecting pins 1 and 10, 2
and 9, 4 and 7, 5 and 6 together with through routing will reduce the clamping voltage performance of
ESD224.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
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11.2 Layout Examples
Figure 15. HDMI Type-A Transmitter Port Layout
NOTE
There is no Through-Routing for the ESD224 Pins Connecting to the High Speed Data
Lines.
14
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: ESD224
15
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
ESD224DQAR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
USON
DQA
10
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
1AR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ESD224DQAR
Package Package Pins
Type Drawing
USON
DQA
10
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
180.0
8.4
Pack Materials-Page 1
1.23
B0
(mm)
K0
(mm)
P1
(mm)
2.7
0.6
4.0
W
Pin1
(mm) Quadrant
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ESD224DQAR
USON
DQA
10
3000
203.2
196.8
33.3
Pack Materials-Page 2
PACKAGE OUTLINE
DQA0010A
USON - 0.55 mm max height
SCALE 6.000
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
B
A
PIN 1 INDEX AREA
2.6
2.4
C
0.55 MAX
SEATING PLANE
(0.13) TYP
0.08 C
5
0.05
0.00
6
4X 0.5
(R0.125)
2X
2
2X
1
PIN 1 ID
(OPTIONAL)
0.45
0.35
0.1
0.05
C A
B
10
8X
10X
0.43
0.30
0.25
0.15
0.1
0.05
C A
C
B
4220328/A 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DQA0010A
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.565)
1
10
8X (0.2)
SYMM
2X (0.4)
4X (0.5)
6
5
(R0.05) TYP
SYMM
(0.835)
LAND PATTERN EXAMPLE
SCALE:30X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220328/A 12/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DQA0010A
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.565)
1
10
8X (0.2)
METAL
TYP
SYMM
3
8
2X (0.36)
4X (0.5)
6
5
(R0.05) TYP
SYMM
(0.835)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PADS 3 & 8:
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
4220328/A 12/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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