Texas Instruments | TPS25740B USB Type-C™ and USB PD Source Controller (Rev. C) | Datasheet | Texas Instruments TPS25740B USB Type-C™ and USB PD Source Controller (Rev. C) Datasheet

Texas Instruments TPS25740B USB Type-C™ and USB PD Source Controller (Rev. C) Datasheet
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TPS25740B
SLVSDR6C – JUNE 2017 – REVISED MARCH 2018
TPS25740B USB Type-C™ and USB PD Source Controller
1 Features
3 Description
•
The TPS25740B, a fully compliant and USB Power
Delivery (PD) 2.0 certified solution, implements a
power source for USB Type-C™ PD. It is easy to use
and minimizes time to market because there is no
firmware or external microcontroller required, just
connect it to the board. The device offers four
voltages with a maximum voltage and power up to
20 V at 100 W. The TPS25740B automatically
handles all USB PD negotiations, handshakes using
the CC pins, and selects the voltage from the power
supply using the CTLx pins. The PCTRL pin allows
for dynamically reducing the amount of power
advertised to enable port power management. The
TPS25740B integrates functions such as OVP, OCP,
ESD, UVLO, OTSD, and VBUS discharge to help
save solution size and cost while enabling a safe and
robust design. The TPS25740B controls an N-ch
MOSFET for the VBUS switch, saving system cost
versus solutions that require a P-ch MOSFET. The
ultra-low standby power of the TPS25740B makes it
easier to pass energy efficiency standards and
extends battery life in mobile applications.
1
•
•
•
•
•
•
USB PD 2.0 Certified (TID# 1030004) and USB
PD 3.0 Compliant Provider
Pin-Selectable Voltage Advertisement
– 5 V, 9 V, 12 V, and 15 V
– 5 V, 9 V, 15 V, and 20 V
Pin-Selectable Peak Power Settings
– 8 Options 18 W – 100 W
High Voltage and Safety Integration
– Overvoltage, Overcurrent, Overtemperature
Protection and VBUS Discharge
– IEC 61000-4-2 Protection on CC1 and CC2
– Input Pin for Fast Shutdown Under Fault
– Control of External N-ch MOSFET
– 3-Pin External Power Supply Control
– Wide VIN Supply (4.65 V – 25 V)
Below 10 µA Quiescent Current When Unattached
Port Attachment Indicator
Self-Directed Port Power Management for DualPort Applications
The TPS25740B typically draws 8.5 µA (or 5.8 µA if
VDD = 3.3 V) when no device is attached. Additional
system power saving is achievable by using the Port
Attachment Indicator (DVDD) output to disable the
power source when no device is attached.
2 Applications
•
•
•
•
•
USB-PD Adaptor (data-less)
Dedicated Charging Port (data-less)
Power Hub (data-less)
Power Bank
Cigarette Lighter Adaptor (CLA)
Protection features include overvoltage protection,
overcurrent protection, over-temperature protection,
IEC for CC pins, and system override to disable the
gate driver (GD).
Device Information(1)
PART NUMBER
PACKAGE
TPS25740B
BODY SIZE (NOM)
VQFN (24)
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
CSD17579Q3A
From AC Mains
VBUS
+
T1
Type-C
Plug
UCC24636
²
P
P
T1
LDO
VDD
HV
GND
TL431
PCTRL
CTL3
CC2
CC1
VBUS
DSCG
ISNS
GDNS
VDD
TPS25740B
ENSRC
GND
AGND
CTL1
CTL2
FB
HIPWR
PSEL
CS
P
DVDD
DRV
GDNG
VS
VAUX
GD
VTX
VPWR
UCC28740
P
Power Supply
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS25740B
SLVSDR6C – JUNE 2017 – REVISED MARCH 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Timing Requirements .............................................. 10
Switching Characteristics ........................................ 11
Typical Characteristics ............................................ 16
Detailed Description ............................................ 18
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
20
20
35
9
Application and Implementation ........................ 36
9.1 Application Information............................................ 36
9.2 Typical Applications ................................................ 45
9.3 System Examples ................................................... 52
10 Power Supply Recommendations ..................... 55
10.1 VDD....................................................................... 55
10.2 VPWR ................................................................... 55
11 Layout................................................................... 56
11.1 Port Current Kelvin Sensing.................................. 56
11.2 Layout Guidelines ................................................. 56
11.3 Layout Example .................................................... 57
12 Device and Documentation Support ................. 58
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
58
58
58
58
58
58
13 Mechanical, Packaging, and Orderable
Information ........................................................... 58
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2017) to Revision C
•
Changed tCC to 1 ms............................................................................................................................................................. 10
Changes from Revision A (September 2017) to Revision B
•
2
Page
Changed Description section.................................................................................................................................................. 1
Changes from Original (June 2017) to Revision A
•
Page
Page
Changed from Advance Information to Production Data ....................................................................................................... 1
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SLVSDR6C – JUNE 2017 – REVISED MARCH 2018
5 Device Comparison Table
DEVICE
COMPLIANT
USB PD POWER
(PDP) OPTIONS
PIN 8
PIN 11
TPS25740
15 W
EN12V
UFP
TPS25740A
15 to 45 W
EN9V
UFP
ENSRC
TPS25740B
(1)
15 to 93 W
(1)
VOLTAGES OFFERED
CTL3
OPTION 1
OPTION 2
OPTION 3
OPTION 4
5V
5 V, 12 V
5 V, 20 V
5 V, 12 V, 20 V
5V
5 V, 9 V
5 V, 15 V
5 V, 9 V, 15 V
5 V, 9 V, 12 V, 15
V
5 V, 9 V, 15 V, 20
V
N/A
N/A
Up to 93 W PDP with a captive cable, and up to 60 W PDP with receptacle.
6 Pin Configuration and Functions
DSCG
GDNS
GDNG
VBUS
VPWR
ISNS
24
23
22
21
20
19
RGE Package
24-Pin VQFN
Top View
VTX
1
18
AGND
CC1
2
17
VDD
CC2
3
16
VAUX
GND
4
15
GD
HIPWR
5
14
PCTRL
CTL1
6
13
DVDD
Thermal
7
8
9
10
11
12
CTL2
CTL3
N/C
N/C
ENSRC
PSEL
Pad
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
VTX
1
O
Bypass pin for transmit driver supply. Connect this pin to GND via the recommended ceramic
capacitor.
CC1
2
I/O
Multifunction configuration channel interface pin to USB Type-C. Functions include connector
polarity, end-device connection detect, current capabilities, and PD communication.
CC2
3
I/O
Multifunction configuration channel interface pin to USB Type-C. Functions include connector
polarity, end-device connection detect, current capabilities, and PD communication.
GND
4
—
Power ground is associated with power management and gate driver circuits. Connect to
AGND and PAD.
HIPWR
5
I
Four-state input pin used to configure the voltages and currents that will be advertised. It
may be connected directly to GND or DVDD, or it may be connected to GND or DVDD via a
resistance R(SEL).
CTL1
6
O
Digital output pin used to control an external voltage regulator.
CTL2
7
O
Digital output pin used to control an external voltage regulator.
CTL3
8
O
Digital output pin used to control an external voltage regulator.
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
N/C
9
—
Connect to GND.
N/C
10
—
Connect to GND.
ENSRC
11
O
Open drain output pin used to indicate when the VBUS needs to be sourced.
PSEL
12
I
A four-state input used for selecting the maximum power that can be provided. It may be
connected directly to GND or DVDD, or it may be connected to GND or DVDD via a
resistance R(SEL)
DVDD
13
O
Internally regulated 1.85 V rail for external use up to 35 mA. Connect this pin to GND via the
recommended bypass capacitor.
PCTRL
14
I
Input pin used to control the power that will be advertised. It may be pulled high or low
dynamically.
GD
15
I
Master enable for the GDNG/GDNS gate driver. The system can drive this low to force the
power path switch off.
VAUX
16
O
Internally regulated rail for use by the power management circuits. Connect this pin to GND
via the recommended bypass capacitor.
VDD
17
I
Optional input supply.
AGND
18
—
ISNS
19
I
The ISNS input is used to monitor a VBUS-referenced sense resistor for over-current events.
VPWR
20
I
Connect to an external voltage as a source of bias power. If VDD is supplied, this supply is
optional while DVDD is low.
VBUS
21
I
The voltage monitor for the VBUS line.
GDNG
22
O
High-voltage open drain gate driver which may be used to drive NMOS power switches.
Connect to the gate terminal.
GDNS
23
I
High-voltage open drain gate driver which may be used to drive NMOS power switches.
Connect to the source terminal.
DSCG
24
O
Discharge is an open-drain output that discharges the system VBUS line through an external
resistor.
Thermal Pad
—
—
Connect thermal pad to GND / AGND plane.
4
Analog ground associated with monitoring and power conditioning circuits. Connect to GND
and PAD.
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SLVSDR6C – JUNE 2017 – REVISED MARCH 2018
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.3
6
V
–0.3
2.1
V
–0.3
4.5
V
–0.3
7
V
–0.3
2.1
V
GDNG (2)
–0.5
40
V
VBUS,VPWR, ISNS, DSCG, GDNS
–0.5
30
V
VBUS,VPWR, ISNS, DSCG, GDNS
–1.5
30
V
V(GDNG) – V(GDNS)
–0.3
20
V
AGND to GND
–0.3
0.3
V
ISNS to VBUS
–0.3
0.3
V
8
mA
GD
100
µA
DSCG
10
mA
DSCG
375
mA
VDD , CTL1, CTL2, CTL3, ENSRC, PCTRL,
CC1, CC2
VTX
(2)
VAUX (2)
Pin voltage (sustained)
GD
(3)
HIPWR, PSEL, DVDD
Pin voltage (transient for 1ms)
Pin-to-pin voltage
(2)
CTL1, CTL2, CTL3, ENSRC
Sinking current (average)
Sinking current (transient, 50 ms pulse 0.25%
duty cycle)
VTX
Internally limited
mA
CC1, CC2
Internally limited
mA
VAUX
0
25
µA
Operating junction temperature range, TJ
–40
125
°C
Storage temperature, Tstg
–65
150
°C
Current sourcing
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Do not apply voltage to these pins.
Voltage allowed to rise above Absolute Maximum provided current is limited.
7.2 ESD Ratings (1)
VALUE
V(ESD)
(1)
(2)
(3)
(4)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (2)
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (3)
±1000
IEC
(4)
61000-4-2 contact discharge, CC1, CC2
±8000
IEC
(4)
61000-4-2 air-gap discharge, CC1, CC2
±15000
UNIT
V
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
These results were passing limits that were obtained on an application-level test board. Individual results may vary based on
implementation. Surges per IEC61000-4-2, 1999 applied between CC1/CC2 and ground of TPS25740BEVM-741 and TPS25740BEVM741
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
VDD
Supply voltage
VI
VI
Pin-to-pin voltage
VIH
High level input voltage
VIL
5.5
V
25
V
PCTRL, CC1, CC2, CTL1, CTL2, CTL3
0
5.5
V
GD
0
6.5
V
DSCG, GDNS, VBUS
0
25
V
HIPWR, PSEL
0
DVDD
V
–0.1
0.1
V
2
1.6
V
GD
PCTRL
V
GD
1.6
V
CTL1, CTL2, CTL3, ENSRC
1.5
µA
GD
80
µA
350
mA
PCTRL
Sinking current
V
DSCG, transient sinking current 50 ms
pulse, 0.25% duty cycle
DSCG, average
5
mA
200
560
600
pF
10
µF
DVDD (C(DVDD))
0.198
0.22
0.242
µF
VAUX (C(VAUX))
0.09
0.1
0.11
µF
VTX (C(VTX))
0.09
0.10
0.11
µF
VDD (C(VDD))
0.09
Configured for 3 A
5
6.4
mΩ
Configured for 5 A
5
5.8
mΩ
1
kΩ
120
kΩ
CC1, CC2 (C(RX))
VBUS (C(PDIN))
CS
Shunt capacitance
RS
Sense resistance
R(PUD)
Pull up/down resistance
R(DSCG)
TJ
HIPWR, PSEL (direct to GND or direct
to DVDD)
Series resistance
UNIT
0
ISNS - VBUS
Low level input voltage
IS
MAX
4.65
VPWR
Applied voltage
NOM
µF
0
HIPWR, PSEL (R(SEL) )
80
Maximum VBUS voltage of 25 V
80
Ω
Maximum VBUS voltage of 15 V
43
Ω
Maximum VBUS voltage of 6 V
20
Operating junction temperature
100
Ω
-40
125
°C
7.4 Thermal Information
TPS25740B
THERMAL METRIC
(1)
RGE (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
33
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
32.6
°C/W
10
ψJT
°C/W
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
10
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.6
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLVSDR6C – JUNE 2017 – REVISED MARCH 2018
7.5 Electrical Characteristics
Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65
V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND; VAUX, VTX, bypassed with
0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage Comparator (VBUS)
V(VBUS_RTH)
VBUS threshold (Rising voltage)
4.25
4.45
4.65
V
V(VBUS_FTH)
VBUS threshold (Falling voltage)
3.5
3.7
3.9
V
VBUS threshold (Hysteresis)
0.75
V
Power Supply (VDD, VPWR)
V(VDD_TH)
VDD UVLO threshold
Rising voltage
2.8
2.91
2.97
Falling voltage
2.8
2.86
2.91
Hysteresis, comes into effect once the
rising threshold is crossed.
V
0.05
V(VPWR_RTH)
VPWR UVLO threshold rising
Rising voltage
4.2
4.45
4.65
V
V(VPWR_FTH)
VPWR UVLO threshold falling
Falling voltage
3.5
3.7
3.9
V
VPWR UVLO threshold hysteresis
Hysteresis, comes into effect once the
rising threshold is crossed.
Supply current drawn from VDD in sleep
mode
Supply current drawn from VPWR in
sleep mode
I(SUPP)
Operating current while sink attached
0.75
V
VPWR = 0 V, VDD = 5 V, CC1 and CC2
pins are open.
9.2
20
µA
VPWR = 0 V, VDD = 5 V,CC1 pin open,
CC2 pin tied to GND.
94
150
µA
VPWR = 5 V, VDD = 0 V, CC1 and CC2
pins are open.
8.5
15
µA
VPWR = 5 V, VDD = 0 V, CC1 pin open,
CC2 pin tied to GND.
90
140
µA
1.8
3
mA
PD Sourcing active, VBUS = 5 V,
VPWR = 5 V, VDD = 3.3 V
1
Over/Under Voltage Protection (VBUS)
V(FOVP)
V(SOVP)
V(SUVP)
Fast OVP threshold, always enabled
Slow OVP threshold, disabled during
voltage transitions. (See Figure 1)
UVP threshold, disabled during voltage
transitions (See Figure 1)
5 V PD contract
5.8
6.05
6.3
V
9 V PD contract
10.1
10.55
11.0
V
12 V PD contract
13.2
13.75
14.3
V
15 V PD contract
16.2
16.95
17.7
V
20 V PD contract
22.1
23.05
24.0
V
5 V PD contract
5.5
5.65
5.8
V
9 V PD contract
10
10.2
10.4
V
12 V PD contract
13.1
13.4
13.7
V
15 V PD contract
16.3
16.5
17
V
20 V PD contract
21.5
22.0
22.5
V
5 V PD contract
3.5
3.65
3.8
V
9 V PD contract
6.8
6.95
7.1
V
12 V PD contract
9.2
9.45
9.7
V
15 V PD contract
11.7
11.95
12.2
V
20 V PD contract
15.7
16.1
16.5
V
2.875
3.2
4.1
VAUX
V(VAUX)
Output voltage
0 ≤ I(VAUX) ≤ I(VAUXEXT)
VAUX current limit
I(VAUXEXT)
1
External load that may be applied to
VAUX.
V
5
mA
25
µA
1.95
V
V
DVDD
V(DVDD)
Output voltage
0 mA ≤ I(DVDD) ≤ 35 mA, CC1 or CC2
pulled to ground via 5.1 kΩ, or both CC1
and CC2 pulled to ground via 1 kΩ
1.75
Load regulation
Overshoot from V(DVDD), 10-mA minimum,
0.198-µF bypass capacitor
1.7
2
Current limit
DVDD tied to GND
40
150
1.85
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Electrical Characteristics (continued)
Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65
V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND; VAUX, VTX, bypassed with
0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.050
1.125
1.200
V
VTX
Output voltage
Not transmitting or receiving, 0 to 2 mA
external load
Current limit
VTX tied to GND
2.5
10
mA
Gate Driver Disable (GD)
Rising voltage
V(GD_TH)
Input enable threshold voltage
V(GDC)
Internal clamp voltage
I(GD) = 80 µA
R(GD)
Internal pulldown resistance
From 0 V to 6 V
Discharge (DSCG)
1.64
Hysteresis
1.725
1.81
0.15
V
V
6.5
7
8.5
V
3
6
9.5
MΩ
(1) (2)
V(DSCGT)
ON state (linear)
I(DSCG) = 100 mA
0.15
0.42
1
I(DSCGT)
ON state (saturation)
V(DSCG) = 4 V, pulsed mode operation
220
553
1300
mA
V
R(DSCGB)
Discharge bleeder
While CC1 is pulled down by 5.1 kΩ and
CC2 is open, V(DSCG) = 25 V
6.6
8.2
10
kΩ
Leakage current
0 V ≤ V(DSCG) ≤ 25 V
2
µA
30
µA
12
V
300
Ω
N-ch MOSFET Gate Driver (GDNG,GDNS)
I(GDNON)
Sourcing current
0 V ≤ V(GDNS) ≤ 25 V,
0 V ≤ V(GDNG) – V(GDNS) ≤ 6 V
V(GDNON)
Sourcing voltage while enabled
(V(GDNG)– V(GDNS))
0 V ≤ V(GDNS) ≤ 25 V, I(GDNON) ≤ 4 µA,
VDD = 0 V
R(GDNGOFF)
Sinking strength while disabled
V(GDNG) – V(GDNS)= 0.5 V,
0 ≤ V(GDNS) ≤ 25 V
150
VDD = 1.4 V, V(GDNG) = 1 V,
V(GDNS) = 0 V, VPWR = 0 V
145
µA
VPWR = 1.4 V, V(GDNG) = 1 V,
V(GDNS) = 0 V, VDD = 0 V
145
µA
Sinking strength UVLO (safety)
Off-state leakage
13.2
20
8.5
V(GDNS) = 25 V, V(GDNG) open
7
µA
Power Control Input (PCTRL)
V(PCTRL_TH)
Threshold voltage (3)
Input resistance
Voltage rising
1.65
Hysteresis
1.75
1.85
100
0 V ≤ V(PCTRL) ≤ V(VAUX)
1.5
0 V ≤ V(HIPWR) ≤ V(DVDD),
0 V ≤ V(PSEL) ≤ V(DVDD)
–1
2.9
V
mV
6
MΩ
1
µA
0.4
V
0.5
µA
Ω
Voltage Select (HIPWR), Power Select (PSEL) (4)
Leakage current
Port Status and Voltage Control (CTL1, CTL2, CTL3, ENSRC)
VOL
Output low voltage
Leakage current
(6)
(5)
IOL = 4 mA sinking
In Hi-Z state, 0 ≤ V(CTLx) ≤ 5.5 V or
0 ≤ VENSRC ≤ 5.5V
–0.5
Transmitter Specifications (CC1, CC2)
RTX
Output resistance (zDriver from USB PD
in Documentation Support)
During transmission
V(TXHI)
Transmit high voltage
V(TXLO)
Transmit low voltage
33
45
75
External Loading per Figure 27
1.05
1.125
1.2
V
External Loading per Figure 27
–75
75
mV
Receiver Specifications (CC1, CC2)
V(RXHI)
Receive threshold (rising)
800
840
885
mV
V(RXLO)
Receive threshold (falling)
485
525
570
mV
Receive threshold (Hysteresis)
(1)
(2)
(3)
(4)
(5)
(6)
8
315
mV
If TJ1 is perceived to have been exceeded an OTSD occurs and the discharge FET is disabled.
The discharge pull-down is not active in the sleep mode.
When voltage on the PCTRL pin is less than V(PCTRL_TH), the amount of power advertised is reduced by half.
Leaving HIPWR or PSEL open is an undetermined state and leads to unpredictable behavior.
These pins are high-z during a UVLO, reset, or in Sleep condition.
The pins were designed for less leakage, but testing only verifies that the leakage does not exceed 0.5 µA.
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Electrical Characteristics (continued)
Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65
V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND; VAUX, VTX, bypassed with
0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
PARAMETER
V(INT)
TEST CONDITIONS
Amplitude of interference that can be
tolerated
MIN
TYP
Interference is 600 kHz square wave,
rising 0 to 100 mV.
Interference is 1 MHz sine wave
MAX
UNIT
100
mV
1
VPP
DFP Specifications (CC1, CC2)
In standard Rp mode (7), voltage rising
V(DSTD)
V(D1.5)
Detach threshold when cable is detached.
V(OCDS)
I(RPSTD)
I(RP1.5)
In 1.5 A Rp mode (8), voltage rising
1.52
Hysteresis
Loaded output current while connected
through CCx
I(RP3.0)
V(RDSTD)
2.50
Ra, Rd detection threshold (falling)
normal mode
2.625
V
V
1.65
V
V
2.75
V
V
2.75
4.35
V
VPWR = 0 V (in UVLO) or in sleep mode
1.8
5.5
V
In standard Rp mode1, CCy open,
0 V ≤ VCCx ≤ 1.5 V (vRd)
64
80
96
µA
In 1.5 A Rp mode 2, CCy open,
0 V ≤ VCCx ≤ 1.5 V (vRd)
166
180
194
µA
In 3 A Rp mode 3, CCy open,
0 V ≤ VCCx ≤ 1.5 V (vRd)
304
330
356
µA
In standard Rp mode1,
0 V ≤ VCCx ≤ 1.5 V (vRd)
0.15
0.19
0.23
V
0.02
In 1.5 A Rp mode2, CCy open
0 V ≤ VCCx ≤ 1.5 V (vRd)
0.35
Hysteresis
0.75
Hysteresis
V(WAKE)
Wake threshold (rising and falling), exit
from sleep mode
VPWR = 4.65 V , 0 V ≤ VDD ≤ 3 V
I(DSDFP)
Output current on CCx in sleep mode to
detect Ra removal
CCx = 0V, CCy floating
0.39
V
0.43
0.02
In 3 A Rp mode3, CCy open
0 V ≤ VCCx ≤ 1.5 V (vRd)
V(RD3.0)
1.585
0.05
Hysteresis
V(RD1.5)
1.65
0.02
Hysteresis
Unloaded output voltage on CC pin
1.585
0.02
In 3 A Rp mode (9), voltage rising
V(D3.0)
V(OCN)
1.52
Hysteresis
0.79
V
0.83
0.02
(10)
1.6
V
V
V
3.0
V
105
µA
19.2
22.6
mV
29
34
mV
40
73
OverCurrent Protection (ISNS, VBUS)
Specified as V(ISNS)-V(VBUS).
3.5 V (11) ≤ VBUS ≤ 25 V
VI(TRIP)
Current trip shunt voltage
HIPWR: 5 A not enabled
HIPWR = DVDD (5 A enabled)
OTSD
TJ1
Die temperature (Analog) (12)
TJ2
Die temperature (Analog)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(13)
TJ ↑
125
Hysteresis
TJ ↑
Hysteresis
135
145
10
140
150
163
10
°C
°C
Standard Rp mode is active after a USB Type-C sink, debug accessory, or audio accessory is attached until the first USB PD message
is transmitted (after GDNG has been enabled).
1.5 A Rp mode is active after a USB PD message is received.
3 A Rp mode is active after GDNG has been enabled until a USB PD message is received.
VWAKE < VOCDS is always true.
Common mode minimum aligns to VBUS UVLO. VBUS must be above its UVLO for the OCP function to be active.
When TJ1 trips a hard reset is transmitted and discharge is disabled, but the bleed discharge is not disabled.
TJ2 trips only when some external heat source drives the temperature up. When it trips the DVDD, and VAUX power outputs are turned
off.
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7.6 Timing Requirements
Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65
V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND; VAUX, VTX, bypassed with
0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
MIN
tFOVPDG
Deglitch for fast over-voltage protection
tOCP
Deglitch filter for over-current protection
MAX
5
Time power is applied until CC1 and CC2
pull-ups are applied.
tCC
NOM
V(VPWR) > V(VPWR_TH) OR
V(VDD) > V(VDD_TH)
2.5
Falling/Rising voltage deglitch time for
detection on CC1 and CC2
UNIT
µs
15
µs
4
ms
1
ms
Transmitter Specifications (CC1, CC2)
tUI
Bit unit Interval
3.05
Rise/fall time, tFall and tRise (refer to USB
PD in Documentation Support)
10
External Loading per Figure 27
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300
3.3
3.70
µs
600
ns
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7.7 Switching Characteristics
Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65
V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND; VAUX, VTX, bypassed with
0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tVP
Delay from enabling external NFET until
under-voltage and OCP protection are
enabled
tSTL
Source settling time, time from CTL1, CTL2,
or CTL3 being changed until a PS_RDY USB
PD message is transmitted to inform the sink
is may draw full current. (refer to USB PD in
Documentation Support)
tSR
Time that GDNG is disabled after a hard
reset. This is tSrcRecover. (refer to USB PD in
Documentation Support)
tHR
MIN
VBUS = GND
TYP
MAX
UNIT
190
ms
260
ms
765
ms
Time after hard reset is transmitted until
GDNG is disabled. This is tPSHardReset. (refer
to USB PD in Documentation Support)
30
ms
tCCDeb
Time until ENSRC is pulled low after sink
attachment, this is the USB Type-C required
debounce time for attachment detection
called tCCDebounce. (refer to USB Type-C in
Documentation Support)
185
ms
tST
Delay after sink request is accepted until
CTL1, CTL2, or CTL3 is changed. This is
called tSnkTransition. (refer to USB PD in
Documentation Support)
30
ms
tFLT
The time in between hard reset transmissions GD = GND or VPWR = GND, sink
in the presence of a persistent supply fault.
attached
1395
ms
tSH
The time in between retries (hard reset
transmissions) in the presence of a persistent VBUS = GND, sink attached
VBUS short.
985
ms
tON
The time from ENSRC being pulled low until
a hard reset is transmitted. Designed to be
greater than tSrcTurnOn. (refer to USB PD in
Documentation Support)
GD = 0 V or VPWR = 0 V
600
ms
Retry interval if USB PD sink stops
communicating without being removed or if
sink does not communicate after a fault
condition. Time GDNG remains enabled
before a hard reset is transmitted. This is the
tNoResponse time. (refer to USB PD in
Documentation Support)
Sink attached
4.8
s
tDVDD
Delay before DVDD is driven high
After sink attached
tGDoff
Turnoff delay, time until V(GDNG) is below 10%
VGD: 5 V → 0 V in < 0.5 µs
of its initial value after the GD pin is low
tFOVP
VBUS ↑ to GDNG OFF
Response time when VBUS exceeds the fast(V(GDNG) below 10% its initial
OVP threshold
value)
TJ > TJ1
5
ms
5
µs
30
µs
OCP large signal response time
5 A enabled, V(ISNS) -V(VBUS): 0 V
→ 42 mV measured to GDNG
transition start
30
µs
Time until discharge is stopped after TJ1 is
exceeded.
0 V ≤ V(DSCG) ≤ 25 V
10
µs
Digital output fall time
V(PULLUP) = 1.8 V, CL = 10 pF,
R(PULLUP) = 10 kΩ, V(CTLx) or
V(ENSRC) : 70% VPULLUP → 30%
VPULLUP
300
ps
20
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V(FOVP) = 13.76 V
V(SOVP) = 13.4 V
V(SUVP) = 9.45 V
9.45V
PCTRL samples prior to sending
Source Capabilities
tSTL
V(FOVP) = 6.08 V
V(FOVP) = 6.08 V
t STL
V(SOVP) = 5.65 V
V(SOVP) = 5.65 V
V(SUVP) = 3.65V
V(SUVP) = 3.65 V
VBUS
tST
0V
tVP
ENSRC
SlowOVP/UVP
enabled
OCP
enabled
Sink
Attached
Detected
Sink
Request
Accepted
Figure 1. Timing Illustration for tVP, tST and tSTL, After Sink Attachment Negotiation to 12 V Then Back to
5 V. V(SOVP) and V(SUVP) are Disabled Around Voltage Transitions.
Enabled
tSR
GDNG
tHR
Disabled
ENSRC
(Pulled high
to DVDD)
Enabled
Disabled
tHR
V(DVDD)
VOL
Figure 2. Timing Illustration for tHR and tSR, After Sink Attachment with Persistent TJ > TJ1
12
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Source
Capabilities
Transmitted
Sink
Attached
5V
VBUS
0V
ENSRC
high-z
(Pulled high
to DVDD)
CC
Voltage
tVP
V(DVDD)
VOL
V(OCDS)
tCcDeb
V(D3.0)
V(DSTD)
Figure 3. Timing Illustration for tCcDeb and tVP, Under Persistent Fault Condition
Enabled
Enabled
tSH
GDNG
tVP
tVP
Disabled
Disabled
V(DVDD)
ENSRC
(Pulled high
To DVDD)
VOL
Figure 4. Timing Illustration for tSH and tVP, with VBUS Shorted to Ground
Enabled
GDNG
Disabled
ENSRC
(Pulled high
to DVDD)
V(DVDD)
<tON
VOL
GD
VPWR
Figure 5. Timing Illustration for tON
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Enabled
GDNG
Disabled
V(DVDD)
ENSRC
(Pulled high
to DVDD)
<tON
VOL
VPWR
GD
Figure 6. Timing Illustration for tON
ENSRC
15 V
5V
5V
VBUS
< 0.8 V
NFET enabled (closed)
NFET disabled (open)
GDNG
tSR
Bleed only
Full
discharge
DSCG
High-z
CTL1, CTL2, and CTL3
Low
Time bounded by 650 ms
(tSafe0V)
Hard Reset
Received
Figure 7. Timing Diagram for ENSRC and GDNG After Receiving a Hard Reset
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ENSRC
15 V
5V
5V
VBUS
< 0.8 V
NFET enabled (closed)
NFET disabled (open)
GDNG
tSR
Bleed
only
Full
discharge
DSCG
High-z
CTL1, CTL2, and CTL3
Low
tHR
Hard Reset
Transmitted
Figure 8. Timing Diagram for ENSRC and GDNG After Transmitting a Hard Reset
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7.8 Typical Characteristics
0.63
650
0.6
625
0.57
600
0.51
I(DSCG) (mA)
V(DSCG) (V)
0.54
0.48
0.45
0.42
575
550
525
500
0.39
475
0.36
450
0.33
0.3
-40
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
425
-40
140
I(DSCG) = 100 mA
Figure 9. V(DSCG) while V(VPWR) > 4.65 V after an unplug
120
140
D005
Pulsed Testing
Figure 10. I(DSCG) while V(VPWR) > 4.65 V after an unplug
VPWR = 5 V, VDD = 0 V
VPWR = 0 V, VDD = 3.3 V
6.09
6.08
9
V(FOVP) for 5 V (V)
Supply Current (PA)
20
40
60
80
100
Junction Temperature (qC)
6.1
9.5
8.5
8
7.5
7
6.5
6.07
6.06
6.05
6.04
6.03
6
6.02
5.5
6.01
5
-40
0
V(DSCG) = 4 V
10.5
10
-20
D004
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
6
-40
140
-20
0
20
40
60
80
100
Junction Temperature (qC)
D006
Figure 11. Supply Current While CC pins Unattached
120
140
D007
Figure 12. V(FOVP) While Supplying 5 V
13.745
10.56
13.74
10.55
V(FOVP) for 12 V (V)
V(FOVP) for 9 V (V)
13.735
10.54
10.53
10.52
13.73
13.725
13.72
13.715
13.71
10.51
13.705
10.5
-40
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
140
13.7
-40
D008
Figure 13. V(FOVP) While Supplying 9 V
16
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-20
0
20
40
60
80
100
Junction Temperature (qC)
120
140
D009
Figure 14. V(FOVP) While Supplying 12 V
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Typical Characteristics (continued)
16.94
23.1
16.935
V(FOVP) for 20 V (V)
V(FOVP) for 15 V (V)
16.93
16.925
16.92
16.915
16.91
16.905
23.05
23
22.95
16.9
16.895
16.89
-40
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
22.9
-40
140
-20
0
D010
Figure 15. V(FOVP) While Supplying 15 V
20
40
60
80
100
Junction Temperature (qC)
120
140
D015
Figure 16. V(FOVP) While Supplying 20 V
21
31.75
20.98
31.7
20.96
20.94
VI(TRIP) (mV)
VI(TRIP) (mV)
31.65
31.6
31.55
20.92
20.9
20.88
20.86
20.84
31.5
20.82
31.45
-40
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
20.8
-40
140
5 A enabled
0
20
40
60
80
100
Junction Temperature (qC)
120
140
D011
3 A enabled
Figure 17. VI(TRIP) When V(VPWR) > 4.65 V
Figure 18. VI(TRIP) When V(VPWR) > 4.65 V
5.5
5.5
VBUS
DVDD
UFP
5
4.5
VBUS
DVDD
UFP
5
4.5
4
4
3.5
3.5
Voltage (V)
Voltage (V)
-20
D016
3
2.5
2
3
2.5
2
1.5
1.5
1
1
0.5
0.5
0
0
0
0.05
0.1
Time (s)
0.15
0.2
-0.5
-0.2
-0.15
D012
Sink attached at time 0
-0.1
-0.05
0
0.05
Time (s)
0.1
0.15
0.2
0.25
D013
Sink detached at time 0s
Sleep mode entered at time 0.19s.
Figure 19. DVDD and ENSRC Upon Sink Attachment
Figure 20. DVDD and ENSRC Upon Sink Attachment
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8 Detailed Description
8.1 Overview
The TPS25740B and supporting circuits perform the functions required to implement a USB Power Delivery (PD)
2.0 as a provider-only and a USB Type-C revision 1.2 source. It uses its CC pins to detect the attachment of a
sinking device or upward facing port (UFP) and to determine which of CC1 or CC2 is connected to the CC wire
of the cable. It then communicates over the CC wire in the cable bundle using USB PD to offer a set of voltages
and currents. USB PD is a technology that utilizes the ubiquitous USB communications and hardware
infrastructure to extend the amount of power available to devices from the 7.5 W range for USB BC1.2 to as high
as 100 W in a dock. It is a compatible overlay to USB 2.0 and USB 3.0, coexisting with the existing 5 V powered
universe of devices by use of adapter cables. Some basic characteristics of this technology relevant to the device
include:
• Increased power achieved by providing higher current and/or higher voltage.
• New 3 A cable and 5 A connector to support greater than the traditional 1.5 A.
– Cables have controlled voltage drop
• Voltages greater than 5 V are negotiated between PD partners.
– Standard 5 V is always the default source voltage.
– Voltage and current provisions are negotiated between PD partners.
• PD partners negotiate over the CC line to avoid conflict with existing signaling (that is, D+, D-)
• Layered communication protocol defined including PHY, Protocol Layer, Policy Engine, and Device Policy
Manager all implemented within the device.
• The Type-C connector standard implements pre-powerup signaling to determine:
– Connector orientation
– Source 5-V capability
– Detect through connection of a UFP (upward facing port) to a DFP (downward facing port).
– Detection of when the connected UFP is disconnected. VBUS is unpowered until a through-connection is
present
Figure 21 and Figure 22 show a typical configuration for the device.
RS
VBUS
10Ÿ
Type-C
receptacle
C(RX)
DSCG
VBUS
ISNS
GDNS
GDNS
VPWR
C(SLEW) R(SLEW)
R(DSCG)
10Ÿ
C(SOURCE)
CC1
CC2
VDD
DVDD
GD
PSEL
GND
AGND
C(DVDD)
C(VAUX)
HIPWR
R(SEL)
VTX
PCTRL
VAUX
TPS25740B
CTL1
CTL2
CTL3
ENSRC
C(VTX)
Power Supply
Voltage Selector (eg. Secondary
voltage in fly-back topology)
C(PDIN)
Output voltage from power supply
C(RX)
CSD17578Q3A (2x)
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Figure 21. Schematic 1
18
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Overview (continued)
CSD17579Q3A (1x)
RS
VBUS
Output voltage from power supply
C(RX)
VBUS
DSCG
ISNS
CC1
CC2
GND
AGND
PSEL
DVDD
GD
C(DVDD)
C(VAUX)
C(VTX)
VTX
PCTRL
VAUX
TPS25740B
HIPWR
CTL1
CTL2
CTL3
ENSRC
Type-C
Plug
C(PDIN)
R(DSCG)
C(SLEW) R(SLEW)
GDNS
VDD
R(SEL)
Voltage selector (eg. Secondary
voltage in fly-back topology)
GDNG
VPWR
Power Supply
C(SOURCE)
10Ÿ
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Figure 22. Schematic 2
8.1.1 VBUS Capacitance
The USB Type-C specification requires that the capacitance on the VBUS pin of an empty receptacle be below
10 µF. This is to protect legacy USB sources that are not designed to handle the larger inrush capacitance and
which may be connected via an A-to-C cable. For applications with USB Type-C receptacles and large bulk
capacitance, this means back-to-back blocking FETs are required as shown in Figure 21. However, for
applications with a USB Type-C plug (that is, a captive cable) this requirement does not apply since an adaptor
cable with a USB Type-C receptacle and a Type-A plug is not defined or allowed by the USB I/F. Figure 22 is a
schematic for such applications.
8.1.2 USB Data Communications
The USB Power Delivery specification requires that sources such as the device advertise in the source
capabilities messages they transmit whether or not they are in a product that supports USB data
communications. The device has this bit hard-coded to 0.
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8.2 Functional Block Diagram
Power
Path
Override
Monitor
OVP, OCP
Analog Drivers
VBUS
VDD
AGND
GND
VPWR
Power
Inputs
ISNS
GD
GDNS
GDNG
DSCG
HV
Analog
Drivers
VTX
DVDD
VAUX
Power Mgmt
Internal
Power
Rails
Configuration
Inputs
CC
Logic
Digital
Control Logic
PCTRL
CC1
USB PD
Modem
HIPWR
PSEL
CC2
Type- C
Interface
ENSRC
CTL1
CTL2
CTL3
COMP
Oscillator
Digital
Outputs
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8.3 Feature Description
This section describes the features associated with each pin for the device.
8.3.1 ENSRC
ENSRC is an open-drain output pin used to indicate whether voltage is being provided to the port. ENSRC goes
low when a sink is attached to the port and VBUS is low. A sink attachment is detected when the voltage on one
(not both) of the CC pins remains between V(RDSTD) and V(DSTD) for tCcDeb and the voltage on the VBUS pin is
below V(VBUS_FTH). After being pulled low, ENSRC remains low until TPS25740B determines that it should remove
voltage from the port at which time it goes to high-z. In some applications, the ENSRC pin may be used to
disable the power supply instead of using a blocking NFET (See Using ENSRC to Enable the Power Supply
upon Sink Attachment).
8.3.2 USB Type-C CC Logic (CC1, CC2)
The device uses a current source to implement the pull up resistance USB Type-C requires for Sources. While
waiting for a valid connection, the device applies a default pullup of I(RPSTD). A sink attachment is detected when
the voltage on one (not both) of the CC pins remains between V(RDSTD) and V(DSTD) for tCcDeb and the voltage on
the VBUS pin is below V(VBUS_FTH). Then after turning on VBUS and disabling the Rp current source for the CCx
pin not connected through the cable, the device applies I(RP3.0) to advertise 3 A to non-PD sinks. Finally, if it is
determined that the attached sink is PD-capable, the device applies I(RP1.5). During this sequence if the voltage
on the monitored CC pin exceeds the detach threshold then the device removes VBUS and begins watching for
a sink attachment again.
The TPS25740B digital logic selects the current source switch as illustrated in Figure 23. The schematic shown
is replicated for each CC pin.
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Feature Description (continued)
V(D3.0)
Digital Control Logic
V(D1.5)
I(RPSTD)
V(DSTD)
I(RP1.5)
I(RP3.0)
V(RD3.0)
CCx
V(RD1.5)
Digital Control Logic
V(RDSTD)
Figure 23. USB Type-C Rp Current Sources and Detection Comparators
If the voltage on both CC pins remains above V(RDSTD) for tCcDeb, then the device goes to the sleep mode. In the
sleep mode a less accurate current source is applied and a less accurate comparator watches for attachment
(see V(WAKE), and I(DSDFP)).
8.3.3 USB PD BMC Transmission (CC1, CC2, VTX)
An example of the BMC signal, specifically the end of the preamble and beginning of start-of-packet (SOP) is
shown below. There is always an edge at the end of each bit or unit interval, and ones have an edge half way
through the unit interval.
Preamble
0
1
0
1
0
SOP.Sync2
SOP.Sync1
1
0
1
0
0
0
1
1
0
0
0
1
1
Data in
BMC
Figure 24. BMC Encoded End of Preamble, Beginning of SOP
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Feature Description (continued)
While engaging in USB PD communications, the device is applying I(RP1.5) or I(RP3.0), so the CC line has a DC
voltage of 0.918 V or 1.68 V, respectively. When the BMC signal is transmitted on the CC line, the transmitter
overrides this DC voltage as shown in Figure 25. The transmitter bias rail (VTX) is internally generated and may
not be used for any other purpose in the system. The VTX pin is only high while the TPS25740B is transmitting a
USB PD message.
VTXHI
DC Bias
DC Bias
VTXLO
VTXHI
DC Bias
DC Bias
VTXLO
Figure 25. USB PD BMC Transmission on the CC Line
The device transmissions meet the eye diagram USB PD requirements (refer to USB PD in Documentation
Support) across the recommended temperature range. Figure 26 shows the transmitter schematic.
To Receiver
CC1
RTX
Driver
CC2
ZDRIVER
Digital Control
Logic
Copyright © 2016, Texas Instruments Incorporated
Figure 26. USB PD BMC Transmitter Schematic
The transmit eye diagram shown in Figure 28 was measured using the test load shown in Figure 27 with a CLOAD
within the allowed range. The total capacitance CLOAD is computed as:
CLOAD = C(RX) + CCablePlug x 2 + Ca + CReceiver
(1)
Where:
• 200 pF < C(RX) < 600 pF
• CCablePlug < 25 pF
• Ca < 625 pF
• 200 pF < CReceiver < 600 pF
Therefore, 400 pF < CLOAD < 1850 pF.
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Feature Description (continued)
CCx
5.1NŸ
CLOAD
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 27. Test Load for BMC Transmitter
Figure 28 shows the transmit eye diagram for the TPS25740B.
Figure 28. Transmit Eye Diagram (BMC)
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Feature Description (continued)
8.3.4 USB PD BMC Reception (CC1, CC2)
The device BMC receiver follows the USB PD requirements (refer to USB PD in Documentation Support) using
the schematic shown in Figure 29.
The device low-pass filter design and receiver threshold design allows it to reject interference that may couple
onto the CC line from a noisy VBUS power supply or any other source (refer to V(INT)).
To Transmitter
V(RXHI)
Digital Control Logic
CC1
Low-Pass Filter
CC2
Digital Control
Logic
V(RXLO)
Copyright © 2016, Texas Instruments Incorporated
Figure 29. USB PD BMC Receiver Schematic
8.3.5 Discharging (DSCG, VPWR)
The DSCG pin allows for two different pull-downs that are used to apply different discharging strengths. In
addition, the VPWR pin is used to apply a load to discharge the power supply bulk capacitance.
If too much power is dissipated by the device (that is, the TJ1 temperature is exceeded) an OTSD occurs that
disables the discharge FET; therefore, an external resistor is recommended in series with the DSCG pin to
absorb most of the dissipated power. The external resistor R(DSCG) should be chosen such that the current sunk
by the DSCG pin does not exceed I(DSCGT).
The VPWR pin should always be connected to the supply side (as opposed to the connector side) of the powerpath switch (Figure 30 shows one example). This pin is monitored before enabling the GDNG gate driver to apply
the voltage to the VBUS pin of the connector.
From sink attachment, and while the device has not finalized a USB PD contract, the device applies R(DSCGB).
Also from sink attachment, and while the device has not finalized a USB PD contract, the device draws I(SUPP)
through the VPWR pin even if VDD is above its UVLO. This helps to discharge the power supply source.
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Feature Description (continued)
Power Supply
VBUS
DSCG
R(DSCG)
GDNS
GDNG
VPWR
C(SLEW)
R(SLEW)
10Ÿ
DSCG
Control
See I(DSCGT) and V(DSCGT)
R(DSCGB)
Copyright © 2016, Texas Instruments Incorporated
Figure 30. Discharge Schematic
The discharge procedure used in the device is intended to allow the DSCG pin to help pull the power supply
down from high voltage, and then also pull VBUS at the connector down to the required level (refer to USB PD in
Documentation Support).
8.3.5.1 Discharging after a Fault (VPWR)
There are two types of faults that cause the TPS25740B to begin a full discharge of VBUS: Slow-shutdown faults
and fast-shutdown faults. When a slow-shutdown fault occurs, the device does not disable GDNG until after
VBUS is measured below V(SOVP) for a 5V contract. When a fast-shutdown fault occurs, the device disables
GDNG immediately and then discharges the connector side of the power-path. In both cases, the bleed
discharge is applied to the DSCG pin and I(SUPP) is drawn from the VPWR
Slow-shutdown faults that do not include transmitting a hard reset:
• Receiving a Hard Reset signal (25 ms < tShutdownDelay < 35 ms)
• Cable is unplugged (tShutdownDelay < 20 µs)
Slow-shutdown faults that include transmitting hard reset (25 ms < tShutdownDelay < 35 ms)
• TJ exceeds TJ1 (an overtemperature event)
• Low voltage alarm occurring outside of a voltage transition
• High voltage alarm occurring outside of a voltage transition (but not high enough to cause OVP)
• Receiving an unexpected PD message during a voltage transition
• Failure of power supply to transition voltages within required time of 600 ms (tPSTransition (refer to USB PD in
Documentation Support).
• A Soft Reset USB PD message is not acknowledged or Accepted (refer to USB PD in Documentation
Support).
• A Request USB PD message is not received in the required time (refer to USB PD in Documentation
Support).
• Failure to discharge down to 0.725 V after a fault of any kind.
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Feature Description (continued)
Fast-shutdown faults (hard reset always sent):
• Fast OVP event occurring at any time.
• OCP event occurring at any time starting from the transmission of the first USB PD message.
– VBUS falling below V(VBUS_FTH) is treated as an OCP event.
• GD falling edge
The DSCG pin is used to discharge the supply line after a slow-shutdown fault occurs. Figure 31 illustrates the
signals involved. Depending on the specific slow-shutdown fault the time tShutdownDelay in Figure 31 is different as
indicated in the list above. If the slow-shutdown fault triggers a hard reset, it is sent at the beginning of the
tShutdownDelay period. However, the device behavior after the time tShutdownDelay is the same for all slow-shutdown
faults. After the tShutdownDelay period, the device sets CTL1, CTL2, and CTL3 to select 5 V from the power supply
and puts the DSCG pin into its ON state (Full Discharge). This discharging continues until the voltage on the
VBUS pin reaches V(SOVP) for a 5-V contract. The device then disables GDNG and again puts the DSCG pin into
its ON state. This discharging state lasts until the voltage on VBUS reaches 0.725 V (nominal). If the discharge
does not complete within 650 ms, then the device sends a Hard Reset signal and the process repeats. In
Figure 31, the times labeled as t15→5 and t5→0 can vary, they depend on the size of the capacitance to be
discharged and the size of the external resistor between the DSCG pin and VBUS. The time labeled as tS is a
function of how quickly the NFET opens.
15 V
5V
VPWR
15 V
5V
VBUS
< 0.8 V
NFET enabled (closed)
NFET disabled (open)
GDNG
tS
Bleed
only
Full
discharge
DSCG
t15:5
t5:0
High-z
CTL1, CTL2, and CTL3
Low
tShutdownDelay
Time bounded by 650 ms
(tSafe0V)
SlowShutdown
Fault occurs
Figure 31. Illustration of Slow-Shutdown VBUS Discharge
Figure 32 illustrates a similar discharge procedure for fast-shutdown faults. The main difference from Figure 31 is
that the NFET is opened immediately. It is assumed for the purposes of this illustration that the power supply
output capacitance (that is, C(SOURCE) in the reference schematics shown in Figure 21 and Figure 22) is not
discharged by the power supply itself, but the VPWR pin is bleeding current from that capacitance. The VPWR
pin then draws I(SUPP) after GDNG disables the external NFET. So, as shown in the figure, the VPWR voltage
discharges slowly, while the VBUS pin is discharged once the full discharge is enabled. If the voltage on the
VPWR pin takes longer than t15→5 + t5→0 + 0.765s to discharge below V(FOVP), then it causes an OVP event and
the process repeats.
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Feature Description (continued)
15 V
5V
VPWR
15 V
5V
VBUS
< 0. 8 V
NFET closed
NFET open
GDNG
tS
Bleed
only
Full
dishcharge
DSCG
t15:5
t5:0
High-z
Low
CTL1, CTL2, and CTL3
FastShutdown
Fault occurs
tPSHardReset
Time bounded by 650 ms
(tSafe0V)
Hard
Reset
Sent
Figure 32. Illustration of Fast-Shutdown Discharge
If the discharge does not complete successfully it is treated as a slow-shutdown fault, and the device repeats the
discharge procedure until it does complete successfully. Once the discharge completes successfully as
described above (that is, VBUS on connector is below 0.725 V), the device waits for 0.765 s (nominal) before
trying to source VBUS again.
8.3.6 Configuring Voltage Capabilities (HIPWR)
The voltages advertised to USB PD-capable sinks can be configured to one of two different sets. Note that
changing the state of the PCTRL pin forces capabilities to be re-transmitted. The device reads the HIPWR pin
after a reset and latches the result.
Table 1. Voltage Programming (TPS25740B)
HIPWR PIN
VOLTAGES ADVERTISED via USB PD [V]
Connected to DVDD or GND directly
5, 9, 15, 20
Connected to DVDD or GND via R(SEL)
5, 9, 12, 15
8.3.7 Configuring Power Capabilities (PSEL, PCTRL, HIPWR)
The power advertised to non-PD Type-C Sinks is always 15 W. However, the device only advertises Type-C
default current until it debounces the Sink attachment for tCcDeb and the VBUS voltage has been given tVP to
stabilize.
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The device does not communicate with the cable to determine its capabilities. Therefore, unless the device is in
a system with a captive cable able to support 5 A, the HIPWR pin should be used to limit the advertised current
to 3 A.
PCTRL is an input pin used to control how much of the maximum allowed power the port will advertise. This pin
may be changed dynamically in the system and the device automatically updates any existing USB PD contract.
If the PCTRL pin is pulled below V(PCTRL_TH), then the source capabilities offers half of the maximum power
specified by the PSEL pin.
The devices read the PSEL and HIPWR pins after a reset and latches the result, but the PCTRL pin is read
dynamically by the device and if its state changes new capabilities are calculated and then transmitted.
While USB PD allows advertising a power of 100 W, UL certification for Class 2 power units (UL 1310) requires
the maximum power remain below 100 W. The device only advertises up to 4.65 A for a 20-V contract, this
allows the VBUS overshoot to reach 21.5 V as allowed by USB PD while remaining within the UL certification
limits. Therefore, the device allows delivering 100 W of power without adding additional voltage tolerance
constraints on the power supply.
The PSEL pin offers four possible maximum power settings, but the devices can actually advertise more power
settings depending upon the state of the HIPWR and PCTRL pins. Table 2 summarizes the four maximum power
settings that are available via PSEL, again note this is not necessarily the maximum power that is advertised.
Table 2. PSEL Configurations
MAXIMUM POWER
(PSEL) [W]
PSEL
P(SEL) = 36
Direct to GND
P(SEL) = 45
DVDD via R(SEL)
P(SEL) = 65
GND via R(SEL)
P(SEL) = 93
Direct to DVDD
Equation 2 provides a quick reference which applies to device to see how the HIPWR, PSEL and PCTRL pins
affect what current is advertised with each voltage in the source capabilities message:
§ Pmax
·
Ix = min ¨
, Imax ¸
Vmax
©
¹
(2)
Where:
• For a voltage Vx, the advertised current is Ix
• If the PCTRL pin is low, then Pmax = P(SEL) / 2
• If the PCTRL pin is high, then Pmax = P(SEL).
• If the HIPWR pin is pulled high, then Imax = 3 A.
• If the HIPWR pin is pulled low, then Imax = 5 A.
Table 3 provides a comprehensive list of the currents and voltages that are advertised for each voltage.
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Table 3. Maximum Current Advertised in the Power Data Object for a Given Voltage
MAXIMUM CURRENT
PCTRL = LOW [A]
MAXIMUM CURRENT
PCTRL = HIGH [A]
3
3
3
3
3
3
3
3
Direct to GND
2
3
DVDD via R(SEL)
2.5
3
3
3
Direct to DVDD
3
3
Direct to GND
1.5
3
1.87
3
2.7
3
PSEL
VOLTAGE [V]
HIPWR
Direct to GND
DVDD via R(SEL)
GND via R(SEL)
5
Direct to DVDD
GND via R(SEL)
DVDD via R(SEL)
GND via R(SEL)
9
12
Direct to DVDD
Max = 3 A
DVDD through
R(SEL) or Direct to
DVDD
Direct to GND
100kΩ to DVDD
100kΩ to GND
15
3
3
1.2
2.4
1.5
3
2.17
3
Direct to DVDD
3
3
Direct to GND
0.9
1.8
1.12
2.24
1.62
3
Direct to DVDD
2.32
3
Direct to GND
3.6
5
4.5
5
5
5
5
5
Direct to GND
2
4
DVDD via R(SEL)
2.5
5
3.61
5
Direct to DVDD
5
5
Direct to GND
1.5
3
1.87
3.74
2.7
5
DVDD via R(SEL)
GND via R(SEL)
DVDD via R(SEL)
GND via R(SEL)
20
5
Direct to DVDD
GND via R(SEL)
DVDD via R(SEL)
GND via R(SEL)
9
12
Direct to DVDD
Max = 5 A
GND through
R(SEL) or Direct to
GND
Direct to GND
100kΩ to DVDD
100kΩ to GND
15
4.16
5
1.2
2.4
1.5
3
2.17
4.33
Direct to DVDD
3.1
5
Direct to GND
0.9
1.8
1.12
2.24
1.62
3.24
2.32
4.64
DVDD via R(SEL)
GND via R(SEL)
20
Direct to DVDD
8.3.8 Gate Driver (GDNG, GDNS)
The GDNG and GDNS pins may control a single NFET or back-to-back NFETs in a common-source
configuration. The GDNS is used to sense the voltage so that the voltage differential between the pins is
maintained.
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VBUS
Power Supply
Power
Management
C(SLEW) R(SLEW)
GDNS
Safety
Turnoff
GDNG
10 :
R(GDNGOFF)
Charge
Pump
Gate Control
Copyright © 2016, Texas Instruments Incorporated
Figure 33. GDNG/GDNS Gate Control
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8.3.9 Fault Monitoring and Protection
8.3.9.1 Over/Under Voltage (VBUS)
The TPS25740B uses the VBUS pin to monitor for overvoltage or undervoltage conditions and implement the
fast-OVP, slow-OVP and slow-UVP features.
VBUS
VBUS
V(FOVP)
Deglitch
tFOVPDG
GDNG
Control
V(SOVP)
Sampled every 1ms
Send Hard
Reset
Sampled every 1ms
Send Hard
Reset
V(SUVP)
Copyright © 2016, Texas Instruments Incorporated
Figure 34. Voltage Monitoring Circuits
If an over-voltage condition is sensed by the Fast OVP mechanism, GDNG is disabled within tFOVP + tFOVPDG,
then a Hard Reset is transmitted and the VBUS discharge sequence is started. At power up the voltage trip point
is set to V(FOVP) (5 V contract). When a contract is negotiated the trip point is set to the corresponding V(FOVP)
value.
The devices employ another slow over-voltage protection mechanism as well that sends the Hard Reset before
disabling the external NFET. It catches many OV events before the Fast OVP mechanism. During intentional
positive voltage transitions, this mechanism is disabled (see Figure 1). However, tVP after the external NFET has
been enabled, if the voltage on the VBUS pin exceeds V(SOVP) then a Hard Reset is transmitted to the Sink and
the VBUS discharge sequence is started.
The devices employ a slow under-voltage protection mechanism as well that sends the Hard Reset before
disabling GDNG. During intentional negative voltage transitions, this mechanism is disabled (see Figure 1).
However, tVP after the external NFET has been enabled if the voltage on the VBUS pin falls below V(SUVP), then a
Hard Reset is transmitted to the Sink and the VBUS discharge sequence is started.
8.3.9.2 Over-Current Protection (ISNS, VBUS)
OCP protection is enabled tVP after the voltage on the VBUS pin has exceeded V(VBUS_RTH). Prior to OCP being
enabled, the GD pin can be used to protect against a short.
The OCP protection circuit monitors the differential voltage across an external sense resistor to detect when the
current outflow exceeds VI(TRIP) which in turn activates an over-current circuit breaker and disables the GDNG /
GDNS gate driver. Once the OCP is enabled, if the voltage on the VBUS pin falls below V(VBUS_FTH) then that is
also treated like an OCP event.
Following the recommended implementation of a 5-mΩ sense resistor, when the device is configured to deliver 3
A (via HIPWR pin), the OCP threshold lies between 3.8 A and 4.5 A. When configured to deliver 5 A (via HIPWR
pin), the OCP threshold lies between 5.8 A and 6.8 A. The resistance of the sense resistor may be tuned to
adjust the current that causes VI(TRIP) to be exceeded.
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RS
Power Supply
VBUS
VBUS
ISNS
V(VBUS_TH)
+
-
VI(TRIP)
+
GDNG
Control
+
Deglitch
-
tOCP
Enable OCP
Copyright © 2016, Texas Instruments Incorporated
Figure 35. Overcurrent Protection Circuit, (ISNS, VBUS)
8.3.9.3 System Fault Input (GD, VPWR)
The gate-driver disable pin provides a method of overriding the internal control of GDNG and GDNS. A falling
edge on GD disables the gate driver within tGDoff. If GD is held low after a sink is attached for 600 ms then a hard
reset will be generated and the device sends a hard reset and go through its startup process again.
The GD input can be controlled by a voltage or current source. An internal voltage clamp is provided to limit the
input voltage in current source applications. The clamp can safely conduct up to 80 µA and will remain high
impedance up to 6.5 V before clamping.
GDNG
GD
Control
V(GD_TH)
R(GD)
Deglitch
tGDoff
V(GDC)
Copyright © 2016, Texas Instruments Incorporated
Figure 36. Overcurrent Protection Circuit, (GD)
If the VPWR pin remains below its falling UVLO threshold (V(VPWR_TH)) for more than 600 ms after a sink is
attached then the devices consider it a fault and will not enable GDNG. If the VPWR pin is between the rising
and falling UVLO threshold, the device may enable GDNG and proceed with normal operations. However, after
GDNG is enabled, if the VBUS pin does not rise above its UVLO within 190 ms the devices consider it a fastshutdown fault and disables GDNG. Therefore, in order to ensure USB Type-C compliance and normal
operation, the VPWR pin must be above its rising UVLO threshold (V(VPWR_TH)) within 275 ms of when ENSRC is
pulled low and the VBUS pin must be above V(VBUS_RTH) within 190 ms of GDNG being enabled.
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8.3.10 Voltage Control (CTL1, CTL2,CTL3)
CTL1, CTL2, and CTL3 are open-drain output pins used to control an external power supply as summarized in
Table 4. Depending upon the voltage requested by the sink, the device sets the CTL pins accordingly. No current
flows into the pin in its high-z state.
Table 4. States of CTL1, CTL2, and CTL3 as a Function of Target Voltage on VBUS (TPS25740B)
VOLTAGE CONTAINED in PDO REQUESTED by UFP
CTL3 STATE
CTL2 STATE
CTL1 STATE
5V
High-z
High-z
High-z
9V
High-z
Low
High-z
12 V (if 12 V enabled by HIPWR pin)
15 V (if 20 V enabled by HIPWR pin)
High-z
Low
Low
15 V (if 12V enabled by HIPWR pin)
20 V (if 20 V enabled by HIPWR pin)
Low
Low
Low
8.3.11 Sink Attachment Indicator (DVDD)
DVDD is a power supply pin that is high-z until a sink or debug accessory or audio accessory is attached, in
which case it is pulled high. Therefore, it can be used as a sink attachment indicator that is active high.
8.3.12 Power Supplies (VAUX, VDD, VPWR, DVDD)
The VAUX pin is the output of a linear regulator and the input supply for internal power management circuitry.
The VAUX regulator draws power from VDD after establishing a USB PD contract unless it is not available in
which case it draws from VPWR. Changes in supply voltages will result in seamless switching between supplies.
If there is a load on the DVDD pin, that current will be drawn from the VPWR pin unless the device has stabilized
into a USB PD contract or VPWR is below its UVLO.
Connect VAUX to GND via the recommended bypass capacitor. Do not connect any external load that draws
more than I(VAUXEXT). Locate the bypass capacitor close to the pin and provide a low impedance ground
connection from the capacitor to the ground plane.
VDD should either be grounded or be fed by a low impedance path and have input bypass capacitance. Locate
the bypass capacitors close to the VDD and VPWR pins and provide a low impedance ground connection from
the capacitor to the ground plane.
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VPWR
VDD
Power Supply
VAUX
0.1…F
Power Management
DVDD
0.22…F
Copyright © 2016, Texas Instruments Incorporated
Figure 37. Power Management
8.3.13 Grounds (AGND, GND)
GND is the substrate ground of the die. Most circuits return to GND, but certain analog circuitry returns to AGND
to reduce noise and offsets. The power pad (on those devices that possess one) is electrically connected to
GND. Connect AGND, GND and the power pad (if present) to the ground plane through the shortest and most
direct connections possible.
8.3.14 Output Power Supply (DVDD)
The DVDD pin is the output of an internal 1.85 V linear regulator, and the input supply for internal digital circuitry.
This regulator normally draws power from VPWR until a USB PD contract has stabilized, but will seamlessly
swap to drawing power from VDD in the event that VPWR drops below its UVLO threshold. External circuitry can
draw up to 35 mA from DVDD. Note that as more power is drawn from the DVDD pin more heat is dissipated in
the device, and if excessive the OTSD could be tripped which resets the device. Connect DVDD to GND via the
recommended ceramic bypass capacitor.
The DVDD pin will only be high when a USB Type-C sink, or audio accessory, or debug accessory is attached,
refer to Figure 19 and Figure 20.
Locate the bypass capacitor close to the pin and provide a low impedance ground connection from the capacitor
to the ground plane.
34
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8.4 Device Functional Modes
8.4.1 Sleep Mode
Many adaptors that include USB PD must consume low quiescent power to meet regulatory requirements (that
is, “Green,” Energy Star, or such). The device supports the sleep mode to minimize power consumption when the
receptacle or plug is unattached. The device enters sleep mode when there is no valid plug termination attached;
a valid plug termination is defined as one of: sink, Audio accessory, or Debug accessory. If an active cable is
attached but its far-end is left unconnected or “dangling,” then the device also enters sleep mode. It exits the
sleep mode whenever the plug status changes, that could be a dangling cable being removed or a sink being
connected.
8.4.2 Checking VBUS at Start Up
When first powered up, the device will not enable GDNG if the voltage on VBUS is already above its UVLO. This
is a protective measure taken to avoid the possibility of turning on while connected to another active power
supply in some non-compliant configuration.
This means that the VBUS pin must be connected between the power-path NFET and the USB connector. This
also allows for a controlled discharge of VBUS all the way down to the required voltage on the connector (refer to
USB PD in Documentation Support).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS25740B implements a fully compliant USB Power Delivery 2.0 provider and Type-C source (also known
as downward facing port (DFP)). The device basic schematic diagram is shown in Figure 38. Subsequent
sections describe detailed design procedures for several applications with differing requirements. The
TPS25740B Design Calculator Tool (refer to USB PD in Documentation Support ) is available for download and
use in calculating the equations in the following sections.
CSD17579Q3A
5mŸ
B340A-13-F
VBUS
6.8 PF
VDD
CC1
CTL1
CC2
G ND
AG ND
PSEL
100 k:
H IPWR
0.22 PF
DVDD
GD
0.1 PF
V TX
0.1 PF
VAUX
TPS25740B
CTL2
CTL3
ENSRC
PCTRL
220 k:
Type-C
Plug
560 pf
DSC G
V BUS
ISN S
GDNS
G DN G
0.33 µF
V PW R
Power
Supply
System
0.1 PF
10 nF
1 k:
D-
120 :
10 :
24.9 :
D+
Copyright © 2016, Texas Instruments Incorporated
Figure 38. Basic Schematic Diagram (P(SEL) = 65 W at 5 V, 9 V, 15 V, 20 V)
9.1.1 System-Level ESD Protection
System-level ESD (per EN61000-4-2) may occur as the result of a cable being plugged in, or a user touching the
USB connector or cable. Figure 39 shows an example ESD protection for the VBUS path that helps protect the
VBUS pin, ISNS and DSCG pins of the device from system-level ESD. The device has ESD protection built into
the CC1 and CC2 pins so that no external protection is necessary. Refer to the Layout Guidelines section for
external component placement and routing recommendations.
The Schottky diode is to protect against VBUS being drawn below ground by an inductive load, the cable
inductance may be as high as 900 nH.
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Application Information (continued)
VBUS
RS
Type-C
Plug/
Receptacle
ISNS
VBUS
DSCG
R(DSCG)
C(PDIN)
D(VBUS)
TPS25740B
Copyright © 2016, Texas Instruments Incorporated
Figure 39. VBUS ESD Protection
9.1.2 Using ENSRC to Enable the Power Supply upon Sink Attachment
ENSRC may be connected to the enable pin of the power supply as shown in Figure 40. This configuration can
eliminate the idle state power loss in the power supply by only turning it on when a sink is attached. In this
configuration, VPWR must be connected to a live source so that the TPS25740B can wake upon sink
attachment.
CSD17579Q3A (1x)
VBUS
C(PDIN)
Type-C
Receptacle
CC1
CC2
C(RX)
GND
AGND
PSEL
DVDD
GD
C(DVDD)
C(VAUX)
C(VTX)
HIPWR
R(SEL)
VTX
PCTRL
VAUX
TPS25740B
CTL1
CTL2
CTL3
ENSRC
C(RX)
VBUS
DSCG
GDNS
ISNS
C(SLEW) R(SLEW)
VDD
GDNG
VPWR
FEEDBACK
NETWORK
R(DSCG)
10Ÿ
FB
POWER
SUPPLY
ENABLE
RS
DC OUT
C(SOURCE)
DC IN
Copyright © 2017, Texas Instruments Incorporated
Figure 40. ENSRC as Power Supply Enable
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Application Information (continued)
Another benefit of this configuration is that only one NFET is required to block the source capacitance of the
power supply when the socket is cold. This requires that the NFET be oriented with drain towards the type C
connector as shown in Figure 40. For this NFET orientation, TPS25740B cannot protect the power supply from
over-current events, so the power supply must implement over-current protection. For this case, RS may be
removed with ISNS directly connected to VBUS. Since VBUS follows DC OUT, power supply start-up overshoot
must be less than V(SOVP5). ENSRC is set to high-z after a delay of tHR whenever TPS25740B detects a fault that
requires a hard reset.
9.1.3
Use of GD Internal Clamp
As described in the Configuring Power Capabilities (PSEL, PCTRL, HIPWR) section, the GD pin has an internal
clamp. Figure 41 shows an example of how it may be used. VOUT is the voltage from a power supply that is to be
provided onto the VBUS wire of the USB Type-C cable through an NFET resistor. If VOUT drops, the NFET
should be automatically disabled by the device. This can be accomplished by tying the GD pin to VOUT via a
resistor.
The internal resistance of the GD pin is specified to exceed R(GD), and the input threshold is V(GD_TH). The GD pin
would therefore draw no more than V(GD_TH) max / R(GD) min < 603 nA. As an example, assume the minimum value
of VOUT for which GD should be high is 4.5 V, then the resistor between GD and VOUT may not exceed (4.5 –
V(GD_TH) max) / 603e-9 = 4.5 MΩ. To make it robust against board leakage a smaller resistor such as 1 MΩ can be
chosen, but the smaller the resistance the more leakage current into the GD pin. In this example, when VOUT is
25 V, the current into the GD pin is (25-V(GDC)) / 1e6 < 1.85 µA.
CSD17579Q3A
VBUS
R(DSCG)
RS
GD
C(RX)
DSCG
VBUS
ISNS
GDNS
VPWR
GDNG
C(SLEW)
10Ÿ
R(SLEW)
RG
Type-C Plug
C(PDIN)
VOUT
CC1
CC2
TPS25740B
Copyright © 2016, Texas Instruments Incorporated
Figure 41. Use of GD Internal Clamp
9.1.4 Resistor Divider on GD for Programmable Start Up
Figure 42 shows an alternative usage of the GD pin can help protect against shorts on the VBUS pin in the
receptacle. A resistor divider is used to minimize the time it takes the GD pin to be pulled low. Consider the
situation where the VBUS pin is shorted at startup. At some point, the device closes the NFET switch to supply 5
V to VBUS. At that point, the short pulls down on the voltage seen at the VPWR pin. With the resistor values
shown in Figure 42, once the voltage at the VPWR pin reaches 3.95 V the voltage at the GD pin is specified to
be below V(GD_TH) min. Without the 700-kΩ resistor, the voltage at the VPWR pin would have to reach V(GD_TH) min
which takes longer. This comes at the expense of increased leakage current.
38
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Application Information (continued)
CSD17579Q3A
VBUS
R(DSCG)
RS
R(GD2)
700NŸ
GD
C(RX)
DSCG
VBUS
ISNS
GDNS
GDNG
VPWR
R(GD1)
10Ÿ
C(SLEW)
R(SLEW)
RG
Type-C Plug
C(PDIN)
VOUT
CC1
CC2
TPS25740B
Copyright © 2016, Texas Instruments Incorporated
Figure 42. Programmable GD Turn On
The GD resistor values can be calculated using the following process. First, calculate the smallest R(GD1) that
should be used to prevent the internal clamp current from exceeding I(GD) of 80 µA. For a 20 V advertised
voltage, the OVP trip point could be as high as 24 V. Using V(GDC) min = 6.5 V and VOUT = V(FOVP20) max = 24 V,
provides Equation 3:
R(GD1) !
V(FOVP20)
V(GDC)
I(GD)
24 V 6.5 V
80 $
219 k
(3)
The actual clamping current is less than 80 µA as some current flows into R(GD2). Next, R(GD2) can be calculated
as shown in Equation 4:
R(GD2) R(GD1) u
V(GD_TH)
V(VPWR)
V(GD_TH)
where
•
V(VPWR) = V(VPWR_TH) falling (max) and V(GD_TH) = V(GD_TH) falling (min).
(4)
9.1.5 Selection of the CTL1, CTL2, and CTL3 Resistors (R(FBL1), R(FBL2), and R(FBL3))
R(FBL1), R(FBL2), and R(FBL3) provide a means to change the power supply output voltage when switched in by the
CTL1, CTL2, and CTL3 open drain outputs, respectively. When CTLx is driven low it will place R(FBLx) in parallel
with R(FBL).
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Application Information (continued)
VOUT
R(FBU)
R(OB)
C(IZ)
R(FBL2)
R(FBL3)
R(FBL)
CTL1
R(FBL1)
CTL2
CTL3
TL431
Copyright © 2016, Texas Instruments Incorporated
Figure 43. Circuit to Change VOUT Upon Sink/UFP Request
R(FBL2) is calculated using Equation 5. In this example, VOUT9 is 9 V, VOUT15 is 15 V, and VOUT20 is 20 V. VOUT is
the default output voltage (5 V) for the regulator and is set by R(FBU), R(FBL) and error amplifier VREF.
R(FBL2) =
R(FBL) × R(FBU) × VREF
R(FBL) × VOUT9 - VREF - R(FBU) × VREF
(5)
R(FBL1) is calculated using Equation 6 after a standard 1% value for R(FBL2) is chosen.
R(FBL2) × R(FBL)
× R(FBU) × VREF
R(FBL2) + R(FBL)
R(FBL1) =
R(FBL2) × R(FBL)
× VOUT15 - VREF - R(FBU) × VREF
R(FBL2) + R(FBL)
(6)
R(FBL1) × R(FBL2) × R(FBL)
× R(FBU) × VREF
R(FBL) × R(FBL2) + R(FBL1) + R(FBL2) × R(FBL1)
R(FBL3) =
R(FBL1) × R(FBL2) × R(FBL)
× VOUT20 - VREF - R(FBU) × VREF
R(FBL) × R(FBL2) + R(FBL1) + R(FBL2) × R(FBL1)
(7)
R(FBLx) resistors should be large enough so that the corresponding CTLx sinking current is minimized (< 1 mA).
The sinking current for CTLx is VREF / R(FBLx).
9.1.6 Voltage Transition Requirements
During VBUS voltage transitions, the slew rate (vSrcSlewPos) must be kept below 30 mV/µs in all portions of the
waveform, settle (tSrcSettle) in less than 275 ms, and be ready (tSrcReady) in less than 285 ms. For most power
supplies, these requirements are met naturally without any special circuitry but in some cases, the voltage
transition ramp rate must be slowed in order to meet the slew rate requirement.
The requirements for linear voltage transitions are shown in Table 5. In all cases, the minimum slew time is
below 1 ms.
Table 5. Minimum Slew-Rate Requirements
VOLTAGE
5 V ↔ 12 V
TRANSITION
Minimum
Slew Time
40
233 µs
5 V ↔ 20 V
12 V ↔ 20 V
5V↔9V
5 V ↔ 15 V
9 V ↔ 15 V
9 V ↔ 12 V
12 V ↔ 15 V
9 V ↔ 20 V
15 V ↔ 20 V
500 µs
267 µs
133 µs
333 µs
200 µs
100 µs
100 µs
367 µs
167 µs
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When transition slew control is required, the interaction of the slew mechanism and dc/dc converter loop
response must be considered. A simple R-C filter between the device CTL pins and converter feedback node
may lead to instability under some conditions. Figure 44 shows a method which controls the slew rate without
adding capacitance to the converter feedback node.
R(CTL2)
R(SL2A)
R(CTL1)
DC/ DC
Converter
R(FBU)
VOUT
R(SL1A)
VCC
CTL1
R(SL2B)
Q(CTL2)
R(FBL2)
Q(SL2)
Q(CTL1)
R(SL1B)
C(SL1)
R(FBL1)
R(FBL)
Q(SL1)
C(SL2)
FB
TPS25740B
CTL2
Copyright © 2016, Texas Instruments Incorporated
Figure 44. Slew-Rate Control Example No. 1
When VOUT = 5 V, all CTL pins are in a high impedance state. When a 5 V to 12 V transition is requested, CTL2
goes low and turns off Q(CTL2). Q(SL2) gate starts to rise towards VCC at a rate determined by R(SL2A) + R(SL2B) and
C(SL2). Q(SL2) gate continues to rise, until Q(SL2) is fully enhanced placing R(FBL2) in parallel with R(FBL). In similar
fashion when C(TL1) goes low, Q(CTL1) turns off allowing R(FBL1) to slew in parallel with R(FBL2) and R(FBL).
The slewing resistors and capacitor can be chosen using the following equations. VT is the VGS threshold
voltage of Q(SL1) and Q(SL2). VREF is the feedback regulator reference voltage. Choose the slewing resistance in
the 100 kΩ range to reduce the loading on the bias voltage source (VCC) and then calculate C(SL). The falling
transitions is shorter than the rising transitions in this topology.
Falling transitions:
• 20 V to 12 V
R(SL1B) × C(SL1) =
•
û720V - 12V
§ V + VREF ·
§ VT ·
ln ¨ T
¸ - ln ¨
¸
¨ V(VCC) ¸
¨ V(VCC) ¸
©
¹
©
¹
(8)
û712V - 5V
§ VT + VREF ·
§ VT ·
ln ¨
¸ - ln ¨
¸
¨ V(VCC) ¸
¨ V(VCC) ¸
©
¹
©
¹
(9)
12 V to 5 V
R(SL2B) × C(SL2) =
Rising transitions:
• 5 V to 12 V
R(SL2A) + R(SL2B) × C(SL2) =
•
û75V - 12V
§
§
VT ·
V + VREF ·
ln ¨ 1 ¸ - ln ¨ 1 - T
¸
¨
¸
¨
V(VCC) ¹
V(VCC) ¸¹
©
©
(10)
û712V - 20V
§
§
VT ·
V + VREF ·
ln ¨ 1 ¸ - ln ¨ 1 - T
¸
¨
¨
V(VCC) ¸¹
V(VCC) ¸¹
©
©
(11)
12 V to 20 V
R(SL1A) + R(SL1B) × C(SL1) =
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Some converter regulators can tolerate a balance of capacitance on the feedback node without affecting loop
stability. The LM5175 has been tested using Figure 45 to combine VOUT slewing with a minimal amount of extra
circuitry.
R(FBU)
VOUT
C(SLU)
CTL1
R(FBL2)
R(FBL)
C(SLL)
R(FBL3)
FB
LM5175
R(FBL1)
TPS25740B
CTL2
CTL3
Copyright © 2016, Texas Instruments Incorporated
Figure 45. Slew-Rate Control Example No. 2
When a higher voltage is requested from TPS25740B, at least one of the CTL pins goes low changing the
sensed voltage at the FB pin. The LM5175 compensates by increasing C(SLU). As VOUT increases, C(SLU) is
charged at a rate proportional to R(FBU). Three time constants yields a voltage change of approximately 95% and
can be used to calculate the desired slew time. C(SLU) can be calculated using Equation 12 and Equation 13.
'T(SLEW) = 3 × R(FBU) × C(SLU)
C(SLU) =
(12)
'T(SLEW)
3 × R(FBU)
(13)
In order to minimize loop stability effects, a capacitor in parallel with R(FBL) is required. The ratio of C(SLU)/C(SLL)
should be chosen to match the ratio of R(FBL)/R(FBU). Choose C(SLL) according to Equation 14.
C(SLL) = C(SLU) ×
R(FBU)
R(FBL)
(14)
A third slew rate method is shown in Figure 46 using an equivalent resistance, REQ and C(SLL) to provide an
exponential slew rate. The slew rate is the derivative of the voltage ramp with the maximum occurring at the
beginning of a transition. A DC-DC converter with programmable soft-start can help minimize VOUT overshoot at
start-up due to C(SLL). Any VOUT overshoot must decay below V(SOVP5) before TPS25740B applies VBUS in
order to prevent OVP shutdown.
R(FBU)
VOUT
DC DC
Converter
TPS25740B
R(FB1)
R(FBL1)
R(FBL)
FB
C(SLL)
R(FBL2)
R(FBL3)
CTL1
CTL2
CTL3
Copyright © 2017, Texas Instruments Incorporated
Figure 46. Slew-Rate Control Example No. 3
For the rising condition, TPS25740B will connect one or more of the R(FBLx) resistors in parallel with C(SLL). The
FB node is treated as a virtual ground so that REQ for the rising condition is R(FB1) in parallel with the R(FBLx)
resistors being grounded through the CTLx pins. For the falling condition, TPS25740B will disconnect one or
more of the R(FBLx) resistors in parallel with C(SLL). REQ for the falling condition is therefore R(FB1) in parallel with
the R(FBLx) resistors remaining grounded.
42
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-t
û9BUS
§ mV ·
u C(SLL)
R
u e EQ
SR ¨
¸ =
P
u
u
s
1000
R
C
©
¹
EQ
(SLL)
where
•
SR = SR(max) at t = 0
(15)
û9BUS
§ mV ·
SR(max) ¨
¸ =
P
u
s
1000
REQ u C(SLL)
©
¹
(16)
The slew rate is proportional to VBUS voltage change and the largest slew rate occurs for the 5 V to 20 V case (or
15 V if 15 V is the highest advertised voltage) where all three R(FBLx) resistors are connected simultaneously.
Size C(SLL) for this case using REQ = R(FB1), R(FBL1), R(FBL2), and R(FBL3) in parallel.
For this method, the procedure to choose the voltage programming resistors differs from the examples in section
Selection of the CTL1, CTL2, and CTL3 Resistors (R(FBL1), R(FBL2), and R(FBL3)) due to the addition of R(FB1). The
TPS25740B Design Calculator Tool (refer to USB PD in Documentation Support ) is available to help with the
calculations for this control method. All slew rate control methods should be verified on the bench to ensure that
the slew rate requirements are being met when the external VBUS capacitance is between 1 µF and 100 µF.
9.1.7 VBUS Slew Control using GDNG C(SLEW)
Care should be taken to control the slew rate of Q1 using C(SLEW); particularly in applications where COUT >>
C(SLEW). The slew rate observed on VBUS when charging a purely capacitive load is the same as the slew rate of
V(GDNG) and is dominated by the ratio I(GDNON) / C(SLEW). R(SLEW) helps block C(SLEW) from the GDNG pin enabling
a faster transient response to OCP.
RS
DSCG
VBUS
ISNS
G DN S
GD N G
V PW R
CF
VDD
VBUS
R(DSCG)
RF
RG
C(SLEW)
R(SLEW)
C(PWR)
D(VBUS)
C(PDIN)
Q1
VOUT
TPS25740B
Copyright © 2016, Texas Instruments Incorporated
Figure 47. Slew-Rate control Using GDNG
There may be fault conditions where the voltage on VBUS triggers an OVP condition and then remains at a high
voltage even after the TPS25740B configures the voltage source to output 5 V via the CTL pins. When this OVP
occurs, the TPS25740B opens Q1 within tFOVP + tFOVPDG. The TPS25740B then issues a hard reset, discharge
the power-path via the R(DSCG), and waits for 795 ms before enabling Q1 again. Due to the fault condition the
voltage again triggers an OVP event when the voltage on VBUS exceeds V(FOVP). This retry process would
continue as long as the fault condition persists, periodically pulsing up to V(FOVP) + VSrcSlewPos x (tFOVP + tFOVPDG)
onto the VBUS of the Type-C receptacle. It is recommended to use a slew rate less than the maximum of
VSrcSlewPos (30 mV / µs) allowed by USB (refer to Documentation Support), the slew rate should instead be set in
order to meet the requirement to have the voltage reach the target voltage within tSrcSettle (275 ms). This also
limits the out-rush current from the COUT capacitor into the C(PDIN) capacitor and help protect Q1 and RS.
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9.1.8 Tuning OCP using RF and CF
In applications where there are load transients or moderate ripple on VOUT, the OCP performance of TPS25740B
may be impacted. Adding the RF/CF filter network as shown in Figure 48 helps mitigate the impact of the ripple
and load transients on OCP performance.
Q1
RS
R(DSCG)
C(SLEW)
R(SLEW)
DSCG
VBUS
ISNS
GDNG
VPWR
GDNS
CF
C(VPWR)
VBUS
C(PDIN)
D(VBUS)
RF
RG
VOUT
VDD
TPS25740B
Copyright © 2016, Texas Instruments Incorporated
Figure 48. ISNS Filtering Example
RF/CF can be tailored to the amount of ripple on VOUT as shown in Table 6.
Table 6. Ripple on VOUT
FREQUENCY x RIPPLE (kHz x V)
44
SUGGESTED FILTER TIME CONSTANT (µs)
< 5 (Ex: 50 mV ripple at 100 kHz)
None
5 to 15
2.2 µs ( RF = 10 Ω, CF = 220 nF)
15 to 35
4.7 µs ( RF = 10 Ω, CF = 470 nF)
35 to 105
10 µs ( RF = 10 Ω, CF = 1 µF)
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9.2 Typical Applications
9.2.1 Typical Application, A/C Power Source (Wall Adapter)
T1
D-
VBUS
DSCG
C(RX)
R(DSCG)
100Ÿ
VBUS
D+
CC1
CC2
VDD
C(VAUX)
ENSRC
GND
AGND
DVDD
HIPWR
PSEL
TPS25740B
C(DVDD)
CTL1
CTL2
CTL3
CIO
P
GDNS
ISNS
R(FBL1)
R(FBL2)
TL431
R(FBL3)
RCS
RF6
CIZ
GND
GDNG C
(SLEW) R(SLEW)
RLC
FB
RF5
PCTRL
ROB
VPWR
C(VPWR)
VB
CS
P
R(FBU)
M1
R(FBL)
CDD1
CDD
HV
UCC28740
VS
DRV
RS2
RS1
RG
VDD
LDO
C(PDIN)
COUT
VAUX
GD
VTX
t
DVC
T1
RS
DS
P
P
Type-C
Plug
CSD17579Q3A
C(VTX)
CB1
CB2
+
From AC Mains
In this design example, PSEL pin is configured so that P(SEL) = 65 W (see Table 7). Voltages offered are 5 V, 9
V, 15 V, and 20 V at a maximum of 3 A. The overcurrent protection (OCP) trip point is set just above 3 A and
VDD on the TPS25740B is grounded. The following example is based on PMP11451 and PMP11455, see
www.ti.com/tool/PMP11451. In this design, the TPS25740B and some associated discretes are located on the
paddle card (PMP11455) which plugs into the power supply card (PMP11451). This allows different paddle cards
with different power and voltage advertisements to be used with a common power supply design.
100kŸ
Copyright © 2016, Texas Instruments Incorporated
Figure 49. Captive Cable Adapter Provider Conceptual Schematic
9.2.1.1 Design Requirements
Table 7. Design Parameters
DESIGN PARAMETER
VALUE
Configured Power Limit, P(SEL)
65 W
Advertised Voltages
5 V, 9V, 15V, 20 V
Advertised Current Limit
3A
Over Current Protection Set point
4.2 A
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Power Pin Bypass Capacitors
•
•
•
•
•
C(VPWR): 0.1 μF, 50 V, ±10%, X7R ceramic at pin 20 (VPWR)
C(VDD): 0.1 μF, 50 V, X7R ceramic at pin 17 (VDD). If VDD is not used in the application, then tie VDD to
GND.
C(DVDD): 0.22 μF, 10 V, ±10%, X5R ceramic at pin 13 (DVDD)
C(VAUX): 0.1 μF, 50 V, ±10%, X7R ceramic at pin 16 (VAUX)
C(VTX): 0.1 μF, 50 V, ±10%, X7R ceramic at pin 1 (VTX)
9.2.1.2.2 Non-Configurable Components
•
•
•
R(SEL): When the application requires advertisement using R(SEL) , use a 100 kΩ, ±1% resistor.
R(PCTRL): If PCTRL will be pulled low with an external device then it can be connected to VAUX using a 220
kΩ, ±1% resistor. If PCTRL is always high, then it can be directly connected to VAUX.
R(SLEW): Use a 1 kΩ, ±1% resistor
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•
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RG: Use a 10 Ω, ±1% resistor
9.2.1.2.3 Configurable Components
•
•
•
•
•
•
•
•
•
46
C(RX): Choose C(RX) between 200 pF and 600 pF. A 560 pF, 50 V, ±5% COG/NPO ceramic is recommended
for both CC1 and CC2 pins.
Q1: For a 3 A application, an N-Channel MOSFET with RDS(on) in the 10 mΩ range is sufficient. BV(DSS) should
be rated for 30 V for applications delivering 20 V, and 25 V for 12 V applications. For this application, the TI
CSD17579Q3A (SLPS527) NexFET™ is suitable.
RS: TPS25740B OCP set point thresholds are targeted towards a 5 mΩ, ±1% sense resistor. Power
dissipation for RS at 3 A load is approximately 45 mW.
R(DSCG): The minimum value of R(DSCG) is chosen based on the application VBUS (max) and I(DSCGT). For
VBUS (max) = 12 V and I(DSCGT) = 350 mA, R(DSCG(min)) = 34.3 Ω. The size of the external resistor can then be
chosen based on the capacitive load that needs to be discharged and the maximum allowed discharge time
of 265 ms. Typically, a 120 Ω, 0.5 W resistor provides suitable performance.
RF/CF: Not used
C(PDIN): The requirement for C(PDIN) is 10 µF maximum. A 6.8 µF, 25 V, ±10% X5R or X7R ceramic capacitor
is suitable for most applications.
D(VBUS): D(VBUS) provides reverse transient protection during large transient conditions when inductive loads
are present. A Schottky diode with a V(RRM) rating of 30 V in a SMA package such as the B340A-13-F
provides suitable reverse voltage clamping performance.
C(SLEW): To achieve a slew rate from zero to 5 V of less than 30 mV / µs using the typical GDNG current of 20
µA then C(SLEW) > 20 µA / 30 mV / µs = 0.67 nF be used. Choosing C(SLEW) = 10 nF yields a ramp rate of 2
mV / µs.
R(FBL1)/R(FBL2)/R(FBL3): In this design example, R(FBU) = 20 kΩ and R(FBL) = 20 kΩ. The feedback error amplifier
is TL431AI which is rated for up to 36 V operation and VREF = 2.495 V. Using the equation for R(FBL2) above
yields a calculated value of 12.44 kΩ and a selected value of 12.4 kΩ. In similar fashion for R(FBL1), the
equation yields a calculated value of 8.34 kΩ and a selected value of 8.25 kΩ. Lastly for R(FBL3), the
calculated value is 10.1 kΩ with a selected value of 10 kΩ.
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9.2.1.3 Application Curves
5
11.99
120 VAC/60 Hz
230 VAC/50 Hz
4.99
120 VAC/60 Hz
230 VAC/50 Hz
11.98
Output Voltage (V)
Output Voltage (V)
11.97
4.98
4.97
4.96
11.96
11.95
11.94
11.93
4.95
11.92
4.94
11.91
0
0.5
1
1.5
2
Load Current (A)
2.5
3
3.5
0
0.5
D001
DFP End - VBUS = 5 V
1
1.5
2
Load Current (A)
2.5
3
3.5
D002
DFP End - VBUS = 12 V
Figure 50. Load Regulation
Figure 51. Load Regulation
20.09
120 VAC/60 Hz
230 VAC/50 Hz
20.08
Output Voltage (V)
20.07
20.06
20.05
20.04
20.03
20.02
20.01
0
0.5
1
1.5
2
Load Current (A)
2.5
3
3.5
D003
No Load
DFP End - VBUS = 20 V
Figure 53. VBUS Startup
Figure 52. Load Regulation
No Load
No Load
Figure 54. VBUS 5 V – 15 V Transition
Figure 55. VBUS 15 V – 5 V Transition
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No Load
No Load
Figure 56. VBUS 15 V – 20 V Transition
No Load
Figure 57. VBUS 20 V – 15 V Transition
No Load
Figure 58. VBUS 5 V – 20 V Transition
48
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Figure 59. VBUS 20 V – 5 V Transition
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9.2.2 Typical Application, D/C Power Source
100 Ÿ
100 Ÿ
C(PDIN)
VBUS
D+
Type-C
plug
D-
DSCG
VBUS
GDNS
ISNS
C(RX)
C(RX)
R(DSCG)
C(SLEW) R(SLEW)
GDNG
VPWR
R(FBU)
CC1
CC2
VDD
TPS25740B
CS
CSG
C(DVDD)
ENSRC
GND
AGND
CTL1
CTL2
CTL3
HIPWR
PSEL
SW2
FB
DVDD
R(FBL2)
C(SLL)
C(VTX)
SW2
0.1 µF
C(VAUX)
CS
CSG
47 pF
PGOOD
HDRV2
AGND
VOUT
0.08 Ÿ
CSG
R(FBL3)
BOOT2
C(SLU)
CS
LDRV2
COMP
VOSNS
0.022 µF
LM5175
SS
ISNS(-)
10 NŸ
1 µF
PGND
SLOPE
ISNS(+)
100 pF
SW2
SW1
VCC
100 pF
0.1µF
4.7 µH
VOUT
0.1µF
PCTRL
VAUX
GD
VTX
RT/SYNC
RG
C(VPWR)
BOOT1
SW1
VIN
HDRV1
LDRV1
BIAS
Rs
COUT
R(FBL)
84.5 NŸ
MODE
DITH
4.7 µF
x5
VCC
0Ÿ
EN/UVLO
249 NŸ
59 NŸ
49.9 NŸ
CSD17579Q3A
VOUT
100 Ÿ
VCC
+
VISNS
68 µF
0.1 µF
+
R(FBL1)
10 Ÿ 0.1 µF
6 V - 42 V
VIN
SW1
In this design example the PSEL pin is configured such that P(SEL) = 65 W (see Table 8). Voltages offered are 5
V, 9 V, 15 V, and 20 V at a maximum of 3 A. The overcurrent protection (OCP) trip point is set just above 3 A
and VDD on the TPS25740B is grounded. The following example is based on TPS25740BEVM-741 (refer to
Documentation Support).
100 NŸ
Copyright © 2016, Texas Instruments Incorporated
Figure 60. DC Power Source
9.2.2.1 Design Requirements
Table 8. Design Parameters
DESIGN PARAMETER
VALUE
Configured Power Limit, P(SEL)
65 W
Advertised Voltages
5 V, 9 V, 15 V, 20 V
Advertised Current Limit
3A
Over Current Protection Set point
4.2 A
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Power Pin Bypass Capacitors
•
•
•
•
•
C(VPWR): 0.1 μF, 50 V, ±10%, X7R ceramic at pin 20 (VPWR)
C(VDD): 0.1 μF, 50 V, X7R ceramic at pin 17 (VDD). If VDD is not used in the application, then tie VDD to
GND.
C(DVDD): 0.22 μF, 10 V, ±10%, X5R ceramic at pin 13 (DVDD)
C(VAUX): 0.1 μF, 50 V, ±10%, X7R ceramic at pin 16 (VAUX)
C(VTX): 0.1 μF, 50 V, ±10%, X7R ceramic at pin 1 (VTX)
9.2.2.2.2 Non-Configurable Components
•
•
•
•
R(SEL): When the application requires advertisement using R(SEL) , use a 100 kΩ, ±1% resistor.
R(PCTRL): If PCTRL will be pulled low with an external device then it can be connected to VAUX using a 220
kΩ, ±1% resistor. If PCTRL will always be high then it can be directly connected to VAUX.
R(SLEW): Use a 1 kΩ, ±1% resistor
RG: Use a 10 Ω, ±1% resistor
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9.2.2.2.3 Configurable Components
•
•
•
•
•
•
•
•
•
•
50
C(RX): Choose C(RX) between 200 pF and 600 pF. A 560 pF, 50 V, ±5% COG/NPO ceramic is recommended
for both CC1 and CC2 pins.
Q1: For a 3 A application, an N-Channel MOSFET with RDS(on) in the 10 mΩ range is sufficient. BV(DSS) should
be rated for 30 V for applications delivering 20 V, and 25 V for 15 V applications. For this application, the TI
CSD17579Q3A (SLPS527) NexFET™ is suitable.
RS: TPS25740B OCP set point thresholds are targeted towards a 5 mΩ, ±1% sense resistor. Power
dissipation for RS at 3 A load is approximately 45 mW.
R(DSCG): The minimum value of R(DSCG) is chosen based on the application VBUS (max) and I(DSCGT). For
VBUS (max) = 15 V and I(DSCGT) = 350 mA, RDS(CG(min)) = 42.9 Ω. The size of the external resistor can then be
chosen based on the capacitive load that needs to be discharged and the maximum allowed discharge time
of 265 ms. Typically, a 120 Ω, 0.5 W resistor provides suitable performance.
RF/CF: Not used
C(PDIN): The requirement for C(PDIN) is 10 µF maximum. A 6.8 µF, 25 V, ±10% X5R or X7R ceramic capacitor
is suitable for most applications.
D(VBUS): D(VBUS) provides reverse transient protection during large transient conditions when inductive loads
are present. A Schottky diode with a V(RRM) rating of 30 V in a SMA package such as the B340A-13-F
provides suitable reverse voltage clamping performance.
C(SLEW): To achieve a slew rate from zero to 5 V of less than 30 mV / µs using the typical GDNG current of 20
µA then C(SLEW) (nF) > 20 µA / 30 mV / µs = 0.67 nF be used. Choosing C(SLEW) = 10 nF yields a ramp rate of
2 mV / µs.
R(FBL1)/R(FBL2)/R(FBL3): In this design example, R(FBU) = 49.9 kΩ and R(FBL) = 9.53 kΩ. The feedback error
amplifier VREF = 0.8 V. Using the equations for R(FBL2) (Equation 5 and Equation 6) provide a calculated value
of 9.9 kΩ and a selected value of 9.76 kΩ. In similar fashion for R(FBL1), a calculated value of 6.74 kΩ and a
selected value of 6.65 kΩ is provided. Lastly for R(FBL3), the calculated value is 8.1 kΩ with a selected value of
8.06 kΩ.
C(SLU)/C(SLL): The value of C(SLU) is calculated based on the desired 95% slew rate using Equation 13 and
Equation 14. Choose a 22 nF capacitor for C(SLU). Choose a 100 nF capacitor for C(SLL).
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9.2.2.3 Application Curves
VBUS
VBUS
VGDNG
VGDNG
VCTL1
VCTL1
VCTL2
VCTL2
No Load
No Load
Figure 61. VBUS 5 V – 9 V Transition
Figure 62. VBUS 9 V – 5 V Transition
VBUS
VBUS
VGDNG
VGDNG
VCTL1
VCTL1
VCTL2
VCTL2
No Load
No Load
Figure 63. VBUS 9 V – 15 V Transition
Figure 64. VBUS 15 V – 9 V Transition
VBUS
VGDNG
VBUS
VGDNG
VCTL1
VCTL1
VCTL2
VCTL2
No Load
No Load
Figure 65. VBUS 5 V – 15 V Transition
Figure 66. VBUS 15 V – 5 V Transition
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9.3 System Examples
9.3.1 D/C Power Source (Power Hub)
In this system design example, the P(SEL) is configured such that P(SEL) = 93 W, so 5 V, 9 V, and 15 V are offered
at a maximum of 5 A, while 20 V is offered at a maximum of 4.64 A. The over-current protection (OCP) trip point
is set just above 5 A.
REN
24V Bulk Power
R(UVLO1)
3 x REN
R(UVLO2)
CSD17578Q3A (2x)
C(PDIN)
C(RX)
VDD
HIPWR
VTX
ENSRC
C(VTX)
220kŸ
VAUX
PCTRL
TPS25740B
C(VAUX)
C(DVDD)
CTL1
CTL2
CTL3
CC1
CC2
AGND
GND
VBUS
DSCG
ISNS
GDNS
GD
Slew Control
SHIELD
C(RX)
R(DSCG)
RG
RG
C(SLEW) R(SLEW)
CC3 RC2
RC3
Type-C
Receptacle
R(PG)
PSEL
C(VDD)
PGND
ILIM
PGOOD
GDNG
TRK
AGND
VDD
DVDD
RC1
R(TRK)
LDRV
COMP
RC4
CC1
TPS40170
COUT
FB
CC2
HDRV
SW
VBP
SS
C(VBP)
C(SS)
R(ILIM)
R(RT)
VPWR
EN
RT
C(BOOT)
VIN
BOOT
SYNC
CIN
UVLO
M/S
Copyright © 2016, Texas Instruments Incorporated
Figure 67. Power Hub Concept (Provider only)
This power hub circuit takes a 24 V input and produces a regulated output voltage. The over-current protection
feature in the TPS25740B is not used; the ISNS and VBUS pins are connected directly. Instead R(ILIM) is chosen
to set the current limit of the TPS40170 synchronous PWM buck controller. If the current limit trips, the GD pin of
the TPS25740B is pulled low by the PGOOD pin of the TPS40170, which causes the power-path switch to be
opened. Other fault conditions may also pull PGOOD low, but the slew rate of the voltage transition should be
controlled as in one of the examples given above (Figure 44, Figure 45, or Figure 47).
VDD on the TPS25740B is grounded, if there is a suitable power supply available in the system the TPS25740B
operates more efficiently if it is connected to VDD since V(VPWR) > V(VDD). See Figure 70 for an example.
52
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System Examples (continued)
9.3.2 A/C Power Source (Wall Adapter)
T1
C(VAUX)
C(PDIN)
C(RX)
R(DSCG)
DSCG
VBUS
GND
AGND
HIPWR
PSEL
ENSRC
DVDD
CIO
CC1
CC2
TPS25740B
CTL1
CTL2
CTL3
C(DVDD)
P
D-
VDD
C(VTX)
TL431
VPWR
CIZ
RCS
GND
R(FBL2)
FB
RF6
RF5
R(FBL3)
ROB
RLC
R(FBU)
VB
CS
R(FBL)
DRV
P
PCTRL
VAUX
GD
VTX
M1
VS
GDNS
ISNS
C(VPWR)
CDD1
CDD1
HV
UCC28740
GDNG C
(SLEW) R(SLEW)
VDD
LDO
RS2
RS1
DVC
RG
100 Ÿ
COUT
R(FBL1)
±
T1
RS
DS
P
P
Type-C
Plug
VBUS
D+
CSD17579Q3A
CB2
CB1
+
From AC Mains
In this system design example, the PSEL pin is configured such that P(SEL) = 36 W, and 5 V, 9 V are offered at a
maximum of 3 A while 15 V is offered at a maximum of 2.4 A and 20 V is offered at a maximum of 1.8A. The
overcurrent protection (OCP) trip point is set just above 3 A. VDD on the TPS25740B is grounded, if there is a
suitable power supply available in the system the TPS25740B operates more efficiently if it is connected to VDD
since V(VPWR) > V(VDD).
Port Status
indicator
100 NŸ
Copyright © 2016, Texas Instruments Incorporated
Figure 68. Adapter Provider Concept
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System Examples (continued)
9.3.3 Dual-Port A/C Power Source (Wall Adaptor)
In this system design example, the PSEL pin is configured such that P(SEL) = 36 W, and 5 V, 9 V, 12 V are
offered at a maximum of 3 A while 15 V is offered at a maximum of 2.4A. The over-current protection (OCP) trip
point is set just above 3 A.
The ENSRC pin from one TPS25740B is attached to the PCTRL pin on the other TPS25740B. When one port is
not active (no UFP attached through the receptacle) its ENSRC pin is left high-z so the PCTRL pin on the other
port is pulled high. This allows the adaptor to provide up to the full 36 W on a single port if a single UFP is
attached. If two UFP’s are attached (one to each port) then each port only offers current that would reach a
maximum of 18 W. So each port is allocated half of the overall power when each port has a UFP attached.
RS
C(PDIN)
VBUS
DSCG
ISNS
GDNS
GDNG
VDD
VBUS
D+
Type-C
receptacle
#2
D-
C(RX)
R(DSCG)
10Ÿ
C(SLEW)
R(SLEW)
10Ÿ
C(PDIN)
RS
CC1
CC2
DVDD
PSEL
VTX
HIPWR
GD
VAUX
TPS25740B
GND
AGND
VPWR
C(RX)
C(RX)
GND
AGND
C(DVDD)
CSD17578Q3A (2X)
CTL1
CTL2
CTL3
ENSRC
PCTRL
220NŸ
D-
R(DSCG)
VBUS
DSCG
ISNS
DVDD
PSEL
C(VTX)
100Ÿ
5V, 9V, 12V, or 15V
Type-C
receptacle
#1
100NŸ
C(AUX)
DC/DC
Buck
Circuit
(36W)
VBUS
D+
CC1
CC2
TPS25740B
GD
VTX
HIPWR
VDD
CTL1
CTL2
CTL3
ENSRC
PCTRL
220NŸ
10Ÿ
GDNS
GDNG
24V
VAUX
AC/DC
Fly-Back
Circuit
(36W)
VPWR
R(SLEW)
10Ÿ
100Ÿ
CSD17578Q3A (2x)
C(RX)
5V, 9V, 12V, or 15V
C(SLEW)
DC/DC
Buck
Circuit
(36W)
100NŸ
C(AUX)
C(VTX)
C(DVDD)
Copyright © 2016, Texas Instruments Incorporated
Figure 69. Dual-Port Adapter Provider Concept
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System Examples (continued)
9.3.4 D/C Power Source (Power Hub with 3.3 V Rail)
In Figure 70, an LDO that outputs at least I(SUPP) at 3.3 V or 5 V is added to the power hub concept, and the
DVDD pin is used to enable the buck regulator since it is active high. This implementation is more power efficient
than the one in Figure 67.
24V Bulk Power
3.3V
LDO
C(PDIN)
DSCG
VDD
VBUS
C(RX)
C(SLEW)
R(DSCG)
R(SLEW)
SHIELD
R(PG)
GD
HIPWR
GND
AGND
C(VTX)
VTX
VAUX
220NŸ
C(VAUX)
C(DVDD)
ENSRC
TPS25740B
DVDD
PSEL
PCTRL
CTL1
CTL2
CTL3
Slew
Control
CC1
CC2
R(SEL)
C(VDD)
PGND
ILIM
PGOOD
ISNS
R(TRK)
GDNS
RC1
LDRV
C(VPWR)
CC1
COMP
TRK
AGND
VDD
GDNG
TPS40170
VPWR
FB
CC1
CC3 RC2
HDRV
SW
VBP
SS
RC3
C(SS)
Type-C
Plug
RG
RC4
RT
COUT
R(RT)
CSD17579Q3A
C(BOOT)
EN
R(ILIM)
SYNC
C(VBP)
UVLO
VIN
BOOT
M/S
CIN
R(UVLO1)
R(UVLO)
Copyright © 2016, Texas Instruments Incorporated
Figure 70. Power Hub Concept (Provider only)
10 Power Supply Recommendations
10.1 VDD
The recommended VDD supply voltage range is 3 V to 5.5 V. The device requires approximately 2 mA (I(SUPP))
typical in normal operating mode and below 10 µA in sleep mode. If the VDD supply is not used, then it may be
connected to AGND/GND.
10.2 VPWR
The recommended VPWR supply voltage range is 0 V to 25 V. The device requires approximately 2 mA (I(SUPP))
typical in normal operating mode and below 10 µA in sleep mode.
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11 Layout
11.1 Port Current Kelvin Sensing
24
13
23
DVDD
VBUS
GDNG
16
22
15
14
21
GD
PCTRL
VPWR
VAUX
ISNS
20
17
19
AGND
VDD
18
Figure 71 provides a routing example for accurate current sensing for the overcurrent protection feature. The
sense amplifier measurement occurs between the ISNS and VBUS pins of the device. Improper connection of
these pins can result in poor OCP performance.
PSEL
12
ENSRC
11
N/C
N/C
10
GDNS
CTL3
8
DSCG
CTL2
7
CC2
GND
HIPWR
CTL1
3
5
6
CC1
4
VTX
1
2
PAD
9
CF
RF
Top Trace
Top Plane
Bottom Trace/ Plane
RS
Q1 Source
VIA
VBUS
Current Flow
Figure 71. Kelvin Sense Layout Example
11.2 Layout Guidelines
11.2.1 Power Pin Bypass Capacitors
• C(VPWR): Place close to pin 20 (VPWR) and connect with low inductance traces and vias according to
Figure 72.
• C(VDD): Place close to pin 17 (VDD) and connect with low inductance traces and vias according to Figure 72.
• C(DVDD): Place close to pin 13 (DVDD) and connect with low inductance traces and vias according to
Figure 72.
• C(VAUX): Place close to pin 16 (VAUX) and connect with low inductance traces and vias according to
Figure 72.
• C(VTX): Place close to pin 1 (VTX) and connect with low inductance traces and vias according to Figure 72.
11.2.2 Supporting Components
• C(RX): Place C(RX1) and C(RX2) in line with the CC1 and CC2 traces as shown in Figure 25. These should be
placed within one inch from the Type C connector. Minimize stubs and tees from on the trace routes.
• Q1: Place Q1 in a manner such that power flows uninterrupted from Q1 drain to the Type C connector VBUS
connections. Provide adequate copper plane from Q1 drain and source to the interconnecting circuits.
• RS: Place RS as shown in Figure 72 to facilitate uninterrupted power flow to the Type C connector. Orient RS
for optimal Kelvin sense connection/routing back to the TPS25740B. In high current applications where the
56
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Product Folder Links: TPS25740B
TPS25740B
www.ti.com
SLVSDR6C – JUNE 2017 – REVISED MARCH 2018
Layout Guidelines (continued)
•
•
•
•
•
•
power dissipation is over 250 mW, provide an adequate copper feed to the pads of RS.
RG: Place RG near Q1 as shown in Figure 72. Minimize stray leakage paths as the GDNG sourcing current
could be affected.
R(SLEW)/C(SLEW): Place R(SLEW) and C(SLEW) near RG as shown in Figure 72.
R(DSCG): Place on top of the VBUS copper route and connect to the DSCG pin with a 15 mil trace.
RF/CF: When required, place RF and CF as shown in Figure 72 to facilitate the Kelvin sense connection back
to the device.
C(VBUS)/D(VBUS): Place C(VBUS) and D(VBUS) within one inch of the Type C connector and connect them to VBUS
and GND using adequate copper shapes.
R(SEL)/R(PCTRL): Place R(SEL) and R(PCTRL) near the device.
11.3 Layout Example
CVAUX
CVDD
GND
RPCNTRL
12
ENSRC
11
N/C
N/C
10
GDNS
CTL3
8
DSCG
CTL2
7
PAD
CTL1
CRX2
5
6
CC2
3
4
CC1
VTX
1
To DC/DC
Converter
9
GND
CRX1
CC2
CC1
RDSCG
CF
CVTX
2
GND
HIPWR
G
4
RSEL
PSEL
RG
RF
CDVDD
RS
Top Trace
DVBUS
CPDIN
VBUS
USB Type-C Plug
24
13
23
DVDD
VBUS
GDNG
16
22
15
14
21
GD
PCTRL
VPWR
VAUX
D
18
ISNS
20
17
D
S
3
19
AGND
VDD
D
S
2
S
Q1
1
CVPWR
5
CSLEW
6
RSLEW
7
D
VOUT
8
DC/DC
Converter
The basic component placement and layout is provided in Figure 72. This layout represents the circuit shown in
Figure 38. The layout for other power configurations will vary slightly from that shown below.
Top Plane
Bottom Trace/ Plane
VIA
Figure 72. Example Layout
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Product Folder Links: TPS25740B
57
TPS25740B
SLVSDR6C – JUNE 2017 – REVISED MARCH 2018
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
USB PD and USB Type-C specifications available at: http://www.usb.org/home
TPS25740BEVM-741 EVM User's Guide
TPS25740B Design Calculator Tool
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
Type-C is a trademark of USB Implementers Forum.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
58
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Product Folder Links: TPS25740B
PACKAGE OPTION ADDENDUM
www.ti.com
12-Dec-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS25740BRGER
NRND
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
25740B
TPS25740BRGET
NRND
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
25740B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Dec-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS25740BRGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
TPS25740BRGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS25740BRGER
VQFN
RGE
24
3000
367.0
367.0
35.0
TPS25740BRGET
VQFN
RGE
24
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
2.5
SYMM
1
PIN 1 ID
(OPTIONAL)
18
24X 0.30
0.18
24
19
SYMM
24X 0.48
0.28
0.1
0.05
C A B
C
4219016 / A 08/2017
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
(
2.7)
19
24
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
TYP
6
13
(R0.05)
12
7
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
19
24
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
(R0.05) TYP
METAL
TYP
25
7
SYMM
12
(0.694)
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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