Texas Instruments | TLK2711-SP 1.6-Gbps to 2.5-Gbps Class V Transceiver (Rev. P) | Datasheet | Texas Instruments TLK2711-SP 1.6-Gbps to 2.5-Gbps Class V Transceiver (Rev. P) Datasheet

Texas Instruments TLK2711-SP 1.6-Gbps to 2.5-Gbps Class V Transceiver (Rev. P) Datasheet
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TLK2711-SP
SGLS307P – JULY 2006 – REVISED FEBRUARY 2018
TLK2711-SP 1.6-Gbps to 2.5-Gbps Class V Transceiver
1 Features
3 Description
•
The TLK2711-SP is a member of the WizardLink
transceiver family of multigigabit transceivers,
intended for use in ultra-high-speed bidirectional
point-to-point data transmission systems. The
TLK2711-SP supports an effective serial interface
speed of 1.6 Gbps to 2.5 Gbps, providing up to
2 Gbps of data bandwidth.
External Component Interconnection
1 nF−10 nF†
1 nF−10 nF†
Recommended use of 0.01-µF
capacitor per VDD terminal
0.01 µF
5 Ω at 100 MHz
RXD0
RXD3
TXD5
4
48
RXD4
GND
5
47
RXD5
TXD6
6
46
RXD6
TXD7
7
45
GND
GTX_CLK
8
44
RXD7
VDD
9
43
RX_CLK
TXD8
10
42
RXD8
TXD9
11
41
RXD9
TXD10
12
40
VDD
GND
13
39
RXD10
TXD11
14
38
RXD11
TXD12
15
37
RXD12
TXD13
16
36
RXD13
GND
49
DINRXN
VDD
3
PRE
50
TXD4
GND
DINRXP
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
51
2
VDDA
1
GND
VDD
TXD3
GND
GND
GND
RXD14
RXD15
GND
RKLSB
17
35
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
RKMSB
GND
†
RXD1
RXD2
0.01 µF 0.01 µF 0.01 µF
0.01 µF
TESTEN
VDD
Point-to-Point High-Speed I/O
Data Acquisition
Data Processing
These units are intended for engineering evaluation only.
They are processed to a non-compliant flow (for example, no
burn-in, and so forth) and are tested to temperature rating of
25°C only. These units are not suitable for qualification,
production, radiation testing, or flight use. Parts are not
warranted for performance on full MIL specified temperature
range of –55°C to 125°C or operating life.
1 nF−10 nF†
1 nF−10 nF†
PRBSEN
(1)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VDDA
•
•
•
BODY SIZE (NOM)
13.97 mm × 13.97 mm
LCKREFN
2 Applications
PACKAGE
CFP (68)
DOUTTXN
•
•
•
PART NUMBER
TLK2711-SP
TKLSB
VDD
ENABLE
•
Device Information(1)
TXD0
•
•
•
•
GND
•
DOUTTXP
•
TXD2
TXD1
•
The primary application of the TLK2711-SP is to
provide high-speed I/O data channels for point-topoint baseband data transmission over controlled
impedance media of approximately 50 Ω. The
transmission media can be printed circuit board,
copper cables, or fiber-optic cable. The maximum
rate and distance of data transfer is dependent upon
the attenuation characteristics of the media and the
noise coupling to the environment.
GND
•
•
TXD14
•
•
1.6 to 2.5-Gbps (Gigabits Per Second)
Serializer/Deserializer
Hot-Plug Protection
High-Performance 68-Pin Ceramic Quad Flat
Pack Package (HFG)
Low-Power Operation
Programmable Preemphasis Levels on Serial
Output
Interfaces to Backplane, Copper Cables, or
Optical Converters
On-Chip 8-Bit/10-Bit Encoding/Decoding, Comma
Detect
On-Chip PLL Provides Clock Synthesis From
Low-Speed Reference
Low Power: < 500 mW
3-V Tolerance on Parallel Data Input Signals
16-Bit Parallel TTL-Compatible Data Interface
Ideal for High-Speed Backplane Interconnect and
Point-to-Point Data Link
Military Temperature Range (–55°C to 125°C
Tcase)
Loss of Signal (LOS) Detection
Integrated 50-Ω Termination Resistors on RX
Engineering Evaluation (/EM) Samples are
Available (1)
TXD15
TKMSB
LOOPEN
1
For ac coupling
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLK2711-SP
SGLS307P – JULY 2006 – REVISED FEBRUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
1
1
1
2
4
5
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 8
Thermal Information .................................................. 8
TTL Input Electrical Characteristics .......................... 8
Transmitter/Receiver Electrical Characteristics ........ 9
Reference Clock (TXCLK) Timing Requirements ... 10
TTL Output Switching Characteristics..................... 10
Typical Characteristics ............................................ 12
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 20
9
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application .................................................. 22
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision O (March 2016) to Revision P
Page
•
Changed column header of Table 4 indicating correct order of receive data bus bits......................................................... 17
•
Added Receiving Notification of Documentation Updates section ....................................................................................... 25
Changes from Revision N (December 2015) to Revision O
•
Page
Changed reference to table note (2) Internal 10-kΩ pulldown for TKLSB and TKMSB ......................................................... 6
Changes from Revision M (October 2014) to Revision N
Page
•
Updated the frequency range of TXCLK ............................................................................................................................... 6
•
Updated Handling Ratings table to an ESD Ratings table and moved Tstg to the Absolute Maximum Ratings table............ 7
•
Added Community Resources ............................................................................................................................................. 25
Changes from Revision L (August 2014) to Revision M
Page
•
Updated Power-On Reset description .................................................................................................................................. 18
•
Removed option 2 from Power-On Reset ........................................................................................................................... 19
Changes from Revision K (July 2014) to Revision L
•
2
Page
Updated Power-On/Reset Timing Diagram options ............................................................................................................. 19
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SGLS307P – JULY 2006 – REVISED FEBRUARY 2018
Changes from Revision J (May 2014) to Revision K
Page
•
Updated pin description for ENABLE ..................................................................................................................................... 5
•
Updated pin voltages in Absolute Maximum Ratings ............................................................................................................. 7
•
Added more information to Power-On Reset detailing two power-on/reset timing options ................................................. 18
Changes from Revision I (January 2014) to Revision J
Page
•
Changed format to meet latest data sheet standards; added new sections and moved existing sections ........................... 1
•
Changed Description .............................................................................................................................................................. 4
•
Changed paragraph for LCKREFN in Description (continued)............................................................................................... 4
•
Changed Description of LCKREFN in ................................................................................................................................... 5
•
Changed Power-On Reset section ...................................................................................................................................... 18
Changes from Revision H (December 2013) to Revision I
Page
•
Added /EM bullet to Features ................................................................................................................................................ 1
•
Deleted Ordering Information table ...................................................................................................................................... 13
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5 Description (continued)
This device can also be used to replace parallel data transmission architectures by providing a reduction in the
number of traces, connector pins, and transmit/receive pins. Parallel data loaded into the transmitter is delivered
to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or
an optical link. It is then reconstructed into its original parallel format. It offers significant power and cost savings
over parallel solutions, as well as scalability for higher data rates in the future.
The TLK2711-SP performs parallel-to-serial and serial-to-parallel data conversion. The clock extraction functions
as a physical layer (PHY) interface device. The serial transceiver interface operates at a maximum speed of 2.5
Gbps. The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (TXCLK). The
16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8b/10b) encoding format. The resulting
20-bit word is then transmitted differentially at 20× the reference clock (TXCLK) rate. The receiver section
performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data
to the recovered clock (RXCLK). It then decodes the 20-bit wide data using the 8-bit/10-bit decoding format
resulting in 16 bits of parallel data at the receive data pins (RXD0–RXD15). The outcome is an effective data
payload of 1.28 to 2 Gbps (16 bits data × the frequency).
The TLK2711-SP is available in a 68-pin ceramic nonconductive tie-bar package (HFG).
NOTE
The errata noted in the commercial TLK2711 device titled Errata to the TLK2711, 1.6-to2.7 GBPS Transceiver Data Sheet– PLL False Lock Problem does not apply to the
TLK2711-SP device. The TLK2711-SP is functionally equivalent to the TLK2711A
commercial device.
The TLK2711-SP provides an internal loopback capability for self-test purposes. Serial data from the serializer is
passed directly to the deserializer, providing the protocol device with a functional self-check of the physical
interface.
The TLK2711-SP has a LOS detection circuit for conditions where the incoming signal no longer has a sufficient
voltage amplitude to keep the clock recovery circuit in lock.
The TLK2711-SP allows users to implement redundant ports by connecting receive data bus pins from two
TLK2711-SP devices together. Asserting the LCKREFN to a low state causes the receive data bus pins (RXD0 RXD15, RXCLK, RKLSB, and RKMSB) to go to a high-impedance state if device is enabled (ENABLE = H). This
places the device in a transmit-only mode, because the receiver is not tracking the data. LCKREFN must be deasserted to a high state during power-on reset (see Power-On Reset section). If the device is disabled (ENABLE
= L), then RKMSB will output the status of the LOS detector (active low = LOS ). All other receive outputs will
remain high-impedance.
The TLK2711-SP I/Os are 3-V compatible. The TLK2711-SP is characterized for operation from –55°C to 125°C
Tcase.
The TLK2711-SP is designed to be hot-plug capable. An on-chip power-on reset circuit holds the RXCLK low,
and goes to high impedance on the parallel-side output signal pins, as well as TXP and TXN during power up.
4
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SGLS307P – JULY 2006 – REVISED FEBRUARY 2018
6 Pin Configuration and Functions
RXD1
RXD2
RXD0
DINRXN
GND
GND
DINRXP
VDDA
VDDA
PRE
GND
DOUTTXP
DOUTTXN
TXD0
GND
TXD2
TXD1
HFG Package
68-Pin CFP
Top View
VDD
1
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
51
TXD3
2
50
VDD
TXD4
3
49
RXD3
TXD5
4
48
RXD4
GND
5
47
RXD5
TXD6
6
46
RXD6
TXD7
7
45
GND
GTX_CLK
8
44
RXD7
VDD
9
43
RX_CLK
TXD8
10
42
RXD8
TXD9
11
41
RXD9
TXD10
12
40
VDD
GND
13
39
RXD10
TXD11
14
38
RXD11
TXD12
15
37
RXD12
TXD13
16
36
RXD13
GND
GND
RXD15
RXD14
RKLSB
RKMSB
GND
TESTEN
PRBSEN
LCKREFN
TKLSB
VDD
ENABLE
TXD15
TKMSB
LOOPEN
GND
17
35
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
TXD14
GND
GND
Pin Functions
PIN
NAME
DOUTTXN
DOUTTXP
ENABLE
GND
LCKREFN
NO.
I/O
DESCRIPTION
63
64
O
Serial transmit outputs. TXP and TXN are differential serial outputs that interface to copper or an
optical I/F module. These pins transmit NRZ data at a rate of 20× the TXCLK value. TXP and TXN
are put in a high-impedance state when LOOPEN is high and are active when LOOPEN is low.
During power-on reset, these pins are high impedance.
25
(1)
Device enable. When this pin is held low, the device is placed in power-down mode. Only the signal
detect circuit on the serial receive pair is active. When in power-down mode, RKMSB will output the
status of signal detect circuit (LOS). When asserted high while the device is in power-down mode,
the transceiver is reset before beginning normal operation.
—
Analog and digital logic ground. Provides a ground for the logic circuits, digital I/O buffers, and the
high-speed analog circuits.
5, 13, 17, 19,
29, 34, 35,
45, 51, 55,
58, 62, 65
26
I
I (1)
Lock to reference. When LCKREFN is low, the receiver clock is frequency locked to TXCLK. This
places the device in a transmit-only mode since the receiver is not tracking the data. When
LCKREFN is asserted low, the receive data bus pins (RXD0 through RXD15, RXCLK, RKLSB, and
RKMSB) are in a high-impedance state if device is enabled (ENABLE = H). If device is disabled
(ENABLE = L), then RKMSB will output the status of the LOS detector (active low = LOS). All other
receive outputs will remain high-impedance.
When LCKREFN is deasserted high, the receiver is locked to the received data stream. LCKREFN
must be deasserted to a high state during power-on reset. See Power-On Reset.
(1)
Internal 10-kΩ pullup.
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
(2)
Loop enable. When LOOPEN is active high, the internal loopback path is activated. The transmitted
serial data is directly routed internally to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The TXP and TXN outputs are held in a highimpedance state during the loopback test. LOOPEN is held low during standard operational state,
with external serial outputs and inputs active.
LOOPEN
22
I
PRE
60
I (2)
Preemphasis control. Selects the amount of preemphasis to be added to the high-speed serial
output drivers. Left low or unconnected, 5% preemphasis is added. Pulled high, 20% preemphasis
is added.
PRBSEN
27
I (2)
PRBS test enable. When asserted high, results of pseudo-random bit stream (PRBS) tests can be
monitored on the RKLSB pin. A high on RKLSB indicates that valid PRBS is being received.
O
K-code indicator/PRBS test results. When RKLSB is asserted high, an 8-bit/10-bit K code was
received and is indicated by data bits RXD0 through RXD7. When RKLSB is asserted low, an 8bit/10-bit D code is received and is presented on data bits RXD0 through RXD7. When PRBSEN is
asserted high, this pin is used to indicate status of the PRBS test results (high = pass).
RKLSB
30
RKMSB
31
O
K-code indicator. When RKMSB is asserted high an 8-bit/10-bit K code was received and is
indicated by data bits RXD8 through RXD15. When RKMSB is asserted low an 8-bit/10-bit D code
was received and is presented on data bits RXD8 through RXD15. If the differential signal on RXN
and RXP drops below 200 mV, RXD0–RXD15, RKLSB, and RKMSB are all asserted high. When
device is disabled (ENABLE = L), RKMSB will output the status of LOS. Active low = LOS detected.
RXCLK
RX_CLK
43
O
Recovered clock. Output clock that is synchronized to RXD0 through RXD9, RKLSB, and RKMSB.
RXCLK is the recovered serial data rate clock divided by 20. RXCLK is held low during power-on
reset.
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
RXD8
RXD9
RXD10
RXD11
RXD12
RXD13
RXD14
RXD15
54
53
52
49
48
47
46
44
42
41
39
38
37
36
33
32
O
Receive data bus. These outputs carry 16-bit parallel data output from the transceiver to the
protocol device, synchronized to RXCLK. The data is valid on the rising edge of RXCLK as shown
in Figure 10. These pins are in high-impedance state during power-on reset.
DINRXN
DINRXP
56
57
I
Serial receive inputs. RXP and RXN together are the differential serial input interface from a copper
or an optical I/F module.
TESTEN
28
I (2)
Test mode enable. This pin should be left unconnected or tied low.
TKLSB
23
I (2)
K-code generator (LSB). When TKLSB is high, an 8-bit/10-bit K code is transmitted as controlled by
data bits TXD0 through TXD7. When TKLSB is low, an 8-bit/10-bit D code is transmitted as
controlled by data bits TXD0 through TXD7.
TKMSB
21
I (2)
K-code generator (MSB). When TKMSB is high, an 8-bit/10-bit K code is transmitted as controlled
by data bits TXD8 through TXD15. When TKMSB is low, an 8-bit/10-bit D code is transmitted as
controlled by data bits TXD8 through TXD15.
TXCLK
GTX_CLK
8
I
Reference clock. TXCLK is a continuous external input clock that synchronizes the transmitter
interface signals TKMSB, TKLSB, and TXD0–TXD15. The frequency range of TXCLK is 80 to 125
MHz. The transmitter uses the rising edge of this clock to register the 16-bit input data TXD0
through TXD15 for serialization.
(2)
6
Internal 10-kΩ pulldown.
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Pin Functions (continued)
PIN
NAME
NO.
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
TXD8
TXD9
TXD10
TXD11
TXD12
TXD13
TXD14
TXD15
66
67
68
2
3
4
6
7
10
11
12
14
15
16
18
20
1, 9, 24, 40,
50
VDD
VDDA
I/O
DESCRIPTION
I
Transmit data bus. These inputs carry the 16-bit parallel data output from a protocol device to the
transceiver for encoding, serialization, and transmission. This 16-bit parallel data is clocked into the
transceiver on the rising edge of TXCLK as shown in Figure 7.
Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
Analog power. VDDA provides a supply reference for the high-speed analog circuits, receiver, and
transmitter.
59, 61
7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.3
3
V
TXD0 to TXD15, ENABLE, TXCLK, TKMSB, TKLSB,
LOOPEN, PRBSEN, LCKREFN, PRE, TESTEN
–0.3
4
RXD0 to RXD15, RKMSB, RKLSB, RXCLK
–0.3
VDD + 0.35
DINRXP, DINRXN, DOUTTXP, DOUTTXN
–0.35
VDDA + 0.35
Supply voltage (2)
VDD
Voltage
Maximum cumulative exposure of unpowered receiver to external inputs (3)
V
10
hours
TC
Characterized case operating temperature
–55
125
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are stated with respect to network ground.
The TLK2711-SP shows no performance degradation when an external powered transmitter sends a signal to an unpowered receiver
for short periods of time (up to 10 hours of lifetime of the device). Characterization was performed using maximum VOD, minimum
frequency and typical VCM from recommended operating conditions for the specified period of time.
7.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
Supply voltage
ICC
Supply current
PD
Power dissipation
Frequency range 1.6 Gbps to 2 Gbps
Frequency range 1.6 Gbps to 2.5 Gbps
MIN
NOM
MAX
2.375
2.5
2.625
2.5
2.6
2.7
Frequency = 1.6 Gbps, PRBS pattern
110
Frequency = 2.5 Gbps, PRBS pattern
160
Frequency = 1.6 Gbps, PRBS pattern
275
Frequency = 2.5 Gbps, PRBS pattern
400
V
mA
mW
Frequency = 2.5 Gbps, PRBS pattern
550
Shutdown current
Enable = 0, VDDA, VDD pins, VDD = MAX
PLL startup lock time
VDD, VDDC = 2.375 V
3
mA
0.1
Data acquisition time
Tc
UNIT
0.4
1024
Operating case temperature
ms
bits
–55
125
°C
7.4 Thermal Information
see
(1)
TLK2711-SP
THERMAL METRIC (2)
HFG (CFP)
UNIT
68 PINS
RθJA
Junction-to-ambient thermal resistance
31.5
°C/W
RθJC
Junction-to-case thermal resistance
2.96
°C/W
(1)
(2)
This CFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on the bottom of the package.
To efficiently remove heat and provide a low-impedance ground path, a thermal land is required on the surface of the PCB directly
underneath the body of the package. During normal surface mount flow solder operations, the heat pad on the underside of the package
is soldered to this thermal land creating an efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it
that provide a thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat removal. TI
typically recommends an 11.9-mm × 11.9-mm board-mount thermal pad with a 4.2-mm × 4.2-mm solder mask defined pad attach
opening. This allows maximum area for thermal dissipation, while allowing leads pad to solder pad clearance. A sufficient quantity of
thermal or electrical vias must be included to keep the device within Recommended Operating Conditions. This pad must be electrically
ground potential.
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 TTL Input Electrical Characteristics
over recommended operating conditions (unless otherwise noted),
TTL signals: TXD0–TXD15, TXCLK, LOOPEN, LCKREFN, ENABLE, PRBS_EN, TKLSB, TKMSB, PRE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.7
UNIT
VIH
High-level input voltage
See Figure 1
VIL
Low-level input voltage
See Figure 1
0.8
V
IIH
Input high current
VDD = MAX, VIN = 2 V
40
µA
IIL
Input low current
VDD = MAX, VIN = 0.4 V
CI
Receiver input capacitance
tr
Rise time, TXCLK, TKMSB, TKLSB, TXD0 to TXD15
0.7 to 1.9 V, C = 5 pF,
See Figure 1
tf
Fall time, TXCLK, TKMSB, TKLSB, TXD0 to TXD15
1.9 to 0.7 V, C = 5 pF,
See Figure 1
tsu
th
(1)
8
TXD0 to TXD15, TKMSB, TKLSB setup to ↑ TXCLK
TXD, TKMSB, TKLSB hold to ↑ TXCLKS
V
–40
µA
6
pF
1
ns
1
ns
See Figure 1
(1)
1.5
ns
See Figure 1
(1)
0.4
ns
Nonproduction tested parameters.
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7.6 Transmitter/Receiver Electrical Characteristics
PARAMETER
VOD(p)
VOD(pp_p)
Preemphasis VOD, direct,
VOD(p) = |VTXP – VTXN|
Differential, peak-to-peak output voltage with
preemphasis
MIN
TYP
MAX
Rt = 50 Ω, PREM = high, DC coupled,
see Figure 3
TEST CONDITIONS
655
800
1100
Rt = 50 Ω, PREM = low, DC coupled,
see Figure 3
590
740
1050
Rt = 50 Ω, PREM = high, DC coupled,
see Figure 3
1310
1600
2200
Rt = 50 Ω, PREM = low, DC coupled,
see Figure 3
1180
1480
2100
UNIT
mV
mVp-p
VOD(d)
Deemphais output voltage,
|VTXP – VTXN|
Rt = 50 Ω, DC coupled, see Figure 3
540
650
950
mV
VOD(pp_d)
Differential, peak-to-peak output voltage with
deemphasis
Rt = 50 Ω, DC coupled, see Figure 3
1080
1300
1900
mVp-p
V(cmt)
Transmit common mode voltage range, (VTXP
+ VTXN) / 2
Rt = 50 Ω, see Figure 3
1000
1250
1450
mV
VID
Receiver input voltage differential,
|VRXP – VRXN|
See
1600
mV
V(cmr)
Receiver common mode voltage range, (VRXP
See
+ VRXN) / 2
2250
mV
Ilkg
Receiver input leakage current
10
µA
CI
Receiver input capacitance
(1)
220
(1)
1000
1250
–10
4
pF
Differential output jitter at 2.5 Gbps,
Random + deterministic, PRBS pattern
0.28
Differential output jitter at 1.6 Gbps,
Random + deterministic, PRBS pattern
0.32
Differential output signal rise, fall time
(20% to 80%)
RL = 50 Ω, CL = 5 pF, see Figure 3
150
Jitter tolerance eye closure
Differential input jitter, random + deterministic,
PRBS pattern at zero crossing (1)
0.4
latency)
Tx latency
See Figure 8
34
38
bits
td(Rx latency)
Rx latency
See Figure 11
76
107
bits
Serial data total jitter (peak to peak)
tt, tf
td(Tx
(1)
(2)
UI (2)
ps
UI
Nonproduction tested parameters.
UI is the time interval of one serialized bit.
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7.7 Reference Clock (TXCLK) Timing Requirements
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Frequency
MIN
Receiver data rate / 20
NOM
MAX
UNIT
–100
100
ppm
Frequency tolerance
–100
100
ppm
Duty cycle
40%
Jitter
50%
60%
Peak to peak
40
ps
MAX
UNIT
7.8 TTL Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
2.1
2.3
VOH
High-level output voltage
IOH = –2 mA, VDD = MIN
VOL
Low-level output voltage
IOL = 2 mA, VDD = MIN
tr(slew)
Slew rate (rising), magnitude of RXCLK, RKLSB,
RKMSB, RXD0 to RXD15
0.8 V to 2 V, C = 5 pF, see Figure 2
0.5
V/ns
tf(slew)
Slew rate (falling), magnitude of RXCLK, RKLSB,
RKMSB, RXD0 to RXD15
0.8 V to 2 V, C = 5 pF, see Figure 2
0.5
V/ns
tsu
RXD0 to RXD15, RKMSB, RKLSB setup to ↑
RXCLK
th
(1)
RXD0 to RXD15, RKMSB, RKLSB hold to ↑ RXCLK
V
0.25
50% voltage swing, TXCLK = 80 MHz,
see Figure 2 (1)
50% voltage swing, TXCLK = 125 MHz,
see Figure 2 (1)
0.5
V
3
ns
2.5
50% voltage swing, TXCLK = 80 MHz,
see Figure 2 (1)
3
50% voltage swing, TXCLK = 125 MHz,
see Figure 2 (1)
2
ns
Nonproduction tested parameters.
3.6 V
2V
TXCLK
0.8 V
0V
tr
tf
3.6 V
2V
TKLSB, TKMSB,
TXD0−TXD15
0.8 V
0V
tr
tsu
tf
th
Figure 1. TTL Data Input Valid Levels for AC Measurements
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2.7 V
2V
RXCLK
0.8 V
0V
tr(slew)
tf(slew)
2.7 V
2V
RKLSB, RKMSB,
RXD0−RXD15
0.8 V
0V
tr(slew)
tsu
tf(slew)
th
Figure 2. TTL Data Output Valid Levels for AC Measurements
VOD(p)
VOD(d)
VOD(pp_d)
0V
VOD(pp_p)
tf
VOD(d)
tr
Bit
Time
Bit
Time
VOD(p)
Figure 3. Differential and Common-Mode Output Voltage
VOD(p)
VOD(d)
VTXN
V(cmt)
VTXP
Bit
Time
Bit
Time
Figure 4. Common-Mode Output Voltage Definitions
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7.9 Typical Characteristics
12
10
Tlife - Years
8
6
4
2
0
100
105
110
115
120
125
130
135
140
145
150
155
Junction Te m pe rature - °C
2.5 GBPS, PRBS = 27 – 1
Figure 5. tlife vs Junction Temperature
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Figure 6. Typical Eye Diagram
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8 Detailed Description
8.1 Overview
The TLK2711-SP is a member of the WizardLink transceiver family of multigigabit transceivers, intended for use
in ultra-high-speed bidirectional point-to-point data transmission systems. The TLK2711-SP supports an effective
serial interface speed of 1.6 Gbps to 2.5 Gbps, providing up to 2 Gbps of data bandwidth.
The following sections describe block-by-block features and operation of the TLK2711-SP transceiver.
8.2 Functional Block Diagram
LOOPEN
PRBSEN
PRBSEN
PRBS
Generator
TXP
10
TXN
10
Parallel to
Serial
BIAS
10
PRE
MUX
TKLSB
9
TKMSB
8b/10b
Encoder
TXD0−TXD15
18 Bit
Register
9
8b/10b
Encoder
2:1
10
MUX
10
Clock
Synthesizer
TXCLK
TESTEN
Controls:
PLL, Bias, RX,
TX
ENABLE
PRBSEN
2:1
MUX
RKLSB
18 Bit
Register
9
RKMSB
PRBS
Verification
PRBSEN
RXCLK
RXD0−RXD15
Interpolator and
Clock Recovery
9
Comma
Detect
and 8b/10b
Decoding
Comma
Detect
and 8b/10b
Decoding
Clock
2:1
MUX
Recovered
Clock
10
1:2
MUX
10
Serial to
Parallel
2:1
MUX
Data
RXP
RXN
10
Signal Detect
(LOS)
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8.3 Feature Description
8.3.1 Transmit Interface
The transmitter interface registers valid incoming 16-bit-wide data (TXD0 to TXD15) on the rising edge of the
TXCLK. The data is then 8-bit/10-bit encoded, serialized, and transmitted sequentially over the differential highspeed I/O channel. The clock multiplier multiplies the reference clock (TXCLK) by a factor of 10×, creating a bit
clock. This internal bit clock is fed to the parallel-to-serial shift register, which transmits data on both the rising
and falling edges of the bit clock, providing a serial data rate that is 20× the reference clock. Data is transmitted
least significant bit (LSB) (TXD0) first.
8.3.2 Transmit Data Bus
The transmit data bus interface accepts 16-bit single-ended TTL parallel data at the TXD0–TXD15 pins. Data
and K-code control is valid on the rising edge of the TXCLK. The TXCLK is used as the word clock. The data, Kcode, and clock signals must be properly aligned as shown in Figure 7. Detailed timing information can be found
in the Transmitter/Receiver Electrical Characteristics.
TXCLK
TXD0−TXD15
tsu
th
TKLSB, TKMSB
Figure 7. Transmit Timing Waveform
8.3.3 Data Transmission Latency
The data transmission latency of the TLK2711-SP is defined as the delay from the initial 16-bit word load to the
serial transmission of bit 0. The transmit latency is fixed after the link is established. However, due to silicon
process variations and implementation variables such as supply voltage and temperature, the exact delay varies
slightly. The minimum transmit latency td(Tx latency) is 34 bit times; the maximum is 38 bit times. Figure 8 shows the
timing relationship between the transmit data bus, TXCLK, and serial transmit pins.
Transmitted 20-Bit Word
TXP,
TXN
td(Tx latency)
TXD0−TXD15
16-Bit Word to Transmit
TXCLK
Figure 8. Transmitter Latency
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Feature Description (continued)
8.3.4 8-Bit/10-Bit Encoder
All true serial interfaces require a method of encoding to ensure minimum transition density, so that the receiving
phase-locked loop (PLL) has a minimal number of transitions to stay locked on. The encoding scheme maintains
the signal DC balance by keeping the number of 1s and 0s the same. This provides good transition density for
clock recovery and improves error checking. The TLK2711-SP uses the 8-bit/10-bit encoding algorithm that is
used by fibre channel and gigabit ethernet. This is transparent to the user, as the TLK2711-SP internally encodes
and decodes the data such that the user reads and writes actual 16-bit data.
The 8-bit/10-bit encoder converts 8-bit-wide data to a 10-bit-wide encoded data character to improve its
transmission characteristics. Because the TLK2711-SP is a 16-bit-wide interface, the data is split into two 8-bitwide bytes for encoding. Each byte is fed into a separate encoder. The encoding is dependent upon two
additional input signals, TKMSB and TKLSB.
Table 1. Transmit Data Controls
TKLSB
TKMSB
0
0
Valid data on TXD0 to TXD7
16-BIT PARALLEL INPUT
Valid data TXD8 to TXD15
0
1
Valid data on TXD0 to TXD7
K code on TXD8 to TXD15
1
0
K code on TXD0 to TXD7
Valid data on TXD8 to TXD15
1
1
K code on TXD0 to TXD7
K code on TXD8 to TXD15
8.3.5 Pseudo-Random Bit Stream (PRBS) Generator
The TLK2711-SP has a built-in 27 – 1 PRBS function. When the PRBSEN pin is forced high, the PRBS test is
enabled. A PRBS is generated and fed into the 10-bit parallel-to-serial converter input register. Data from the
normal input source is ignored during the PRBS mode. The PRBS pattern is then fed through the transmit
circuitry as if it were normal data and sent out to the transmitter. The output can be sent to a bit error rate tester
(BERT), the receiver of another TLK2711-SP, or looped back to the receive input. Because the PRBS is not
really random, but a predetermined sequence of 1s and 0s, the data can be captured and checked for errors by
a BERT.
8.3.6 Parallel to Serial
The parallel-to-serial shift register takes in the 20-bit-wide data word multiplexed from the two parallel 8-bit/10-bit
encoders and converts it to a serial stream. The shift register is clocked on both the rising and falling edge of the
internally generated bit clock, which is 10× the TXCLK input frequency. The LSB (TXD0) is transmitted first.
8.3.7 High-Speed Data Output
The high-speed data output driver consists of a voltage mode logic (VML) differential pair optimized for a 50-Ω
impedance environment. The magnitude of the differential-pair signal swing is compatible with pseudo emitter
coupled logic (PECL) levels when AC coupled. The line can be directly coupled or AC coupled. See Figure 13
and Figure 14 for termination details. The outputs also provide preemphasis to compensate for AC loss when
driving a cable or PCB backplane trace over a long distance (see Figure 9). The level of preemphasis is
controlled by PRE (see Table 2).
VOD(p)
Table 2. Programmable Preemphasis
VOD(d)
0V
PRE
PREEMPHASIS LEVEL (%)
VOD(P), VOD(D) (1)
0
5%
1
20%
VOD(d)
Bit
Time
Bit
Time
VOD(p)
Figure 9. Output Voltage Under Preemphasis
(VTXP to VTXN)
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(1)
VOD(p): Voltage swing when there is a transition in the data
stream.
VOD(d): Voltage swing when there is no transition in the data
stream.
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8.3.8 Receive Interface
The receiver interface of the TLK2711-SP accepts 8-bit/10-bit encoded differential serial data. The interpolator
and clock recovery circuit locks to the data stream and extracts the bit-rate clock. This recovered clock is used to
retime the input data stream. The serial data is then aligned to two separate 10-bit word boundaries, 8-bit/10-bit
decoded, and output on a 16-bit-wide parallel bus synchronized to the extracted receive clock. The data is
received LSB (RXD0) first.
8.3.9 Receive Data Bus
The receive bus interface drives 16-bit-wide single-ended TTL parallel data at the RXD0 to RXD15 pins. Data is
valid on the rising edge of the RXCLK. The RXCLK is used as the recovered word clock. The data, RKLSB,
RKMSB, and clock signals are aligned as shown in Figure 10. Detailed timing information can be found in the
TTL Output Switching Characteristics.
RXCLK
RXD0−RXD15
tsu
th
RKLSB, RKMSB
Figure 10. Receive Timing Waveform
8.3.10 Data Reception Latency
The serial-to-parallel data receive latency is the time from when the first bit arrives at the receiver until it is output
in the aligned parallel word. The receive latency is fixed after the link is established. However, due to silicon
process variations and implementation variables such as supply voltage and temperature, the exact delay varies
slightly. The minimum receive latency td(Rx latency) is 76-bit times; the maximum is 107-bit times. Figure 11 shows
the timing relationship between the serial receive pins, the recovered word clock (RXCLK), and the receive data
bus.
20-Bit Encoded Word
RXN,
RXP
td(Rx latency)
RXD0−RXD15
16-Bit Decoded Word
RXCLK
Figure 11. Receiver Latency
8.3.11 Serial to Parallel
Serial data is received on the RXP and RXN pins. The interpolator and clock recovery circuit locks to the data
stream if the clock to be recovered is within 200 PPM of the internally generated bit rate clock. The recovered
clock is used to retime the input data stream. The serial data is then clocked into the serial-to-parallel shift
registers. The 10-bit-wide parallel data is then multiplexed and fed into two separate 8-bit/10-bit decoders, where
the data is then synchronized to the incoming data stream word boundary by detection of the comma 8-bit/10-bit
synchronization pattern.
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8.3.12 Comma Detect and 8-Bit/10-Bit Decoding
The TLK2711-SP has two parallel 8-bit/10-bit decode circuits. Each 8-bit/10-bit decoder converts 10-bit encoded
data (half of the 20-bit received word) back into 8 bits. The comma-detect circuit is designed to provide for byte
synchronization to an 8-bit/10-bit transmission code. When parallel data is clocked into a parallel-to-serial
converter, the byte boundary that was associated with the parallel data is now lost in the serialization of the data.
When the serial data is received and converted to parallel format again, a method is needed to recognize the
byte boundary. Typically, this is accomplished through the use of a synchronization pattern. This is typically a
unique pattern of 1s and 0s that either cannot occur as part of valid data or is a pattern that repeats at defined
intervals. The 8-bit/10-bit encoding contains a character called the comma (b0011111 or b1100000), which is
used by the comma-detect circuit on the TLK2711-SP to align the received serial data back to its original byte
boundary. The decoder detects the comma, generating a synchronization signal aligning the data to their 10-bit
boundaries for decoding; the comma is mapped into the LSB. The decoder then converts the data back into 8-bit
data. The output from the two decoders is latched into the 16-bit register synchronized to the recovered parallel
data clock (RXCLK) and output valid on the rising edge of the RXCLK.
NOTE
The TLK2711-SP only achieves byte alignment on the 0011111 comma.
Decoding provides two additional status signals, RKLSB and RKMSB. When RKLSB is asserted, an 8-bit/10-bit
K code is received and the specific K code is presented on the data bits RXD0 to RXD7; otherwise, an 8-bit/10bit D code is received. When RKMSB is asserted, an 8-bit/10-bit K code is received and the specific K-code is
presented on data bits RXD8 to RXD15; otherwise, an 8-bit/10-bit D code is received (see Table 3). The valid K
codes the TLK2711-SP; decodes are provided in Table 4. An error detected on either byte, including K codes not
in Table 4, causes that byte only to indicate a K0.0 code on the RKxSB and associated data pins, where K0.0 is
known to be an invalid 8-bit/10-bit code. A loss of input signal causes a K31.7 code to be presented on both
bytes, where K31.7 is also known to be an invalid 8-bit/10-bit code.
Table 3. Receive Status Signals
RKLSB
RKMSB
0
0
Valid data on RXD0 to RXD7
DECODED 20-BIT OUTPUT
Valid data RXD8 to RXD15
0
1
Valid data on RXD0 to RXD7
K code on RXD8 to RXD15
1
0
K code on RXD0 to RXD7
Valid data on RXD8 to RXD15
1
1
K code on RXD0 to RXD7
K code on RXD8 to RXD15
Table 4. Valid K Characters
K CHARACTER
RECEIVE DATA BUS
RXD7:RXD0 OR RXD15:RXD8
K28.0
000 11100
K28.1 (1)
001 11100
K28.2
010 11100
K28.3
011 11100
K28.4
100 11100
K28.5 (1)
101 11100
K28.6
110 11100
K28.7
(1)
(1)
111 11100
K23.7
111 10111
K27.7
111 11011
K29.7
111 11101
K30.7
111 11110
Should only be present on RXD0 to RXD7 when in running disparity
< 0.
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8.3.13 LOS Detection
The TLK2711-SP has a LOS detection circuit for conditions where the incoming signal no longer has a sufficient
voltage level to keep the clock recovery circuit in lock. The signal detection circuit is intended to be an indication
of gross signal error conditions, such as a detached cable or no signal being transmitted, and not an indication of
signal coding health. The TLK2711-SP reports this condition by asserting RKLSB, RKMSB, and RXD0 to RXD15
pins to a high state. As long as the differential signal is above 200 mV in differential magnitude, the LOS circuit
does not signal an error condition. When the device is disabled (ENABLE = L), RKMSB will output the status of
LOS. Active low = LOS detected.
8.3.14 PRBS Verification
The TLK2711-SP also has a built-in BERT function in the receiver side that is enabled by the PRBSEN. It can
check for errors and report the errors by forcing the RKLSB pin low.
8.3.15 Reference Clock Input
The reference clock (TXCLK) is an external input clock that synchronizes the transmitter interface. The reference
clock is then multiplied in frequency 10× to produce the internal serialization bit clock. The internal serialization
bit clock is frequency locked to the reference clock and used to clock out the serial transmit data on both its
rising and falling edges, providing a serial data rate that is 20× the reference clock.
8.3.16 Operating Frequency Range
The TLK2711-SP operates at a serial data rate from 1.6 to 2.5 Gbps. To achieve these serial rates, TXCLK must
be within 80 to 125 MHz. The TXCLK must be within ±100 PPM of the desired parallel data rate clock.
8.3.17 Testability
The TLK2711-SP has a comprehensive suite of built-in self-tests. The loopback function provides for at-speed
testing of the transmit/receive portions of the circuitry. The enable pin allows for all circuitry to be disabled so that
a quiescent current test can be performed. The PRBS function allows for built-in self-test (BIST).
8.3.18 Loopback Testing
The transceiver can provide a self-test function by enabling (LOOPEN) the internal loopback path. Enabling this
pin causes serial-transmitted data to be routed internally to the receiver. The parallel data output can be
compared to the parallel input data for functional verification. The external differential output is held in a highimpedance state during the loopback testing.
8.3.19 BIST
The TLK2711-SP has a BIST function. By combining PRBS with loopback, an effective self-test of all the circuitry
running at full speed can be realized. The successful completion of the BIST is reported on the RKLSB pin.
8.3.20 Power-On Reset
Upon application of minimum valid power and valid GTX_CLK with device enabled (ENABLE = HIGH), the
TLK2711-SP generates a power-on reset. During the power-on reset the RXD0 to RXD15, RKLSB, and RKMSB
signal pins go to a high-impedance state. The RXCLK is held low. LCKREFN must be deasserted (logic high
state) with active transitions on the receiver during the power-on reset period. Active transitions on receiver can
be accomplished with transitions on RXP/N or by assertion of LOOPEN. For TX-only applications, LOOPEN and
LCKREFN can be driven logic high together. The receiver circuit requires this to properly reset. After power-up
reset period, LCKREFN can be asserted for transmit only applications. The length of the power-on reset cycle
depends on the TXCLK frequency, but is less than 1 ms. See Figure 12 . TI recommends that the receiver be
reset immediately after power up. In some conditions, it is possible for the receiver circuit to power up in state
with internal contention.
If LCKREFN cannot be deasserted high during or for the complete power-on reset period, it can be deasserted
high at the end of or after the power-on reset period for minimum of 1 µs with active transitions on receiver to
properly complete reset of receiver.
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Min VCC/VCCA
2.375 V
VCC/VDDA
GTX_CLK
ENABLE
Internal Power-On
Reset Complete
LCKREFN
RXP/N data or
LOOPEN
Min 1 ms
Min 1 ms
Min 1 ms
Min 1 ms
Min 1 ms
Figure 12. Power-On/Reset Timing Diagram
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8.4 Device Functional Modes
8.4.1 Power-Down Mode
The TLK2711-SP goes into power-down mode when the ENABLE pin is pulled low. In the power-down mode, the
serial transmit pins (TXN), the receive data bus pins (RXD0 to RXD15), and RKLSB goes into a high-impedance
state. In the power-down condition, the signal detection circuit draws less than 15 mW. When the TLK2711-SP is
in the power-down mode, the clock signal on the TXCLK pin must be provided if LOS functionality is needed.
8.4.2 High-Speed I/O Directly-Coupled Mode
TXP
50 Ω
RXP
VDDA
Transmission
Line
50 Ω
4 kΩ
50 Ω
6 kΩ
50 Ω
TXN
Transmitter
Transmission
Line
Media
+
_
GND
RXN
Receiver
Figure 13. High-Speed I/O Directly-Coupled Mode Schematic
8.4.3 High-Speed I/O AC-Coupled Mode
TXP
50 Ω
RXP
VDDA
Transmission
Line
50 Ω
4 kΩ
50 Ω
6 kΩ
50 Ω
TXN
Transmitter
Transmission
Line
Media
+
_
GND
RXN
Receiver
Figure 14. High-Speed I/O AC-Coupled Mode Schematic
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLK2711-SP may be operated as full link with send/receive functions or each end of link may be transmit
only or receive only.
The transmitter is always operational in either case as GTX_CLK is required to source the PLL. In transmit only
cases, LCKREFN can be pulled low to disable the RX interface. See Power-On Reset for requirements.
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9.2 Typical Application
1 nF−10 nF†
1 nF−10 nF†
1 nF−10 nF†
1 nF−10 nF†
Recommended use of 0.01-µF
capacitor per VDD terminal
0.01 µF
5 Ω at 100 MHz
RXD1
RXD2
RXD0
RXD3
TXD5
4
48
RXD4
GND
5
47
RXD5
TXD6
6
46
RXD6
TXD7
7
45
GND
GTX_CLK
8
44
RXD7
VDD
9
43
RX_CLK
TXD8
10
42
RXD8
TXD9
11
41
RXD9
TXD10
12
40
VDD
GND
13
39
RXD10
TXD11
14
38
RXD11
TXD12
15
37
RXD12
TXD13
16
36
RXD13
GND
49
DINRXN
3
GND
DINRXP
VDD
TXD4
PRE
50
VDDA
2
GND
TXD3
DOUTTXP
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
51
DOUTTXN
1
GND
VDD
GND
GND
GND
RXD14
RXD15
RKLSB
RKMSB
GND
TESTEN
PRBSEN
LCKREFN
TKLSB
VDD
ENABLE
TXD15
TKMSB
LOOPEN
GND
17
35
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
TXD14
GND
†
TXD0
TXD2
TXD1
0.01 µF 0.01 µF 0.01 µF
0.01 µF
VDDA
VDD
For ac coupling
Copyright © 2018, Texas Instruments Incorporated
Figure 15. External Component Interconnection
22
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SGLS307P – JULY 2006 – REVISED FEBRUARY 2018
Typical Application (continued)
9.2.1 Design Requirements
Input conditions in the data sheet were created and validated to achieve a bit error rate (BER) of 1 error in 1E12
bits or better. Other aspects that affect BER are power supply noise, quality (loss), and matching of 50-Ω
controlled impedance for transmit and receive differential pins.
9.2.2 Detailed Design Procedure
Detailed design procedures involve careful examination of system properties, design, and error rate goals.
Understanding these properties allows for creation of jitter budget to ensure design BER goals are achieved.
Application note SLLA071 is based on the TLK2500. The TLK2500 shares the same architecture and similar jitter
properties.
9.2.3 Application Curves
2.5
850
2.0
800
VOUT_Differential (mV)
VOUT (V)
Figure 16 shows typical TTL output voltage characteristics at maximum 2-mA load at minimum VCC = 2.375 V.
Figure 17 shows typical differential output voltage VOD(p) across temperature for each preemphasis condition at
minimum VCC = 2.375 V.
1.5
VOH
VOL
1.0
0.5
750
700
650
VOD(1)
VOD(0)
0.0
600
±75
±50
±25
0
25
50
75
100
Temperature (ƒC)
VCC = 2.375 V
125
150
±75
IOH/IOL = ±2 mA
VOD
VOD
Figure 16. VOH/VOL vs Temperature
Copyright © 2006–2018, Texas Instruments Incorporated
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
150
C002
VCC = 2.375 V
(0) represents 5% emphasis enabled.
(1) represents 20% emphasis enabled.
Figure 17. VOD (0), VOD (1) vs Temperature
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10 Power Supply Recommendations
Power supplies must be within recommended operating range and should have less than 100 mV of ripple.
Exceeding 100-mV ripple can impact transmitted jitter and receiver jitter tolerance.
VDDA should be filtered from VDD. Filter values should be set to minimize any frequency components from
power supply and/or digital logic that may exist in the system in the range of the PLL jitter transfer
characteristics. The PLL is sensitive to noise in the range of 300 kHz to 3 MHz.
11 Layout
11.1 Layout Guidelines
Standard high-speed differential routing best practices must be employed. Routing should be 50-Ω matched
impedance and length for differential transmit and receive. Minimize layer transitions and stubs to reduce any
impedance mismatches. Connecting the thermal pad to board ground improves device performance by supplying
lower impedance path to ground minimizing ground bounce and improves thermal dissipation.
11.2 Layout Example
Figure 18. Layout Recommendation
24
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2006–2018, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
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2-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-0522101VXC
ACTIVE
CFP
HFG
68
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
TLK2711HFG/EM
ACTIVE
CFP
HFG
68
1
TBD
Call TI
N / A for Pkg Type
25 to 25
59620522101VXC
TLK2711HFGQMLV
TLK2711HFG/EM
EVAL ONLY
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2019
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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