Texas Instruments | TPS25741, TPS25741A USB Type-C™ and USB Power Delivery Host Port Controllers (Rev. D) | Datasheet | Texas Instruments TPS25741, TPS25741A USB Type-C™ and USB Power Delivery Host Port Controllers (Rev. D) Datasheet

Texas Instruments TPS25741, TPS25741A USB Type-C™ and USB Power Delivery Host Port Controllers (Rev. D) Datasheet
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TPS25741, TPS25741A
SLVSDJ5D – AUGUST 2016 – REVISED JANUARY 2018
TPS25741, TPS25741A USB Type-C™ and USB Power Delivery Host Port Controllers
1 Features
3 Description
•
The TPS25741, TPS25741A implements a source
compliant to USB Power Delivery 2.0 and USB TypeC revision 1.2. It can be used in either a power mux
or DC-DC implementation shown in the figure below.
1
•
•
•
•
•
•
USB Power Delivery 2.0 Certified Provider,
USB Type-C™ Revision 1.2 Compliant Source
Pin-Selectable Voltage Advertisement
– 5 V, 12 V, 20 V (TPS25741)
– 5 V, 9 V, 15 V (TPS25741A)
Pin-Selectable Peak Power Settings
– 12 Options 15 W to 100 W (TPS25741)
– 11 Options 15 W to 81 W (TPS25741A)
High Voltage and Safety Integration
– Overvoltage, Overcurrent, Overtemperature
Protection and VBUS Discharge
– IEC 61000-4-2 Protection on CC1 and CC2
– Input Pin for Fast Shutdown Under Fault
– Control of External N-ch MOSFETs and P-ch
MOSFETs for Single Power Path or Power
Mux Architecture
– 2-Pin External Power Supply Control
– Wide VIN Supply (4.65 V – 25 V)
5.4-µA Quiescent Current When Unattached
Port Power Management, Plug Polarity, Plug
Status, Audio and Debug Accessory Indicators
Built-in 1.8 V at 35-mA Supply Output
The device monitors the CC pin to detect a USB
Type-C sink attachment, then enables the GDNG and
G5V gate drivers to apply 5 V to VBUS (refer to figure
below). It then offers up to three voltages using USB
Power Delivery. In order to source the second voltage
the G5V gate driver is disabled and the GDPG gate
driver is enabled. In power mux implementations all
gate drivers are used and the CTL pins are not
necessary. In DC-DC implementations only the
GDNG gate driver is necessary and the CTL pins
program the power supply for the required voltage.
The device automatically discharges VBUS per USB
Power Delivery requirements. The PSEL, HIPWR,
PCTRL, and EN9V/EN12V pins are used to configure
the voltages and currents advertised.
The device typically draws 5.4 µA (8 µA if VDD = 0 V)
when no device is attached. The Port Attachment
indicator (UFP or DVDD) outputs may be used to
disable the power source until a sink is attached for
more system power savings.
Protection features include over-voltage, over-current,
over-temperature, IEC for CC pins, and system
override of gate drivers (GD).
2 Applications
•
•
•
Desktop and All-in-One Computers
Hub Downstream Ports
USB-Power Delivery Adaptor (USB data capable)
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS25741
VQFN (32)
4.00 mm x 4.00 mm
TPS25741A
VQFN (32)
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Implementations in DFP Host Ports
VBUS
2nd Voltage
Type C
Connector
5V/9V/15V@3A
or
5V/12V/20V@3A
VBUS
Type C
Connector
DC-DC
VIN
GDPG
VCONN
/VDD
5V
TPS25741/41A
D+ DTX1/RX1
POL
TX1/RX1
IEC
ESD
BC1.2
TPS2546
CC1
CC2
CTL1 CTL2
GDNG
TPS25741/41A
SBU
SBU
UFP
D+/D-
5V
CC VCONN
CC2
G5V GDNG
5V
D+/D-
USB3.1
2.0
VCONN
/VDD
POL
D+ D-
CC1
TX1/RX1
CC VCONN
5V/3A
D+/D-
IEC
ESD
BC1.2
TPS2546
TX1/RX1
D+/D-
USB3.1
2.0
TX/RX
TX2/RX2
Power Mux Implementation
TX2/RX2
TX2/RX2
SS MUX
TX2/RX2
DC-DC Implementation
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS25741, TPS25741A
SLVSDJ5D – AUGUST 2016 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
4
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings ............................................................ 6
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Electrical Characteristics........................................... 8
Timing Requirements .............................................. 12
Switching Characteristics ........................................ 12
Typical Characteristics ............................................ 16
Detailed Description ............................................ 19
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
19
21
21
38
9
Application and Implementation ........................ 39
9.1 Application Information............................................ 39
9.2 Typical Applications ................................................ 47
9.3 System Examples ................................................... 55
10 Power Supply Recommendations ..................... 57
10.1 VDD....................................................................... 57
10.2 VCONN ................................................................. 57
10.3 VPWR ................................................................... 57
11 Layout................................................................... 58
11.1 Layout Guidelines ................................................. 58
11.2 Layout Example .................................................... 59
12 Device and Documentation Support ................. 60
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
60
60
60
60
60
60
60
13 Mechanical, Packaging, and Orderable
Information ........................................................... 61
4 Revision History
Changes from Revision C (June 2017) to Revision D
•
Page
Deleted Application: Automotive Infotainment........................................................................................................................ 1
Changes from Revision B (January 2017) to Revision C
Page
•
Changed Shunt capacitance, VCONN value From: MAX = 10 µF To: MIN = 10 µF MAX = 220 µF in the
Recommended Operating Conditions table............................................................................................................................ 7
•
Deleted the row for TPS25741A Input resistance, and changed the MAX value From: 5 MΩ To: 6 MΩ in the
Electrical Characteristics table ............................................................................................................................................. 10
•
Changed the Unloaded output voltage on CC pin MIN value From: 2.8 V to 2.7 V and the MAX value From: 5.5 V to
4.35 V in the Electrical Characteristics table ........................................................................................................................ 11
•
Deleted tWD Watchdog Timer from the Timing Requirements table ..................................................................................... 12
•
Deleted tST row for TPS25741A in the Switching Characteristics table ............................................................................... 13
•
Deleted the last sentence from the Sleep Mode section: "The TPS25741 will wake up every tWD and check for a
connection before returning to sleep mode"......................................................................................................................... 38
•
Added test: "The TPS25740/TPS25740A Design Calculator Tool.." to the Application Information section ....................... 39
•
Added sentence "All slew rate control methods" to the Voltage Transition Requirements section...................................... 44
•
Deleted the Enabling Power Muxing Architecture section.................................................................................................... 47
•
Added text: "The following example is based on TPS25741..." to the A/C Multiplexing Power Source section.................. 47
•
Deleted Q4 and Note from Figure 50 ................................................................................................................................... 47
•
Changed From: A 400 pF, 50 V, ±5% COG/NPO ceramic To: A 470 pF, 50 V, ±5% COG/NPO ceramic in the
Configurable Components section ....................................................................................................................................... 48
•
Changed From: RF/CF: Not used To: RF/CF: Provide filtering of both ripple... in the Configurable Components section .... 48
•
Changed From: A 400 pF, 50 V, ±5% COG/NPO ceramic To: A 470 pF, 50 V, ±5% COG/NPO ceramic in the
Configurable Components section ....................................................................................................................................... 53
•
Added document links to the Documentation Support section............................................................................................. 60
2
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SLVSDJ5D – AUGUST 2016 – REVISED JANUARY 2018
Changes from Revision A (September 2016) to Revision B
Page
•
Added row to Input resistance for TPS25741A in the Electrical Characteristics table......................................................... 10
•
Changed the Test Conditions tWD Watchdog Timer From: CC pins floating To: CC pins floating (TPS25741) in the
Timing Requirements table................................................................................................................................................... 12
•
Added TPS25741 to the test conditions for tST in the Switching Characteristics table. Added row to tST for
TPS25741A in the test conditions and TYP value of 30 ms in the Switching Characteristics table .................................... 13
•
Changed the last sentence of the Sleep Mode section: From: "The TPS25741/TPS25741A will also wake up every
tWD and check for a connection before returning to sleep mode." To: "The TPS25741 will wake up every tWD and
check for a connection before returning to sleep mode ...................................................................................................... 38
•
Changed section title From: VOUT Ripple Filtering using RF and CF To: Tuning OCP Using RF and CF. Updated
section text............................................................................................................................................................................ 46
•
Added Note to Q4 of Figure 50 ........................................................................................................................................... 47
•
Changed section title From: Dual-Port A/C Power Source (Wall Adaptor) To: Dual-Port Power Managed A/C Power
Source (Wall Adaptor) .......................................................................................................................................................... 56
Changes from Original (August 2016) to Revision A
•
Page
Changed From: Product Preview To: Production Data for the TPS25741............................................................................. 1
Copyright © 2016–2018, Texas Instruments Incorporated
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5 Device Comparison Table
(1)
DEVICE NUMBER
VOLTAGE OPTION
TPS25741
Offers 5 V, 12 V, and 20 V
TPS25741A (1)
Offers 5 V, 9 V, and 15 V
Product Preview. Contact TI factory for more information.
6 Pin Configuration and Functions
ISNS
AGND
VDD
VAUX
GD
PCTRL
DVDD
VIO
24
23
22
21
20
19
18
17
RSM Package
32-Pin VQFN
Top View
VPWR
25
16
PSEL
VBUS
26
15
DEBUG
GDPG
27
14
UFP
AUDIO
28
13
N/C
GDNG
29
12
N/C
GDNS
30
11
N/C
DSCG
31
10
EN9V/EN12V
G5V
32
9
Thermal
1
2
3
4
5
6
7
8
VTX
CC1
VCONN
CC2
GND
HIPWR
CTL1
CTL2
Pad
POL
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NUMBER
AGND
23
—
Analog ground is associated with monitoring and power conditioning circuits. Connect to GND and PAD.
AUDIO
28
O
Low when an audio accessory is present, high-z otherwise.
CC1
2
I/O
Multifunction configuration channel interface pin to USB Type-C. Functions include connector polarity,
end-device connection detect, current capabilities, and Power Delivery communication.
CC2
4
I/O
Multifunction configuration channel interface pin to USB Type-C. Functions include connector polarity,
end-device connection detect, current capabilities, and Power Delivery communication.
CTL1
7
O
Digital output pin used to control an external voltage regulator.
CTL2
8
O
Digital output pin used to control an external voltage regulator.
DEBUG
15
O
Low when a debug accessory is present, high-z otherwise.
DSCG
31
O
Discharge is an open-drain output that discharges the system VBUS line through an external resistor.
DVDD
18
O
Internally regulated 1.85 V rail for external use up to 35 mA. Connect this pin to GND via the
recommended bypass capacitor.
4
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Pin Functions (continued)
PIN
NAME
NUMBER
TYPE
DESCRIPTION
EN9V/EN12V
10
I
For TPS25741:
If it is pulled high, then the 12 V PDO may be transmitted. If it is pulled low, the 12-V PDO will not be
advertised.
For TPS25741A:
If it is pulled high, then the 9 V PDO may be transmitted. If it is pulled low, the 9-V PDO will not be
advertised.
GDPG
27
O
High-voltage open drain gate driver which may be used to drive PMOS power switches.
G5V
32
O
Analog gate drive output for an external NMOS power switch.
GD
20
I
Master enable for the GDNG/GDNS gate driver. The system can drive this low to force the power path
switch off.
GDNG
29
O
High-voltage open drain gate driver which may be used to drive NMOS power switches. Connect to the
gate terminal.
GDNS
30
O
High-voltage open drain gate driver which may be used to drive NMOS power switches. Connect to the
source terminal.
GND
5
—
Power ground is associated with power management and gate driver circuits. Connect to AGND and PAD.
HIPWR
6
I
Four-state input pin used to configure the voltages and currents that will be advertised. It may be
connected directly to GND or DVDD, or it may be connected to GND or DVDD via a resistance RSEL.
ISNS
24
I
The ISNS input is used to monitor a VBUS-referenced sense resistor for over-current events.
PCTRL
19
I
Input pin used to control the power that will be advertised. It may be pulled high or low dynamically.
POL
9
O
Low when a UFP is connected on CC2, high-z otherwise.
PSEL
16
I
A four-state input used for selecting the maximum power that can be provided. It may be connected
directly to GND or DVDD, or it may be connected to GND or DVDD via a resistance RSEL
UFP
14
O
Digital output pin used to indicate that either CC1 or CC2 (but not both) is pulled down by a USB Type-C
Sink.
VAUX
21
O
Internally regulated rail for use by the power management circuits. Connect this pin to GND via the
recommended bypass capacitor.
VBUS
26
I
The voltage monitor for the VBUS line. The USB connector VBUS line is the high-side power conductor.
VCONN
3
I
The voltage applied to this pin will be internally current limited and routed through the TPS25741 to the
CCx pin that is not connected to the CC wire in the USB cable once the UFP pin is pulled low. Connect
this pin to GND via the recommended bypass capacitor.
VDD
22
I
Optional input supply.
VIO
17
I
Connect VIO to the DVDD pin.
VPWR
25
I
Connect to an external voltage as a source of bias power. If VDD is supplied, this supply is optional while
is UFP high.
VTX
1
O
Bypass pin for transmit driver supply. Use a 0.1-µF ceramic capacitor.
N/C
11
Connect to GND.
N/C
12
Connect to GND.
N/C
13
Connect to GND.
THERMAL
PAD
Connect PAD to GND / AGND plane.
Copyright © 2016–2018, Texas Instruments Incorporated
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
AUDIO, VDD , EN12V, EN9V, CTL1, CTL2,
UFP, PCTRL, CC1, CC2, DEBUG, POL, VIO
VTX
(2)
VAUX (2)
GD
Pin voltage (sustained)
Pin voltage (transient for 1 ms)
Pin-to-pin voltage
(3)
MIN
MAX
UNIT
–0.3
6
V
–0.3
2.1
V
–0.3
4.5
V
–0.3
7
V
HIPWR, PSEL, DVDD (2)
–0.3
2.1
V
GDPG
–0.3
30
V
G5V
–0.3
20
V
GDNG (2)
–0.5
40
V
VCONN
–0.3
7
V
VBUS,VPWR, ISNS, DSCG, GDNS
–0.5
30
V
VBUS,VPWR, ISNS, DSCG, GDNS
–1.5
30
V
V(GDNG) – V(GDNS)
–0.3
20
V
AGND to GND
–0.3
0.3
V
ISNS to VBUS
–0.3
0.3
V
3.5
mA
8
mA
AUDIO, GDPG
CTL1, CTL2, UFP, DEBUG, POL
Sinking current (average)
Sinking current (transient, 50 ms pulse 0.25%
duty cycle)
GD
100
µA
DSCG
10
mA
DSCG
375
mA
VTX, VCONN, CC1, CC2
Internally limited
mA
VAUX
0
25
µA
Operating junction temperature range, TJ
–40
125
°C
Storage temperature, Tstg
–65
150
°C
Current sourcing
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Do not apply voltage to these pins.
Voltage allowed to rise above Absolute Maximum provided current is limited.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
(3)
(4)
6
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
IEC
(3)
61000-4-2 contact discharge, CC1, CC2
±8000
IEC
(4)
61000-4-2 air-gap discharge, CC1, CC2
±15000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
These results were passing limits that were obtained on an application-level test board. Individual results may vary based on
implementation. Surges per IEC61000-4-2, 1999 applied between CC1/CC2 and output ground of TPS25741EVM-802 and
TPS25741AEVM-802
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCONN
VIN
Supply Voltage
VIH
VIL
Applied Voltage
High-Level Input Voltage
Low-Level Input Voltage
5.5
V
5.5
V
4.65
25
V
AUDIO, EN9V, EN12V, PCTRL, CC1,
CC2, CTL1, CTL2, DEBUG, POL
0
5.5
V
GD
0
6.5
V
DSCG, GDNS, VBUS
0
25
V
GDPG
0
25
V
G5V
0
16
V
HIPWR, PSEL
0
1.96
V
EN9V, EN12V
1.36
V
PCTRL
1.65
V
GD
1.64
V
EN9V, EN12V
0.53
V
PCTRL
1.85
V
GD
1.81
CTL1, CTL2, UFP, DEBUG, POL
Sinking Current
GD
DSCG, transient sinking current 50ms
pulse, 0.25% duty cycle
DSCG, average
Sourcing Current
RDSCG
TJ
Series resistance
Operating junction temperature
Copyright © 2016–2018, Texas Instruments Incorporated
mA
µA
350
mA
mA
mA
200
560
600
pF
10
µF
DVDD
0.198
0.22
0.242
µF
VAUX
0.09
0.1
0.11
µF
VTX
0.09
0.1
0.11
µF
220
µF
VDD
Pull up/down resistance
5
80
5
VCONN
RPUD
mA
600
VBUS (CPDIN)
Shunt capacitance
V
1
200
VCONN
CC1, CC2 (CRX)
CS
UNIT
0
AUDIO, GDPG
IS
MAX
4.65
VDD
VPWR
VI
NOM
HIPWR, PSEL (direct to GND or direct
to DVDD)
10
0.09
µF
0
kΩ
120
kΩ
HIPWR, PSEL (RSEL)
80
Maximum VBUS voltage of 25 V
80
Ω
Maximum VBUS voltage of 15 V
43
Ω
Maximum VBUS voltage of 6 V
20
-40
100
1
Ω
125
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7.4 Thermal Information
THERMAL METRIC
TPS25741
TPS25741A
(1)
UNIT
RSM (VQFN)
32 PINS
RθJA
Junction-to-ambient thermal resistance
37.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32.1
°C/W
RθJB
Junction-to-board thermal resistance
8.5
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
8.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65
V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND;EN9V = GND; EN12V =
GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage Comparator (VBUS)
VBUS_RTH
VBUS Threshold (Rising voltage)
4.25
4.45
4.65
V
VBUS_FTH
VBUS Threshold (Falling voltage)
3.5
3.7
3.9
V
VBUS Threshold (Hysteresis)
0.75
V
Power Supply (VDD, VPWR)
VDD_TH
VDD UVLO threshold
Rising voltage
2.8
2.91
2.97
Falling voltage
2.8
2.86
2.91
Hysteresis, comes into effect once the
rising threshold is crossed.
VPWR_TH
VPWR UVLO threshold
Rising voltage
4.2
4.45
4.65
Falling voltage
3.5
3.7
3.9
Hysteresis, comes into effect once the
rising threshold is crossed.
Supply current drawn from VDD in sleep
mode
Supply current drawn from VPWR in
sleep mode
ISUPP
Typical operating current (from VPWR
and VDD)
V
0.05
V
0.75
VPWR = 0 V, VDD = 5 V, CC1 and CC2
pins are open. TJ = 25°C
8.5
µA
VPWR = 0 V, VDD = 3.3 V, CC1 and
CC2 pins are open. TJ = 25°C
5.4
µA
VPWR = 0 V, VDD = 5 V,CC1 pin open,
CC2 pin tied to GND. TJ = 25°C
93
µA
VPWR = 5 V, VDD = 0 V, CC1 and CC2
pins are open. TJ = 25°C
8
µA
VPWR = 5 V, VDD = 0 V, CC1 pin open,
CC2 pin tied to GND. TJ = 25°C
89
µA
Power Delivery Sourcing active, VBUS =
5 V,
VPWR = 5 V, VDD = 3.3 V
1
1.8
3
mA
5.8
6.05
6.3
V
12 V Power Delivery contract (TPS25741)
13.2
13.75
14.3
V
20 V Power Delivery contract (TPS25741)
22.1
23.05
24.0
V
9 V Power Delivery contract
(TPS25741A)
10.1
10.55
11.0
V
15 V Power Delivery contract
(TPS25741A)
16.2
16.95
17.7
V
Over/Under Voltage Protection (VBUS)
5 V Power Delivery contract
VFOVP
8
Fast OVP threshold, always enabled
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Electrical Characteristics (continued)
Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65
V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND;EN9V = GND; EN12V =
GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5.5
5.65
5.8
V
12 V Power Delivery contract (TPS25741)
13.1
13.4
13.7
V
20 V Power Delivery contract (TPS25741)
21.5
22.0
22.5
V
10
10.2
10.4
V
15 V Power Delivery contract
(TPS25741A)
16.3
16.5
17
V
5 V Power Delivery contract
3.5
3.65
3.8
V
12 V Power Delivery contract (TPS25741)
9.2
9.45
9.7
V
20 V Power Delivery contract (TPS25741)
15.7
16.1
16.5
V
9 V Power Delivery contract
(TPS25741A)
6.8
6.95
7.1
V
15 V Power Delivery contract
(TPS25741A)
11.7
11.95
12.2
V
2.875
3.2
4.1
5 V Power Delivery contract
VSOVP
VSUVP
Slow OVP threshold, disabled during
voltage transitions. (see Figure 1)
UVP threshold, disabled during voltage
transitions (see Figure 1)
9 V Power Delivery contract
(TPS25741A)
UNIT
VAUX
VVAUX
Output voltage
0 ≤ IVAUX ≤ IVAUXEXT
VAUX Current limit
IVAUXEXT
1
External load that may be applied to
VAUX.
V
5
mA
25
µA
1.95
V
DVDD
VDVDD
0 mA ≤ IDVDD ≤ 35 mA, CC1 or CC2
pulled to ground via 5.1 kΩ, or both CC1
and CC2 pulled to ground via 1 kΩ
1.75
Overshoot from VDVDD, 10-mA minimum,
0.198-µF bypass capacitor
1.7
2
V
Undershoot from VDVDD, 10-mA minimum,
0.198-µF bypass capacitor
1.7
2
V
Current limit
DVDD tied to GND
40
150
Output voltage
Not transmitting or receiving, 0 to 2 mA
external load
Current Limit
VTX tied to GND
Output voltage
Load Regulation
1.85
mA
VTX
1.050
1.125
2.5
1.200
10
V
mA
Gate Driver Disable (GD)
Rising voltage
VGD_TH
Input enable threshold voltage
VGDC
Internal clamp voltage
IGD = 80 µA
RGD
Internal pulldown resistance
Discharge (DSCG)
1.64
Hysteresis
1.725
1.81
0.15
V
V
6.5
7.5
8.5
V
From 0 V to 6 V
3
6
9.5
MΩ
(1) (2)
VDSCGT
ON state (linear)
IDSCG = 100 mA
0.15
0.42
1
IDSCGT
ON state (saturation)
VDSCG = 4 V, pulsed testing
220
553
1300
mA
V
RDSCGB
Discharge bleeder
While CC1 is pulled down by 5.1 kΩ and
CC2 is open, VDSCG = 25 V, compute
VDSCG/IDSCG
6.6
8.2
10
kΩ
Leakage current
0 V ≤ VDSCG ≤ 25 V
2
µA
48
µA
2
µA
P-ch MOSFET Gate Driver (GDPG)
IGDPG
Sinking current (ON)
2 V ≤ VGDPG ≤ 25 V
ILGDPG
Leakage current
0 V ≤ VGDPG ≤ 25 V
34
41
N-ch MOSFET Gate Driver (G5V)
IG5VON
Sourcing current
0 V ≤ VG5V ≤ 9 V
6.6
VG5VON
Sourcing voltage (ON)
IG5V ≤ 2 µA
10
(1)
(2)
10
µA
16
V
If TJ1 is perceived to have been exceeded an OTSD occurs and the discharge FET is disabled.
The discharge pull-down is not active in the sleep mode.
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Electrical Characteristics (continued)
Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65
V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND;EN9V = GND; EN12V =
GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
PARAMETER
RG5VOFF
TEST CONDITIONS
Sinking strength (OFF)
MIN
TYP
VG5V = 1 V
Sinking strength UVLO (safety)
Off-state leakage
MAX
200
VDD = 1.3 V, VPWR = 0 V, VG5V = 1 V
288
VPWR = 1.3 V, VDD = 0 V, VG5V = 1 V
343
VG5V = 15V
UNIT
Ω
µA
µA
2
µA
30
µA
7
12
V
8.5
12
V
300
Ω
N-ch MOSFET Gate Driver (GDNG,GDNS)
0 V ≤ VGDNS ≤ 25 V,
0 V ≤ VGDNG – VGDNS ≤ 6 V
IGDNGON
Sourcing current
VGDNGON
Sourcing voltage while enabled (VGDNG –
VGDNS)
RGDNGOFF
Sinking strength while disabled
Sinking strength UVLO (safety)
Off-state leakage
0 V ≤ VGDNS ≤ 25 V, IGDNGON ≤ 4 µA,
VPWR = 0 V
0 V ≤ VGDNS ≤ 25 V, IGDNGON ≤ 4 µA, VDD
=0V
13.2
20
VGDNG – VGDNS= 0.5 V,
0 ≤ VGDNS ≤ 25 V
150
VDD = 1.4 V, VGDNG = 1 V,
VGDNS = 0 V, VPWR = 0 V
145
µA
VDD = 1.4 V, VGDNG = 1 V,
VGDNS = 0 V, VDD = 0 V
145
µA
VGDNS = 25 V, VGDNG open
7
µA
Power Control Input (PCTRL)
VPCTRL_TH
Voltage rising
Active threshold voltage (3)
1.65
Hysteresis
Input resistance
1.75
1.85
100
0 V ≤ VPCTRL ≤ VVAUX
1.5
0 V ≤ VHIPWR ≤ VDVDD,
0 V ≤ VPSEL ≤ VDVDD
–1
2.9
V
mV
6
MΩ
1
µA
0.4
V
0.5
µA
46
kΩ
2
µA
0.585
V
Voltage Select (HIPWR), Power Select (PSEL) (4)
Leakage current
Port Status and Voltage Control (CTL1, CTL2, UFP, POL, DEBUG) (5)
VOL
Output low voltage
Leakage Current
Presence of Audio Accessory (AUDIO)
IAUD
IOL = 4 mA sinking
In Hi-Z state, 0 ≤ VCTLx ≤ 5.5 V or
0 ≤ VUFP ≤ 5.5V
(6)
–0.5
(7)
Current pull down
VAUDIO = 1 V
Leakage current
0 V ≤ VAUDIO ≤ 5.5 V
34
40
Enable 9 V, 12 V Capability (EN9V, EN12V) (8)
VILGIO
Input low threshold voltage
VIHGIO
Input high threshold voltage
1.225
Input hysteresis
V
0.25
V
Transmitter Specifications (CC1, CC2)
RTX
Output resistance (zDriver, refer to USB
Power Delivery in Documentation
Support)
During transmission
VTXHI
Transmit high voltage
VTXLO
Transmit low voltage
33
48
75
External Loading per Figure 28
1.05
1.125
1.2
V
External Loading per Figure 28
–75
75
mV
Ω
Receiver Specifications (CC1, CC2)
VRXHI
Receive threshold (rising)
800
840
885
mV
VRXLO
Receive threshold (falling)
485
525
570
mV
Receive threshold (hysteresis)
(3)
(4)
(5)
(6)
(7)
(8)
10
315
mV
When voltage on the PCTRL pin is less than V(PCTRL_TH), the amount of power advertised is reduced by half.
Leaving HIPWR or PSEL open is an undetermined state and leads to unpredictable behavior.
These pins are high-z during a UVLO, reset, or in Sleep condition.
The pins were designed for less leakage, but testing only verifies that the leakage does not exceed 1 µA.
AUDIO is high-z during a UVLO, reset, or Device Sleep condition.
Protection is provided against a voltage greater than VDVDD being applied externally.
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SLVSDJ5D – AUGUST 2016 – REVISED JANUARY 2018
Electrical Characteristics (continued)
Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65
V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND;EN9V = GND; EN12V =
GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Interference is 600 kHz square wave,
rising 0 to 100 mV.
Amplitude of interference that can be
tolerated.
Interference is 1 MHz sine wave
MAX
UNIT
100
mV
1
VPP
DFP Specifications (CC1, CC2)
VDSTD
VD1p5
In standard DFP mode (9), voltage rising
Detach threshold when cable is detached
while in standard DFP mode.
Detach threshold when cable is detached.
VD3p0
Detach threshold when cable is detached
VOCN
Unloaded output voltage on CC pin
1.52
Hysteresis
1.585
1.65
0.02
In 1.5 A DFP mode (10), voltage rising
1.52
Hysteresis
1.585
V
1.65
0.02
In 3 A DFP mode (11), voltage rising
2.50
Hysteresis
2.625
V
V
V
2.75
0.05
V
V
normal mode
2.7
4.35
V
VPWR = 0 V (in UVLO) or in sleep mode
1.8
5.5
V
IRPSTD
Loaded output current while connected
through CCx
In standard DFP mode (9), CCy open,
0 V ≤ VCCx ≤ 1.5 V (vRd)
64
80
96
µA
IRP1.5
Loaded output current while connected
through CCx
In 1.5 A DFP mode (10), CCy open,
0 V ≤ VCCx ≤ 1.5 V (vRd)
166
180
194
µA
IRP3.0
Loaded output current while connected
through CCx
In 3 A DFP mode (11), CCy open,
0 V ≤ VCCx ≤ 1.5 V (vRd)
304
330
356
µA
VRDSTD
Ra, Rd detection threshold (falling)
In standard DFP mode (9),
0 V ≤ VCCx ≤ 1.5 V (vRd)
0.15
0.19
0.23
V
VOCDS
Hysteresis
VRD1.5
0.02
In 1.5 A DFP mode (10), CCy open
0 V ≤ VCCx ≤ 1.5 V (vRd)
Ra, Rd detection threshold (falling)
0.35
Hysteresis
0.39
V
0.43
0.02
V
V
(11)
VRD3.0
Ra, Rd detection threshold (falling)
VWAKE
Wake threshold (rising and falling), exit
from sleep mode
IDSDFP
Output current on CCx in sleep mode to
detect Ra removal.
In 3 A DFP mode , CCy open
0 V ≤ VCCx ≤ 1.5 V (vRd)
0.75
Hysteresis
Connector Power Specifications (CC1, CC2, VCONN)
UVLO for VCONN
RDSON
IOS
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
0.83
0.02
VPWR = 4.65 V , 0 V ≤ VDD ≤ 3 V
1.6
CCx = 0V, CCy floating
40
2.2
V
V
3.0
V
73
105
µA
2.4
2.6
V
(12)
(13)
Resistance from VCONN to CC1 or
CC2 (14) (15)
Current limit measured on CC1 or CC2 (16)
Fault threshold
0.79
Turn-on, VCONN rising
Hysteresis
0.1
4.75 V ≤ VCONN ≤ 5.5 V
(Fixed Supply mode),
ICCx = 250 mA
–40°C ≤ TJ ≤ 125°C
300
500
mΩ
4.75 V ≤ VCONN ≤ 5.5 V
(Fixed Supply mode),
ICCx = 250 mA
TJ = 25°C
300
350
mΩ
490
562
mA
1.25×IOS
mA
4.75 V ≤ VCONN ≤ 5.5 V
(Fixed Supply mode)
415
1.1×IOS
V
Standard DFP mode is active after a USB Type-C sink, debug accessory, or audio accessory is attached until the first USB Power
Delivery message is transmitted (after GDNG has been enabled).
1.5 A DFP mode is active after a USB Power Delivery contract has been negotiated.
3 A DFP mode is active after GDNG has been enabled until a USB Power Delivery message is received.
VCONN is always applied when a UFP is attached, regardless of whether Ra is detected.
The VCONN pin has reverse blocking.
Based on 120 mV drop at 250 mA (to deliver more than 1 W at VCONN = 4.75 V).
There are requirements for the VCONN voltage supplied to CC1 or CC2 in [1]; customers need to take the RDSON into account when
designing to meet those requirements.
While providing VCONN power, the CCx output is monitored for faults (overloads). Thermal shutdown is provided with thermal cycling
(auto-restart).
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Electrical Characteristics (continued)
Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65
V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND;EN9V = GND; EN12V =
GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
19.2
22.6
mV
29
34
mV
Over-Current Protection (ISNS, VBUS)
VITRIP
Current trip shunt voltage
Specified as VISNS – VBUS. The OCP trip
point setting assumes the sense resistor
is 5 mΩ
HIPWR: 5 A not enabled
HIPWR: 5 A enabled
OTSD
TJ1
Die Temperature (Analog) (17)
TJ2
Die Temperature (Analog) (18)
TJ ↑
125
Hysteresis
135
145
10
TJ ↑
140
Hysteresis
150
163
10
°C
°C
(17) When TJ1 trips a hard reset is transmitted and discharge is disabled, but the bleeder discharge is not disabled.
(18) TJ2 trips only when some external heat source drives the temperature up. When it trips the DVDD, and VAUX power outputs are turned
off.
7.6 Timing Requirements
Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3.0 V ≤ VDD ≤ 5.5 V,
4.65 V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND, EN9V = GND; EN12V =
GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted).
MIN
tFOVPDG
Deglitch for fast over-voltage protection
tOCP
Deglitch Filter for over-current protection
Time power is applied until CC1 and CC2
pull-ups are applied.
tCC
NOM
MAX
9
VVPWR > VPWR_TH OR
VVDD > VDD_TH
2.5
Falling/Rising voltage deglitch time for
detection on CC1 and CC2
UNIT
µs
15
µs
4
ms
120
µs
Transmitter Specifications (CC1, CC2)
tUI
Bit unit interval
Rise/fall time, tFall and tRise (refer to USB
Power Delivery in Documentation Support)
3.05
External Loading per Figure 28
3.3
300
3.70
µs
600
ns
7.7 Switching Characteristics
Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3.0 V ≤ VDD ≤ 5.5 V,
4.65 V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND, EN9V = GND; EN12V =
GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
PARAMETER
tVP
Delay from enabling external NFET until
under-voltage and OCP protection are
enabled
tSTL
Source settling time, time from CTL1 and
CTL2 being changed until a PS_RDY USB
Power Delivery message is transmitted to
inform the sink is may draw full current per
USB Power Delivery in Documentation
Support.
tSR
Time that VBUS is held low after a hard
reset. This is tSrcRecover in USB Power
Delivery in Documentation Support.
tHR
Time after hard reset is transmitted until
GDNG is disabled. This is tPSHardReset in USB
Power Delivery in Documentation Support.
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TEST CONDITIONS
VBUS = GND
TJ > TJ1
MIN
TYP
MAX
UNIT
190
ms
260
ms
765
ms
30
ms
Copyright © 2016–2018, Texas Instruments Incorporated
TPS25741, TPS25741A
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SLVSDJ5D – AUGUST 2016 – REVISED JANUARY 2018
Switching Characteristics (continued)
Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3.0 V ≤ VDD ≤ 5.5 V,
4.65 V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND, EN9V = GND; EN12V =
GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tCCDeb
Time until UFP or AUDIO or DEBUG is pulled
low after an attachment, this is the USB
Type-C required debounce time for
attachment detection called tCCDebounce [1].
185
ms
tST
Delay after sink request is accepted until
CTL1 and/or CTL2 is changed. This is called
tSnkTransition in USB Power Delivery in
Documentation Support.
30
ms
tFLT
The time in between hard reset transmissions GD = GND or VPWR = GND, sink
in the presence of a persistent supply fault.
attached
1395
ms
tSH
The time in between retries (hard reset
transmissions) in the presence of a persistent VBUS = GND, sink attached
VBUS short.
985
ms
tON
The time from UFP being pulled low until a
hard reset is transmitted. Designed to be
greater than tSrcTurnOn in USB Power Delivery
in Documentation Support.
GD = 0 V or VPWR = 0 V
600
ms
Retry interval if USB Power Delivery sink
stops communicating without being removed
or if sink does not communicate after a fault
condition. Time GDNG remains enabled
before a hard reset is transmitted. This is the
tNoResponse time in USB Power Delivery in
Documentation Support.
Sink attached
4.8
s
tDVDD
Delay before DVDD is driven high
After sink attached
5
ms
tGDoff
Turnoff delay, time until VGDNG is below 10%
of its initial value after the GD pin is low.
VGD: 5 V → 0 V in < 0.5 µs.
5
µs
tFOVP
VBUS ↑ to GDNG OFF
Response time when VBUS exceeds the fast(VGDNG below 10% its initial
OVP threshold
value)
30
µs
tVCON
OCP large signal response time
5 A enabled, VISNS – VVBUS: 0 V
→ 42 mV measured to GDNG
transition start.
30
µs
Time until discharge is stopped after TJ1 is
exceeded.
0 V ≤ VDSCG ≤ 25 V
10
µs
Digital output fall time
VPULLUP = 1.8 V, CLoad = 10 pF,
RPULLUP = 10 kΩ, V(CTLx) or
VUFP : 70% VPULLUP → 30%
VPULLUP
300
ns
VCONN turn-on time
Measured from when UFP is
pulled low until VCONN FET is
enabled.
2
ms
VBUS turn-on time
Measured from when UFP is
pulled low until GDNG begins
sourcing its full current
2
ms
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VFOVP=13.76V
VSOVP=13.4V
PCTRL, and EN9V or EN12V
samples prior to sending
Source Capabilities
VSUVP=9.45V
9.45V
tSTL
tSTL
VFOVP=6.08V
VFOVP=6.08V
VSOVP=5.65V
VSOVP=5.65V
VSUVP=3.65V
VSUVP=3.65V
VBUS
0V
tST
tVP
UFP
SlowOVP/UVP
enabled
OCP
enabled
Sink
Request
Accepted
Figure 1. Timing Diagram for tVP, tST, and tSTL, After Sink Attachment. VSOVP and VSUVP are Disabled
Around Voltage Transitions
Enabled
Enabled
tSR
GDNG
tHR
Disabled
UFP
tHR
Disabled
VDVDD
VOL
(Pulled high
to DVDD)
Figure 2. Timing Diagram for tHR and tSR, After Sink Attachment with TJ > TJ1
Source
Capabilities
Transmitted
Sink
Attached
5V
VBUS
0V
UFP
(Pulled high
high-z
tCD
VDVDD
VOL
to DVDD)
CC
Voltage
VOCDS
tCcDeb
VD3p0
VDSTD
Figure 3. Timing Diagram for tCcDeb and tCD, Under Persistent Fault Condition
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SLVSDJ5D – AUGUST 2016 – REVISED JANUARY 2018
Enabled
Enabled
tSH
GDNG
tVP
Disabled
tVP
Disabled
VDVDD
UFP
VOL
(Pulled high
to DVDD)
Figure 4. Timing Diagram for tSH and tVP, with VBUS Shorted to Ground
Enabled
GDNG
Disabled
VDVDD
UFP
< tON
(Pulled high
VOL
to DVDD)
GD
VPWR
Figure 5. Timing Diagram for tON
Sink
Requests
9V
Sink
Requests
5V
9V
Fastshutdown
Fault
Occurs
5V
VBUS
0V
UFP
GDNG
disabled
enabled
tHR
G5V
GDPG
disabled
enabled
disabled
enabled
Figure 6. Timing Diagram for GDPG, G5V, and GDNG with Fast-Shutdown Fault
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7.8 Typical Characteristics
0.63
650
0.6
625
0.57
600
0.51
I(DSCG) (mA)
V(DSCG) (V)
0.54
0.48
0.45
0.42
575
550
525
500
0.39
475
0.36
450
0.33
0.3
-40
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
425
-40
140
-20
IDSCG = 100 mA
20
40
60
80
100
Junction Temperature (qC)
VDSCG = 4 V
Figure 7. VDSCG when VPWR > 4.65 V
120
140
D005
pulsed testing
Figure 8. IDSCG when VPWR > 4.65 V
10
6.1
VPWR = 5 V, VDD = 0 V
VPWR = 0 V, VDD = 3.3 V
9.5
6.09
9
6.08
8.5
V(FOVP) for 5 V (V)
Supply Current (PA)
0
D004
8
7.5
7
6.5
6
6.07
6.06
6.05
6.04
6.03
5.5
6.02
5
6.01
4.5
-40
-20
0
20
40
60
80
TJ - Junction Temperature (oC)
100
6
-40
120
-20
0
20
40
60
80
100
Junction Temperature (qC)
D001
120
140
D007
CC pins are open
Figure 9. Supply Current when VPWR = 5 V
Figure 10. VFOVP While Supplying 5 V
13.745
10.56
13.74
10.55
V(FOVP) for 12 V (V)
V(FOVP) for 9 V (V)
13.735
10.54
10.53
10.52
13.73
13.725
13.72
13.715
13.71
10.51
13.705
10.5
-40
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
140
D008
Figure 11. VFOVP While Supplying 9 V, TPS25741A
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13.7
-40
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
140
D009
Figure 12. VFOVP While Supplying 12 V, TPS25741
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Typical Characteristics (continued)
16.94
23.1
16.935
V(FOVP) for 15 V (V)
16.93
V(FOVP) for 20 V (V)
16.925
16.92
16.915
16.91
16.905
23.05
23
22.95
16.9
16.895
16.89
-40
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
22.9
-40
140
-20
0
D010
Figure 13. VFOVP While Supplying 15 V, TPS25741A
20
40
60
80
100
Junction Temperature (qC)
120
140
D015
Figure 14. VFOVP While Supplying 20 V, TPS25741
21
31.75
20.98
20.96
20.94
31.65
VI(TRIP) (mV)
VI(TRIP) (mV)
31.7
31.6
31.55
20.92
20.9
20.88
20.86
20.84
31.5
20.82
31.45
-40
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
20.8
-40
140
5 A enabled
0
20
40
60
80
100
Junction Temperature (qC)
120
140
D011
3 A enabled
Figure 15. VITRIP When VPWR > 4.65 V
Figure 16. VITRIP When VPWR > 4.65 V
5.5
5.5
VBUS
DVDD
UFP
5
4.5
VBUS
DVDD
UFP
5
4.5
4
4
3.5
3.5
Voltage (V)
Voltage (V)
-20
D016
3
2.5
2
3
2.5
2
1.5
1.5
1
1
0.5
0.5
0
0
0
0.05
0.1
Time (s)
0.15
0.2
D012
Sink attached at time 0
UFP pulled up to DVDD
Figure 17. DVDD and UFP Upon Sink Attachment
Copyright © 2016–2018, Texas Instruments Incorporated
-0.5
-0.2
-0.15
-0.1
-0.05
0
0.05
Time (s)
0.1
0.15
0.2
0.25
D013
Sink detached at time 0.19s
Sleep mode entered at time 0.39s.
UFP pulled up to DVDD
Figure 18. DVDD and UFP Upon Sink Attachment
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Typical Characteristics (continued)
14
VBUS
CC1/VCONN
CC2/CC
12
Voltage (V)
10
8
6
4
2
0
0
0.1
0.2
0.3
0.4
Time (s)
0.5
0.6
0.7
D001
VDD = 5 V
Figure 19. VBUS, CC1, and CC2 Upon Attachment
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8 Detailed Description
8.1 Overview
The TPS25741/TPS25741A and supporting circuits perform the functions required to implement a USB Power
Delivery 2.0 Power Delivery as a provider-only and a USB Type-C revision 1.2 source. It uses its CC pins to
detect the attachment of a sinking device or upward facing port (UFP) and to determine which of CC1 or CC2 is
connected to the CC wire of the cable. It will then communicate over the CC wire in the cable bundle using USB
Power Delivery to offer a set of voltages and currents. USB Power Delivery is a technology that utilizes the
ubiquitous USB communications and hardware infrastructure to extend the amount of power available to devices
from the 7.5 W range for USB BC1.2 to as high as 100 W in a dock. It is a compatible overlay to USB 2.0 and
USB 3.0, coexisting with the existing 5 V powered universe of devices by use of adapter cables. Some basic
characteristics of this technology relevant to the TPS25741/TPS25741A include:
• Increased power achieved by providing higher current and/or higher voltage.
• New 3 A cable and 5 A connector to support greater than the traditional 1.5 A.
– Cables have controlled voltage drop
• Voltages greater than 5 V are negotiated between Power Delivery partners.
– Standard 5 V is always the default source voltage.
– Voltage and current provisions are negotiated between Power Delivery partners.
• Power Delivery partners negotiate over the CC line to avoid conflict with existing signaling (that is, D+, D-)
• Layered communication protocol defined including PHY, Protocol Layer, Policy Engine, and Device Policy
Manager all implemented within the TPS25741/TPS25741A.
• The Type-C connector standard implements pre-powerup signaling to determine:
– Connector orientation
– Source 5-V capability
– Detect through connection of a UFP (upward facing port) to a DFP (downward facing port)
– Detection of when the connected UFP is disconnected. VBUS is unpowered until a through-connection is
present
Figure 20, Figure 21, and Figure 22 show typical configurations for the TPS25741/TPS25741A.
RS
4.65 V ± 25 V
10:
Gate Driver
Disable
GD
ISNS
DSCG
VBUS
VIO
VAUX
DVDD
Port
Status
CDVDD
Voltage/Current
settings
CC1
CC2
DEBUG
AUDIO
POL
UFP
CVAUX
GND
AGND
CVCONN
4.65V ± 5.5V
VTX
G5V
GDPG
VCONN
VDD
Gate
Drivers
TPS25741 /
TPS25741A
CVTX
VPWR
CTL1
CTL2
GDNG
GDNS
RDSCG
PSEL
HIPWR
PCTRL
EN9V/EN12V
CSLEW
Power Supply
RSLEW
USB Type-C
Receptacle
10:
VBUS
Copyright © 2016, Texas Instruments Incorporated
Figure 20. Reference Schematic 1
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Overview (continued)
RS
4.65 V ± 5.5 V
10:
VBUS
USB Type-C
Receptacle or Plug
Power Supply
12V or 20V (TPS25741)
9V or 15V (TPS25741A)
10:
DSCG
VBUS
ISNS
GDPG
G5V
CVCONN
VPWR
GDNG
GDNS
CSLEW
RDSCG
RSLEW
VCONN
CC1
CC2
Gate Driver
Disable
TPS25741 / GD
TPS25741A DEBUG
AUDIO
POL
UFP
Port
Status
CDVDD
CVAUX
Voltage/Current
settings
DVDD
VAUX
VTX
CVTX
GND
AGND
VDD
VIO
PSEL
HIPWR
PCTRL
EN9V/EN12V
CTL1
CTL2
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Reference Schematic 2
RS
4.65 V ± 25 V
VBUS
DSCG
VBUS
RDSCG
ISNS
GDNG
GDNS
CC1
CC2
GD
Gate Driver
Disable
VIO
Port
Status
CDVDD
CVAUX
CVTX
Voltage/Current
settings
VAUX
DVDD
DEBUG
AUDIO
POL
UFP
VTX
CVCONN
4.65V ± 5.5V
G5V
GDPG
VCONN
VDD
GND
AGND
Gate
Drivers
TPS25741 /
TPS25741A
PSEL
HIPWR
PCTRL
EN9V/EN12V
CSLEW
Power Supply
VPWR
CTL1
CTL2
USB Type-C
Plug
10m:
RSLEW
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Reference Schematic 3
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Overview (continued)
8.1.1 VBUS Capacitance
The USB Type-C specification requires that the capacitance on the VBUS pin of an empty receptacle be below 10
µF. This is to protect legacy USB sources that are not designed to handle the larger inrush capacitance and
which may be connected via an A-to-C cable. For applications with USB Type-C receptacles and large bulk
capacitance, this means back-to-back blocking FETs are required as shown in Figure 20. However, for
applications with a USB Type-C plug this requirement does not apply since an adaptor cable with a USB Type-C
receptacle and a Type-A plug is not defined or allowed by the USB I/F.
8.1.2 USB Data Communications
The USB Power Delivery specification requires that sources such as the TPS25741/TPS25741A advertise in the
source capabilities messages they transmit whether or not they are in a product that supports USB data
communications. The TPS25741/TPS25741A is designed for systems with data communication, so it has this bit
hard-coded to 1.
8.2 Functional Block Diagram
HV
Analog
Drivers
Power
Path
Override
Power
Inputs
VPWR
GND
AGND
VDD
VBUS
ISNS
GD
G5V
GDPG
GDNS
GDNG
DSCG
Monitor
OVP, OCP
Analog Drivers
VTX
DVDD
VAUX
Power Mgmt
Internal
Power
Rails
ILIM
Pullup
Digital
Control Logic
BB
Modem
EN9V/
EN12V
HIPWR
PSEL
Level
Detecters
Configuration
Inputs
VIO
VCONN
CC1
CC2
Type-C
Interface
PCTRL
COMP
POL
AUDIO
DEBUG
UFP
CTL2
CTL1
Oscillator
Digital
Outputs
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
This section describes the features associated with each pin for the TPS25741 and TPS25741A.
8.3.1 USB Type-C CC Logic (CC1, CC2)
The TPS25741/TPS25741A uses a current source to implement the pull up resistance USB Type-C requires for
Sources. While waiting for a valid connection, the TPS25741/TPS25741A applies a default pullup of IRPSTD. A
sink attachment is detected when the voltage on one (not both) of the CC pins remains between VRDSTD and
VDSTD for tCcDeb and the voltage on the VBUS pin is below VBUS_FTH. Then after turning on VBUS and disabling
the Rp current source and applying VCONN to the CCx pin not connected through the cable, the
TPS25741/TPS25741A applies IRP3.0 to advertise 3A to non-Power Delivery sinks. Finally, if it is determined that
the attached sink is Power Delivery-capable, the TPS25741/TPS25741A applies IRP1.5. During this sequence if
the voltage on the monitored CC pin exceeds the detach threshold then the TPS25741/TPS25741A removes
VBUS and begins watching for a sink attachment again.
The TPS25741 or TPS25741A digital logic selects the current source switch as illustrated in Figure 23.
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Feature Description (continued)
VD3.0
Digital Control Logic
VD1.5
IRPSTD
VDSTD
IRP1.5
IRP3.0
VRD3.0
CCx
VRD1.5
Digital Control Logic
VRDSTD
Figure 23. USB Type-C Rp Current Sources and Detection Comparators
If the voltage on both CC pins remains above VRDSTD for tCcDeb, then the TPS25741 or TPS25741A goes to the
sleep mode. In the sleep mode a less accurate current source is applied and less accurate comparator watches
for attachment (see VWAKE, and IDSDFP).
8.3.2 9.3.2 VCONN Supply (VCONN, CC1, CC2)
Once a sink attachment is detected and the power supply is ready, the TPS25741/TPS25741A applies VCONN
to either CC1 or CC2. VCONN is passed through to whichever of CC1 or CC2 is not connected to the sink via
the CC wire in the cable.
RDSON
CC1
VCONN
Cable
VCONN
CC2
CC
CC
Sink
IOS
Current Limit
Gate Control
Digital
Control Logic
Figure 24. VCONN Current-Limiting Switch
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Feature Description (continued)
8.3.3 USB Power Delivery BMC Transmission (CC1, CC2, VTX)
An example of the BMC signal, specifically the end of the preamble and beginning of start-of-packet (SOP) is
shown below. There is always an edge at the end of each bit or unit interval, and ones have an edge half way
through the unit interval.
Preamble
0
1
0
1
0
SOP.Sync1
1
0
1
0
0
0
SOP.Sync2
1
1
0
0
0
1
1
Data in
BMC
Figure 25. BMC Encoded End of Preamble, Beginning of SOP
While engaging in USB Power Delivery communications, the TPS25741 or TPS25741A is applying IRP1.5 or IRP3.0,
so the CC line has a DC voltage of 0.918 V or 1.68 V, respectively. When the BMC signal is transmitted on the
CC line, the transmitter overrides this DC voltage as shown in Figure 26. The transmitter bias rail (VTX) is
internally generated and may not be used for any other purpose in the system. The VTX pin is only high while
the TPS25741 or TPS25741A is transmitting a USB Power Delivery message.
VTXHI
DC Bias
DC Bias
VTXLO
VTXHI
DC Bias
DC Bias
VTXLO
Figure 26. USB Power Delivery BMC Transmission on the CC Line
The device transmissions meet the eye diagram requirements from USB Power Delivery in Documentation
Support. Figure 27 shows the transmitter schematic.
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Feature Description (continued)
To Receiver
CC1
RTX
Driver
CC2
ZDRIVER
Digital Control
Logic
Copyright © 2016, Texas Instruments Incorporated
Figure 27. USB Power Delivery BMC Transmitter Schematic
The transmit eye diagram shown in Figure 29 was measured using the test load shown in Figure 28 with a CLOAD
within the allowed range. The total capacitance CLOAD is computed as:
CLOAD = CRX + CCablePlug x 2 + Ca + CReceiver
(1)
Where:
• 200 pF < CRX < 600 pF
• CCablePlug < 25 pF
• Ca < 625 pF
• 200 pF < CReceiver < 600 pF
Therefore, 400 pF < CLOAD < 1850 pF.
CCx
5.1NŸ
CLOAD
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Test Load for BMC Transmitter
Figure 29 shows the transmit eye diagram for the TPS25741 and TPS25741A.
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Feature Description (continued)
Figure 29. Transmit Eye Diagram (BMC)
The transmitter bias rail (VTX) is internally generated and may not be used for any other purpose in the system.
Connect a 0.1-µF capacitor to GND from this pin. The VTX pin is only high while the TPS25741/TPS25741A is
transmitting a USB Power Delivery message.
8.3.4 USB Power Delivery BMC Reception (CC1, CC2)
The TPS25741 or TPS25741A BMC receiver follows the requirements in Application Information using the
schematic shown in Figure 30.
To Transmitter
VRXHI
CC1
Low-Pass
Filter
CC2
Digital Control
Logic
VRXLO
Figure 30. USB Power Delivery BMC Receiver Schematic
The device low-pass filter design and receiver threshold design allows it to reject interference that may couple
onto the CC line from a noisy VBUS power supply or any other source.
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Feature Description (continued)
8.3.5 Discharging (DSCG, VPWR)
The DSCG pin allows for two different pull-downs that are used to apply different discharging strengths. In
addition, a load may be applied to the VPWR pin to discharge the power supply.
If too much power is dissipated by the device (that is, the TJ1 temperature is exceeded) an OTSD occurs that
disables the discharge FET; therefore, an external resistor is recommended in series with the DSCG pin to
absorb most of the dissipated power. The external resistor RDSCG should be chosen such that the current sunk by
the DSCG pin does not exceed IDSCGT.
The VPWR pin should always be connected to the supply side (as opposed to the connector side) of the powerpath switch (Figure 31 shows one example). This pin is monitored before enabling the GDNG gate driver to apply
the voltage to the VBUS pin of the connector.
From sink attachment, and while the device has not finalized a USB Power Delivery contract, the device applies
RDSCGB.
Also from sink attachment, and while the device has not finalized a USB Power Delivery contract, the device
draws ISUPP through the VPWR pin even if VDD is above its UVLO. This helps to discharge the power supply
source bulk capacitance.
Power Supply
VBUS
10:
DSCG
GDNS
GDNG
VPWR
RSLEW CSLEW
RDSCG
DSCG Control
RDSCGB
See IDSCGSAT &
VDSCGSAT
Copyright © 2016, Texas Instruments Incorporated
Figure 31. Discharge Schematic
The discharge procedure used in the TPS25741 or TPS25741A is intended to allow the DSCG pin to help pull
the power supply down from high voltage, and then also pull VBUS at the connector down to the required level
quickly (refer to USB Power Delivery in Documentation Support).
8.3.5.1 Discharging after a Fault (VPWR)
There are two types of faults that cause the TPS25741 or TPS25741A to begin a full discharge of VBUS: Slowshutdown faults and fast-shutdown faults. When a slow-shutdown fault occurs, the device does not disable
GDNG until after VBUS is measured below VSOVP (for 5 V contract). When a fast-shutdown fault occurs, the
device disables GDNG immediately and then discharges the connector side of the power-path. In both cases, the
bleed discharge is applied to the DSCG pin and ISUPP is drawn from the VPWR pin.
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Feature Description (continued)
Slow-shutdown faults that do not include transmitting a hard reset:
• Receiving a Hard Reset signal (25 ms < tShutdownDelay < 35 ms)
• Cable is unplugged (tShutdownDelay < 20 µs)
Slow-shutdown faults that include transmitting hard reset (25 ms < tShutdownDelay < 35 ms)
• TJ exceeds TJ1 (an overtemperature event)
• Low voltage alarm occurring outside of a voltage transition
• High voltage alarm occurring outside of a voltage transition (but not high enough to cause OVP)
• Receiving an unexpected message during a voltage transition
• Failure of power supply to transition voltages within required time of 600 ms (tPSTransition [refer to USB
Power Delivery in Documentation Support]).
• A Soft Reset USB Power Delivery message is not acknowledged or Accepted (as required per USB Power
Delivery in Documentation Support).
• A Request USB Power Delivery message is not received in the required time (as required per USB Power
Delivery in Documentation Support).
• Failure to discharge down to 0.725 V after a fault of any kind.
Fast-shutdown faults (hard reset always sent):
• Fast OVP event occurring at any time.
• OCP event occurring at any time starting from the transmission of the first USB Power Delivery message.
– VBUS falling below VBUS_FTH is treated as an OVP event.
• GD falling edge
The DSCG pin is used to discharge the supply line after a slow-shutdown fault occurs. Figure 32 illustrates the
signals involved. Depending on the specific slow-shutdown fault the time tShutdownDelay in Figure 32 is different as
indicated in the list above. If the slow-shutdown fault triggers a hard reset, it is sent at the beginning of the
tShutdownDelay period. However, the device behavior after the time tShutdownDelay is the same for all slow-shutdown
faults. After the tShutdownDelay period, the device sets CTL1 and CTL2 to select 5 V from the power supply and puts
the DSCG pin into its ON state (Full Discharge). This discharging continues until the voltage on the VBUS pin
reaches VSOPV (for 5 V contract). The device then disables GDNG and again puts the DSCG pin into its ON
state. This discharging state lasts until the voltage on VBUS reaches 0.725 V (nominal). If the discharge does not
complete within 650 ms, then the device sends a Hard Reset signal and the process repeats. In Figure 32, the
times labeled as T20->5 and T5->0 can vary, they depend on the size of the capacitance to be discharged and the
size of the external resistor between the DSCG pin and VBUS. The time labeled as TS is a function of how quickly
the NFET opens.
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Feature Description (continued)
20 V
5V
VPWR
20 V
5V
VBUS
< 0.8 V
NFET enabled (closed)
GDNG
GDPG
NFET disabled (open)
PFET enabled (closed)
G5V
PFET disabled (open)
NFET disabled (open)
TS
Bleed
only
Full
discharge
DSCG
T20->5
T5->0
High-z
CTL1/2
Low
tShutdownDelay
Time bounded by 650 ms
(tSafe0V)
SlowShutdown
Fault occurs
Figure 32. Illustration of Slow-Shutdown VBUS Discharge
Figure 33 illustrates a similar discharge procedure for fast-shutdown faults. The main difference from Figure 32 is
that the NFET is opened immediately. It is assumed for the purposes of this illustration that the power supply
output capacitance (that is, CSOURCE in the reference schematics shown in Figure 20 and Figure 21) is not
discharged by the power supply itself, but the VPWR pin is bleeding current from that capacitance. The VPWR
pin then draws ISUPP after GDNG disables the external NFET. So, as shown in the figure, the VPWR voltage
discharges slowly, while the VBUS pin is discharged quickly once the full discharge is enabled. If the voltage on
the VPWR pin takes longer than T20->5 + T5->0 + 0.765s to discharge below VFOVP, then it causes an OVP event
and the process repeats.
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Feature Description (continued)
20 V
5V
VPWR
20 V
5V
VBUS
< 0.8 V
NFET closed
GDNG
NFET open
GDPG
PFET open
PFET closed
G5V
NFET disabled
Bleed
only
TS
Full
discharge
DSCG
T20->5
T5->0
High-z
CTL1/2
Low
tPSHardReset
FastShutdown
Fault occurs
Hard
Reset
Sent
Time bounded by 650 ms
(tSafe0V)
Figure 33. Illustration of Fast-Shutdown Discharge
If the discharge does not complete successfully it is treated as a slow-shutdown fault, and the TPS25741 or
TPS25741A repeats the discharge procedure until it does complete successfully. Once the discharge completes
successfully as described above (that is, VBUS on connector is below 0.725 V), the device waits for 0.765 s
(nominal) before trying to source VBUS again.
8.3.6 Configuring Voltage Capabilities (HIPWR, EN9V, EN12V)
The voltages advertised to USB Power Delivery-capable sinks can be configured to one of four different sets.
The EN12V, or EN9V pin is not envisioned to be changed dynamically in the system, so changing its state does
not trigger sending source capabilities. However, the TPS25741 or TPS25741A checks the status of the pin each
time before it sends a source capabilities message using USB Power Delivery. Note that changing the state of
the PCTRL pin forces capabilities to be re-transmitted. The device reads the HIPWR pin after a reset and latches
the result.
Table 1. Voltage Programming (TPS25741)
HIPWR PIN
VOLTAGES ADVERTISED via USB POWER
DELIVERY [V]
High
Connected to DVDD or GND directly
5, 12, 20
High
Connected to DVDD or GND via RSEL
5, 12
Low
Connected to DVDD or GND directly
5, 20
EN12V PIN
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Feature Description (continued)
Table 1. Voltage Programming (TPS25741) (continued)
EN12V PIN
HIPWR PIN
VOLTAGES ADVERTISED via USB POWER
DELIVERY [V]
Low
Connected to DVDD or GND via RSEL
5
Table 2. Voltage Programming (TPS25741A)
EN9V PIN
HIPWR PIN
VOLTAGES ADVERTISED via USB POWER
DELIVERY [V]
High
Connected to DVDD or GND directly
5, 9, 15
High
Connected to DVDD or GND via RSEL
5, 9
Low
Connected to DVDD or GND directly
5, 15
Low
Connected to DVDD or GND via RSEL
5
8.3.7 Configuring Power Capabilities (PSEL, PCTRL, HIPWR)
The power advertised to non-Power Delivery Type-C Sinks is always 15 W. However, the TPS25741 or
TPS25741A only advertises Type-C default current until it debounces the Sink attachment for tCcDeb and the
VBUS voltage has been given tVP to stabilize.
The device does not communicate with the cable to determine its capabilities. Therefore, unless the device is in
a system with a USB Type-C plug and a cable built to support 5 A, the HIPWR pin should be used to limit the
advertised current to 3 A.
PCTRL is an input pin used to control how much of the maximum allowed power the port will advertise. This pin
may be changed dynamically in the system and the device automatically updates any existing USB Power
Delivery contract. If the PCTRL pin is pulled below VPCTRL_TH, then the source capabilities offers half of the
maximum power specified by the PSEL pin.
The devices read the PSEL and HIPWR pins after a reset and latches the result, but the PCTRL pin is read
dynamically by the device and if its state changes new capabilities are calculated and then transmitted.
While USB Power Delivery allows a maximum power of 100 W, the TPS25741 only advertises up to 93 W, which
allows margin to ensure the output power remains below 100 W.
The PSEL pin offers four possible maximum power settings, but the devices can actually advertise more power
settings depending upon the state of the HIPWR and PCTRL pins. Table 3 summarizes the four maximum power
settings that are available via PSEL, again note this is not necessarily the maximum power that is advertised.
Table 3. PSEL Configurations
MAXIMUM POWER
(PSEL) [W]
PSEL
PSEL = 36
Direct to GND
PSEL = 45
DVDD via RSEL
PSEL = 65
GND via RSEL
PSEL = 93
Direct to DVDD
The following list provides a quick reference which applies to both TPS25741 and TPS25741A to see how the
HIPWR, PSEL, and PCTRL pins affect what current is advertised with each voltage in the source capabilities
message:
• If the PCTRL pin is low, then Pmax = PSEL/2
• If the PCTRL pin is high, then Pmax = PSEL.
• If the HIPWR pin is pulled high, then Imax = 3 A.
• If the HIPWR pin is pulled low, then Imax = 5 A.
• For a voltage Vx, the advertised current is Ix
– Ix = min( Pmax/Vx, Imax)
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Table 4 and Table 5 provide a comprehensive list of the currents and voltages that are advertised for each
voltage.
Table 4. Maximum Current Advertised in the Power Data Object for a Given Voltage (TPS25741)
MAXIMUM CURRENT
PCTRL = LOW [A]
MAXIMUM CURRENT
PCTRL = HIGH [A]
Direct to GND
3
3
DVDD via RSEL
3
3
3
3
3
3
1.5
3
1.87
3
2.7
3
PSEL
GND via RSEL
VOLTAGE [V]
5
Max = 3 A
DVDD through
RSEL or Direct to
DVDD
Direct to DVDD
Direct to GND
DVDD via RSEL
GND via RSEL
HIPWR
12
Direct to DVDD
3
3
Direct to GND
0.9
1.8
1.12
2.24
1.62
3
Direct to DVDD
2.32
3
Direct to GND
3.6
5
DVDD via RSEL
4.5
5
5
5
5
5
DVDD via RSEL
GND via RSEL
GND via RSEL
20
5
Max = 5 A
GND through
RSEL or Direct to
GND
Direct to DVDD
Direct to GND
DVDD via RSEL
GND via RSEL
Max = 3 A
Direct to DVDD
12
1.5
3
1.87
3.74
2.7
5
Direct to DVDD
4.16
5
Direct to GND
0.9
1.8
1.12
2.24
1.62
3.24
2.32
4.64
DVDD via RSEL
GND via RSEL
20
Max = 5 A
Direct to GND
Direct to DVDD
Table 5. Maximum Current Advertised in the Power Data Object for a Given Voltage (TPS25741A)
MAXIMUM CURRENT
PCTRL = LOW [A]
MAXIMUM CURRENT
PCTRL = HIGH [A]
Direct to GND
3
3
DVDD via RSEL
3
3
3
3
3
3
2
3
2.5
3
3
3
PSEL
GND via RSEL
VOLTAGE [V]
5
Max = 3 A
DVDD through
RSEL or Direct to
DVDD
Direct to DVDD
Direct to GND
DVDD via RSEL
GND via RSEL
HIPWR
9
Direct to DVDD
3
3
Direct to GND
1.2
2.4
1.5
3
2.17
3
3
3
DVDD via RSEL
GND via RSEL
15
Max = 3 A
Direct to DVDD
Direct to DVDD
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Table 5. Maximum Current Advertised in the Power Data Object for a Given Voltage
(TPS25741A) (continued)
PSEL
VOLTAGE [V]
HIPWR
MAXIMUM CURRENT
PCTRL = LOW [A]
MAXIMUM CURRENT
PCTRL = HIGH [A]
3.6
5
4.5
5
5
5
5
5
Direct to GND
DVDD via RSEL
GND via RSEL
5
Max = 5 A
GND through
RSEL or Direct to
GND
Direct to DVDD
Direct to GND
DVDD via RSEL
GND via RSEL
9
2
4
2.5
5
3.61
5
Direct to DVDD
5
5
Direct to GND
1.2
2.4
DVDD via RSEL
GND via RSEL
Max = 5 A
Direct to GND
15
Direct to DVDD
1.5
3
2.17
4.34
3.1
5
8.3.8 Gate Drivers
8.3.8.1 GDNG, GDNS
The GDNG and GDNS pins may control a single NFET or back-to-back NFETs in a common-source
configuration. The GDNS is used to sense the voltage so that the voltage differential between the pins is
maintained.
Power Supply
VBUS
10:
Power
Management
Charge
Pump
GDNS
GDNG
Safety
Turnoff
RSLEW CSLEW
See VGDNGON
& IGDNGON
RGDNGOFF
Gate Control
Copyright © 2016, Texas Instruments Incorporated
Figure 34. GDNG/GDNS Gate Control
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8.3.8.2 G5V
The G5V pin may control an external NFET when the TPS25741/TPS25741A is used in a power multiplexor
configuration, where one of two voltage inputs is connected to the VBUS pin. When G5V is not used to control
an NFET, then it can be used to indicate if VBUS is being sourced at 5 V or not.
Power Supply
VBUS
G5V
See VG5VON
& IG5VON
Safety
Turnoff
Power
Management
RG5VOFF
Charge
Pump
Gate Control
Copyright © 2016, Texas Instruments Incorporated
Figure 35. G5V Gate Control
8.3.8.3 GDPG
The GDPG pin may control an external PFET (single or back-to-back) when the TPS25741/TPS25741A is used
in a power multiplexor configuration, where one of two voltage inputs is connected to the VBUS pin. When not
used to control a PFET, this pin may be used to indicate when VBUS is being sourced at more than 5 V.
Power Supply
CSLP
RPPU
GDPG
CPPU
VBUS
Power
Management
IGDPG
Copyright © 2016, Texas Instruments Incorporated
Figure 36. GDPG Gate Control
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8.3.9 Fault Monitoring and Protection
8.3.9.1 Over/Under Voltage (VBUS)
The TPS25741 or TPS25741A uses the VBUS pin to monitor for overvoltage or undervoltage conditions and
implement the fast-OVP, slow-OVP, and slow-UVP features.
VBUS
VBUS
VFOVP
Deglitch
tFOVPDG
GDNG
Control
Sampled every 1ms
Digital
Control
Sampled every 1ms
Digital
Control
VSOVP
VSUVP
Figure 37. Voltage Monitoring Circuits
If an over-voltage condition is sensed by the Fast OVP mechanism, GDNG is disabled within tFOVP + tFOVPDG,
then a Hard Reset is transmitted and the VBUS discharge sequence is started. At power up the voltage trip point
is set to VVFOVP (5 V contract). When a contract is negotiated the trip point is set to the corresponding VFOVP
value.
The devices employ another slow over-voltage protection mechanism as well that sends the Hard Reset before
disabling the external NFET. It catches many OV events before the Fast OVP mechanism. During intentional
positive voltage transitions, this mechanism is disabled (see Figure 1). However, tVP after the external NFET has
been enabled if the voltage on the VBUS pin exceeds VSOVP, a Hard Reset is transmitted to the Sink then the
VBUS discharge sequence is started. Once a Power Delivery contract has been negotiated, if the voltage on the
VBUS pin exceeds the selected voltage threshold (VSOVP) a Hard Reset is transmitted to the Sink then the VBUS
discharge sequence is started.
The devices employ a slow under-voltage protection mechanism as well that sends the Hard Reset before
disabling GDNG. During intentional negative voltage transitions, this mechanism is disabled (see Figure 1).
However, tVP after the external NFET has been enabled if the voltage on the VBUS pin falls below VSUVP, a Hard
Reset is transmitted to the Sink then the VBUS discharge sequence is started..
8.3.9.2 Over-Current Protection (ISNS, VBUS)
OCP protection is enabled tVP after the voltage on the VBUS pin has exceeded VBUS_RTH, see Figure 38. Prior to
OCP being enabled, the GD pin can be used to protect against a short.
The OCP protection circuit monitors the differential voltage across an external sense resistor to detect when the
current outflow exceeds VITRIP which in turn activates an over-current circuit breaker and disables the GDNG /
GDNS gate driver. Once the OCP is enabled, if the voltage on the VBUS pin falls below VBUS_FTH then that is
also treated like an OCP event.
Following the recommended implementation of a 5 mΩ sense resistor, when the device is configured to deliver 3
A (via HIPWR pin), the OCP threshold lies between 3.8 A and 4.5 A. When configured to deliver 5 A (via HIPWR
pin), the OCP threshold lies between 5.8 A and 6.8 A. The sense resistor may be increased to tighten the OCP
threshold.
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5m:
Power Supply
VBUS
ISNS
VBUS
VBUS_TH
GDNG
Control
VITRIP
Deglitch
tOCP
OCP Control
Logic
Copyright © 2016, Texas Instruments Incorporated
Figure 38. Overcurrent Protection Circuit
8.3.9.3 System Fault Input (GD, VPWR)
The gate-driver disable pin provides a method of overriding the internal control of GDNG and GDNS. A falling
edge on GD disables the gate driver within tGDoff. If GD is held low after a sink is attached for 600 ms then a hard
reset will be generated and the device sends a hard reset and goes through its startup process again.
The GD input can be controlled by a voltage or current source. An internal voltage clamp is provided to limit the
input voltage in current source applications. The clamp can safely conduct up to 80 µA and will remain high
impedance up to VGDC before clamping.
GD
GDNG
Control
VGD_TH
RGD
Deglitch
tGDoff
VGDC
Copyright © 2016, Texas Instruments Incorporated
Figure 39. Overcurrent Protection Circuit
If the VPWR pin remains below its falling UVLO threshold (VPWR_TH) for more than 600 ms after a sink is
attached then the devices consider it a fault and will not enable GDNG. If the VPWR pin is between the rising
and falling UVLO threshold, the TPS25741/TPS25741A may enable GDNG and proceed with normal operations.
However, after GDNG is enabled, if the VBUS pin does not rise above its UVLO within 190 ms the devices
consider it a fast-shutdown fault and disables GDNG. Therefore, in order to ensure USB Type-C compliance and
normal operation, the VPWR pin must be above its rising UVLO threshold (VPWR_TH) within 275 ms of when UFP
is pulled low and the VBUS pin must be above VBUS_RTH within 190 ms of GDNG being enabled.
8.3.10 Voltage Control (CTL1, CTL2)
CTL1 and CTL2 are open-drain output pins used to control an external power supply as summarized in Table 6.
Depending upon the voltage requested by the sink, the device sets the CTL pins accordingly. No current flows
into the pin in its high-z state.
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Table 6. States of CTL1 and CTL2 as a Function of Target Voltage on VBUS for TPS25741 and
TPS25741A
VOLTAGE CONTAINED in PDO
REQUESTED by UFP
CTL2 STATE
CTL1 STATE
5V
High-z
High-z
9 V (TPS25741A)
Low
High-z
12 V (TPS25741)
Low
High-z
15 V (TPS25741A)
Low
Low
20 V (TPS25741)
Low
Low
8.3.11 Sink Attachment Indicator (UFP, DVDD)
UFP is an open-drain output pin used to indicate the status of the port. It is high-z unless a sink is attached to the
port, in which case it is pulled low. A sink attachment is detected when the voltage on one (not both) of the CC
pins remains between VRDSTD and VDSTD for tCcDeb and the voltage on the VBUS pin is below VBUS_FTH. After
being pulled low, UFP remains low until the sink has been removed for tCcDeb.
DVDD is a power supply pin that is high-z until a sink is attached, in which case it is pulled high. Therefore, it can
be used as a sink attachment indicator that is active high. However, DVDD will also be high when an Audio or
Debug accessory is attached. See Figure 18 for typical behavior.
8.3.12 Accessory Attachment Indicator (AUDIO, DEBUG)
AUDIO is an open-drain output pin used to indicate the attachment of a USB Type-C audio accessory. After both
CC1 and CC2 are pulled below VRDSTD for at least tCcDeb, AUDIO is pulled low until at least one of the CC pins
rises above VRDSTD for at least tCcDeb.
DEBUG is an open-drain output pin used to indicate the attachment of a USB Type-C debug accessory. After
both CC1 and CC2 are between VDSTD and VRDSTD for at least tCcDeb, DEBUG is pulled low until at least one of
the CC pins rises above VDSTD or below VRDSTD. This complies with the USB Type-C version 1.1 debug
accessory detection.
8.3.13 Plug Polarity Indication (POL)
The POL pin is pulled low when the CC wire in the attached USB Type-C cable is connected to the CC2 pin. This
pin is open-drain if the attached cable has the opposite polarity or if nothing is attached.
8.3.14 Power Supplies (VAUX, VDD, VPWR, DVDD)
The VAUX pin is the output of a linear regulator and the input supply for internal power management circuitry.
The VAUX regulator draws power from VDD after establishing a USB Power Delivery contract unless it is not
available in which case it draws from VPWR. Changes in supply voltages will result in seamless switching
between supplies.
If there is a load on the DVDD pin, that current will be drawn from the VPWR pin unless the
TPS25741/TPS25741A has stabilized into a USB Power Delivery contract or VPWR is below its UVLO.
The TPS25741/TPS25741A cannot function properly until VPWR is above its UVLO. However, for improved
system efficiency when UFP is high-z, VPWR can be low (the high voltage power supply can be disabled) if VDD
is above its UVLO.
Connect a 0.1-µF ceramic capacitor from VAUX to GND. Do not connect any external load that draws more than
IVAUXEXT. Locate the bypass capacitor close to the pin and provide a low impedance ground connection from the
capacitor to the ground plane.
VDD should either be grounded or be fed by a low impedance path and have input bypass capacitance. Locate
the bypass capacitors close to the VDD and VPWR pins and provide a low impedance ground connection from
the capacitor to the ground plane.
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VPWR
VDD
Power Supply
VAUX
0.1PF
Power Management
DVDD
0.22PF
Copyright © 2016, Texas Instruments Incorporated
Figure 40. Power Management
8.3.15 Grounds (AGND, GND)
GND is the substrate ground of the die. Most circuits return to GND, but certain analog circuitry returns to AGND
to reduce noise and offsets. The power pad (on those devices that possess one) is electrically connected to
GND. Connect AGND, GND and the power pad (if present) to the ground plane through the shortest and most
direct connections possible.
8.3.16 Output Power Supply (DVDD)
The DVDD pin is the output of an internal 1.85 V linear regulator, and the input supply for internal digital circuitry.
This regulator normally draws power from VPWR until a USB Power Delivery contract has stabilized, but will
seamlessly swap to drawing power from VDD in the event that VPWR drops below its UVLO threshold. External
circuitry can draw up to 35 mA from DVDD. Note that as more power is drawn from the DVDD pin more heat will
be dissipated in the TPS25741/TPS25741A, and if excessive the OTSD could be tripped which will reset the
TPS25741/TPS25741A.
Connect a 0.22-µF or 0.33-µF ceramic capacitor from DVDD to GND (do not exceed this recommended bypass
capacitance value).
Locate the bypass capacitor close to the pin and provide a low impedance ground connection from the capacitor
to the ground plane.
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8.4 Device Functional Modes
8.4.1 Sleep Mode
Many adaptors that include USB Power Delivery must consume very low quiescent power to meet regulatory
requirements (for example “Green”, Energy Star, or the like). The TPS25741/TPS25741A supports the sleep
mode to minimize power consumption when the receptacle or plug is unattached. The TPS25741/TPS25741A
will enter sleep mode when there is no valid plug termination attached; a valid plug termination is defined as one
of: sink, Audio accessory, or Debug accessory. If an active cable is attached but its far-end is left unconnected or
“dangling”, then the TPS25741/TPS25741A will also enter sleep mode. It will exit the sleep mode whenever the
plug status changes. This could be a dangling cable being removed or a sink being connected.
8.4.2 Checking VBUS at Start Up
When first powered up, the TPS25741/TPS25741A will not enable GDNG if the voltage on VBUS is already
above its UVLO. This is a protective measure taken to avoid the possibility of turning on while connected to
another active power supply in some non-compliant configuration.
This means that the VBUS pin must be connected between the power-path NFET and the USB connector. This
also allows for a controlled discharge of VBUS all the way down to the required voltage on the connector (refer to
USB Power Delivery in Documentation Support).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS25741/TPS25741A implements a fully compliant USB Power Delivery 2.0 provider and Type-C source
(also known as downward facing port (DFP)). The TPS25741/TPS25741A basic schematic diagram is shown in
Figure 41. Subsequent sections describe detailed design procedures for several applications with differing
requirements. The TPS25741/TPS25741A Design Calculator Tool (refer to the Documentation Support) is
available for download and use in calculating the equations in the following sections.
CSD17578Q3A (2x)
5mŸ
B340A-13-F
VBUS
100:
6.8µF
560pF
560pF
CC1
CC2
DEBUG
AUDIO
POL
G5V
GDPG
System
100kŸ
VIO
HIPWR
EN12V
0.22µF
DVDD
VAUX
GD
47nF
220kŸ
0.1µF
PCTRL
VTX
VDD
DSCG
VBUS
VCONN
10µF
120Ÿ
24.9Ÿ
TPS25741
Type-C
Connector
D-
PSEL
GND
AGND
CTL1
CTL2
UFP
ISNS
GDNG
0.33µF
VPWR
GDNS
Power
Supply
System
0.1µF
10nF 1kŸ
10Ÿ
10Ÿ
D+
Copyright © 2016, Texas Instruments Incorporated
Figure 41. Basic Schematic Diagram (PSEL = 65 W at 5 V, 12 V, 20 V)
9.1.1 System-Level ESD Protection
System-level ESD (per EN61000-4-2) may occur as the result of a cable being plugged in, or a user touching the
USB connector or cable. Figure 42 shows an example ESD protection for the VBUS path that helps protect the
VBUS pin, ISNS and DSCG pins of the TPS25741/TPS25741A from system-level ESD. The
TPS25741/TPS25741A has ESD protection built into the CC1 and CC2 pins so that no external protection is
necessary. Refer to the layout guidelines section for external component placement and routing
recommendations.
The Schottky diode is to protect against VBUS being drawn below ground by an inductive load, the cable
inductance may be as high as 900 nH.
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Application Information (continued)
VBUS
RS
Type-C
Plug/
Receptacle
DSCG
VBUS
ISNS
RDSCG
CPDIN
DVBUS
TPS25741
TPS25741A
Copyright © 2016, Texas Instruments Incorporated
Figure 42. VBUS ESD Protection
9.1.2
Use of GD Internal Clamp
As described in the Configuring Power Capabilities (PSEL, PCTRL, HIPWR) section, the GD pin has an internal
clamp. Figure 43 shows an example of how it may be used. VOUT is the voltage from a power supply that is to be
provided onto the VBUS wire of the USB Type-C cable through an NFET. If VOUT drops, the NFET should be
automatically disabled by the device. This can be accomplished by tying the GD pin to VOUT via a resistor.
The internal resistance of the GD pin is specified to exceed RGD, and the input threshold is VGD_TH. The GD pin
would therefore draw no more than VGD_TH(max) / RGD(min) < 603 nA. As an example, assume the minimum
value of VOUT for which GD should be high is 4.5 V, then the resistor between GD and VOUT may not exceed
(4.5 – VGD_TH(max) / 603e-9 = 4.5 MΩ. To make it robust against board leakage a smaller resistor such as 1 MΩ
can be chosen, but the smaller the resistance the more leakage current into the GD pin. In this example, when
VOUT is 25 V, the current into the GD pin is (25-VGDC) / 1e6 < 18.5 µA.
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Application Information (continued)
CSD17579Q3A
VBUS
VOUT
Type-C Plug
RS
RDSCG
RSLEW
CRX
CSLEW
1M:
VBUS
DSCG
ISNS
GDNS
GDNG
VPWR
CC1
CC2
TPS25741
TPS25741A
GD
CRX
CPDIN
RG
Copyright © 2016, Texas Instruments Incorporated
Figure 43. Use of GD Internal Clamp
9.1.3 Resistor Divider on GD for Programmable Start Up
Figure 44 shows an alternative usage of the GD pin can help protect against shorts on the VBUS pin in the
receptacle. A resistor divider is used to minimize the time it takes the GD pin to be pulled low. Consider the
situation where the VBUS pin is shorted at startup. At some point, the device closes the NFET switch to supply 5
V to VBUS. At that point, the short pulls down on the voltage seen at the VPWR pin. With the resistor values
shown in Figure 44, once the voltage at the VPWR pin reaches 3.95 V the voltage at the GD pin is specified to
be below VGD_TH(min). Without the 700-kΩ resistor, the voltage at the VPWR pin would have to reach
VGD_TH(min) which takes longer. This comes at the expense of increased leakage current.
CSD17579Q3A
VBUS
VOUT
Type-C Plug
RS
RDSCG
RSLEW
CRX
CSLEW
RGD1
1M:
VBUS
DSCG
ISNS
GDNS
GDNG
VPWR
RGD2
700k:
GD
CRX
CPDIN
RG
TPS25741
TPS25741A
CC1
CC2
Copyright © 2016, Texas Instruments Incorporated
Figure 44. Programmable GD Turn On
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Application Information (continued)
The GD resistor values can be calculated using the following process. First, calculate the smallest RGD1 that
should be used to prevent the internal clamp current from exceeding IGD of 80 µA. For a 20 V advertised voltage,
the OVP trip point could be as high as 24 V. Using VGDC(min) = 6.5 V and VOUT = VFOVP20(max) = 24 V, provides
Equation 2:
V
VGDC
RGD1 ! FOVP20
IGD
24 V 6.5 V
80 $
219 k
(2)
The actual clamping current is less than 80 µA as some current flows into RGD2. Next, RGD2 can be calculated as
follows:
RGD2
RGD1 u
VGD_TH
VVPWR
VGD_TH
(3)
where V(VPWR) = V(PWR_TH) falling (max) and V(GD_TH) = V(GD_TH) falling (min).
For this case, VVPWR = VPWR_TH falling (max) and VGD_TH = VGD_TH falling (min).
9.1.4 Selection of the CTL1 and CTL2 Resistors (RFBL1 and RFBL2)
RFBL1 and RFBL2 provide a means to change the power supply output voltage when switched in by the CTL1 and
CTL2 open drain outputs, respectively. When 12 V is requested by the UFP then CTL2 will go low and place
RFBL2 in parallel with RFBL. When 20 V is requested by the UFP then CTL2 remains low and CTL1 goes low
placing RFBL1 in parallel with RFBL2 and RFBL.
ROB
RFBU
VOUT
TL431
RFBL2
RFBL
CIZ
RFBL1
CTL1
CTL2
Copyright © 2016, Texas Instruments Incorporated
Figure 45. Circuit to Change VOUT Upon Sink/UFP Request
RFBL2 is calculated using Equation 4. In this example, VOUT12 is 12 V and VOUT20 is 20 V. VOUT is the default
output voltage (5 V) for the regulator and is set by RFBU, RFBL, and error amplifier VREF.
RFBL2
RFBL u RFBU u VREF
RFBL u VOUT12 - VREF - RFBU u VREF
(4)
RFBL1 is calculated using the equation below after a standard 1% value for RFBL2 is chosen.
RFBL1
RFBL2 u RFBL
u RFBU u VREF
RFBL2 RFBL
RFBL2 u RFBL
u VOUT20 - VREF - RFBU u VREF
RFBL2 RFBL
(5)
RFBL1 and RFBL2 should be large enough so that the CTL1/CTL2 sinking current is minimized (< 1 mA). The
sinking current for CTL1 and CTL2 is VREF / RFBL1 and VREF/RFBL2 respectively.
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Application Information (continued)
9.1.5 Voltage Transition Requirements
During VBUS voltage transitions, the slew rate (vSrcSlewPos in USB in Documentation Support) must be kept below
30 mV/µs in all portions of the waveform, settle (tSrcSettle) in less than 275 ms, and be ready (tSrcReady in USB in
Documentation Support) in less than 285 ms. For most power supplies, these requirements are met naturally
without any special circuitry but in some cases, the voltage transition ramp rate must be slowed in order to meet
the slew rate requirement.
The requirements for linear voltage transitions are shown in Table 7. In all cases, the minimum slew time is
below 1 ms.
Table 7. Minimum Slew-Rate Requirements
VOLTAGE
TRANSITION
5 V ↔ 12 V
5 V ↔ 20 V
12 V ↔ 20 V
5V↔9V
5 V ↔ 15 V
9 V ↔ 15 V
Minimum Slew
Time
233 µs
500 µs
267 µs
133 µs
333 µs
200 µs
When transition slew control is required, the interaction of the slew mechanism and dc/dc converter loop
response must be considered. A simple R-C filter between the device CTL pins and converter feedback node
may lead to instability under some conditions. Figure 46 shows a method which manages the slew control
without adding capacitance to the converter feedback node.
VCC
VOUT
RCTL2
RSL2A
RCTL1
RSL1A
RFBU
DC/DC
Converter
CTL1
FB
QSL1
QSL2
RFBL
RSL1B
RSL2B
QCTL1
TPS25741
QCTL2
CSL2
RFBL2
CSL1
RFBL1
CTL2
Copyright © 2016, Texas Instruments Incorporated
Figure 46. Slew-Rate Control Example Number 1
When VOUT = 5 V, both CTL1 and CTL2 are in a high impedance state. When a 5 V to 12 V transition is
requested, CTL2 goes low and turns off QCTL2. QSL2 gate starts to rise towards VCC at a rate determined by
RSL2A + RSL2B and CSL2. QSL2 gate continues to rise, until QSL2 is fully enhanced placing RFBL2 in parallel with
RFBL. In similar fashion when CTL1 goes low, QCTL1 turns off allowing RFBL1 to slew in parallel with RFBL2 and
RFBL.
The slewing resistors and capacitor can be chosen using the following equations. VT is the VGS threshold voltage
of QSL1 and QSL2. VREF is the feedback regulator reference voltage. Choose the slewing resistance in the 100 kΩ
range to reduce the loading on the bias voltage source (VCC) and then calculate CSL. The falling transitions are
shorter than the rising transitions in this topology.
Falling transitions:
• 20 V to 12 V
RSL1B u CSL1
'T20V 12V
§ VT VREF ·
§ VT ·
ln ¨
¸ ln ¨
¸
© VVCC ¹
© VVCC ¹
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(6)
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•
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12 V to 5 V
RSL2B u CSL2
'T12V 5V
§V
§ VT ·
VREF ·
ln ¨ T
¸ ln ¨
¸
V
VCC
©
¹
© VVCC ¹
(7)
Rising transitions:
• 5 V to 12 V
RSL2B u CSL2
RSL2A
•
'T5V 12V
§
§ VT VREF ·
VT ·
ln ¨1
¸ ln ¨ 1
¸
V
VVCC ¹
VCC ¹
©
©
(8)
'T12V 20V
§
§ VT VREF ·
VT ·
ln ¨ 1
¸ ln ¨ 1
¸
V
VVCC ¹
VCC ¹
©
©
(9)
12 V to 20 V
RSL1B u CSL1
RSL1A
Some converter regulators can tolerate a balance of capacitance on the feedback node without affecting loop
stability. The LM5175 has been tested using Figure 47 to combine VOUT slewing with a minimal amount of extra
circuitry.
CSLU
FB
CSLL
RFBL2
RFBL1
RFBL
LM5175
RFBU
VOUT
CTL1
TPS25741
CTL2
Copyright © 2016, Texas Instruments Incorporated
Figure 47. Slew-Rate Control Example Number 2
When a higher voltage is requested from TPS25741, CTL1 or CTL2 goes low changing the sensed voltage at the
FB pin. The LM5175 compensates by increasing VOUT. As VOUT increases, CSLU is charged at a rate proportional
to RFBU. Three time constants yield a voltage change of approximately 95% and can be used to calculate the
desired slew time. CSLU can be calculated using Equation 10 and Equation 11.
'TSLEW
CSLU
3 u RFBU u CSLU
'TSLEW
3 u RFBU
(10)
(11)
In order to minimize loop stability effects, a capacitor CSLL in parallel with RFBL is required. The ratio of CSLU/CSLL
should be chosen to match the ratio of RFBL/RFBU. Choose CSLL according to Equation 12.
CSLL
R
CSLU u FBU
RFBL
(12)
All slew rate control methods should be verified on the bench to ensure that the slew rate requirements are being
met when the external VBUS capacitance is between 1 μF and 100 μF.
44
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9.1.6 VBUS Slew Control using GDNG CSLEW
Care should be taken to control the slew rate of Q1 using CSLEW; particularly in applications where COUT >>
CSLEW. The slew rate observed on VBUS when charging a purely capacitive load is the same as the slew rate of
VGDNG and is dominated by the ratio IGDNGON /CSLEW. RSLEW helps block CSLEW from the GDNG pin enabling a
faster transient response to OCP.
Q1
RS
CPDIN
DSCG
VBUS
ISNS
GDNS
GDNG
CF
VPWR
VBUS
RDSCG
CSLEW
RSLEW
CVPWR
DVBUS
RF
RG
VOUT
VDD
TPS25741
Copyright © 2016, Texas Instruments Incorporated
Figure 48. Slew-Rate Control Using GDNG
There may be fault conditions where the voltage on VBUS triggers an OVP condition and then remains at a high
voltage even after the TPS25741 configures the voltage source to output 5 V via CTL1 and CTL2. When this
OVP occurs, the TPS25741 opens Q1 within tFOVP + tFOVPDG. The TPS25741 then issues a hard reset,
discharges the power-path via the RDSCG, and waits for 795 ms before enabling Q1 again. Due to the fault
condition the voltage again triggers an OVP event when the voltage on VBUS exceeds VFOVP. This retry process
would continue as long as the fault condition persists, periodically pulsing up to VFOVP + VSrcSlewPos x (tFOVP +
tFOVPDG) onto the VBUS of the Type-C receptacle. It is recommended to use a slew rate less than the maximum of
VSrcSlewPos (30 mV/µs), refer to Documentation Support section, the slew rate should instead be set in order to
meet the requirement to have the voltage reach the target voltage within tSrcSettle (275 ms) (refer to USB Power
Delivery in Documentation Support). This also limits the out-rush current from the COUT capacitor into the CPDIN
capacitor and helps protect Q1 and RS.
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9.1.7 Tuning OCP Using RF and CF
In applications where there are load transients or moderate ripple on COUT, the OCP performance of TPS25741
or TPS25741A may be impacted. Adding the RF/CF filter network as shown in Figure 49 helps mitigate the impact
of the ripple and load transients on OCP performance.
Q1
RS
RDSCG
CSLEW
RSLEW
DSCG
VBUS
ISNS
GDNS
GDNG
VPWR
CVPWR
CF
VDD
VBUS
CPDIN
DVBUS
RF
RG
VOUT
TPS25741
Copyright © 2016, Texas Instruments Incorporated
Figure 49. ISNS Filtering Example
RF/CF can be tailored to the amount of ripple on COUT as shown in Table 8.
Table 8. Ripple on COUT
46
FREQUENCY x RIPPLE (kHz x V)
SUGGESTED FILTER TIME CONSTANT (µs)
< 5 (Ex: 50 mV ripple at 100 kHz)
None
5 to 15
2.2 µs (RF = 10 Ω, CF = 220 nF)
15 to 35
4.7 µs (RF = 10 Ω, CF = 470 nF)
35 to 105
10 µs (RF = 10 Ω, CF = 1 µF)
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9.2 Typical Applications
9.2.1 A/C Multiplexing Power Source
In this design example, two system power supply voltages are available with a limited power budget. The
TPS25741 can act as a power multiplexer and switch between the two sources when requested. GDNG and G5V
manage the 5-V path and GDPG manages the 12-V path. CTL2 and UFP can be used as optional power supply
ON/OFF for applications where additional power saving is required and the LDO can be used to keep the
TPS25741 powered when the 5-V power supply is off. The following example is based on TPS25741 Power
Multiplexing Introduction and Design Considerations and TPS25741EVM-802 (refer to Documentation Support).
Q2B
CPPU
RPPU
Q2A
CSLP
DQ1B
RS
RF
CRX2
CRX1
VBUS
DSCG
ISNS
CC2
System
HIPWR
PSEL
EN12V
GND
AGND
VIO
CDVDD
Type-C
Connector
D-
RDSCG
RG
G5V
CVTX
CVAUX
UFP
VBUS
D+
CC1
DEBUG
AUDIO
POL
TPS25741
VAUX
PCTRL
VTX
RUFP
CVCONN
GDNS
GDPG
GDNG
CF
VDD
CTL1
CTL2
GD
VCONN
Optional Controls
CPDIN
Q1B
CSLEW RSLEW RG
3.3VDC
LDO
DVBUS
100:
Q1A
5V
DVDD
5VDC
Buck
(18W)
RGD1
LDO is
optional
12V
VPWR
AC-24VDC
Adapter
(36W)
12VDC
Buck
(36W)
CVPWR
24V
RSEL
Copyright © 2016, Texas Instruments Incorporated
Figure 50. 12-V, 5-V Power Multiplexer Schematic
9.2.1.1 Design Requirements
Table 9. Design Parameters
DESIGN PARAMETER
VALUE
Advertised Power Limit
18 W, 36 W
Advertised Voltages
5 V, 12 V
Advertised Current Limit
3A
Over Current Protection Set point
4.2 A
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Power Pin Bypass Capacitors
•
•
•
•
•
•
•
CVPWR: 0.1 μF, 50 V, ±10%, X7R ceramic at pin 25 (VPWR). If VPWR is tied to a lower voltage source, then
the voltage rating of the capacitor can be reduced.
CVDD: 0.1 μF, 10 V, X7R ceramic at pin 22 (VDD). If VDD is not used in the application, then tie VDD to GND.
VDD and VCONN may be connected to the same 5-V supply.
CVCONN: 10 μF, 10 V, X7R ceramic at pin 3 (VCONN). If VCONN is not used in the application, then tie
VCONN to GND. VCONN and VDD may be connected to the same 5-V supply.
CDVDD: 0.22 μF, 10 V, ±10%, X5R ceramic at pin 18 (DVDD)
CVIO: Connect pin 17 (VIO) to DVDD (pin 18)
CVAUX: 0.1 μF, 10 V, ±10%, X7R ceramic at pin 21 (VAUX)
CVTX: 0.1 μF, 10 V, ±10%, X7R ceramic at pin 1 (VTX)
9.2.1.2.2 Non-Configurable Components
•
•
•
•
•
•
RSEL: When the application requires advertisement using RSEL, use a 100 kΩ, ±1% resistor.
RPCTRL: If PCTRL will be pulled low with an external device then it can be connected to VAUX using a 220
kΩ, ±5% resistor. If PCTRL is always high, then it can be directly connected to VAUX.
RSLEW: Use a 1 kΩ, ±1% resistor
RG: Use a 10 Ω, ±1% resistor
RUFP: Use a 220 kΩ, ±5% resistor
RGD1: Use a 1 MΩ, ±1% resistor
9.2.1.2.3 Configurable Components
•
•
•
•
•
•
•
•
•
•
•
•
•
48
CRX: Choose CRX between 200 pF and 600 pF. A 470 pF, 50 V, ±5% COG/NPO ceramic is recommended for
both CC1 and CC2 pins.
Q1A/Q1B: For a 3-A application, an N-Channel MOSFET with RDS(on) in the 10 mΩ range is sufficient. BVDSS
should be rated for 30 V for applications delivering 20 V, and 25 V for 12 V applications. For this application,
the TI CSD17579Q3A (SLPS527) NexFET™ is suitable.
DQ1B: During the dead time between Q1B open and Q2 closed, 5V current is sourced onto VBUS through the
body diode of Q1B with a small voltage drop. To reduce the voltage drop, an external Schottky can be added
in parallel with Q1B.
Q2A/Q2B: For a 3-A application, an P-Channel MOSFET with RDS(on) in the 10 mΩ range is sufficient. BVDSS
should be rated for 30 V for applications delivering 20 V and 20 V for 12 V applications. For this application,
the TI CSD25404Q3 (SLPS570) NexFET™ is suitable.
RS: TPS25741 or TPS25741A OCP set point thresholds are targeted towards a 5 mΩ, ±1% sense resistor.
Power dissipation for RS at 3 A load is approximately 45 mW.
RDSCG: The minimum value of RDSCG is chosen based on the application VBUS(max) and IDSCGT. For
VBUS(max) = 12 V and IDSCGT = 350 mA, RDSCG(min) = 34.3 Ω. The size of the external resistor can then be
chosen based on the capacitive load that needs to be discharged and the maximum allowed discharge time
of 265 ms. Typically, a 120 Ω, 0.5 W resistor provides suitable performance.
RF/CF: Provide filtering of both ripple and transients. For this example, RF is a 24 Ω, 5% resistor and CF is a
0.33 μF, ceramic capacitor.
CPDIN: The requirement for CPDIN is 10 µF maximum. A 6.8 µF, 25 V, ±10% X5R or X7R ceramic capacitor is
suitable for most applications.
DVBUS: DVBUS provides reverse transient protection during large transient conditions when inductive loads are
present. A Schottky diode with a VRRM rating of 30 V in a SMA package such as the B340A-13-F provides
suitable reverse voltage clamping performance.
CSLEW: To achieve a slew rate from zero to 5 V of less than 30 mV/µs using the typical GDNG current of 20
µA then CSLEW (nF) > 20 µA/30 mV/µs = 0.67 nF be used. Choosing CSLEW = 10 nF yields a ramp rate of 2
mV/µs.
RFBL1/RFBL2: Not used
CSLU/CSLL: Not used
RPPU: RPPU is the Q2 gate drive pullup resistor. The TPS25741 applies a sink current of 40 µA typical to turn
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on Q2 and RPPU should be large enough to fully enhance Q2 but not too large as it also discharges CSLP
during turn off. The CSD25404Q3 lists an acceptable RDS(on) with VGS = -4.5V and ID = -10A. Using IGMV(min) =
34 µA and VGS = -4.5V yields R PPU = 132kΩ. Use a standard 1% resistor = 133kΩ resistor for RPPU.
CSLP: CSLP provides slew rate and inrush current limiting from the 12 V supply during VBUS transition from 5
V to 12 V. While the sink is attached, there could be as much as 110 µF on VBUS. The slew time must be >
233 µs and the inrush current must be < 3.85 A (VITRIP(min)/RS). For this design, target an inrush current of 2
A during 5 V to 12 V slew. The charge rate across CSLP will be the same as for the 110 µF load capacitor
such that ILOAD/CLOAD = ICSLP/CSLP. Using the CSD25404Q3 Gate Charge curve, a plateau threshold voltage
of VPTH ~ 1.8 V can be used to calculate CSLP with the equations below.
VPTH
IGDPG
I
RPPU
CSLP CLOAD u CSLP CLOAD u
ILOAD
ILOAD
(13)
CLOAD = 110 µF, IGDPG = 40 µA, VPTH = 1.8V, RPPU = 133 kΩ, ILOAD = 2 A
40PA
CSLP
110PF u
1.8V
133k:
2A
(14)
1.46nF
(15)
Choose CSLP = 1.5 nF
Slew time
1.5nF u
7V
1.8V
40PA
133k:
397Ps
(16)
CPPU: CPPU contributes a small Q2 turn on delay just prior to the 5 V to 12 V transition, but the primary
function is to inhibit Q2 output turn on during ramp up of the 12 V power supply. When the 12 V power supply
is OFF CSLP will be discharged. As the 12 V power supply ramps up, the common sources of Q2 will rise and
CSLP will be charged through RPPU. CPPU is required to prevent Q2 VGS from exceeding the turn on threshold
and prematurely charging VBUS for the case where the 12V bus ramps up quickly. CPPU and CSLP form a
capacitive divider network with VGS(th) ≈ 12 V x CSLP / (CSLP + CPPU). Choose CPPU ≈ (12 V/VGS(th) –1) x CSLP.
For this example, VGS(th) = 0.9 V and CPPU = 18 nF. If the 12 V power supply is enabled while the 5 V supply
is on then CPPU can be smaller set by the voltage difference between the 12 V and 5 V supply. Always
validate the final design on the test bench.
For faster fault turn off, Q3 can be connected as shown in Figure 51 and triggered using the GDNG pin. Q3
must have a ±20V VGS(max) rating for 20 V muxing applications.
12V
Q2A
RS VBUS
Q2B
1.5nF
1nF
18nF
Q3
GDNG
133k:
•
12V 5V
VPTH
IGDPG
RPPU
499k:
•
CSLP u
GDPG
Copyright © 2016, Texas Instruments Incorporated
Figure 51. Fast Turnoff Circuit
•
Power Supply ON/OFF Considerations: For applications that can disable one or both of the power supplies,
additional considerations apply. Refer to the TPS25741EVM-802 User Guide (refer to Documentation
Support). for more information.
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9.2.1.3 Application Curves
No Load
Figure 52. VBUS 12 V – 5 V Transition, TPS25741
No Load
Figure 54. VBUS 15 V – 5 V Transition, TPS25741A
4Ω, 100µF
Figure 56. VBUS 5 V – 12 V – 5 V Transition, TPS25741
50
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4Ω, 100µF
Figure 53. VBUS 12 V – 5 V Transition, TPS25741
No Load
Figure 55. VBUS 15 V – 9 V Transition, TPS25741A
No Load
Figure 57. VBUS 5 V – 12 V – 5 V Transition, TPS25741
Copyright © 2016–2018, Texas Instruments Incorporated
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SLVSDJ5D – AUGUST 2016 – REVISED JANUARY 2018
Zoomed
4Ω, 100µF
Figure 58. VBUS 5 V – 12 V Transition, TPS25741
No Load
Figure 60. VBUS 5 V – 15 V Transition, TPS25741A
No Load
Figure 62. VBUS 9 V – 15 V Transition, TPS25741A
Copyright © 2016–2018, Texas Instruments Incorporated
No Load
Zoomed
Figure 59. VBUS 5 V – 12 V Transition, TPS25741
No Load
Figure 61. VBUS 5 V – 9 V Transition, TPS25741A
No Load
Figure 63. VBUS 9 V – 5 V Transition, TPS25741A
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9.2.2 D/C Power Source
In this design example the PSEL is configured such that PSEL = 65 W (see Table 10). Voltages offered are 5 V, 9
V, and 15 V at a maximum of 3 A. The overcurrent protection (OCP) trip point is set just above 3 A and VDD on
the TPS25741A is grounded.
SW1
0.1 µF
CSD17579Q3A
VOUT
VCC
SW2
VCC
0.1 µF
CSLL
HDRV2
DSCG
VBUS
ISNS
TPS25741A
FB
CS
47 pF
CSG
100 Ÿ
CC1
CC2
DEBUG
AUDIO
POL
UFP
GDPG
G5V
100:
System
Indicators
GND
AGND
CTL2
SW2
PCTRL
VAUX
GD
VTX
PGOOD
CSG
ISNS(+)
CS
100 Ÿ
SW2
VDD
VCONN
CTL1
CVAUX
VOUT
ISNS(±)
VOSNS
AGND
CVTX
10 NŸ 0.022 µF
GDNS
RFBL1
VCC
RFBL2
BOOT2
0.08 Ÿ
RFBL
COMP
CSG
100 pF
VPWR
CSLU
CS
LDRV2
GDNG
PGND
LM5175
SS
RFBU
1µF
SLOPE
0.1 µF
CRX
CSLEW
100 pF
VIO
RT/SYNC
RDSCG
4.7 µH
SW1
0.1µF
DVDD
BIAS
84.5 NŸ
CDVDD
VOUT
DITH
Type-C
Plug
D-
CRX
LDRV1
0Ÿ
CPDIN
RG
CVPWR
BOOT1
SW1
COUT
RSLEW
MODE
HDRV1
VIN
59 NŸ
93.1 NŸ
EN/UVLO
VISNS
68 µF
4.7 µF
x5
249 NŸ
VBUS
D+
RS
+
+
HIPWR
PSEL
0.1 µF
EN12V
10 Ÿ
6V-42V
VIN
100k:
Copyright © 2016, Texas Instruments Incorporated
Figure 64. DC Power Source
9.2.2.1 Design Requirements
Table 10. Design Parameters
DESIGN PARAMETER
VALUE
Advertised Power Limit
65 W
Advertised Voltages
5 V, 9 V, 15 V
Advertised Current Limit
3A
Over Current Protection Set point
4.2 A
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Power Pin Bypass Capacitors
•
•
•
•
•
•
•
CVPWR: 0.1 μF, 50 V, ±10%, X7R ceramic at pin 25 (VPWR)
CVDD: 0.1 μF, 50 V, X7R ceramic at pin 22 (VDD). If VDD is not used in the application, then tie VDD to GND.
VDD and VCONN may be connected to the same 5-V supply.
CVCONN: 10 μF, 10 V, X7R ceramic at pin 3 (VCONN). If VCONN is not used in the application, then tie
VCONN to GND. VCONN and VDD may be connected to the same 5-V supply.
CDVDD: 0.22 μF, 10 V, ±10%, X5R ceramic at pin 18 (DVDD)
CVIO: Connect pin 17 (VIO) to DVDD (pin 18)
CVAUX: 0.1 μF, 50 V, ±10%, X7R ceramic at pin 21 (VAUX)
CVTX: 0.1 μF, 50 V, ±10%, X7R ceramic at pin 1 (VTX)
9.2.2.2.2 Non-Configurable Components
•
•
•
•
52
RSEL: When the application requires advertisement using RSEL, use a 100 kΩ, ±1% resistor.
RPCTRL: If PCTRL will be pulled low with an external device then it can be connected to VAUX using a 220
kΩ, ±5% resistor. If PCTRL will always be high then it can be directly connected to VAUX.
RSLEW: Use a 1 kΩ, ±1% resistor
RG: Use a 10 Ω, ±1% resistor
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9.2.2.2.3 Configurable Components
•
•
•
•
•
•
•
•
•
•
CRX: Choose CRX between 200 pF and 600 pF. A 470 pF, 50 V, ±5% COG/NPO ceramic is recommended for
both CC1 and CC2 pins.
Q1: For a 3 A application, an N-Channel MOSFET with RDS(on) in the 10 mΩ range is sufficient. BVDSS should
be rated for 30 V for applications delivering 20 V, and 25 V for 12 V applications. For this application, the TI
CSD17579Q3A (SLPS527) NexFET™ is suitable.
RS: TPS25741 or TPS25741A OCP set point thresholds are targeted towards a 5 mΩ, ±1% sense resistor.
Power dissipation for RS at 3 A load is approximately 45 mW.
RDSCG: The minimum value of RDSCG is chosen based on the application VBUS(max) and IDSCGT. For
VBUS(max) = 12 V and I(DSCGT) = 350 mA, RDSCG(min) = 34.3 Ω. The size of the external resistor can then be
chosen based on the capacitive load that needs to be discharged and the maximum allowed discharge time
of 90 ms. Typically, a 120 Ω, 0.5 W resistor provides suitable performance.
RF/CF: Not used
CPDIN: The requirement for CPDIN is 10 µF maximum. A 6.8 µF, 25 V, ±10% X5R or X7R ceramic capacitor is
suitable for most applications.
DVBUS: DVBUS provides reverse transient protection during large transient conditions when inductive loads are
present. A Schottky diode with a VRRM rating of 30 V in a SMA package such as the B340A-13-F provides
suitable reverse voltage clamping performance.
CSLEW: To achieve a slew rate from zero to 5 V of less than 30 mV/µs using the typical GDNG current of 20
µA then CSLEW (nF) > 20 µA/30 mV/µs = 0.67 nF be used. Choosing CSLEW = 10 nF yields a ramp rate of 2
mV/µs.
RFBL1/RFBL2: In this design example, RFBU = 49.9 kΩ and RFBL = 9.53 kΩ. The feedback error amplifier VREF =
0.8 V. Using the equations for RFBL2 (Equation 4 and Equation 5) provide a calculated value of 9.9 kΩ and a
selected value of 9.76 kΩ. In similar fashion for RFBL1, a calculated value of 6.74 kΩ and a selected value of
6.65 kΩ is provided.
CSLU/CSLL: The value of CSLU is calculated based on the desired 95% slew rate of 3 ms. CSLU = 3 ms/(3 x 49.9
kΩ) = 20 nF. Choose a 22-nF capacitor for CSLU. Next, CSLL is calculated as CSLU x (RFBU/RFBL) = 22 nF x
(49.9 kΩ/9.53 kΩ) = 115 nF. Choose a 100-nF capacitor for CSLL.
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9.2.2.3 Application Curves
VBUS
VBUS
VGDNG
VGDNG
VCTL1
VCTL1
VCTL2
VCTL2
No Load
No Load
Figure 65. VBUS 5 V – 9 V Transition
Figure 66. VBUS 9 V – 5 V Transition
VBUS
VBUS
VGDNG
VGDNG
VCTL1
VCTL1
VCTL2
VCTL2
No Load
No Load
Figure 67. VBUS 9 V – 15 V Transition
Figure 68. VBUS 15 V – 9 V Transition
VBUS
VGDNG
VBUS
VGDNG
VCTL1
VCTL1
VCTL2
VCTL2
No Load
Figure 69. VBUS 5 V – 15 V Transition
54
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No Load
Figure 70. VBUS 15 V – 5 V Transition
Copyright © 2016–2018, Texas Instruments Incorporated
TPS25741, TPS25741A
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SLVSDJ5D – AUGUST 2016 – REVISED JANUARY 2018
9.3 System Examples
9.3.1 A/C Power Source (Wall Adapter)
CB2
RS
DS
t
P
VBUS
D+
COUT
RG
M1
CRX
CTL2
DSCG
VBUS
GDNS
ISNS
TPS25741
CTL1
DVDD
RFBL2
VDD
VCONN
CC1
CC2
DEBUG
AUDIO
POL
UFP
GDPG
G5V
System
Indicators
VIO
EN12V
PSEL
GND
AGND
CIO
RFBL
RCS
TL431
P
RFBL1
HIPWR
CIZ
GND
RF6
RF5
VPWR
ROB
RLC
FB
GDNG
VB
CS
RFBU
DRV
P
CSLEW
VS
PCTRL
VAUX
GD
VTX
UCC28740
D-
RDSCG
HV
CVPWR
CDD1
CDD
VDD
RS2
RS1
LDO
RSLEW
DVC
T1
CPDIN
P
100:
CB1
Type-C
Plug
CSD17579Q3A
CRX
T1
+
From AC Mains
In this system design example, the PSEL is configured such that PSEL = 36 W, and only 5 V and 12 V are offered
at a maximum of 3 A. The over-current protection (OCP) trip point is set just above 3 A. VDD on the TPS25741
is grounded, if there is a suitable power supply available in the system the TPS25741 operates more efficiently if
it is connected to VDD since VVPWR > VVDD.
CDVDD
CTX
CAUX
100k:
Copyright © 2016, Texas Instruments Incorporated
Figure 71. Adapter Provider Concept
Copyright © 2016–2018, Texas Instruments Incorporated
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System Examples (continued)
9.3.2 Dual-Port Power Managed A/C Power Source (Wall Adapter)
In this system design example, the PSEL is configured such that PSEL = 36 W, and only 5 V and 12 V are offered
at a maximum of 3 A. The over-current protection (OCP) trip point is set just above 3 A.
The UFP pin from one TPS25741 is attached to the PCTRL pin on the other TPS25741. When one port is not
active (no UFP attached through the receptacle) its UFP pin is left high-z so the PCTRL pin on the other port is
pulled high. This allows the adaptor to provide up to the full 36 W on a single port if a single UFP is attached. If
two UFP’s are attached (one to each port) then each port only offers current that would reach a maximum of 18
W. So each port is allocated half of the overall power when each port has a UFP attached.
CSD17579Q3A (2x)
VBUS
D+
RS
10:
10:
Type-C
receptacle
#1
D-
RDSCG
RSLEW
CRX
CC1
VIO
EN12V
PSEL
GND
AGND
CC2
DVDD
VAUX
GD
VTX
CTL2
UFP
PCTRL
HIPWR
TPS25741
CTL1
100k:
CAUX
CTX
CDVDD
220k:
CSD17579Q3A (2x)
5V, 12V, or 20V
VBUS
D+
10:
10:
Type-C
receptacle
#2
D-
RSLEW
RDSCG
100:
RS
CPDIN
DC/DC
Buck
Circuit
(36W)
CRX
VBUS
VDD
DSCG
ISNS
GDNG
VPWR
24V
GDNS
CSLEW
AC/DC Fly-Back
Circuit
(36W)
100:
5V, 12V, or 20V
CPDIN
DC/DC
Buck
Circuit
(36W)
CRX
CRX
VBUS
DSCG
ISNS
GDNS
GDNG
VPWR
CSLEW
VDD
CC1
CC2
VIO
EN12V
PSEL
GND
AGND
DVDD
PCTRL
VAUX
GD
VTX
CTL2
UFP
HIPWR
TPS25741
CTL1
CTX
CAUX
CDVDD
100k:
220k:
Copyright © 2016, Texas Instruments Incorporated
Figure 72. Dual-Port Adapter Provider Concept
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10 Power Supply Recommendations
10.1 VDD
The recommended VDD supply voltage range is 3 V to 5.5 V. The device requires approximately 2 mA (ISUPP)
typical in normal operating mode and below 10 µA in sleep mode. If the VDD supply is not used, then it may be
connected to AGND/GND.
10.2 VCONN
The recommended VCONN supply voltage range is 4.65 V to 5.5 V. If the VCONN supply is not used, then it
may be connected to AGND/GND.
10.3 VPWR
The recommended VPWR supply voltage range is 0 V to 25 V. The device requires approximately 2 mA (ISUPP)
typical in normal operating mode and below 10 µA in sleep mode.
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11 Layout
11.1 Layout Guidelines
11.1.1 Port Current Kelvin Sensing
VPWR
25
26
GDPG
20 GD
19 PCTRL
18 DVDD
17 VIO
21 VAUX
23 AGND
22 VDD
ISNS
24
Figure 73 provides a routing example for accurate current sensing for the overcurrent protection feature. The
sense amplifier measurement occurs between the ISNS and VBUS pins of the device. Improper connection of
these pins can result in poor OCP performance.
16
VBUS
27
AUDIO 28
13 N/C
PAD
GDNG 29
12 N/C
GDNS 30
11 N/C
DSCG 31
10 EN12V
G5V 32
7
8
CTL2
GND
6
4
5
CC2
HIPWR
CTL1
3
VCONN
2
CC1
1
9
VTX
CF
RF
PSEL
15 DEBUG
14 UFP
POL
Top Trace
Top Plane
RS
Q1 Source
VBUS
Current Flow
Bottom Trace/ Plane
VIA
Figure 73. Kelvin Sense Layout Example
11.1.2 Power Pin Bypass Capacitors
• CVPWR: Place close to pin 25 (VPWR) and connect with low inductance traces and vias according to
Figure 74.
• CVDD: Place close to pin 22 (VDD) and connect with low inductance traces and vias according to Figure 74.
• CVCONN: Place close to pin 3 (VDD) and connect with low inductance traces and vias according to Figure 74.
• CDVDD: Place close to pin 18 (DVDD) and connect with low inductance traces and vias according to Figure 74.
• CVIO: Place close to pin 17 (VDD) and connect with low inductance traces and vias according to Figure 74.
• CVAUX: Place close to pin 21 (VAUX) and connect with low inductance traces and vias according to Figure 74.
• CVTX: Place close to pin 1 (VTX) and connect with low inductance traces and vias according to Figure 74.
11.1.3 Supporting Components
• CRX: Place CRX1 and CRX2 in line with the CC1 and CC2 traces as shown in Figure 26. These should be
placed within one inch from the Type C connector. Minimize stubs and tees from on the trace routes.
• Q1: Place Q1 in a manner such that power flows uninterrupted from Q1 drain to the Type C connector VBUS
connections. Provide adequate copper plane from Q1 drain and source to the interconnecting circuits.
• RS: Place RS as shown in Figure 74 to facilitate uninterrupted power flow to the Type C connector. Orient RS
for optimal Kelvin sense connection/routing back to the TPS25741 or TPS25741A. In high current applications
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SLVSDJ5D – AUGUST 2016 – REVISED JANUARY 2018
Layout Guidelines (continued)
•
•
•
•
•
•
where the power dissipation is over 250 mW, provide an adequate copper feed to the pads of RS.
RG: Place RG near Q1 as shown in Figure 74. Minimize stray leakage paths as the GDNG sourcing current
could be affected.
RSLEW/CSLEW: Place RSLEW and CSLEW near RG as shown in Figure 74.
RDSCG: Place on top of the VBUS copper route and connect to the DSCG pin with a 15 mil trace.
RF/CF: When required, place RF and CF as shown in Figure 74 to facilitate the Kelvin sense connection back
to the device.
CVBUS/DVBUS: Place CVBUS and DVBUS within one inch of the Type C connector and connect them to VBUS and
GND using adequate copper shapes.
RSEL/RPCTRL: Place RSEL and RPCTRL near the device.
11.2 Layout Example
CVAUX
CVDD
GND
RPCNTRL
17
GD
PCTRL
PSEL 16
14
N/C
13
N/C
12
GDNS
N/C
11
31
DSCG
EN12V
10
32
G5V
7 CTL1
6 HIPWR
4 CC2
5 GND
1 VTX
2 CC1
8 CTL2
30
PAD
RSEL
15
DEBUG
UFP
AUDIO
GDNG
3 VCONN
RSLEW
G
GDPG
29
28
RG
4
S
3
S
2
S
Q1
1
27
CDVDD
VIO
20
19
VAUX
26 VBUS
DVDD 18
21
VDD
24
23
22
ISNS
AGND
CVPWR
VPWR
25
D
D
D
D
5
6
7
CSLEW
VOUT
8
DC/DC
Converter
The basic component placement and layout is provided in Figure 74. This layout represents the circuit shown in
Figure 41. The layout for other power configurations will vary slightly from that shown below.
To DC/DC
Converter
9
POL
CRX2
CRX1
CVTX
RDSCG
CF
RF
CC2
CVCONN
CC1
VBUS
Top Trace
DVBUS
CVBUS
RS
Type C Connector
GND
Top Plane
Bottom Trace/ Plane
VIA
Figure 74. Layout Example
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www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
USB Power Delivery and USB Type-C specifications available at: http://www.usb.org/home
TPS25741EVM-802 and TPS25741AEVM-802 EVM User's Guide for Desktops
TPS25741/TPS25741A Design Calculator Tool
TPS25741 Power Multiplexing Introduction and Design Considerations
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 11. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS25741
Click here
Click here
Click here
Click here
Click here
TPS25741A
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
USB Type-C is a trademark of USB Implementers Forum.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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SLVSDJ5D – AUGUST 2016 – REVISED JANUARY 2018
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2016–2018, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Dec-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS25741ARSMR
NRND
VQFN
RSM
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
25741A
TPS25741ARSMT
NRND
VQFN
RSM
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
25741A
TPS25741RSMR
NRND
VQFN
RSM
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PTPS BX
25741
TPS25741RSMT
NRND
VQFN
RSM
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PTPS BX
25741
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Dec-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS25741ARSMR
VQFN
RSM
32
TPS25741ARSMT
VQFN
RSM
TPS25741RSMR
VQFN
RSM
TPS25741RSMT
VQFN
RSM
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
32
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
32
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
32
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS25741ARSMR
VQFN
RSM
32
3000
367.0
367.0
35.0
TPS25741ARSMT
VQFN
RSM
32
250
210.0
185.0
35.0
TPS25741RSMR
VQFN
RSM
32
3000
367.0
367.0
35.0
TPS25741RSMT
VQFN
RSM
32
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RSM 32
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4 x 4, 0.4 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224982/A
www.ti.com
PACKAGE OUTLINE
RSM0032B
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
B
4.1
3.9
A
0.45
0.25
0.25
0.15
DETAIL
PIN 1 INDEX AREA
OPTIONAL TERMINAL
TYPICAL
4.1
3.9
(0.1)
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2.8 0.05
2X 2.8
(0.2) TYP
4X (0.45)
9
16
28X 0.4
8
SEE SIDE WALL
DETAIL
17
EXPOSED
THERMAL PAD
2X
2.8
SEE TERMINAL
DETAIL
PIN 1 ID
(OPTIONAL)
SYMM
33
24
1
32X
32
25
SYMM
32X
0.25
0.15
0.1
0.05
C A B
0.45
0.25
4219108/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 2.8)
SYMM
32
25
32X (0.55)
1
32X (0.2)
24
( 0.2) TYP
VIA
(1.15)
SYMM
33
(3.85)
28X (0.4)
17
8
(R0.05)
TYP
9
(1.15)
16
(3.85)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219108/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.715)
4X ( 1.23)
25
32
(R0.05) TYP
32X (0.55)
1
24
32X (0.2)
(0.715)
33
SYMM
(3.85)
28X (0.4)
17
8
METAL
TYP
16
9
SYMM
(3.85)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 33:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219108/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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