Texas Instruments | HD3SS3412A 4-Channel High-Performance Differential Switch | Datasheet | Texas Instruments HD3SS3412A 4-Channel High-Performance Differential Switch Datasheet

Texas Instruments HD3SS3412A 4-Channel High-Performance Differential Switch Datasheet
Order
Now
Product
Folder
Technical
Documents
Support &
Community
Tools &
Software
HD3SS3412A
SLAS974 – DECEMBER 2017
HD3SS3412A 4-Channel High-Performance Differential Switch
1 Features
3 Description
•
The HD3SS3412A device is a high-speed passive
switch capable of switching four differential channels,
including applications such as two full PCI Express x1
lanes from one source to one of two target locations
in a PC or server application. With its bidirectional
capability,
the
HD3SS3412A
also
supports
applications that allow connections between one
target and two source devices, such as a shared
peripheral between two platforms. The HD3SS3412A
has a single control line (SEL pin) which can be used
to control the signal path between Port A and either
Port B or Port C.
1
•
•
•
•
•
•
•
Compatible With Multiple Interface Standards
Operating up to 12 Gbps Including PCI Express
Gen III and USB 3.0
Wide –3-dB Differential BW of Over 8 GHz
Excellent Dynamic Characteristics (at 4 GHz)
– Crosstalk = –35 dB
– Off Isolation = –19 dB
– Insertion Loss = –1.5 dB
– Return Loss = –11 dB
Bidirectional "MUX/De-MUX" Type Differential
Switch
VDD Operating Range 3.3 V ±10%
Small 3.5-mm × 9.0-mm, 42-Pin WQFN Package
Common Industry Standard Pinout
Supports XAUI and SGMII
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
The HD3SS3412A is offered in an industry standard
42-pin WQFN package available in a common
footprint shared by several other vendors. The device
is specified to operate from a single supply voltage of
3.3 V over the full temperature range of 0°C to 70ºC.
Desktop and Notebook PCs
Server and Storage Area Networks
PCI Express Backplanes
Shared I/O Ports
PACKAGE
BODY SIZE (NOM)
WQFN (42)
9.00 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
HD3SS3412A Switch Flow Through Routing
GND
GND
VDD
NC
HD3SS3412A Pinout
HD3SS3412A
1
A0+
A0-
B0+
B0B1+
B1C0+
Top View
RUA
Package
GND
VDD
A1+
C0C1+
A1NC
C1VDD
SEL
GND
B2+
A2+
B2-
A2-
B3+
VDD
GND
B3C2+
GND
Pad
A3+
C2-
GND
VDD
21
NC
GND
22
18
18
21
C3+
C3-
17
22
17
A3GND
38
39
42
1
38
39
42
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
HD3SS3412A
SLAS974 – DECEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
6
6
6
6
7
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 13
10 Application and Implementation........................ 14
10.1 Application Information.......................................... 14
10.2 Typical Application ................................................ 15
11 Power Supply Recommendations ..................... 17
12 Layout................................................................... 17
12.1 Layout Guidelines ................................................. 17
12.2 Layout Example .................................................... 17
13 Device and Documentation Support ................. 18
13.1
13.2
13.3
13.4
13.5
Parameter Measurement Information ................ 10
Detailed Description ............................................ 12
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
14 Mechanical, Packaging, and Orderable
Information ........................................................... 18
9.1 Overview ................................................................. 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2017
*
Initial release.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
HD3SS3412A
www.ti.com
SLAS974 – DECEMBER 2017
5 Description (continued)
The HD3SS3412A is a generic 4-CH high-speed MUX/de-MUX type of switch that can be used for routing highspeed signals between two different locations on a circuit board. Although it was designed specifically to address
PCI Express Gen III applications, the HD3SS3412A will also support several other high-speed data protocols
with a differential amplitude of <1800 mVpp and a common-mode voltage of < 2.0 V, as with USB 3.0 and
DisplayPort 1.2. The device’s one select input (SEL) pin can easily be controlled by an available GPIO pin within
a system or from a microcontroller.
6 Pin Configuration and Functions
1
38
39
42
GND
GND
GND
VDD
NC
RUA Package
42-Pin WQFN
Top View
A0+
A0-
B0+
B0B1+
B1C0+
Top View
RUA
Package
GND
VDD
A1+
C0C1+
A1NC
C1VDD
SEL
GND
B2+
A2+
B2-
A2-
B3+
VDD
GND
B3C2+
GND
Pad
A3+
C222
17
VDD
NC
GND
18
21
C3+
C3-
GND
A3GND
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
SWITCH PORT A
A0+
2
I/O
Port A, Channel 0, High-Speed Positive Signal
A0–
3
I/O
Port A, Channel 0, High-Speed Negative Signal
A1+
6
I/O
Port A, Channel 1, High-Speed Positive Signal
A1–
7
I/O
Port A, Channel 1, High-Speed Negative Signal
A2+
11
I/O
Port A, Channel 2, High-Speed Positive Signal
A2–
12
I/O
Port A, Channel 2, High-Speed Negative Signal
A3+
15
I/O
Port A, Channel 3, High-Speed Positive Signal
A3–
16
I/O
Port A, Channel 3, High-Speed Negative Signal
B0+
38
I/O
Port B, Channel 0, High-Speed Positive Signal
B0–
37
I/O
lPort B, Channel 0, High-Speed Negative Signal
SWITCH PORT B
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
3
HD3SS3412A
SLAS974 – DECEMBER 2017
www.ti.com
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
B1+
36
I/O
Port B, Channel 1, High-Speed Positive Signal
B1–
35
I/O
Port B, Channel 1, High-Speed Negative Signal
B2+
29
I/O
Port B, Channel 2, High-Speed Positive Signal
B2–
28
I/O
Port B, Channel 2, High-Speed Negative Signal
B3+
27
I/O
Port B, Channel 3, High-Speed Positive Signal
B3–
26
I/O
Port B, Channel 3, High-Speed Negative Signal
4
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
HD3SS3412A
www.ti.com
SLAS974 – DECEMBER 2017
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
SWITCH PORT C
C0+
34
I/O
Port C, Channel 0, High-Speed Positive Signal
C0–
33
I/O
Port C, Channel 0, High-Speed Negative Signal
C1+
32
I/O
Port C, Channel 1, High-Speed Positive Signal
C1–
31
I/O
Port C, Channel 1, High-Speed Negative Signal
C2+
25
I/O
Port C, Channel 2, High-Speed Positive Signal
C2–
24
I/O
Port C, Channel 2, High-Speed Negative Signal
C3+
23
I/O
Port C, Channel 3, High-Speed Positive Signal
C3–
22
I/O
Port C, Channel 3, High-Speed Negative Signal
—
Electrically not connected. May connect to VDD or GND, or leave unconnected.
CONTROL, SUPPLY, AND NO CONNECT
8
NC
18
42
1
4
10
14
GND
17
19
Supply
Negative power supply voltage
21
39
41
Center Pad
SEL
9
I
Select between port B or port C. Internally tied to GND through a 100-kΩ resistor
5
13
VDD
20
Supply
Positive power supply voltage
30
40
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
5
HD3SS3412A
SLAS974 – DECEMBER 2017
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1) (2)
Supply voltage (VDD)
Voltage
MIN
MAX
UNIT
Absolute minimum/maximum supply voltage
–0.5
4
V
Differential I/O
–0.5
4
Control pin (SEL)
–0.5
VDD + 0.5
–65
150
Storage temperature, Tstg
(1)
(2)
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Typical values for all parameters are at VDD = 3.3 V and TA = 25°C. (Temperature limits are specified by design)
VDD
Supply voltage
VIH
Input high voltage (SEL pin)
VIL
Input low voltage (SEL pin)
VI/O_Diff
Differential voltage (differential pins)
Switch I/O diff voltage
VI/O_CM
Common voltage (differential pins)
Switch I/O common-mode voltage
TA
Operating free-air temperature
Ambient temperature
MIN
NOM
MAX
3.0
3.3
3.6
V
2.0
VDD
V
–0.1
0.8
V
0
1.8
VPP
0
2.0
0
70
UNIT
V
o
C
7.4 Thermal Information
HD3SS3412A
THERMAL METRIC (1)
RUA (WQFN)
UNIT
42 PINS
RθJA
Junction-to-ambient thermal resistance
53.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
38.2
°C/W
RθJB
Junction-to-board thermal resistance
21.9
°C/W
ψJT
Junction-to-top characterization parameter
27.4
°C/W
ψJB
Junction-to-board characterization parameter
5.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
27.3
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
HD3SS3412A
www.ti.com
SLAS974 – DECEMBER 2017
7.5 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEVICE PARAMETERS
IIH
Input High Voltage (SEL)
VDD = 3.6 V; VIN = VDD
95
µA
IIL
Input Low Voltage (SEL)
VDD = 3.6 V; VIN = GND
1
µA
Leakage Current (Differential
I/O pins)
ILK
VDD = 3.6 V; VIN = 0 V; VOUT = 2 V
(ILK On OPEN outputs) [Ports B and C]
130
µA
VDD = 3.6 V, VIN = 2 V; VOUT = 0 V
(ILK On OPEN outputs) [Port A]
4
IDD
Supply Current
VDD = 3.6 V; SEL = VDD/GND; Outputs Floating
4.7
CON
Outputs ON Capacitance
VIN = 0 V; Outputs Open; Switch ON
1.5
COFF
Outputs OFF Capacitance
VIN = 0 V; Outputs Open, Switch OFF
1
RON
Output ON resistance
VDD = 3.3 V; VCM = 0.5 V to 1.5 V ; IO = –8 mA
5
ΔRON
VDD = 3.3 V; –0.35 V ≤ VIN ≤ 1.2 V
tPD
Switch propagation delay
Rsc and RLOAD = 50 Ω
SEL-to-switch TON
SEL-to-switch TOFF
Inter-pair output skew (CHCH)
TSKEW_Intra Intra-pair output skew (bit-bit)
Rsc and RLOAD = 50 Ω
Ω
0.7
Ω
1.15
Ω
85
ps
250
250
Rsc and RLOAD = 50 Ω
Rsc and RLOAD = 50 Ω
Differential Crosstalk(VCM = 0 f = 0.3 MHz
V)
f = 2500 MHz
Also see Typical
f = 4000 MHz
Characteristics
–90
Differential Off-Isolation(VCM
= 0 V)
Also see Typical
Characteristics
f = 0.3 MHz
–75
OIRR
f = 2500 MHz
–22
f = 4000 MHz
–19
f = 0.3 MHz
–0.5
IL
Differential Insertion Loss
(VCM = 0 V)
Also see Typical
Characteristics
f = 2500 MHz
–1.1
f = 4000 MHz
–1.5
Bandwidth
At –3 dB
BW
2
70
–28
XTALK
Ω
70
Differential return loss (VCM = f = 0.3 MHz
0 V)
f = 2500 MHz
Also see Typical
f = 4000 MHz
Characteristics
RL
pF
8
ON-resistance match between
VDD = 3.3 V; –0.35 V ≤ VIN ≤ 1.2 V; IO = –8 mA
pairs of the same channel
ON-resistance flatness
(RON(MAX) – RON(MAIN)
mA
pF
ON-resistance match between
VDD = 3.3 V ; –0.35 V ≤ VIN ≤ 1.2 V; IO = –8 mA
channels
RFLAT_ON
TSKEW_Inter
6
ns
20
ps
8
ps
–12
dB
–11
–39
dB
–35
dB
dB
8
GHz
7.6 Dissipation Ratings
PD
Power Dissipation
MIN
MAX
UNIT
15.5
21.6
mW
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
7
HD3SS3412A
SLAS974 – DECEMBER 2017
www.ti.com
50%
SEL
90%
VOUT
10%
Toff
Ton
Figure 1. Switch ON and OFF Timing Diagram
VDD
RSC = 50W
An+
RSC = 50W
HD3SS3412
Bn+/Cn+
RL = 50W
An-
Bn-/CnRL = 50W
SEL
VDD
VIN+
50%
50%
50%
50%
0V
VDD
VIN-
0V
VDD
VOUT+
50%
50%
50%
50%
0V
VDD
VOUT+
0V
tP1
tP1
TSKEWInter = Difference between tPD for any two pairs of outputs
TSKEWIntra = Difference between tP1 and tP2 of same pair
Figure 2. Propagation Delay Timing Diagram and Test Setup
8
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
HD3SS3412A
www.ti.com
SLAS974 – DECEMBER 2017
7.7 Typical Characteristics
m1
5
m2 m3
m1
freq=300.0kHz
freq=300.0kHz
dB(SDD21)=-0.491
m4
-2
dB (SDD21)
-4
m2
freq= 2.514GHz
dB(SDD21)=-1.221
-6
-8
m3
freq= 3.985GHz
dB(SDD21)=-1.536
-10
-12
-14
m5
freq= 329.0kHz
dB(SDD11)=-28.545
0
dB (SDD11)
0
-5
-15
m7
freq= 3.985GHz
dB(SDD11)=-11.177
-20
-25
m5
-30
2E10
1E10
1E9
1E8
1E7
1E6
2E10
1E10
1E9
1E8
1E7
1E6
m4
freq= 8.331GHz
dB(SDD21)=-2.998
freq, Hz
freq, Hz
Figure 3. Differential Insertion Loss
-20
Figure 4. Differential Return Loss
0
m1
freq=300.0kHz
dB(SDD21)=-97.081
-40
m2
freq=2.514GHz
dB(SDD21)=-39.567
-60
-80
m3
freq=3.985GHz
dB(SDD21)=-34.786
m1
-100
m1
freq=300.0kHz
dB(SDD21)=-74.449
m2 m3
-20
dB (SDD21)
m3
m2
dB (SDD21)
m6
freq= 2.514GHz
dB(SDD11)=-13.842
m7
m6
-10
m2
freq=2.514GHz
dB(SDD21)=-22.000
-40
-60
m1
m3
freq=3.985GHz
dB(SDD21)=-18.935
-80
-100
2E10
1E10
1E9
1E8
1E7
2E10
1E10
1E9
1E8
1E7
1E6
1E6
-120
freq, Hz
freq, Hz
Figure 5. Differential Crosstalk
Figure 6. Differential Off Isolation
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
9
HD3SS3412A
SLAS974 – DECEMBER 2017
www.ti.com
8 Parameter Measurement Information
Network
Analyzer
P2
P1
VDD
B0+
A0+
100 W
A0B0HD3SS3412
SEL
B1+
A1+
100 W
A1B1-
Figure 7. Cross Talk Measurement Setup
Network
Analyzer
P2
P1
VDD
A0+
B0+
A0-
100 W
B0-
HD3SS3412
SEL
B1+
B1-
Figure 8. Off Isolation Measurement Setup
10
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
HD3SS3412A
www.ti.com
SLAS974 – DECEMBER 2017
Parameter Measurement Information (continued)
A
3.1 Inches Rogers
Microstrip
Oscilloscope
10Gbps PRBS 2 7- 1
Vi=0.8Vpp ; Vcm =0V
Figure 9. Source Eye Diagram Test Setup
A
1.4 Inches
Rogers
Microstrip
1.7 Inches
Rogers
Microstrip
7
10Gbps PRBS 2 - 1
Vi=0.8Vpp ; Vcm =0V
Oscilloscope
Figure 10. Output Eye Diagram Test Setup
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
11
HD3SS3412A
SLAS974 – DECEMBER 2017
www.ti.com
9 Detailed Description
9.1 Overview
The HD3SS3412A is a high-speed passive switch offered in an industry standard 42-pin WQFN package
available in a common footprint shared by several other vendors. The device is specified to operate from a single
supply voltage of 3.3 V over the commercial temperature range of 0°C to 70°C. The HD3SS3412A is a generic 4CH high-speed mux/demux type of switch that can be used for routing high-speed signals between two different
locations on a circuit board. Although it was designed specifically to address PCI Express Gen III applications,
the HD3SS3412A will also support several other high-speed data protocols with a differential amplitude of < 1800
mVpp and a common-mode voltage of < 2.0 V, as with USB 3.0 and DisplayPort 1.2. The device’s one select
input (SEL) pin can easily be controlled by an available GPIO pin within a system or from a microcontroller.
9.2 Functional Block Diagram
VDD
MUX 0
B0+
B0C0+
C0-
A0+
A0SEL
SEL
100kO
C1+
C1-
SEL
MUX 1
B1+
B1-
A1+
A1-
SEL
C2+
C2-
MUX 2
B2+
B2A2+
A2-
C3+
C3-
MUX 3
SEL
B3+
B3-
A3+
A3-
GND
12
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
HD3SS3412A
www.ti.com
SLAS974 – DECEMBER 2017
9.3 Feature Description
The HD3SS3412A has a single control line (SEL Pin) which can be used to control the signal path between Port
A and either Port B or Port C. The one select input (SEL) pin of the device can easily be controlled by an
available GPIO pin within a system or from a microcontroller. The input signal is selected using the SEL pin.
Table 1. Mux Pin Connections (1)
PORT B OR PORT C CHANNEL
CONNECTED TO PORT A CHANNEL
PORT A CHANNEL
A0+
(1)
SEL = L
SEL = H
B0+
C0+
A0–
B0–
C0–
A1+
B1+
C1+
A1–
B1–
C1–
A2+
B2+
C2+
A2–
B2–
C2–
A3+
B3+
C3+
A3–
B3–
C3–
The HD3SS3412A can tolerate polarity inversions for all differential signals on Ports A, B, and C. Take care to ensure the same polarity
is maintained on Port A versus Port B/C.
9.4 Device Functional Modes
Table 2 lists the functional modes for the HD3SS3412A.
Table 2. HD3SS3412A Control Logic
PORT A TO PORT B
CONNECTION STATUS
PORT A TO PORT C
CONNECTION STATUS
L (Default State)
Connected
Disconnected
H
Disconnected
Connected
CONTROL PIN (SEL)
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
13
HD3SS3412A
SLAS974 – DECEMBER 2017
www.ti.com
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 AC Coupling Caps
Many interfaces require AC coupling between the transmitter and receiver. The 0402 capacitors are the preferred
option to provide AC coupling, and the 0603 size capacitors also work. The 0805 size capacitors and C-packs
should be avoided. When placing AC coupling capacitors symmetric placement is best. A capacitor value of 0.1
µF is best and the value should be match for the ± signal pair. The placement should be along the TX pairs on
the system board, which are usually routed on the top layer of the board.
There are several placement options for the AC coupling capacitors. Because the switch requires a bias voltage,
the capacitors must only be placed on one side of the switch. If they are placed on both sides of the switch, a
biasing voltage should be provided. A few placement options are shown below. In Figure 11, the coupling
capacitors are placed between the switch and endpoint. In this situation, the switch is biased by the system/host
controller.
Figure 11. AC Coupling Capacitors Between Switch Tx and Endpoint Tx
In Figure 12, the coupling capacitors are placed on the host transmit pair and endpoint transmit pair. In this
situation, the switch on the top is biased by the endpoint and the lower switch is biased by the host controller.
Figure 12. AC Coupling Capacitors on Host Tx and Endpoint Tx
14
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
HD3SS3412A
www.ti.com
SLAS974 – DECEMBER 2017
Application Information (continued)
If the common-mode voltage in the system is higher than 2 V, the coupling capacitors are placed on both sides
of the switch (shown in Figure 13). A biasing voltage of less than 2 V is required in this case.
Figure 13. AC Coupling Capacitors on Both Sides of Switch
HD3SS3412
Chipset
Memory/GPU
Hub
Port B
x2
Port C
x2
Port B
x2
Port C
x2
x8
x16
HD3SS3412
Chipset
I/O Hub
HD3SS3412
iGPU
GPIO
Port B
x2
Port C
x2
x8 Graphics Card Slot
Port A
x2
x16 Graphics Card Slot
Microprocessor
HD3SS3412
10.2 Typical Application
Port B
x2
Port C
x2
SEL Pins
Figure 14. Typical Application Block Diagram
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
15
HD3SS3412A
SLAS974 – DECEMBER 2017
www.ti.com
Typical Application (continued)
10.2.1 Design Requirements
Table 3 lists the design parameters of this example.
Table 3. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
Input voltage range
3.3 V
Decoupling capacitors
0.1 µF
AC capacitors
75 nF – 200 nF (100 nF shown) USBAA TX p and
n lines require AC capacitors. Alternate mode
signals may or may not require AC capacitors
10.2.2 Detailed Design Procedure
• Connect VDD and GND pins to the power and ground planes of the printed circuit board, with 0.1-uF bypass
capacitor
• Use +3.3-V TTL/CMOS logic level at SEL
• Use controlled-impedance transmission media for all the differential signals
• Ensure the received complimentary signals are with a differential amplitude of <1800 mVpp and a commonmode voltage of <2 V
10.2.3 Application Curves
Figure 15. 10-gbps Source Eye Diagram at a: VID = 800
Mvpp; 27–1 Prbs; VCM= 0 V
16
Figure 16. 10-gbps Output Eye Diagram at a: VID = 800
Mvpp; 27–1 Prbs; VCM= 0v; VDD= 3.3 V; Sel= 0 V
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
HD3SS3412A
www.ti.com
SLAS974 – DECEMBER 2017
11 Power Supply Recommendations
The HD3SS3412A requires +3.3-V digital power sources. VDD 3.3 supply must have 0.1-μF bypass capacitors to
VSS (ground) in order for proper operation. The recommendation is one capacitor for each power terminal. Place
the capacitor as close as possible to the terminal on the device and keep trace length to a minimum. Smaller
value capacitors like 0.01-μF are also recommended on the digital supply terminals.
12 Layout
12.1 Layout Guidelines
•
•
•
•
•
Decoupling caps should be placed next to each power terminal on the HD3SS3412A. Take care to minimize
the stub length of the race connecting the capacitor to the power pin.
Avoid sharing vias between multiple decoupling caps
Place vias as close as possible to the decoupling cop solder pad
Widen VDD/GND planes to reduce effect if static and dynamic IR drop
The VBUS traces/planes must be wide enough to carry maximum of 2-A current
12.2 Layout Example
Use controlled-impedance
Transmission media for all
Differential signals
VIA to SW Cooper Pour
VDD3P3
VDD3P3
AX+
AXBX+
BXCX+
CXVSS
SEL
VBUS
GND
Exposed Thermal
Pad Are
3.3V Logic level
VBUS traces wide
enough to carry 2A
current
Figure 17. Layout Example
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
17
HD3SS3412A
SLAS974 – DECEMBER 2017
www.ti.com
13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: HD3SS3412A
PACKAGE OPTION ADDENDUM
www.ti.com
2-Apr-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
HD3SS3412ARUAR
ACTIVE
WQFN
RUA
42
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
HD3SS3412
HD3SS3412ARUAT
ACTIVE
WQFN
RUA
42
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
HD3SS3412
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Apr-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
HD3SS3412ARUAT
Package Package Pins
Type Drawing
WQFN
RUA
42
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
24.4
Pack Materials-Page 1
3.9
B0
(mm)
K0
(mm)
P1
(mm)
9.4
1.0
8.0
W
Pin1
(mm) Quadrant
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
HD3SS3412ARUAT
WQFN
RUA
42
250
211.0
193.0
46.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising