Texas Instruments | TS5USBC400 Dual 2:1 USB 2.0 Mux/DeMux with 16-V Overvoltage Protection (Rev. A) | Datasheet | Texas Instruments TS5USBC400 Dual 2:1 USB 2.0 Mux/DeMux with 16-V Overvoltage Protection (Rev. A) Datasheet

Texas Instruments TS5USBC400 Dual 2:1 USB 2.0 Mux/DeMux with 16-V Overvoltage Protection (Rev. A) Datasheet
Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
TS5USBC400
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
TS5USBC400 Dual 2:1 USB 2.0 Mux/DeMux with 16-V Overvoltage Protection
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
Supply Range 2.3 V to 5.5 V
Differential 2:1 or 1:2 Switch/Multiplexer
0-V to 16-V Overvoltage Protection (OVP) on
Common Pins
Powered Off Protection When VCC = 0 V
Low RON of 9 Ω Maximum
BW of 1.1 GHz Typical
CON of 4.5 pF Typical
Low Power Disable Mode
1.8-V Compatible Logic Inputs
ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (HBM)
TS5USBC400: Standard Temperature Range of
0°C to 70°C
TS5USBC400I: Industrial Temperature Range of
-40°C to 85°C
Small DSBGA Package
Mobile
PC/Notebook
Tablet
Anywhere a USB Type-C™ or Micro-B Connector
is Used
3 Description
The TS5USBC400 is a bidirectional low-power dual
port, high-speed, USB 2.0 analog switch with
integrated protection for USB Type-C™ systems. The
device is configured as a dual 2:1 or 1:2 switch and is
optimized for handling the USB 2.0 D+/- lines in a
USB Type-C™ systems.
The TS5USBC400 protection on the I/O pins can
tolerate up to 16V with automatic shutoff circuitry to
protect system components behind the switch.
The TS5USBC400 comes in a small 12 pin DSBGA
package making it a perfect candidate for mobile and
space constrained applications.
Device Information(1)
PART NUMBER
TS5USBC400
TS5USBC400I
PACKAGE
DSBGA (12)
BODY SIZE (NOM)
1.582 mm × 1.182 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
TS5USBC400
UART
USB
VCC
OVP
DP_T
USB
Connector
VBUS
Simplified Schematic
DP_B
D1+
D2+
DM_T
D1D2SEL1
OE
Logic
Control
GND
SEL2
DM_B
USB
FLT
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS5USBC400
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dynamic Characteristics ...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 16
9
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 17
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 21
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2017) to Revision A
•
2
Page
Added ICC Active supply current and Supply current during OVP condition to the Electrical Specification table .................. 4
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
5 Pin Configuration and Functions
YFP Package
12-Pin DSBGA
Top View
1
2
3
4
A
SEL1
D+
D-
FLT
B
VCC
SEL2
GND
OE
C
D2+
D2-
D1+
D1-
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
SEL1
A1
I
D+
A2
I/O
Data switch input (Differential +)
Switch select1 (Active high)
D–
A3
I/O
Data switch input (Differential –)
FLT
A4
O
Fault indicator output pin (Active low) - open drain
VCC
B1
PWR
SEL2
B2
I
GND
B3
GND
OE
B4
I
D2+
C1
I/O
Data switch output 2 (Differential +)
D2–
C2
I/O
Data switch output 2 (Differential -)
D1+
C3
I/O
Data switch output 1 (Differential +)
D1–
C4
I/O
Data switch output 1 (Differential -)
Copyright © 2017, Texas Instruments Incorporated
Supply Voltage
Switch select2 (Active high)
Ground
Output enable (Active low)
Submit Documentation Feedback
3
TS5USBC400
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2)
MIN
MAX
UNIT
VCC
Supply voltage (3)
–0.5
6
V
VI/O
Input/Output DC voltage (D+, D-) (3)
–0.5
18
V
(3)
VI/O
Input/Output DC voltage (D1+/D1-, D2+/D2-)
–0.5
6
V
VI
Digital input voltage (SEL1, SEL2, OE)
–0.5
6
V
VO
Digital output voltage (FLT)
–0.5
6
V
IK
Input-output port diode current (D+, D-,
D1+, D1-, D2+, D2-)
VIN < 0
–50
mA
IIK
Digital logic input clamp current (SEL1,
SEL2, OE) (3)
VI < 0
–50
mA
ICC
Continuous current through VCC
IGND
Continuous current through GND
–100
Tstg
Storage temperature
–65
(1)
(2)
(3)
100
mA
mA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VCC
Supply voltage
VI/O (D+, D-)
VI/O (D1, D1-, D2+, D2-)
Analog input/output voltage
MIN
MAX
UNIT
2.3
5.5
V
0
18
V
0
3.6
V
V
VI
Digital input voltage (SEL1, SEL2, OE)
0
5.5
VO
Digital output voltage (FLT)
0
5.5
V
II/O (D+, D-, D1+, D1-, D2+, D2-)
Analog input/output port continuous current
-50
50
mA
IOL
Digital output current
3
mA
TA
Operating free-air temperature (TS5USBC400) Standard
0
70
ºC
TA
Operating free-air temperature (TS5USBC400I) Industrial
–40
85
ºC
TJ
Junction temperature
–40
125
ºC
4
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
6.4 Thermal Information
TS5USBC400
THERMAL METRIC
(1)
YFP
UNIT
12 PINS
RθJA
Junction-to-ambient thermal resistance
91.8
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
0.8
°C/W
Junction-to-board thermal resistance
22.8
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
23.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard), VCC = 2.3 V to 5.5 V, GND = 0V, Typical values are at VCC =
3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VCC
Power supply voltage
5.5
V
72
100
µA
OE = 0 V
SEL1, SEL2 = 0 V, 1.8 V or VCC
VI/O > VPOS_THLD
80
120
µA
OE = 1.8 V or VCC
SEL1 = 0 V, 1.8 V, or VCC
SEL2 = 0 V, 1.8 V, or VCC
2.2
10
µA
Active supply current
Supply current during OVP condition
Standby powered down supply
current
ICC
ICC_PD
2.3
OE = 0 V
SEL1, SEL2 = 0 V, 1.8 V or VCC
0 V < VI/O < 3.6 V
DC Characteristics
RON
ON-state resistance
VI/O = 0.4 V
ISINK = 8 mA
Refer to ON-State Resistance Figure
5.6
9
Ω
ΔRON
ON-state resistance match between
channels
VI/O = 0.4 V
ISINK = 8 mA
Refer to ON-State Resistance Figure
0.07
0.3
Ω
RON (FLAT)
ON-state resistance flatness
VI/O = 0 V to 0.4 V
ISINK = 8 mA
Refer to ON-State Resistance Figure
0.07
0.4
Ω
IOFF
ION
I/O pin OFF leakage current
ON leakage current
VD± = 0 V or 3.6 V
VCC = 2.3 V to 5.5 V
VD1±or VD2+/- = 3.6 V or 0 V
Refer to Off Leakage Figure
-1
1.2
6
µA
VD± = 0 V or 16 V
VCC = 2.3 V to 5.5 V
VD1± or VD2+/- = 0 V
Refer to Off Leakage Figure
-1
165
200
µA
VD± = 0 V or 3.6 V
VD1± and VD2+/- = high-Z
Refer to On Leakage Figure
-1
1.2
6
µA
Digital Characteristics
VIH
Input logic high
SEL1, SEL2, OE
VIL
Input logic low
SEL1, SEL2, OE
0.5
V
VOL
Output logic low
FLT
IOL = 3 mA
0.4
V
IIH
Input high leakage current
SEL1, SEL2, OE = 1.8 V, VCC
-1
1
5
μA
IIL
Input low leakage current
SEL1, SEL2, OE = 0 V
-1
±0.2
5
μA
Copyright © 2017, Texas Instruments Incorporated
1.4
V
Submit Documentation Feedback
5
TS5USBC400
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
www.ti.com
Electrical Characteristics (continued)
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard), VCC = 2.3 V to 5.5 V, GND = 0V, Typical values are at VCC =
3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
RPD
Internal pull-down resistor on digital
input pins
CI
Digital input capacitance
TEST CONDITIONS
MIN
SEL1, SEL2 = 0 V, 1.8 V or VCC
f = 1 MHz
TYP
MAX
UNIT
6
MΩ
3.4
pF
Protection
VOVP_TH
OVP positive threshold
4.5
4.8
5.2
V
VOVP_HYST
OVP threshold hysteresis
75
230
425
mV
VCLAMP_V
Maximum voltage to appear on D1±
and D2± pins during OVP scenario
VD± = 0 to 18 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = Open
Switch on or off
OE = 0 V
0
9.6
V
VD± = 0 to 18 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = 50Ω
Switch on or off
OE = 0 V
0
9.0
V
tEN_OVP
OVP enable time
RPU = 10 kΩ to VCC (FLT)
CL = 35 pF
Refer to OVP Timing Diagram Figure
0.6
3
μs
tREC_OVP
OVP recovery time
RPU = 10 kΩ to VCC (FLT)
CL = 35 pF
Refer to OVP Timing Diagram Figure
1.5
5
μs
6
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
6.6 Dynamic Characteristics
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard), VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC =
3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
OISO
MIN
TYP
MAX
UNIT
1.2
3.5
6.2
pF
D+, D- off capacitance
D1+, D1-, D2+, D2- off
capacitance
VD+/- = 0 or 3.3 V,
OE = VCC or OE = 0V with SEL1, Switch OFF or
SEL2 (switch not selected)
not selected
f = 240 MHz
1.2
3.5
6.2
pF
IO pins ON capacitance
VD+/- = 0 or 3.3 V,
f = 240 MHz
Switch ON
1.4
4.5
6.2
pF
RL = 50 Ω
CL = 5 pF
f = 100 kHz
Refer to Off Isolation Figure
Switch OFF
-90
dB
RL = 50 Ω
CL = 5 pF
f = 240 MHz
Refer to Off Isolation Figure
Switch OFF
-22
dB
RL = 50 Ω
CL = 5 pF
f = 100 kHz
Refer to Crosstalk Figure
Switch ON
-90
dB
Switch ON
1.1
GHz
Switch ON
-0.7
dB
COFF
CON
TEST CONDITIONS
VD+/- = 0 or 3.3 V,
OE = VCC
f = 240 MHz
Differential off isolation
XTALK
Channel to Channel crosstalk
BW
Bandwidth
ILOSS
Insertion loss
Switch OFF
RL = 50 Ω; Refer to BW and
Insertion Loss Figure
RL = 50 Ω
f = 240 MHz; Refer to BW and
Insertion Loss Figure
6.7 Timing Requirements
TA = –40°C to +85°C (Industrial), TA = 0℃ to 70℃ (Standard), VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC =
3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tswitch
Switching time between channels
(SEL1, SEL2 to output)
VD+/- = 0.8 V
Refer to Tswitch Timing Figure
ton
Device turn on time (OE to output)
VD+/- = 0.8 V
Refer to Ton and Toff Figure
toff
Device turn off time (OE to output)
VD+/- = 0.8 V
Refer to Ton and Toff Figure
tSK(P)
Skew of opposite transitions of
same output (between D+ and D-)
VD+/- = 0.4 V
Refer to Tsk Figure
tpd
Propagation delay
VD+/- = 0.4 V
Refer to Tpd Figure
Copyright © 2017, Texas Instruments Incorporated
MIN
NOM
MAX
0.45
1.2
µs
100
250
µs
0.35
1
µs
RL = 50 Ω,
CL = 1 pF,
VCC = 2.3 V to 5.5 V
9
50
ps
RL = 50 Ω,
CL = 5 pF,
VCC = 2.3 V to 5.5 V
130
180
ps
RL = 50 Ω,
CL = 5 pF,
VCC = 2.3 V to 5.5 V
Submit Documentation Feedback
UNIT
7
TS5USBC400
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
www.ti.com
6.8 Typical Characteristics
8
RON, Resistance (:)
7.5
7
6.5
6
5.5
5
4.5
4
0
0.4
0.8
1.2
1.6
2
2.4
VIN, Input Voltage (V)
2.8
3.2
3.6
D001
VCC = 3.3 V
TA = 25°C
Figure 1. ON-Resistance vs Input Voltage
8
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
7 Parameter Measurement Information
V
VD+/-
ISINK
Switch
Channel ON, RON = V/ISINK
Figure 2. ON-State Resistance (RON)
VD+/-
A
A
VDX+/-
Switch
Figure 3. Off Leakage
VD+/-
A
Switch
Figure 4. On Leakage
VD1+/VD+/-
VD2+/-
SEL
CL
CL
RL
RL
VSEL
1.8 V
1.8 V
VSEL
0.8 V
VSEL
1.2 V
1.2 V
0.8 V
0V
0V
tSWITCH
tSWITCH
tSWITCH
tSWITCH
VD+/-
VD+/-
VD1+/-
80 %
VD2+/-
20 %
80 %
20 %
0V
0V
Copyright © 2017, Texas Instruments Incorporated
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2)
CL includes probe and jig capacitance.
Figure 5. tSWITCH Timing
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
9
TS5USBC400
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
www.ti.com
Parameter Measurement Information (continued)
2.3 V
VCC
VD+/-
1.8 V
VOE
CL
OE
0.8 V
1.2 V
RL
0V
tON
tOFF
VD+/-
VDX+/-
VOE
90 %
10 %
0V
Copyright © 2017, Texas Instruments Incorporated
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2)
CL includes probe and jig capacitance.
Figure 6. tON, tOFF for OE
Network Analyzer
Switch
50 O
D+
50 O
Source
Signal
50 O
D-
50 O
Source
Signal
50 O
50 O
Copyright © 2017, Texas Instruments Incorporated
Figure 7. Off Isolation
Network Analyzer
50
Switch
D+
50
Source
Signal
50
D50
50
50
Copyright © 2017, Texas Instruments Incorporated
Figure 8. Cross Talk
10
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
Parameter Measurement Information (continued)
Network Analyzer
Switch
50
D+
50
Source
Signal
50
D50
Source
Signal
50
50
Copyright © 2017, Texas Instruments Incorporated
Figure 9. BW and Insertion Loss
18 V
VD+/-
VD+/-
VPOS_THLD
0V
CL
OE
RL
tEN_OVP
tREC_OVP
VOE
VCC
FLT
10 %
10 %
0V
Copyright © 2017, Texas Instruments Incorporated
Figure 10. tEN_OVP and tDIS_OVP Timing Diagram
Switch
D+/50
0.4 V
VD+/-
50 %
50 %
0V
50
tPD
tPD
VDX+/-
50 %
0.4 V
50 %
0V
Copyright © 2017, Texas Instruments Incorporated
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2)
CL includes probe and jig capacitance.
Figure 11. tPD
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
11
TS5USBC400
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
www.ti.com
Parameter Measurement Information (continued)
Switch
D+
0.4 V
50 O
VD+/0V
50 O
0.4 V
VDX+
D-
50 %
50 %
0V
tSK
50 O
50 O
tSK
0.4 V
VDX-
50 %
50 %
0V
Copyright © 2017, Texas Instruments Incorporated
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2)
CL includes probe and jig capacitance.
Figure 12. tSK
12
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
8 Detailed Description
8.1 Overview
The TS5USBC400 is a bidirectional low-power dual port, high-speed, USB 2.0 analog switch with integrated
protection for USB Type-C systems. The device is configured as a dual 2:1 or 1:2 switch and is optimized for
handling the USB 2.0 D+/- lines in a USB Type-C system as shown in Figure 13.
Figure 13. USB Type-C Connector Pinout
The TS5USBC400 also works in traditional USB systems that need protection from fault conditions such as
automotive and applications that require higher voltage charging. The device maintains excellent signal integrity
through the optimization of both RON and BW while protecting the system with 0 V to 16 V OVP protection. The
OVP implementation is designed to protect sensitive system components behind the switch that cannot survive a
fault condition where VBUS is shorted the D+ and D- pins on the connector.
8.2 Functional Block Diagram
VCC
SEL1
6M
SEL2
Control
Logic
6M
FLT
OE
6M
VOVP
OVP
D1+
D+
D1-
D2+
DD2Switches
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
13
TS5USBC400
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
www.ti.com
8.3 Feature Description
8.3.1 Powered-off Protection
When the TS5USBC400 is powered off the I/Os of the device remain in a high-Z state. The crosstalk, offisolation, and leakage remain within the Electrical Specifications.
This prevents errant voltages from reaching the rest of the system and maintains isolation when the system is
powering up.
8.3.2 Overvoltage Protection
The OVP of the TS5USBC400 is designed to protect the system from D+/- shorts to VBUS at the USB and USB
Type-C connector. Figure 14 depicts a moisture short that would cause 16 V to appear on an existing USB
solution that could pass through the device and damage components behind the device.
VBUS
VBUS
SBU2
CC1
D+
D-
D+
Moisture
16 V
D-
CC2
SBU1
VBUS
VBUS
D1+
D2+
DD+
UART
USB
Existing Solutions
D1D2-
USB
Copyright © 2017, Texas Instruments Incorporated
Figure 14. Existing Solution Being Damaged by a Short, 16 V
The TS5USBC400 will open the switches and protect the rest of the system by blocking the 16 V as depicted in .
14
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
Feature Description (continued)
16 9 GRHVQ¶W UHDFK
rest of system
VBUS
VBUS
SBU2
CC1
UART
USB
D+
D-
D+
D+
D-
D2+
D-
Moisture
16 V
D1+
D1D2-
CC2
SBU1
VBUS
VBUS
USB
Copyright © 2017, Texas Instruments Incorporated
Figure 15. Protecting During a 16-V Short
Figure 16 is a waveform showing the voltage on the pins during an over-voltage scenario.
16 V
VOVP_THLD
D+/0V
D1/D2
0V
FLT
Figure 16. Overvoltage Protection Waveform, 16 V
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
15
TS5USBC400
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
www.ti.com
8.4 Device Functional Modes
8.4.1 Pin Functions
Table 1. Function Table
16
OE
SEL1
SEL2
D- Connection
D+ Connection
H
X
X
High-Z
High-Z
L
L
L
D- to D1-
D+ to D1+
L
L
H
D- to D1-
D+ to D2+
L
H
L
D- to D2-
D+ to D1+
L
H
H
D- to D2-
D+ to D2+
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
There are many USB applications in which the USB hubs or controllers have a limited number of USB I/Os or
need to route signals from a single USB connector. The TS5USBC400 solution can effectively expand the limited
USB I/Os by switching between multiple USB buses to interface them to a single USB hub or controller or route
signals from on connector to two different locations. With independent control of the two switches using SEL1
and SEL2, TS5USBC400 can be used to cross switch single ended signals.
9.2 Typical Application
USB
Connector
VCC
VBUS
TS5USBC400 USB/UART switch. The TS5USBC400 is used to switch signals between the USB path, which
goes to the baseband or application processor, or the UART path, which goes to debug port. The TS5USBC400
has internal 6-MΩ pull-down resistors on SEL1, SEL2, and OE. The pull-down on SEL1 and SEL2 pins ensure
the D1+/D1- channel is selected by default. The pull-down on OE enables the switch when power is applied.
UART
USB
VCC
DP_T
100 nF
OVP
DP_B
D1+
D2+
DM_T
D1D2SEL1
OE
Logic
Control
GND
SEL2
DM_B
USB
FLT
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 17. Typical TS5USBC400 Application
9.2.1 Design Requirements
Design requirements of USB 1.0,1.1, and 2.0 standards must be followed. The TS5USBC400 has internal 6-MΩ
pulldown resistors on SEL1, SEL2, and OE, so no external resistors are required on the logic pins. The internal
pull-down resistor on SEL1 and SEL2 pins ensures the D1+ and D1- channels are selected by default. The
internal pull-down resistor on OE enables the switch when power is applied to VCC.
9.2.2 Detailed Design Procedure
The TS5USBC400can be properly operated without any external components. However, TI recommends that
unused pins must be connected to ground through a 50-Ω resistor to prevent signal reflections back into the
device. TI does recommend a 100nF bypass capacitor placed close to TS5USBC400 VCC pin.
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
17
TS5USBC400
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
www.ti.com
Typical Application (continued)
0.4
0.4
0.2
0.2
Differential Signal (V)
Differential Signal (V)
9.2.3 Application Curves
0.0
-0.2
0.0
-0.2
-0.4
-0.4
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Time (ns)
Time (ns)
Figure 18. High Speed Eye Diagram With TS5USBC400
Figure 19. High Speed Eye Diagram Without TS5USBC400
10 Power Supply Recommendations
Power to the device is supplied through the VCC pin and must follow the USB 1.0, 1.1, and 2.0 standards. TI
recommends placing a 100nF bypass capacitor as close to the supply pin VCC as possible to help smooth out
lower frequency noise to provide better load regulation across the frequency spectrum.
18
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
11 Layout
11.1 Layout Guidelines
1. Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the
D± traces.
2. The high-speed D± must match and be no more than 4 inches long; otherwise, the eye diagram performance
may be degraded. A high-speed USB connection is made through a shielded, twisted pair cable with a
differential characteristic impedance. In layout, the impedance of D+ and D– traces must match the cable
characteristic differential impedance for optimal performance.
3. Route the high-speed USB signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points on twisted
pair lines; through-hole pins are not recommended.
4. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
5. Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices or ICs that use or duplicate clock signals.
6. Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable,
then the stub must be less than 200 mm.
7. Route all high-speed USB signal traces over continuous GND planes, with no interruptions.
8. Avoid crossing over anti-etch, commonly found with plane splits.
9. Due to high frequencies associated with the USB, a printed circuit board with at least four layers is
recommended; two signal layers separated by a ground and power layer as shown in Figure 20.
Signal 1
GND Plane
Power Plane
Signal 2
Figure 20. Four-Layer Board Stack-Up
The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer must
be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power
plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the
number of signal vias reduces EMI by reducing inductance at high frequencies.
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
19
TS5USBC400
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
www.ti.com
11.2 Layout Example
Example 4 layer PCB Stackup
Top Layer 1 (Signal1)
Inner Layer 2 (GND)
Inner Layer 3 (VCC)
Bottom Layer 4 (Signal2)
Via to layer 2 (GND)
Via to layer 3 (VCC)
Via to layer 4 (Signal)
D+
D-
FLT#
SEL1
A1
A2
A2
B2
B3
A3
Place near VCC pin.
VCC
SEL2
C1
D2+
OE#
B4
B1
C2
D2-
GND
C3
C4
D1+
D1-
Figure 21. Layout Example
20
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• USB 2.0 Board Design and Layout Guidelines
• High-Speed Layout Guidelines Application Report
• High-Speed Interface Layout Guidelines
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
USB Type-C is a trademark of USB Implementers Forum.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
21
TS5USBC400
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
www.ti.com
PACKAGE OUTLINE
YFP0012-C01
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
1.612
1.552
B
A
BALL A1
CORNER
1.212
1.152
C
0.5 MAX
SEATING PLANE
0.19
0.13
BALL TYP
0.05 C
1.2 TYP
SYMM
C
0.8
TYP
SYMM
B
0.4 TYP
A
1
12X
0.015
0.25
0.21
C A B
2
3
4
0.4
TYP
4223498/B 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
22
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
TS5USBC400
www.ti.com
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
EXAMPLE BOARD LAYOUT
YFP0012-C01
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
12X (
0.23)
1
2
3
4
A
(0.4) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:50X
( 0.23)
METAL
SOLDER MASK
OPENING
0.05 MAX
0.05 MIN
EXPOSED
METAL
EXPOSED
METAL
NON-SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
( 0.23)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223498/B 04/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
23
TS5USBC400
SCDS374A – SEPTEMBER 2017 – REVISED SEPTEMBER 2017
www.ti.com
EXAMPLE STENCIL DESIGN
YFP0012-C01
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
12X ( 0.25)
1
3
2
4
A
(0.4) TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:50X
4223498/B 04/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
24
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
6-Oct-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TS5USBC400IYFPR
ACTIVE
DSBGA
YFP
12
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
USB4
TS5USBC400IYFPT
ACTIVE
DSBGA
YFP
12
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
USB4
TS5USBC400YFPR
ACTIVE
DSBGA
YFP
12
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
0 to 70
USB4
TS5USBC400YFPT
ACTIVE
DSBGA
YFP
12
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
0 to 70
USB4
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Oct-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Mar-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TS5USBC400IYFPR
DSBGA
YFP
12
3000
180.0
8.4
TS5USBC400IYFPT
DSBGA
YFP
12
250
180.0
TS5USBC400YFPR
DSBGA
YFP
12
3000
180.0
TS5USBC400YFPT
DSBGA
YFP
12
250
180.0
1.32
1.72
0.62
4.0
8.0
Q2
8.4
1.32
1.72
0.62
4.0
8.0
Q2
8.4
1.32
1.72
0.62
4.0
8.0
Q2
8.4
1.32
1.72
0.62
4.0
8.0
Q2
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Mar-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TS5USBC400IYFPR
DSBGA
YFP
12
3000
182.0
182.0
20.0
TS5USBC400IYFPT
DSBGA
YFP
12
250
182.0
182.0
20.0
TS5USBC400YFPR
DSBGA
YFP
12
3000
182.0
182.0
20.0
TS5USBC400YFPT
DSBGA
YFP
12
250
182.0
182.0
20.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising