Texas Instruments | TPD4E001-Q1 4-Channel ESD Protection Array With 1.5-pF I/O Capacitance (Rev. F) | Datasheet | Texas Instruments TPD4E001-Q1 4-Channel ESD Protection Array With 1.5-pF I/O Capacitance (Rev. F) Datasheet

Texas Instruments TPD4E001-Q1 4-Channel ESD Protection Array With 1.5-pF I/O Capacitance (Rev. F) Datasheet
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TPD4E001-Q1
SLLSEG0F – MARCH 2013 – REVISED SEPTEMBER 2017
TPD4E001-Q1 4-Channel ESD Protection Array With 1.5-pF I/O Capacitance
1 Features
3 Description
•
The TPD4E001-Q1 device is a low-capacitance TVS
diode array designed for ESD protection in sensitive
electronics connected to communication lines. Each
channel consists of a pair of transient-voltagesuppression diodes that steer ESD pulses to VCC or
GND. The TPD4E001-Q1 protects against ESD
events up to ±8-kV contact discharge and ±15-kV airgap discharge, as specified in IEC 61000-4-2
international standard. This device has a low
capacitance of 1.5-pF per channel making it ideal for
use in high-speed data interfaces. The low leakage
current (10 nA maximum) ensures minimum power
consumption for the system and high accuracy for
analog interfaces.
1
•
•
•
•
•
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 3B
– HBM Level 15 kV
– Device CDM ESD Classification Level C5
IEC 61000-4-2 Level 4 ESD Protection
– ±8-kV Contact Discharge
– ±15-kV Air-Gap Discharge
IEC 61000-4-5 Surge Protection
– 5.5 A (8/20 µs)
Low 1.5-pF Input Capacitance
Low 10-nA Maximum Leakage Current
0.9-V to 5.5-V Supply Voltage Range
Additionally, this device is ideal for protecting
automotive head units, automotive rear seat
entertainment, and automotive rear camera systems
that use USB 2.0, Ethernet, or precision analog
interfaces.
2 Applications
•
•
Device Information(1)
End Equipment
– Automotive Head Unit
– Automotive Rear Seat Entertainment
– Automotive Rear Camera Systems
Interfaces
– USB 2.0
– Ethernet
– Precision Analog Interfaces
PART NUMBER
TPD4E001-Q1
PACKAGE
SOT-23 (6)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Schematic
VBUS
0.1 µF
VCC
D+
D–
RT
GND
IO4
IO1
USB
Controller
D1
IO3
IO2
VBUS
D+
GND
D–
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD4E001-Q1
SLLSEG0F – MARCH 2013 – REVISED SEPTEMBER 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
5
5
6
Absolute Maximum Ratings .....................................
ESD Ratings—AEC Specification .............................
ESD Ratings—IEC Specification ..............................
ESD Ratings—ISO Specification ..............................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description .................................................. 7
7.4 Device Functional Modes.......................................... 8
8
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application ................................................... 9
9 Power Supply Recommendations...................... 11
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................. 12
10.2 Layout Example .................................................... 12
11 Device and Documentation Support ................. 13
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13
12 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (June 2017) to Revision F
•
Added ISO Specification......................................................................................................................................................... 4
Changes from Revision D (March 2015) to Revision E
•
Page
Page
Updated Typical Application Schematic ................................................................................................................................. 9
Changes from Revision C (June 2013) to Revision D
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
•
Changed Device CDM ESD Classification Level from C4B to C5 ........................................................................................ 1
Changes from Revision B (February 2012) to Revision C
•
Page
Changed maximum ICC supply current in Electrical Characteristics....................................................................................... 5
Changes from Revision A (April 2013) to Revision B
Page
•
Revised text in DESCRIPTION section .................................................................................................................................. 1
•
Revised Figure 2 graph .......................................................................................................................................................... 5
•
Revised APPLICATION INFORMATION schematic .............................................................................................................. 9
2
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5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
IO1
1
6
IO4
GND
2
5
VCC
IO2
3
4
IO3
Pin Functions
PIN
NAME
NO.
GND
2
IO1
1
IO2
3
IO3
4
IO4
6
VCC
5
TYPE
GND
I/O
I
DESCRIPTION
Ground
ESD-protected channel
Power-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.3
7
V
VIO
I/O voltage tolerance
–0.3
VCC + 0.3
V
IPP
Peak pulse current (Tp = 8/20 µs) (2)
5.5
A
PPP
Peak pulse power (Tp = 8/20 µs) (2)
100
W
TA
Free air operating temperature
125
°C
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–40
–65
SStresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Non-repetitive current pulse 8/20 µs exponentially decaying waveform according to IEC 61000-4-5.
6.2 ESD Ratings—AEC Specification
VALUE
V(ESD)
(1)
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002
(1)
UNIT
±15000
Charged-device model (CDM), per AEC Q100-011
V
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC Specification
VALUE
V(ESD)
Electrostatic discharge
IEC 61000-4-2 contact discharge
±8000
IEC 61000-4-2 air-gap discharge
±15000
UNIT
V
6.4 ESD Ratings—ISO Specification
VALUE
V(ESD)
4
Electrostatic discharge
ISO 10605 (330 pF, 330 Ω) contact discharge
±8000
ISO 10605 (330 pF, 330 Ω) air-gap discharge
±15000
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UNIT
V
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6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
TA
Free air operating temperature
–40
125
°C
VCC pin
Operating voltage
0.9
5.5
V
IO1, IO2, IO3,
IO4 pins
Operating voltage
0
VCC
V
6.6 Thermal Information
TPD4E001-Q1
THERMAL METRIC
(1)
DBV (SOT-23)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
202.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
146.2
°C/W
RθJB
Junction-to-board thermal resistance
47.1
°C/W
ψJT
Junction-to-top characterization parameter
37.6
°C/W
ψJB
Junction-to-board characterization parameter
46.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.7 Electrical Characteristics
VCC = 5 V ± 10%, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ICC
Supply current
VF
Diode forward voltage
IF = 10 mA
VBR
Breakdown voltage
IBR = 10 mA
MIN
TYP (1)
1
0.65
MAX
UNIT
200
nA
0.95
V
11
V
(2)
VCLAMP
Clamping voltage
Surge strike on IO pin, GND pin
grounded, VCC = 5.5 V, IPP = 5.5 A
VRWM
Reverse standoff voltage
IO pin to GND pin
IIO
Channel leakage current
VIO = GND to VCC
CIO
Channel input capacitance
VCC = 5 V, bias of VCC/2, f = 10 MHz
(1)
(2)
Positive transients
16
V
5.5
V
±10
nA
1.5
pF
Typical values are at VCC = 5 V and TA = 25°C.
Non-repetitive current pulse 8/20 µs exponentially decaying waveform according to IEC 61000-4-5.
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6.8 Typical Characteristics
2.20
100
VIO = 5.5 V
VCC = 5.5 V
90
IO Leakage Current (pA)
IO Capacitance (pF)
2.00
1.80
1.60
1.40
1.20
80
70
60
50
40
30
20
10
1.00
1.00
2.00
2.50
3.00
4.00
0
5.00
±55
±35
±15
IO Voltage (V)
IPP (A)
6
25
45
65
85
105
Temperature (ºC)
Figure 1. IO Capacitance vs IO Voltage (VCC = 5 V)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5
125
C001
Figure 2. IO Leakage Current vs Temperature
100
90
80
70
Current (A)
60
50
40
PPP (W)
0.00
30
Power (W)
20
10
0
5
10
15
20
25
30
35
40
45
Time (μs)
Figure 3. Peak Pulse Waveform, VCC = 5.5 V
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50
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7 Detailed Description
7.1 Overview
The TPD4E001-Q1 device is a low-capacitance, TVS diode array designed for ESD protection in sensitive
electronics connected to communication lines. Each channel consists of a pair of transient voltage suppression
diodes that steer ESD pulses to VCC or GND. The TPD4E001-Q1 device protects against ESD events up to ±8kV contact discharge and ±15-kV air-gap discharge, as specified in IEC 61000-4-2 international standard. This
device has a low capacitance of 1.5-pF per channel making it ideal for use in high-speed data interfaces. The
low-leakage current (10 nA maximum) ensures minimum power consumption for the system and high accuracy
for analog interfaces.
7.2 Functional Block Diagram
VCC
IO1
IO3
IO2
IO4
GND
7.3 Feature Description
7.3.1 AEC-Q100 Qualified
This device is qualified according to the AEC-Q100 standard. The device temperature rating is Grade 1 (–40°C
to +125°C). The HBM Classification Level passed is 3B (> 8 kV). The CDM Classification Level passed is C5 (all
pins 750 V to <1000 V).
7.3.2 IEC 61000-4-2 Level 4 ESD Protection
The device is specified at ±8-kV contact discharge and ±15-kV air gap discharge.
7.3.3 IEC 61000-4-5 Surge Protection
This device is rated to pass at least 5.5-A of peak pulse current according to the IEC 61000-4-5 (8/20-µs pulse)
standard.
7.3.4 Low 1.5-pF Input Capacitance
This device has a typical capacitance of 1.5-pF on each of the four IO pins. This allows for high speed signals on
the IO pins in excess of 1 Gbps.
7.3.5 Low 10-nA (Maximum) Leakage Current
This device is rated to have a maximum leakage current of 10-nA on each of the four IO pins.
7.3.6 0.9-V to 5.5-V Supply Voltage Range
This device is specified to operate with a supply voltage (on VCC) between 0.9-V and 5.5-V to ensure sufficient
signal integrity.
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7.4 Device Functional Modes
The TPD4E001-Q1 device is a passive integrated circuit that triggers when voltages are above VBR or below the
lower diodes VF (–0.6 V). During ESD events, voltages as high as ±8 kV (contact) can be directed to ground via
the internal diode network. Once the voltages on the protected line fall below the trigger levels of TPD4E001-Q1
(usually within 10s of nano-seconds) the device reverts back to its high-impedance state.
8
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPD4E001-Q1 device is a TVS diode array which is typically used to provide a path to ground for dissipating
ESD events on high-speed signal lines between a human interface connector and a system. As the current from
ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage
presented to the protected IC. The triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
For this design example, one TPD4E001-Q1 device is being used in a dual USB 2.0 application. This provides a
complete port protection scheme.
VBUS
0.1 µF
VCC
D+
D–
RT
GND
IO4
IO1
USB
Controller
D1
IO3
IO2
VBUS
D+
GND
D–
GND
Figure 4. Typical Application Schematic
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, a single TPD4E001-Q1 device is used to protect all the pins on two USB2.0 connectors.
Given the USB application, known parameters are listed in the Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
Signal range on IO1, IO2, IO3, or IO4
0 V to 3.6 V
Voltage range on VCC
0 V to 5.25 V
Operating Frequency on IO1, IO2, IO3, or IO4
240 MHz
8.2.2 Detailed Design Procedure
To begin the design process, some parameters must be decided upon; the designer needs to know the following:
• Signal range on all protected lines
• Operating frequency on all protected lines
8.2.2.1 Signal Range on IO1 Through IO4
The TPD4E001-Q1 device has 4 identical protection channels for signal lines. The symmetry of the device
provides flexibility when selecting which of the 4 IO channels protects which signal lines. Any IO supports a
signal range of 0 to (VCC + 0.3) V. Therefore, this device supports the USB 2.0 signal swing assuming VCC is set
appropriately.
8.2.2.2 Voltage Range on VCC
The VCC pin can be connected in one of two ways:
• If the VCC pin connects to the system power supply, the TPD4E001-Q1 device works as a transient
suppressor for any signal swing above VCC + VF. TI recommends a 0.1-μF capacitor on the device VCC pin for
ESD bypass.
• If the VCC pin does not connect to the system power supply, the TPD4E001-Q1 device can tolerate higher
signal swing in the range up to 10 V. Note that TI still recommends a 0.1-μF capacitor at the VCC pin for ESD
bypass.
If this pin is connected to the USB 2.0 VBUS supply or left floating, the allowable signal swing is enough for a USB
2.0 application.
8.2.2.3 Bandwidth on IO1 Through IO4
Each IO pin on the TPD4E001-Q1 device has a typical capacitance of 1.5 pF. This capacitance is low enough to
easily support USB 2.0 data rates.
10
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8.2.3 Application Curve
100
90
80
70
60
Time (ns)
50
40
30
20
10
0
-10
-20
-30
-40
-15
0
15
30
45
60 75 90
Voltage (V)
105 120 135 150
G001
Figure 5. IEC 61000-4-2 Voltage Clamp Waveform 8-kV Contact
9 Power Supply Recommendations
This device is a passive ESD protection device so there is no need to power it. Do not violate the maximum
voltage specifications for each pin.
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10 Layout
10.1 Layout Guidelines
When placed near the connector, the TPD4E001-Q1 device's ESD solution offers little or no signal distortion
during normal operation due to low IO capacitance and ultra-low leakage-current specifications. The TPD4E001Q1 device ensures that the core circuitry is protected and the system is functioning properly in the event of an
ESD strike. For proper operation, observe the following layout and design guidelines:
• Place the TPD4E001-Q1 device solution close to the connector. This allows the device to take away the
energy associated with ESD strike before it reaches the internal circuitry of the system board.
• Place a 0.1-μF capacitor very close to the VCC pin. This limits any momentary voltage surge at the IO pin
during the ESD strike event.
• Ensure that there is enough metallization for the VCC and GND loop. During normal operation, the TPD4E001Q1 device consumes nA leakage current. But during the ESD event, VCC and GND may see 15 A to 30 A of
current, depending on the ESD level. Sufficient current path enables safe discharge of all the energy
associated with the ESD strike.
• Leave the unused IO pins floating.
• One can connect the VCC pin in two different ways:
a. If the VCC pin connects to the system power supply, the TPD4E001-Q1 works as a transient suppressor
for any signal swing above VCC + VF. TI recommends a 0.1-μF capacitor on the device VCC pin for ESD
bypass.
b. If the VCC pin does not connect to the system power supply, the TPD4E001-Q1 can tolerate higher signal
swing in the range up to 10 V. Note that TI still recommends a 0.1-μF capacitor at the VCC pin for ESD
bypass.
• The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
IO1
IO2
GND
0.1µF
GND
VCC
IO3
IO4
Legend
= VIA to GND
= VIA to other layer
= top layer
= bottom layer
12
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Reading and Understanding an ESD Protection Datasheet
• ESD Layout Guide
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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23-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPD4E001QDBVRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOT-23
DBV
6
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
AAXQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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OTHER QUALIFIED VERSIONS OF TPD4E001-Q1 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2017
• Catalog: TPD4E001
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPD4E001QDBVRQ1
Package Package Pins
Type Drawing
SPQ
SOT-23
3000
DBV
6
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
178.0
9.0
Pack Materials-Page 1
3.23
B0
(mm)
K0
(mm)
P1
(mm)
3.17
1.37
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD4E001QDBVRQ1
SOT-23
DBV
6
3000
180.0
180.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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