Texas Instruments | TUSB212-Q1 USB 2.0 High Speed Signal Conditioner | Datasheet | Texas Instruments TUSB212-Q1 USB 2.0 High Speed Signal Conditioner Datasheet

Texas Instruments TUSB212-Q1 USB 2.0 High Speed Signal Conditioner Datasheet
Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TUSB212-Q1
SLLSF35 – SEPTEMBER 2017
TUSB212-Q1 USB 2.0 High Speed Signal Conditioner
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
Qualified for Automotive Applications:
– Device Temperature Grade 2: –40°C to 105°C
Ambient Operating Temperature
– Device HBM Classification Level H1C
– Device CDM Classification Level C3
Compatible with USB 2.0, OTG 2.0 and BC 1.2
Pin strap or I2C configurable
Support for LS, FS, HS signaling
Ultra-low USB Disconnect and Shutdown Power
Consumption
Selectable Signal Gain Via Daisy Chain Device for
High Loss Applications
D1P/M and D2P/M Interchangeable and
Host/Device Agnostic
Supports up to 5m pre-channel or 2m postchannel Cable Length
– Four Selectable AC Boost Settings Via
External Pulldown Resistor
– DC Boost Along With AC Boost for Best Signal
Integrity
Automotive Infotainment
Notebooks
Desktops
Docking Stations
Tablets
Cell Phones
Active Cable, Cable Extenders
Backplane
Televisions
3 Description
The TUSB212-Q1 is a USB High-Speed (HS) signal
conditioner, designed to compensate for ISI signal
loss in a transmission channel.
TUSB212-Q1 has a patent-pending design which is
agnostic to USB Low Speed (LS) and Full Speed
(FS) signals. LS and FS signal characteristics are
unaffected by the TUSB212-Q1 while HS signals are
compensated.
Programmable signal AC boost and DC boost permits
fine tuning device performance to optimize High
Speed signals at the connector. This helps to pass
USB High Speed electrical compliance tests.
In addition, TUSB212-Q1 is compatible with the USB
On-The-Go (OTG) and Battery Charging (BC)
protocols.
Device Information
PART NUMBER
TUSB212-Q1
PACKAGE
X2QFN (12)
(1)
BODY SIZE (NOM)
1.60 mm x 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
SPACER
Display
Simplified Schematic
3.3 V
VCC
TUSB212-Q1
USB Host
(Head Unit)
Cable
D2
D1
USB
Connector
Copyright © 2017, Texas Instruments Incorporated
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB212-Q1
SLLSF35 – SEPTEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
2
DATE
REVISION
NOTES
September 2017
*
Initial release.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
TUSB212-Q1
www.ti.com
SLLSF35 – SEPTEMBER 2017
5 Pin Configuration and Functions
RWB Package
12 Pin (X2QFN)
Top View
D1P D1M
3
SCL/CD
4
11 VREG
RSTN
5
10 GND
EQ
6
2
7
12
VCC
SDA
1
8
9
DC_BOOST/
ENA_HS
D2P D2M
Pin Functions
PIN
INTERNAL
PULLUP/PULLDOWN
I/O
NAME
NO.
DESCRIPTION
D1M
1
I/O
N/A
USB High Speed negative port..
D1P
2
I/O
N/A
USB High Speed positive port.
SDA (1)
3
I/O
RSTN asserted: 500 kΩ PD
I2C Mode:
Bidirectional I2C data pin [I2C address = 0x2C].
In non I2C mode:
Reserved for TI test purpose.
RSTN asserted: 500 kΩ PD
In I2C mode:
I2C clock pin [I2C address = 0x2C].
Non I2C mode:
After reset: Output CD. Flag indicating that a USB device is attached (connection
detected). Asserted from an unconnected state upon detection of DP or DM pull-up
resistor. De-asserted upon detection of disconnect.
SCL (1)/CD
4
I/O
RSTN
5
I
500 kΩ PU
Device disable/enable.
Low – Device is at reset and in shutdown, and
High – Normal operation.
Recommend 0.1-µF external capacitor to GND to ensure clean power on reset if not
driven.
If the pin is driven, it must be held low until the supply voltage for the device reaches
within specifications.
EQ
6
I
N/A
USB High Speed AC boost select via external pull down resistor.
Sampled upon de-assertion of RSTN. Does not recognize real time adjustments.
Auto selects max AC Boost when left floating.
D2P
7
I/O
N/A
USB High Speed positive port.
D2M
8
I/O
N/A
USB High Speed negative port.
In I2C mode:
Reserved for TI test purpose.
In non-I2C mode:
At reset: 3-level input signal DC_BOOST. USB High Speed DC signal boost selection.
H (pin is pulled high) – 80 mV
M (pin is left floating) – 60 mV
L (pin is pulled low) – 40 mV
After reset: Output signal ENA_HS. Flag indicating that channel is in High Speed mode.
Asserted upon:
1. Detection of USB-IF High Speed test fixture from an unconnected state followed by
transmission of USB TEST_PACKET pattern.
2. Squelch detection following USB reset with a successful HS handshake [HS
handshake is declared to be successful after single chirp J chirp K pair where each chirp
is within 18 μs – 128 μs].
DC_BOOST (2)/
ENA_HS
9
I/O
GND
10
P
N/A
Ground
VREG
11
O
N/A
1.8-V LDO output. Only enabled when operating in High Speed mode. Requires 0.1-µF
external capacitor to GND to stabilize the core.
VCC
12
P
N/A
(1)
(2)
Supply power
2
Pull-up resistors for SDA and SCL pins in I C mode should be 4.7 kΩ (5%). If both SDA and SCL are pulled up at reset the device
enters into I2C mode.
Pull-down and pull-up (to 3.3 V) resistors for DC_BOOST pins must be between 22 kΩ to 47 kΩ in non I2C mode.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
3
TUSB212-Q1
SLLSF35 – SEPTEMBER 2017
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature and voltage range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
-0.3
3.8
V
Voltage Range
on I/O pins
DxP, DxM, RSTN, EQ, SCL, SDA, DC_BOOST, VREG
-0.3
3.8
V
Tstg
Storage temperature
-65
150
°C
Supply Voltage
Range
(1)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature and voltage range (unless otherwise noted)
VCC
Supply Voltage
TA
Ambient temperature
TUSB212Q1
TJ
Junction temperature
TUSB212Q1
MIN
NOM
MAX
3
3.3
3.6
UNIT
V
-40
105
°C
-40
125
°C
6.4 Thermal Information
THERMAL METRIC (1)
RWB (VQFN)
UNIT
12 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ΨJT
Junction-to-top characterization parameter
1.9
°C/W
ΨJB
Junction-to-board characterization parameter
67.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
137.4
°C/W
62
°C/W
67.2
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
TUSB212-Q1
www.ti.com
SLLSF35 – SEPTEMBER 2017
6.5 Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER
High-speed (HS) active curent
USB channel = HS mode; 480 Mbps
traffic; VCC = 3.3V; VCC supply stable;
DC Boost = 60 mV
22
30
mA
IIDLE_HS
High-speed idle current
USB channel = HS mode; no traffic; VCC
= 3.3V; VCC supply stable; DC Boost =
60 mV
14
22
mA
ISUSPEND
High-speed suspend current
USB channel = HS suspend mode; VCC
= 3.3V; VCC supply stable
0.55
1.5
mA
IFS_LS
Full/Low speed current
USB channel = FS mode or LS mode;
VCC = 3.3V
0.6
1.5
mA
IDISCONN
Disconnect current
Host side application; No device
attachment; VCC = 3.3V
0.7
1.5
mA
IRSTN
Disable current
RSTN driven low; VCC supply stable; VCC
= 3.3V
13
80
µA
ILKG_FS
Pin fail-safe leakage current for SDA,
SCL, DC_BOOST, DxP/N, RSTN
VCC = 0 V; Pin at 3.6 V
40
µA
VIH
High-level input voltage
VCC = 3.0V
2
3.6
V
VIL
Low-level input voltage
VCC = 3.6V
0
0.8
V
IIH
High-level input current
VIH = 3.6 V
-4
4
µA
IIL
Low-level input current
VIL = 0 V
-11
11
µA
IACTIVE_H
S
_HS
ECT
RSTN
EQ
AC Boost Level 0
REQ
External pull-down resistor on EQ pin.
160
Ω
AC Boost Level 1
1.4
2
kΩ
AC Boost Level 2
3.7
3.9
kΩ
AC Boost Level 3
6
kΩ
2.4
V
CD, ENA_HS
VOH
High-level output voltage
IO = -50µA
VOL
Low-level output voltage
IO = 50µA
0.4
V
4
150
pF
2
SCL, SDA
CI2CBUS
I2C Bus capacitance
VIH
SDA and SCL input high level voltage
VCC = 3.0V
3.6
V
VIL
SDA and SCL input low level voltage
VCC = 3.6V
0.8
V
VSDA_OL
SDA low level output voltage
4.7kΩ pullup to 3.6V; VCC = 3.0V
0.4
V
ISDA_OL
SDA low level output current
VCC = 3.6V
1.1
2.4
mA
DC_BOOST
VIH
High-level input voltage
VCC = 3.3V
VIM
Mid-level input voltage
VCC = 3.3V
VIL
Low-level input voltage
VCC = 3.3V
Capacitance to GND
Measured with LCR meter and device
powered down. 1 MHz sinusoid, 30
mVpp ripple
3.6
1.6
0
V
V
0.4
V
DxP, DxM
CIO_DXX
2.4
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
pF
5
TUSB212-Q1
SLLSF35 – SEPTEMBER 2017
www.ti.com
6.6 Switching Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
FBR_DXX
TEST CONDITIONS
MIN
USB channel = HS mode; 480 Mbps
traffic; VCC supply stable
DxP/M bit rate
TYP
MAX
UNIT
480.24
Mbps
tRISE_DXX DxP/M rise time
10% - 90%; VCC = 3.6V; Max AC Gain;
100
ps
tFALL_DXX DxP/M fall time
90% - 10%; VCC = 3.6V; Max AC Gain;
100
ps
20
µs
100
µs
tRSTN_PU
LSE_WIDT
H
Minimum width to detect a valid RSTN
signal assert when the pin is actively
driven
tSTABLE
VCC stable before RSTN de-assertion
tVCC_RAM
VCC ramp time
VCC = 3.0 V; Refer to Figure 1
Refer to Figure 1
0.2
100
ms
P
tRSTN_PULSE_WIDTH
RSTN
VIL(MAX)
tSTABLE
VCC(MIN)
VCC
Figure 1. Power On and Reset Timing
6
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
TUSB212-Q1
www.ti.com
SLLSF35 – SEPTEMBER 2017
6.7 Typical Characteristics
Figure 2. USB2.0 HS Eye Diagram, Host far-end with 2m
cable post-channel loss without TUSB212-Q1
Figure 3. USB 2.0 HS Eye Diagram, Host far-end with 2m
cable post-channel loss with TUSB212-Q1
Figure 4. USB2.0 HS Eye Diagram, Host far-end with 5m
cable pre-channel loss without TUSB212-Q1
Figure 5. USB2.0 HS Eye Diagram, Host far-end with 5m
cable pre-channel loss with TUSB212-Q1
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
7
TUSB212-Q1
SLLSF35 – SEPTEMBER 2017
www.ti.com
7 Detailed Description
7.1 Overview
The TUSB212-Q1 is a USB High-Speed (HS) signal conditioner, designed to compensate for ISI signal loss in a
transmission channel. TUSB212-Q1 has a patent-pending design which is agnostic to USB Low Speed (LS) and
Full Speed (FS) signals and does not alter their signal characteristics, while HS signals are compensated. In
addition, the design is compatible with USB On-The-Go (OTG) and Battery Charging (BC) specifications.
Programmable signal gain through an external resistor permits fine tuning device performance to optimize signals
helping to pass USB HS electrical compliance tests at the connector. Additional DC boost configurable by three
level input DC_BOOST helps overcoming the cable losses.
The footprint of TUSB212-Q1 allows a board layout using this device such that it does not break the continuity of
the DP/DM signal traces. This permits risk free system design of a complete USB channel with flexible use of
one or multiple TUSB212-Q1 devices as needed for optimal signal integrity. This allows system designers to plan
for this device and use it only if signal integrity analysis and/or lab measurements sow a need. If such a need is
not warranted, the device can be left unpopulated without any board rework.
7.2 Functional Block Diagram
Low and Full
Speed Bypass
USB
TRANSCEIVER
OPTIONAL
PLD
D1P
D2P
High Speed
Compensation
D1M
ESD
PROTECTION
D2M
USB
CONNECTOR
CD
Status Flags
ENA_HS
7.3 Feature Description
7.3.1 EQ
The EQ pin of the TUSB212-Q1 is used to configure the AC boost of the device. The four levels are set through
different values of an external pulldown resistor at this pin.
7.3.2 DC BOOST
The DC_BOOST pin of the TUSB212-Q1 is a tri-level pin, used to set the DC gain of the device according to
Table 1.
Table 1. DC Boost Settings
DC BOOST SETTING VIA PIN STRAP
8
DC_BOOST
DC Boost Setting (mV)
VIL
40
VIM
60
VIH
80
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
TUSB212-Q1
www.ti.com
SLLSF35 – SEPTEMBER 2017
7.4 Device Functional Modes
7.4.1 Low Speed (LS) Mode
TUSB212-Q1 automatically detects a LS connection and does not enable signal compensation. CD pin is
asserted high.
7.4.2 Full Speed (FS) Mode
TUSB212-Q1 automatically detects a FS connection and does not enable signal compensation. CD pin is
asserted high.
7.4.3 High Speed (HS) Mode
TUSB212-Q1 automatically detects a HS connection and will enable signal compensation as determined by the
configuration of the DC_BOOST pin and the external pulldown resistance on its EQ pin. CD pin is asserted high.
7.4.4 Shutdown Mode
TUSB212-Q1 is disabled when its RSTN pin is asserted low. In shutdown mode the USB channel is still fully
operational, but there is neither signal compensation nor any indication from the CD pin as to the status of the
channel.
7.4.5 I2C Mode
TUSB212-Q1 supports 100 kHz I2C for device configuration, status readback and test purposes. This controller is
enabled after SCL and SDA pins are sampled high shortly after de-assertion of RSTN. In this mode, the register
as described in Table 2 can be accessed by I2C read/write transaction to 7-bit slave address 0x2C. It is
necessary to set CFG_ACTIVE bit and reset it to zero after making changes to the EQ and DC Boost level
registers to restart the state machine.
NOTE
All registers or fields in Table 2 which are not specifically mentioned are considered
reserved. The default value of these reserved registers or fields must not be changed. It is
suggested to perform a read-modify-write operation to maintain the default value of the
reserved fields.
Table 2. Register definition
Offset
Bit(s)
Name
Type
Default
Description
Sets the level of AC Boost
0x01
6:4
ACB_LVL
RW
XXX (Sampled from EQ
pin at reset)
000 : Level 0 AC Boost programmed [MIN]
001 : Level 1 AC Boost programmed
011 : Level 2 AC Boost programmed
111 : Level 3 AC Boost programmed [MAX]
Configuration mode
0 : Normal mode. State machine enabled.
0x03
0
CFG_ACTIVE
RW
1b
RW
XXX (Sampled from
DC_BOOST pin at reset)
1 : Configuration mode: State machine disabled.
After reset, if I2C mode is true (SCL and SDA are
both pulled high) it is maintained until it is cleared
by an I2C write, but, if I2C mode is not true, it is
cleared automatically.
Sets the level of DC Boost
0x0E
2:0
DCB_LVL
011 : 40mV (DC_Boost = L)
101 : 60mV (DC_Boost = M, default)
111 : 80mV (DC_Boost = H)
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
9
TUSB212-Q1
SLLSF35 – SEPTEMBER 2017
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The primary purpose of the TUSB212-Q1 is to re-store the signal integrity of a USB High Speed channel up to
the USB receptacle. The loss in signal quality stems from reduced channel bandwidth due to high loss PCB trace
and other components that contribute a capacitive load. This can cause the channel to fail the USB near end eye
mask. Proper use of the TUSB212-Q1 can help to pass this eye mask.
A secondary purpose is to use the CD pin of the TUSB212-Q1 to control other blocks on the customer platform if
so desired.
8.2 Typical Application
USB
Host or Hub
D1M
D2M
D1P
D2P
USB Receptacle
A typical application is shown in Figure 6. In this setup, D2P and D2M face the USB connector while D1P and
D1M face the USB host. If desired, the orientation may be reversed [that is, D2 faces transceiver and D1 faces
connector].
Copyright © 2017, Texas Instruments Incorporated
Figure 6. Typical Application
8.2.1 Design Requirements
For this design example, use parameters shown in the table below.
Table 3. Design Parameters
PARAMETER
VALUE
VCC (3.0V to 3.6V)
3.3 V
2
I C support required in system (Yes/No)
AC Boost
10
No
REQ
Level
0Ω
0
1.69 k ±1%
1
3.83 k ±1%
2
DNI
3
Submit Documentation Feedback
AC Boost Level 2:
REQ = 3.83 K
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
TUSB212-Q1
www.ti.com
SLLSF35 – SEPTEMBER 2017
Typical Application (continued)
Table 3. Design Parameters (continued)
PARAMETER
DC Boost
VALUE
RDC1
RDC2
Level
22 kΩ - 47 kΩ
Do Not Install (DNI)
40 mV Low DC Boost
DNI
DNI
60 mV Mid DC Boost
DNI
22 kΩ - 47 kΩ
80 mV High DC Boost
Mid DC Level:
RDC1 = DNI
RDC2 = DNI
8.2.2 Detailed Design Procedure
TUSB212-Q1 requires a valid reset signal as described in the power supply recommendations section. The
capacitor at RSTN pin is not required if a microcontroller drives the RSTN pin according to recommendations.
VREG pin is the internal LDO output that requires a 0.1-μF external capacitor to GND to stabilize the core.
The ideal AC/DC Boost setting is dependent upon the signal chain loss characteristics of the target platform. The
general recommendation is to start with AC Boost level 0, and then increment to AC Boost level 1, etc. when
needed. Same applies to the DC boost setting where it is recommended to plan for the required pad to change
boost settings.
In order for the TUSB212-Q1 to recognize any change to the AC or DC boost settings, the RSTN pin must be
toggled. This is because the EQ and DC_BOOST pins are latched on power up and the pins are ignored
thereafter.
Further D1P has to be shorted to D2P and D1M shorted to D2M on the board for correct functionality of the
device.
Placement of the device is also dependent on the application goal. Table 4 summarizes our recommendations.
Table 4. Platform Placement Guideline
PLATFORM GOAL
SUGGESTED TUSB212-Q1 PLACEMENT
Pass USB Near End Mask
Close to measurement point
Pass USB Far End Eye Mask
Close to USB PHY
Cascade multiple TUSB212-Q1 to improve device enumeration
Midway between each USB interconnect
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
11
TUSB212-Q1
SLLSF35 – SEPTEMBER 2017
www.ti.com
+3.3 V
1 PF
REQ
EQ
RDC2
100 nF
100 nF
RSTN
+3.3 V
RDC1
SCL/CD
USB_DN
SDA
D2P
D1P
D2M
VREG
USB_DP
DCBOOST/ENA_HS
GND
USB Receptacle
VCC
D1N
USB_DP
USB_DN
USB
Host or Hub
100 nF
Copyright © 2017, Texas Instruments Incorporated
D2P must be shorted to D1P on PCB.
D2N must be shorted to D1N on PCB.
Figure 7. Reference Schematic
8.2.2.1 Test Procedure to Construct USB High Speed Eye Diagram
NOTE
USB-IF certification tests for High Speed eye masks require the mandated use of the
USB-IF developed test fixtures. These test fixtures do not require the use of oscilloscope
probes. Instead they use SMA cables. More information can be found at the USB-IF
Compliance Updates Page. It is located under the ‘Electricals’ section, ID 86 dated March
2013.
The following procedure must be followed before using any oscilloscope compliance software to construct a USB
High Speed Eye Mask:
8.2.2.1.1 For a Host Side Application
1.
2.
3.
4.
5.
6.
12
Configure the TUSB212-Q1 to the desired AC and DC boost settings.
Power on (or toggle the RSTN pin if already powered on) the TUSB212-Q1
Using SMA cables, connect the oscilloscope and the USB-IF host-side test fixture to the TUSB212-Q1
Enable the host to transmit USB TEST_PACKET
Execute the oscilloscope USB compliance software.
Repeat the above steps in order to re-test TUSB212-Q1 with different AC and DC boost settings.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
TUSB212-Q1
www.ti.com
SLLSF35 – SEPTEMBER 2017
8.2.2.1.2 For a Device Side Application
1. Configure the TUSB212-Q1 to the desired AC and DC boost settings.
2. Power on (or toggle the RSTN pin if already powered on) the TUSB212-Q1
3. Connect a USB host, the USB-IF device-side test fixture, and USB device to the TUSB212-Q1. Ensure that
the USB-IF device test fixture is configured to the ‘INIT’ position
4. Allow the host to enumerate the device
5. Enable the device to transmit USB TEST_PACKET
6. Using SMA cables, connect the oscilloscope to the USB-IF device-side test fixture and ensure that the
device-side test fixture is configured to the ‘TEST’ position.
7. Execute the oscilloscope USB compliance software.
8. Repeat the above steps in order to re-test TUSB212-Q1 with different AC and DC boost settings.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
13
TUSB212-Q1
SLLSF35 – SEPTEMBER 2017
www.ti.com
8.2.3 Application Curves
TUSB21xEVM
DP
2m USB A-B Cable
Lecroy 25 GHz Scope
1m SMA to SMA cables
USB Host
USBIF Compliance
Test Fixture
DM
Figure 8. Eye Diagram Bench Setup
Figure 9. No TUSB212-Q1
14
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
TUSB212-Q1
www.ti.com
SLLSF35 – SEPTEMBER 2017
Figure 10. Low DC Boost, AC Boost Level 0
Figure 11. Mid DC Boost, AC Boost Level 0
Figure 12. High DC Boost, AC Boost Level 0
Figure 13. Low DC Boost, AC Boost Level 1
Figure 14. Mid DC Boost, AC Boost Level 1
Figure 15. High DC Boost, AC Boost Level 1
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
15
TUSB212-Q1
SLLSF35 – SEPTEMBER 2017
16
www.ti.com
Figure 16. Low DC Boost, AC Boost Level 2
Figure 17. Mid DC Boost, AC Boost Level 2
Figure 18. High DC Boost, AC Boost Level 2
Figure 19. Low DC Boost, AC Boost Level 3
Figure 20. Mid DC Boost, AC Boost Level 3
Figure 21. High DC Boost, AC Boost Level 3
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
TUSB212-Q1
www.ti.com
SLLSF35 – SEPTEMBER 2017
9 Power Supply Recommendations
On power up, the interaction of the RSTN pin and power on ramp could result in digital circuits not being set
correctly. The device should not be enabled until the power on ramp has settled to 3 V or higher to ensure a
correct power on reset of the digital circuitry. If RSTN cannot be held low by microcontroller or other circuitry until
the power on ramp has settled, then an external capacitor from the RSTN pin to GND is required to hold the
device in the low power reset state.
The RC time constant should be larger than five times of the power on ramp time (0 to VCC). With a typical
internal pullup resistance of 500 kΩ, the recommended minimum external capacitance is calculated as:
[Ramp Time x 5] ÷ [500 kΩ]
(1)
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
17
TUSB212-Q1
SLLSF35 – SEPTEMBER 2017
www.ti.com
10 Layout
10.1 Layout Guidelines
The USB signal trace must not be broken when placing TUSB212-Q1. Thus, even with the TUSB212-Q1
powered down, or not populated, the USB link is still fully operational. To avoid the need for signal vias, it is
highly recommend to route the High Speed traces directly underneath the TUSB212-Q1 package, as illustrated in
the PCB land pattern shown in Figure 22.
Although the land pattern shown below has matched trace width to pad width, optimal impedance control is
based on the user's own PCB stack-up. It is recommended to maintain 90 Ω differential routing underneath the
device.
All dimensions are in millimetres (mm).
10.2 Layout Example
Figure 22. DP and DM Routing Underneath Device Package
18
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
TUSB212-Q1
www.ti.com
SLLSF35 – SEPTEMBER 2017
11 Device and Documentation Support
11.1 Documentation Support
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TUSB212-Q1
19
PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TUSB212QRWBRQ1
ACTIVE
X2QFN
RWB
12
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
22
TUSB212QRWBTQ1
ACTIVE
X2QFN
RWB
12
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
22
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2017
OTHER QUALIFIED VERSIONS OF TUSB212-Q1 :
• Catalog: TUSB212
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Sep-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TUSB212QRWBRQ1
X2QFN
RWB
12
3000
180.0
9.5
1.8
1.8
0.45
4.0
8.0
Q1
TUSB212QRWBTQ1
X2QFN
RWB
12
250
180.0
9.5
1.8
1.8
0.45
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Sep-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TUSB212QRWBRQ1
X2QFN
RWB
12
3000
189.0
185.0
36.0
TUSB212QRWBTQ1
X2QFN
RWB
12
250
189.0
185.0
36.0
Pack Materials-Page 2
PACKAGE OUTLINE
RWB0012A
X2QFN - 0.4 mm max height
SCALE 6.500
PLASTIC QUAD FLATPACK - NO LEAD
1.65
1.55
B
A
PIN 1 INDEX AREA
1.65
1.55
C
0.4 MAX
SEATING PLANE
0.05 C
2X 1.2
SYMM
3
6
2
7
SYMM
2X
0.4
1
0.6
0.4
8X
8
12
4X
0.05
0.00
6X 0.4
(0.13)
TYP
0.4
0.2
9
12X
0.25
0.15
0.07
0.05
C B A
C
4221631/B 07/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RWB0012A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.3)
6X (0.4)
9
12
4X (0.7)
1
8
SYMM
2X (0.4)
(1.5)
7
2
8X (0.5)
3
6
SYMM
12X (0.2)
(R0.05) TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221631/B 07/2017
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RWB0012A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.3)
6X (0.4)
9
12
4X (0.67)
1
8
SYMM
2X (0.4)
(1.5)
2
7
8X
METAL
8X (0.5)
6
3
12X (0.2)
SYMM
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PADS 1,2,7 & 8
96% PRINTED SOLDER COVERAGE BY AREA
SCALE:50X
4221631/B 07/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising