Texas Instruments | TCA6416A Low-Voltage 16-Bit I2C and SMBus I/O Expander With Voltage Translation, Interrupt Output, Reset Input, and Configuration Registers (Rev. D) | Datasheet | Texas Instruments TCA6416A Low-Voltage 16-Bit I2C and SMBus I/O Expander With Voltage Translation, Interrupt Output, Reset Input, and Configuration Registers (Rev. D) Datasheet

Texas Instruments TCA6416A Low-Voltage 16-Bit I2C and SMBus I/O Expander With Voltage Translation, Interrupt Output, Reset Input, and Configuration Registers (Rev. D) Datasheet
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TCA6416A
SCPS194D – MAY 2009 – REVISED AUGUST 2017
TCA6416A Low-Voltage 16-Bit I2C and SMBus I/O Expander With Voltage Translation,
Interrupt Output, Reset Input, and Configuration Registers
1 Features
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1
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2 Applications
2
I C to Parallel Port Expander
Operating Power-Supply Voltage Range of 1.65 V
to 5.5 V
Allows Bidirectional Voltage-Level Translation and
GPIO Expansion Between 1.8-V, 2.5-V, 3.3-V,
and 5-V I2C Bus and P-Ports
Low Standby Current Consumption of 3 μA
5-V Tolerant I/O Ports
400-kHz Fast I2C Bus
Hardware Address Pin Allows Two TCA6416A
Devices on the Same I2C/SMBus Bus
Active-Low Reset Input (RESET)
Open-Drain Active-Low Interrupt Output (INT)
Input/Output Configuration Register
Polarity Inversion Register
Internal Power-On Reset
Power-Up With All Channels Configured as Inputs
No Glitch On Power Up
Noise Filter on SCL/SDA Inputs
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
•
•
•
•
Servers
Routers (Telecom Switching Equipment)
Personal Computers
Personal Electronics (For Example, Gaming
Consoles)
Industrial Automation
Products With GPIO-Limited Processors
•
•
3 Description
The TCA6416A is a 24-pin device that provides 16bits of general purpose parallel input/output (I/O)
expansion for the two-line bidirectional I2C bus (or
SMBus) protocol. The device can operate with a
power supply voltage ranging from 1.65 V to 5.5 V on
the I2C bus side (VCCI) and a power supply voltage
ranging from 1.65 V to 5.5 V on the P-port side
(VCCP).
The device supports both 100-kHz (Standard-mode)
and 400-kHz (Fast-mode) clock frequencies. I/O
expanders such as the TCA6416A provide a simple
solution when additional I/Os are needed for
switches, sensors, push-buttons, LEDs, fans, etc.
Device Information(1)
PART NUMBER
TCA6416A
PACKAGE
BODY SIZE (NOM)
TSSOP (24)
7.80 mm × 4.40 mm
WQFN (24)
4.00 mm × 4.00 mm
BGA Microstar
Junior (24)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VCCI
I2C or SMBus
Master
VCCP
P00
P01
P02
P03
P04
P05
P06
P07
SDA
SCL
INT
RESET
(processor)
TCA6416A
ADDR
GND
P10
P11
P12
P13
P14
P15
P16
P17
Peripheral
Devices
B
B
B
B
RESET,
ENABLE,
or control
inputs
INT or
status
outputs
LEDs
Keypad
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA6416A
SCPS194D – MAY 2009 – REVISED AUGUST 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
5
5
5
6
7
8
8
8
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Interface Timing Requirements...........................
Reset Timing Requirements .....................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 12
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2
8.3
8.4
8.5
8.6
9
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Maps .........................................................
17
18
19
19
20
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application ................................................. 26
10 Power Supply Recommendations ..................... 29
10.1 Power-On Reset Requirements ........................... 29
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 32
12 Device and Documentation Support ................. 33
12.1 Trademarks ........................................................... 33
12.2 Electrostatic Discharge Caution ............................ 33
12.3 Glossary ................................................................ 33
13 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2015) to Revision D
Page
•
Changed the tvd(data) MAX value From: 1 µs To: 0.9 µs in the I2C Interface Timing Requirements table............................... 8
•
Changed the tvd(ack) MAX value From: 1 µs To: 0.9 µs in the I2C Interface Timing Requirements table................................ 8
Changes from Revision B (January 2015) to Revision C
•
Changed units for tIV and tIR parameters from ns to µs .......................................................................................................... 8
Changes from Revision A (November 2009) to Revision B
•
2
Page
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
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SCPS194D – MAY 2009 – REVISED AUGUST 2017
5 Pin Configuration and Functions
PW Package
24-Pin TSSOP
Top View
2
23
3
22
4
21
5
20
6
19
SDA
SCL
ADDR
P17
P16
P15
P14
P13
P12
P11
P10
7
18
8
17
9
16
10
15
11
14
12
13
ZQS Package
24-Pin BGA Microstar Junior
Top View
SDA
SCL
VCCP
INT
VCCP
24
RESET
VCCI
1
24 23 22 21 20 19
P00
P01
P02
P03
P04
P05
18
1
2
17
Exposed
Center
Pad
3
4
16
15
5
14
6
13
7
8
ADDR
P17
P16
P15
P14
P13
E
D
C
B
A
9 10 11 12
5 4 3 2 1
P06
P07
GND
P10
P11
P12
INT
VCCI
RESET
P00
P01
P02
P03
P04
P05
P06
P07
GND
RTW Package
24-Pin WQFN
Top View
The exposed center pad, if used, must be connected
only as a secondary GND or must be left electrically open.
Table 1. ZQS Package Pin Assignments
(1)
E
P13
P11
P10
GND
P06
D
P15
P14
P12
P07
P05
C
P16
P17
P01
P04
P03
B
ADDR
VCCP
VCCI
NB (1)
P02
A
SCL
SDA
INT
RESET
P00
5
4
3
2
1
NB — No ball at this position
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Pin Functions
PIN
DESCRIPTION
TSSOP
(PW)
QFN
(RTW)
BGA
(ZQS)
INT
1
22
A3
Interrupt output. Connect to VCCI or VCCP through a pull-up resistor.
VCCI
2
23
B3
Supply voltage of I2C bus. Connect directly to the supply voltage of the external I2C master.
RESET
3
24
A2
Active-low reset input. Connect to VCCI or VCCP through a pull-up resistor, if no active connection
is used.
P00
4
1
A1
P-port input/output (push-pull design structure). At power on, P00 is configured as an input.
P01
5
2
C3
P-port input/output (push-pull design structure). At power on, P01 is configured as an input.
P02
6
3
B1
P-port input/output (push-pull design structure). At power on, P02 is configured as an input.
P03
7
4
C1
P-port input/output (push-pull design structure). At power on, P03 is configured as an input.
P04
8
5
C2
P-port input/output (push-pull design structure). At power on, P04 is configured as an input.
P05
9
6
D1
P-port input/output (push-pull design structure). At power on, P05 is configured as an input.
P06
10
7
E1
P-port input/output (push-pull design structure). At power on, P06 is configured as an input.
P07
11
8
D2
P-port input/output (push-pull design structure). At power on, P07 is configured as an input.
GND
12
9
E2
Ground
P10
13
10
E3
P-port input/output (push-pull design structure). At power on, P10 is configured as an input.
P11
14
11
E4
P-port input/output (push-pull design structure). At power on, P11 is configured as an input.
P12
15
12
D3
P-port input/output (push-pull design structure). At power on, P12 is configured as an input.
P13
16
13
E5
P-port input/output (push-pull design structure). At power on, P13 is configured as an input.
P14
17
14
D4
P-port input/output (push-pull design structure). At power on, P14 is configured as an input.
P15
18
15
D5
P-port input/output (push-pull design structure). At power on, P15 is configured as an input.
P16
19
16
C5
P-port input/output (push-pull design structure). At power on, P16 is configured as an input.
P17
20
17
C4
P-port input/output (push-pull design structure). At power on, P17 is configured as an input.
ADDR
21
18
B5
Address input. Connect directly to VCCP or ground.
SCL
22
19
A5
Serial clock bus. Connect to VCCI through a pull-up resistor.
SDA
23
20
A4
Serial data bus. Connect to VCCI through a pull-up resistor.
VCCP
24
21
B4
Supply voltage of TCA6416A for P-ports
NAME
4
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SCPS194D – MAY 2009 – REVISED AUGUST 2017
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCCI
Supply voltage
–0.5
6.5
V
VCCP
Supply voltage
–0.5
6.5
V
VI
Input voltage
–0.5
6.5
V
VO
Output voltage
–0.5
6.5
V
IIK
Input clamp current
ADDR, RESET, SCL
VI < 0
±20
mA
IOK
Output clamp current
INT
VO < 0
±20
mA
P port
VO < 0 or VO > VCCP
±20
SDA
VO < 0 or VO > VCCI
±20
P port
VO = 0 to VCCP
50
SDA, INT
VO = 0 to VCCI
25
P port
VO = 0 to VCCP
50
(2)
(2)
IIOK
Input/output clamp current
IOL
Continuous output low current
IOH
Continuous output high current
ICC
Tstg
(1)
(2)
Continuous current through GND
200
Continuous current through VCCP
160
Continuous current through VCCI
10
Storage temperature
–65
mA
mA
mA
mA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
VCCI
Supply voltage
1.65
5.5
VCCP
Supply voltage
1.65
5.5
SCL, SDA
VIH
High-level input voltage
VCCI
0.7 × VCCI
5.5
ADDR, P17–P00
0.7 × VCCP
5.5
SCL, SDA, RESET
–0.5
0.3 × VCCI
ADDR, P17–P00
–0.5
0.3 × VCCP
Low-level input voltage
IOH
High-level output current
P17–P00
IOL
Low-level output current
P17–P00
TA
Operating free-air temperature
–40
V
(1)
RESET
VIL
(1)
0.7 × VCCI
UNIT
V
V
10
mA
25
mA
85
°C
The SCL and SDA pins shall not be at a higher potential than the supply voltage VCCI in the application, or an increase in current
consumption will result.
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6.4 Thermal Information
TCA6416A
THERMAL METRIC
(1)
PW (TSSOP)
RTW (WQFN)
ZQS
(BGA MICROSTAR JUNIOR)
24 PINS
24 PINS
24 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
108.8
43.6
159.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
54.0
46.2
138.2
°C/W
RθJB
Junction-to-board thermal resistance
62.8
22.1
93.6
°C/W
ψJT
Junction-to-top characterization parameter
11.1
1.5
10.7
°C/W
ψJB
Junction-to-board characterization parameter
62.3
22.2
95.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
10.7
N/A
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SCPS194D – MAY 2009 – REVISED AUGUST 2017
6.5 Electrical Characteristics
over recommended operating free-air temperature range, VCCI = 1.65 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCP
MIN
–1.2
VIK
Input diode clamp
II = –18 mA
voltage
1.65 V to 5.5 V
VPOR
Power-on reset
voltage
1.65 V to 5.5 V
VI = VCCP or GND, IO = 0
IOH = –8 mA
P-port high-level
output voltage
VOH
IOH = –10 mA
IOL = 8 mA
P-port low-level
output voltage
VOL
IOL = 10 mA
TYP (1)
1.2
2.3 V
1.8
3V
2.6
4.5 V
4.1
1.65 V
1.1
2.3 V
1.7
3V
2.5
4.5 V
4.0
0.45
0.25
3V
0.25
4.5 V
0.2
1.65 V
0.6
2.3 V
0.3
3V
0.25
4.5 V
3
INT
VOL = 0.4 V
1.65 V to 5.5 V
3
SCL, SDA,
RESET
VI = VCCI or GND
ADDR
VI = VCCP or GND
IIH
P port
VI = VCCP
IIL
P port
VI = GND
ICC
(ICCI + ICCP)
ΔICCI
ΔICCP
Ci
Cio
(1)
V on SCL, SDA and RESET= VCCI or GND,
SCL, SDA, P port, I
VI on P port and ADDR = VCCP,
ADDR, RESET
IO = 0, I/O = inputs, fSCL = 0
SCL,SDA,
RESET
One input at VCCI – 0.6 V,
Other inputs at VCCI or GND
P port, ADDR
One input at VCCP – 0.6 V,
Other inputs at VCCP or GND
SCL
VI = VCCI or GND
SDA
VIO = VCCI or GND
P port
VIO = VCCP or GND
mA
15
±0.1
1.65 V to 5.5 V
μA
±0.1
1.65 V to 5.5 V
VI on SDA and RESET = VCCI or GND,
VI on P port and ADDR = VCCP,
IO = 0, I/O = inputs, fSCL = 400 kHz
V
0.2
1.65 V to 5.5 V
SDA, P port,
ADDR, RESET
V
V
2.3 V
VOL = 0.4 V
II
1.4
1.65 V
SDA
IOL
UNIT
V
1
1.65 V
MAX
1
μA
1
μA
3.6 V to 5.5 V
10
20
2.3 V to 3.6 V
6.5
15
1.65 V to 2.3 V
4
9
3.6 V to 5.5 V
1.5
7
2.3 V to 3.6 V
1
3.2
1.65 V to 2.3 V
0.5
1.7
μA
25
1.65 V to 5.5 V
μA
80
1.65 V to 5.5 V
1.65 V to 5.5 V
6
7
7
8
7.5
8.5
pF
pF
Except for ICC, all typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C. For ICC, the typical
values are at VCCP = VCCI = 3.3 V and TA = 25°C.
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6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 18)
STANDARD MODE
I2C BUS
MIN
MAX
100
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
2
tscl
I C clock low time
tsp
I2C spike time
tsds
I2C serial data setup time
FAST MODE
I2C BUS
MAX
0
400
0.6
4.7
50
μs
0
250
50
100
0
kHz
μs
1.3
0
2
UNIT
MIN
ns
ns
tsdh
I C serial data hold time
ticr
I2C input rise time
1000
20 + 0.1Cb (1)
300
ns
ticf
I2C input fall time
300
20 + 0.1Cb (1)
300
ns
tocf
I2C output fall time; 10 pF to 400 pF bus
300
20 + 0.1Cb (1)
300
μs
2
0
ns
tbuf
I C bus free time between Stop and Start
4.7
1.3
μs
tsts
I2C Start or repeater Start condition setup time
4.7
0.6
μs
tsth
I2C Start or repeater Start condition hold time
4
0.6
μs
2
tsps
I C Stop condition setup time
tvd(data)
Valid data time; SCL low to SDA output valid
1
0.9
μs
tvd(ack)
Valid data time of ACK condition; ACK signal from SCL low to SDA
(out) low
1
0.9
μs
(1)
4
0.6
μs
Cb = total capacitance of one bus line in pF
6.7 Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 21)
STANDARD MODE
I2C BUS
MIN
FAST MODE
I2C BUS
MAX
MIN
UNIT
MAX
tW
Reset pulse duration
4
4
ns
tREC
Reset recovery time
0
0
ns
600
600
ns
tRESET
(1)
Time to reset
(1)
Minimum time for SDA to become high or minimum time to wait before doing a START
6.8 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 18)
PARAMETER
FROM
TO
STANDARD
MODE
I2C BUS
MIN
FAST MODE
I2C BUS
MAX
MIN
UNIT
MAX
tIV
Interrupt valid time
P port
INT
4
4
µs
tIR
Interrupt reset delay time
SCL
INT
4
4
µs
tPV
Output data valid
SCL
P7–P0
400
400
ns
tPS
Input data setup time
P port
SCL
0
0
ns
tPH
Input data hold time
P port
SCL
300
300
ns
8
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6.9 Typical Characteristics
TA = 25°C (unless otherwise noted)
22
2000
Supply Current, ICC (µA)
18
Supply Current, ICC (nA)
VCC = 5.5 V
20
VCC = 5 V
16
14
12
10
VCC = 3.3 V
8
VCC = 2.5 V
6
4
VCC = 1.8 V
2
VCC = 1.65 V
0
-40
-15
10
35
1800
VCC = 5.5 V
1600
VCC = 5 V
1400
1200
VCC = 3.3 V
1000
VCC = 2.5 V
800
600
VCC = 1.8 V
400
VCC = 1.65 V
200
60
0
–40
85
–15
10
35
60
85
Temperature, TA (°C)
Temperature, TA (°C)
Figure 1. Supply Current vs Temperature
Figure 2. Standby Supply Current vs Temperature
22
30
VCC = 1.65 V
Sink Current, ISINK (mA)
Supply Current, ICC (µA)
20
18
16
14
12
10
8
6
4
25
TA = –40°C
20
TA = 25°C
15
10
TA = 85°C
5
2
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0
0.0
0.1
0.2
0.3
0.5
0.4
0.6
Supply Voltage, VCC (V)
Output Low Voltage, VOL (V)
Figure 3. Supply Current vs Supply Voltage
Figure 4. I/O Sink Current vs Output Low Voltage
50
VCC = 1.8 V
VCC = 2.5 V
TA = –40°C
30
Sink Current, ISINK (mA)
Sink Current, ISINK (mA)
35
25
20
TA = 25°C
15
10
TA = 85°C
5
0
0.0
0.1
0.2
0.3
0.4
0.5
40
30
TA = 25°C
20
TA = 85°C
10
0
0.0
0.6
TA = –40°C
0.1
0.2
0.3
0.4
0.5
0.6
Output Low Voltage, VOL (V)
Output Low Voltage, VOL (V)
Figure 5. I/O Sink Current vs Output Low Voltage
Figure 6. I/O Sink Current vs Output Low Voltage
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
60
70
VCC = 5.0 V
Sink Current, ISINK (mA)
Sink Current, ISINK (mA)
VCC = 3.3 V
TA = –40°C
50
40
TA = 25°C
30
20
TA = 85°C
10
0
0.0
0.1
0.2
0.3
0.5
0.4
TA = –40°C
50
40
TA = 25°C
30
20
TA = 85°C
10
0
0.0
0.6
0.1
0.2
0.3
0.4
0.5
0.6
Output Low Voltage, VOL (V)
Output Low Voltage, VOL (V)
Figure 7. I/O Sink Current vs Output Low Voltage
Figure 8. I/O Sink Current vs Output Low Voltage
250
Sink Current, ISINK (mA)
VCC = 5.5 V
60
Output Low Voltage, VOL (mV)
70
TA = –40°C
50
40
TA = 25°C
30
20
TA = 85°C
10
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
VCC = 1.8 V, ISINK = 10 mA
200
150
VCC = 5 V, ISINK = 10 mA
100
VCC = 1.8 V, ISINK = 1 mA
50
VCC = 5 V, ISINK = 1 mA
0
-40
-15
10
35
60
85
Output Low Voltage, VOL (V)
Temperature, TA (°C)
Figure 9. I/O Sink Current vs Output Low Voltage
Figure 10. I/O Low Voltage vs Temperature
25
VCC = 1.65 V
Source Current, ISOURCE (mA)
Source Current, ISOURCE (mA)
20
TA = –40°C
15
TA = 25°C
10
TA = 85°C
5
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
VCC = 1.8 V
TA = –40°C
20
15
TA = 25°C
10
TA = 85°C
5
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
VCCP – VOH (V)
VCCP – VOH (V)
Figure 11. I/O Source Current vs Output High Voltage
10
60
Figure 12. I/O Source Current vs Output High Voltage
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
50
VCC = 2.5 V
TA = –40°C
30
Source Current, ISOURCE (mA)
Source Current, ISOURCE (mA)
35
25
20
TA = 25°C
15
TA = 85°C
10
5
0
0.0
0.1
0.2
0.3
0.4
0.5
VCC = 3.3 V
30
TA = 25°C
20
TA = 85°C
10
0
0.6
0.0
0.1
VCCP – VOH (V)
Source Current, ISOURCE (mA)
Source Current, ISOURCE (mA)
40
TA = 25°C
30
TA = 85°C
10
0
0.0
0.1
0.2
0.3
0.4
0.4
0.5
0.6
70
50
20
0.3
Figure 14. I/O Source Current vs Output High Voltage
TA = –40°C
VCC = 5.0 V
0.2
VCCP – VOH (V)
Figure 13. I/O Source Current vs Output High Voltage
60
TA = –40°C
40
0.5
0.6
VCC = 5.5 V
TA = –40°C
60
50
40
TA = 25°C
30
20
TA = 85°C
10
0
0.0
0.1
VCCP – VOH (V)
0.2
0.3
0.4
0.5
0.6
VCCP – VOH (V)
Figure 15. I/O Source Current vs Output High Voltage
Figure 16. I/O Source Current vs Output High Voltage
350
ISOURCE = –10 mA
VCC – VOH (mV)
300
250
VCC = 1.8 V
200
VCC = 5 V
150
100
50
0
-40
-15
10
35
60
85
Temperature, TA (°C)
Figure 17. I/O High Voltage vs Temperature
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7 Parameter Measurement Information
VCCI
RL = 1 kW
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Two Bytes for READ Input Port Register
(see Figure 9)
Address
Bit 7
(MSB)
Stop
Start
Condition Condition
(P)
(S)
tscl
Address
Bit 1
R/W
Bit 0
(LSB)
Data
Bit 7
(MSB)
ACK
(A)
Data
Bit 0
(LSB)
Stop
Condition
(P)
tsch
0.7 ´ VCCI
SCL
0.3 ´ VCCI
ticr
tsp
ticf
tbuf
tvd
tvd
tocf
tsts
tsps
SDA
0.7 ´ VCCI
0.3 ´ VCCI
ticr
ticf
tsth
tsdh
tsds
tvd(ack)
Repeat Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
2
1
I C address
2
Input register port data
A.
CL includes probe and jig capacitance. tocf is measured with CL of 10 pF or 400 pF.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 18. I2C Interface Load Circuit And Voltage Waveforms
12
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Parameter Measurement Information (continued)
VCCI
RL = 4.7 kW
INT
DUT
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
Start
Condition
8 Bits
(One Data Byte)
From Port
R/W
Slave Address
S
0
1
0
0
0
0
AD
DR
1
A
1
2
3
4
5
6
7
8
A
Data 1
ACK
From Slave
Data From Port
A
Data 2
1
P
A
tir
tir
B
B
INT
tiv
A
tsps
A
Data
Into
Port
Address
Data 1
0.5 ´ VCCI
INT
SCL
Data 2
0.7 ´ VCCI
R/W
tiv
A
0.3 ´ VCCI
tir
0.5 ´ VCCP
Pn
0.5 ´ VCCI
INT
View A−A
View B−B
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 19. Interrupt Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
500 W
Pn
DUT
2 ´ VCCP
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
SCL
P0
A
0.7 ´ VCCP
P3
0.3 ´ VCCI
Slave
ACK
SDA
tpv
(see Note B)
Pn
Unstable
Data
Last Stable Bit
WRITE MODE (R/W = 0)
0.7 ´ VCCI
SCL
P0
A
tps
P3
0.3 ´ VCCI
tph
Pn
0.5 ´ VCCP
READ MODE (R/W = 1)
A.
CL includes probe and jig capacitance.
B.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 20. P-Port Load Circuit and Timing Waveforms
14
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Parameter Measurement Information (continued)
VCCI
RL = 1 kW
500 W
Pn
SDA
DUT
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
2 ´ VCCP
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 ´ VCCI
tRESET
VCCP/2
RESET
tREC
tREC
tW
VCCP/2
Pn
tRESET
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
The outputs are measured one at a time, with one transition per measurement.
D.
I/Os are configured as inputs.
E.
All parameters and waveforms are not applicable to all devices.
Figure 21. Reset Load Circuits and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The TCA6416A is a 16-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 1.65-V to 5.5-V
operation. It provides general-purpose remote I/O expansion and bidirectional voltage translation for processors
through I2C communication, an interface consisting of serial clock (SCL), and serial data (SDA) signals.
The major benefit of the TCA6416A is its voltage translation capability over a of a wide supply voltage range.
This allows the TCA6416A to interface with modern processors on the I2C side, where supply levels are lower to
conserve power. In contrast to the dropping power supplies of processors, some PCB components such as
LEDs, still require a 5-V power supply.
The VCCI pin is the power supply for the I2C bus, and therefore the pull-up resistors connected to the SCL, SDA,
INT, and RESET pins should be terminated at VCCI on the opposite side. level of the I2C bus to the TCA6416A.
The VCCP pin is the power supply for the P-ports and if pull-up resistors are used on any P-port or LEDs are
driven by any P-port, then the resistor(s) or LED(s) connected to P00-P07 and P10-P17 should be terminated at
VCCP on the opposite side. The device P-ports configured as outputs have the ability to sink up to 25 mA for
directly driving LEDs, but the current must be limited externally with an additional resistance.
The features of the device include an interrupt that is generated on the INT pin whenever an input port changes
state. The devices can also be reset to its default state by applying a low logic level to the RESET pin or by
cycling power to the device and causing a power-on reset. The ADDR hardware selectable address pin allows
two TCA6416A devices to be connected to the same I2C bus.
The TCA6416A open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed. The INT
pin can be connected to the interrupt input of a processor. By sending an interrupt signal on this line, the
TCA6416A can inform the processor if there is incoming data on the remote I/O ports without having to
communicate via the I2C bus. Thus, the TCA6416A can remain a simple slave device.
The system master can reset the TCA6416A in the event of a timeout or other improper operation by asserting a
low on the RESET input pin or by cycling the power to the VCCP pin and causing a power-on reset (POR). A
reset puts the registers in their default state and initializes the I2C /SMBus state machine. The RESET feature
and a POR cause the same reset/initialization to occur, but the RESET feature does so without powering down
the part.
One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow two devices to
share the same I2C bus or SMBus.
The TCA6416A's digital core consists of eight 8-bit data registers: two Configuration registers (input or output
selection), two Input Port registers, two Output Port registers, and two Polarity Inversion registers. At power on or
after a reset, the I/Os are configured as inputs. However, the system master can configure the I/Os as either
inputs or outputs by writing to the Configuration registers. The data for each input or output is kept in the
corresponding Input Port or Output Port register. The polarity of the Input Port register can be inverted with the
Polarity Inversion register. All registers can be read by the system master.
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8.2 Functional Block Diagrams
INT
ADDR
1
Interrupt
Logic
LP Filter
4-11
21
P00–P07
SCL
SDA
22
23
Input
Filter
Shift
Register
2
I C Bus
Control
16 Bits
I/O Port
13-20
P10–P17
VCCI
VCCP
RESET
GND
2
Write Pulse
Read Pulse
24
3
Power-On
Reset
12
A.
All I/Os are set to inputs at reset.
B.
Pin numbers shown are for the PW package.
Figure 22. Logic Diagram (Positive Logic)
Data From
Shift Register
Data From
Shift Register
Output Port
Register Data
VCCP
Configuration
Register
D
Q
Q1
FF
Write Configuration
Pulse
CK Q
D
Q
FF
Write Pulse
P00 to P17
CK Q
Output
Port
Register
Q2
ESD Protection Diode
Input
Port
Register
GND
Input Port
Register Data
Q
D
FF
Read Pulse
CK Q
To INT
Data From
Shift Register
D
Polarity
Register Data
Q
FF
Write Polarity Pulse
CK Q
Polarity
Inversion
Register
A.
On power up or reset, all registers return to default values.
Figure 23. Simplified Schematic of P0 to P17
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8.3 Feature Description
8.3.1 Voltage Translation
Table 2 lists all of the optional voltage supply level combinations for the I2C bus (VCCI) and the P-ports (VCCP)
supported by the TCA6416A.
Table 2. Voltage Translation
VCCI (SDA AND SCL OF I2C MASTER)
(V)
VCCP (P-PORTS)
(V)
1.8
1.8
1.8
2.5
1.8
3.3
1.8
5
2.5
1.8
2.5
2.5
2.5
3.3
2.5
5
3.3
1.8
3.3
2.5
3.3
3.3
3.3
5
5
1.8
5
2.5
5
3.3
5
5
8.3.2 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
8.3.3 Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur
during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this
pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the Input Port register.
The INT output has an open-drain structure and requires pull-up resistor to VCCP or VCCI depending on the
application. INT should be connected to the voltage source of the device that requires the interrupt information.
8.3.4 Reset Input (RESET)
The RESET input can be asserted to initialize the system while keeping the VCCP at its operating level. A reset
can be accomplished by holding the RESET pin low for a minimum of tW. The TCA6416A registers and
I2C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1),
the I/O levels at the P port can be changed externally or through the master. This input requires a pull-up resistor
to VCCI, if no active connection is used.
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8.4 Device Functional Modes
8.4.1 Power-On Reset
When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6416A in a reset condition
until VCCP has reached VPOR. At that time, the reset condition is released, and the TCA6416A registers and
I2C/SMBus state machine initializes to their default states. After that, VCCP must be lowered to below VPORF and
back up to the operating voltage for a power-reset cycle.
8.5 Programming
8.5.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output, while the SCL input is high (see Figure 24). After the Start condition, the device address
byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must
not be changed between the Start and the Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 25).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 24).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 26). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Stop Condition
Start Condition
Figure 24. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Change
Figure 25. Bit Transfer
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Programming (continued)
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 26. Acknowledgment on the I2C Bus
Table 3. Interface Definition
BYTE
I2C slave address
I/O data bus
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
L
H
L
L
L
L
ADDR
R/W
P07
P06
P05
P04
P03
P02
P01
P00
P17
P16
P15
P14
P13
P12
P11
P10
8.6 Register Maps
8.6.1 Device Address
The address of the TCA6416A is shown in Figure 27.
Slave Address
0
1
0
0
Fixed
0
AD
0 DR R/W
Programmable
Figure 27. TCA6416A Address
Table 4. Address Reference
20
ADDR
I2C BUS SLAVE ADDRESS
L
32 (decimal), 20 (hexadecimal)
H
33 (decimal), 21 (hexadecimal)
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The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
8.6.2 Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is
stored in the control register in the TCA6416A. Three bits of this data byte state the operation (read or write) and
the internal registers (input, output, polarity inversion, or configuration) that will be affected. This register can be
written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a new command has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent.
B6
B7
B5
B4
B3
B2
B1
B0
Figure 28. Control Register Bits
Table 5. Command Byte
CONTROL REGISTER BITS
B7
B6
B5
B4
B3
B2
B1
B0
COMMAND BYTE
(HEX)
REGISTER
PROTOCOL
POWER-UP
DEFAULT
0
0
0
0
0
0
0
0
00
Input Port 0
Read byte
xxxx xxxx (1)
0
0
0
0
0
0
0
1
01
Input Port 1
Read byte
xxxx xxxx (1)
0
0
0
0
0
0
1
0
02
Output Port 0
Read/write byte
1111 1111
0
0
0
0
0
0
1
1
03
Output Port 1
Read/write byte
1111 1111
0
0
0
0
0
1
0
0
04
Polarity Inversion 0
Read/write byte
0000 0000
0
0
0
0
0
1
0
1
05
Polarity Inversion 1
Read/write byte
0000 0000
0
0
0
0
0
1
1
0
06
Configuration 0
Read/write byte
1111 1111
0
0
0
0
0
1
1
1
07
Configuration 1
Read/write byte
1111 1111
(1)
Undefined
8.6.3 Register Descriptions
The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the
pin is defined as an input or an output by the Configuration register. They act only on read operation. Writes to
these registers have no effect. The default value (X) is determined by the externally applied logic level. Before a
read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input
Port register will be accessed next.
Table 6. Registers 0 and 1 (Input Port Registers)
BIT
I-07
I-06
I-05
I-04
I-03
I-02
I-01
I-00
DEFAULT
X
X
X
X
X
X
X
X
BIT
I-17
I-16
I-15
I-14
I-13
I-12
I-11
I-10
DEFAULT
X
X
X
X
X
X
X
X
The Output Port registers (registers 2 and 3) shows the outgoing logic levels of the pins defined as outputs by
the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads
from these registers reflect the value that is in the flip-flop controlling the output selection, not the actual pin
value.
Table 7. Registers 2 and 3 (Output Port Registers)
BIT
O-07
O-06
O-05
O-04
O-03
O-02
O-01
O-00
DEFAULT
1
1
1
1
1
1
1
1
BIT
O-17
O-16
O-15
O-14
O-13
O-12
O-11
O-10
DEFAULT
1
1
1
1
1
1
1
1
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The Polarity Inversion registers (register 4 and 5) allow polarity inversion of pins defined as inputs by the
Configuration register. If a bit in these registers is set (written with 1), the corresponding port pin's polarity is
inverted. If a bit in these registers is cleared (written with a 0), the corresponding port pin's original polarity is
retained.
Table 8. Registers 4 and 5 (Polarity Inversion Registers)
BIT
P-07
P-06
P-05
P-04
P-03
P-02
P-01
DEFAULT
0
0
0
0
0
0
0
P-00
0
BIT
P-17
P-16
P-15
P-14
P-13
P-12
P-11
P-10
DEFAULT
0
0
0
0
0
0
0
0
The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a bit in these registers is
set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in these
registers is cleared to 0, the corresponding port pin is enabled as an output.
Table 9. Registers 6 and 7 (Configuration Registers)
BIT
C-07
C-06
C-05
C-04
C-03
C-02
C-01
DEFAULT
1
1
1
1
1
1
1
C-00
1
BIT
C-17
C-16
C-15
C-14
C-13
C-12
C-11
C-10
DEFAULT
1
1
1
1
1
1
1
1
8.6.4 Bus Transactions
Data is exchanged between the master and TCA6416A through write and read commands.
8.6.4.1 Writes
Data is transmitted to the TCA6416A by sending the device address and setting the least-significant bit (LSB) to
a logic 0 (see Figure 27 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte. There is no limitation on the number of data bytes sent
in one write transmission.
The eight registers within the TCA6416A are configured to operate as four register pairs. The four pairs are input
ports, output ports, polarity inversion ports and configuration ports. After sending data to one register, the next
data byte is sent to the other register in the pair (see Figure 29 and Figure 30). For example, if the first byte is
send to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register
may be updated independently of the other registers.
SCL
1
2
3
4
5
6
7
8
9
Command Byte
Slave Address
SDA
S
0
1
0
0 0
Start Condition
0
AD 0
DR
A 0
0
0
R/W Acknowledge
From Slave
0
0
0
1
Data to Port 0
0
A 0.7
Data to Port 1
0.0 A 1.7
Data 0
Acknowledge
From Slave
Data 1
1.0 A
P
Acknowledge
From Slave
Write to Port
Data Out from Port 0
tpv
Data Valid
Data Out from Port 1
tpv
Figure 29. Write to Output Port Register
<br/>
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SCL
1
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2
3
5
4
6
8
7
9
1
3
2
Slave Address
SDA
S
0
0
1
0
0
4
5
6
8
7
0 AD
DR 0
1
A
0
0
0
0
0
3
2
5
4
6
8
7
9
1
1 1/0 0/1
Data 0
A MSB
3
2
Data to Register
R/W Acknowledge
From Slave
Start Condition
9
Command Byte
4
5
Data to Register
Data1
LSB A MSB
Acknowledge
From Slave
LSB A
P
Acknowledge
From Slave
Figure 30. Write to Configuration or Polarity Inversion Registers
8.6.4.2 Reads
The bus master first must send the TCA6416A address with the LSB set to a logic 0 (see Figure 27 for device
address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register
defined by the command byte then is sent by the TCA6416A (see Figure 31 and Figure 32).
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart
occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original
command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the
register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but
the data now reflects the information in the other register in the pair. For example, if Input Port 1 is read, the next
byte read is Input Port 0.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
Slave Address
S
0
1
0
0
0
Acknowledge
From Slave
Acknowledge
From Slave
0 AD
DR 0
A
Command Byte
R/W
A
S
Slave Address
0
1
0
0
0
0
At this moment, master transmitter
becomes master receiver, and
slave receiver becomes slave transmitter.
Acknowledge
From Slave
AD 1
DR
Data From Lower
or Upper Byte Acknowledge
of Register
From Master
Data
A MSB
R/W
LSB A
First Byte
Data From Upper
or Lower Byte No Acknowledge
of Register
From Master
MSB
Data
LSB NA P
Last Byte
Figure 31. Read From Register
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1
SCL
2
3
4
5
6
www.ti.com
7
R
9
Data From Port
Slave Address
S 0
SDA
1
0
0
0
AD
0 DR 1
Start
Condition
R/W
Data From Port
Data 1
A
Data 4
A
ACK From
Master
ACK From
Slave
NA P
NACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
tph
Data 3
Data 4
Data 5
tps
INT is cleared
by Read from Port
INT
tiv
Stop not needed
to clear INT
tir
A.
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B.
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P port (see Figure 31).
Figure 32. Read Input Port Register
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Applications of the TCA6416A will have this device connected as a slave to an I2C master (processor), and the
I2C bus may contain any number of other slave devices. The TCA6416A will be in a remote location from the
master, placed close to the GPIOs to which the master needs to monitor or control.
A typical application of the TCA6416A will operate with a lower voltage on the master side (VCCI), and a higher
voltage on the P-port side (VCCP). The P-ports can be configured as outputs connected to inputs of devices
such as enable, reset, power select, the gate of a switch, and LEDs. The P-ports can also be configured as
inputs to receive data from interrupts, alarms, status outputs, or push buttons.
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9.2 Typical Application
Figure 33 shows an application in which the TCA6416A can be used.
VCCI
VCCP
10 kW (´ 7)
VCCI
(1.8 V)
10 kW
VCC
10 kW
VCCI
22
SCL
Master
Controller SDA
23
1
INT
GND
2
10 kW
10 kW
3
RESET
24
VCCP
4
P00
SCL
ALARM
(see Note E)
Subsystem 1
(e.g., Alarm)
A
SDA
5
P01
INT
ENABLE
RESET
B
6
P02
P03
P04
TCA6416A P05
P06
P07
P10
P11
P12
P13
21
ADDR
P14
P15
P16
P17
GND
7
8
9
10
11
13
14
Keypad
15
16
17
18
19
20
12
A.
Device address configured as 0100000 for this example.
B.
P00 and P02–P10 are configured as inputs.
C.
P01 and P11–P17 are configured as outputs.
D.
Pin numbers shown are for the PW package.
E.
Resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float, a resistor
is not needed. Outputs (in the P port) do not need pullup resistors.
Figure 33. Typical Application Schematic
9.2.1 Design Requirements
Table 10. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
2
I C input voltage (VCCI)
26
1.8 V
P-port input/output voltage (VCCP)
5V
Output current rating, P-port sinking (IOL)
25 mA
Output current rating, P-port sourcing (IOH)
10 mA
I2C bus clock (SCL) speed
400 kHz
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9.2.2 Detailed Design Procedure
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all slaves on the I2C bus. The minimum pull-up resistance is a function of
VCC, VOL,(max), and IOL:
Rp(min) =
VCC - VOL(max)
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL =
400 kHz) and bus capacitance, Cb:
Rp(max) =
tr
0.8473 ´ Cb
(2)
2
The maximum bus capacitance for an I C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the TCA9538, Ci for SCL or
Cio for SDA, the capacitance of wires/connections/traces, and the capacitance of additional slaves on the bus.
9.2.2.1 Minimizing ICC When I/Os Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 34. For a P-port configured as an input, ICC increases as VI becomes lower than VCC. The LED is a diode,
with threshold voltage VT, and when a P-port is configured as an input the LED will be off but VI is a VT drop
below VCC.
For battery-powered applications, it is essential that the voltage of P-ports controlling LEDs is greater than or
equal to VCC when the P-ports are configured as input to minimize current consumption. Figure 34 shows a highvalue resistor in parallel with the LED. Figure 35 shows VCC less than the LED supply voltage by at least VT.
Both of these methods maintain the I/O VI at or above VCC and prevents additional supply current consumption
when the P-port is configured as an input and the LED is off.
VCC
LED
100 k
VCC
LEDx
Figure 34. High-Value Resistor in Parallel With LED
3.3 V
VCC
5V
LED
LEDx
Figure 35. Device Supplied by a Lower Voltage
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9.2.3 Application Curves
25
1.8
Standard-mode
Fast-mode
1.6
1.4
Rp(min) (kOhm)
Rp(max) (kOhm)
20
15
10
1.2
1
0.8
0.6
0.4
5
VCC > 2V
VCC <= 2
0.2
0
0
0
50
100
150
200
250
Cb (pF)
300
350
400
450
0.5
1
1.5
2
2.5
3
VCC (V)
3.5
4
4.5
5
5.5
D009
VOL = 0.2 × VCC, IOL = 2 mA when VCC ≤ 2 V
VOL = 0.4 V, IOL = 3 mA when VCC > 2 V
Standard-mode: fSCL= 100 kHz, tr = 1 µs
Fast-mode: fSCL= 400 kHz, tr= 300 ns
Figure 36. Maximum Pullup Resistance (Rp(max)) vs Bus
Capacitance (Cb)
28
0
D008
Figure 37. Minimum Pullup Resistance (Rp(min)) vs Pullup
Reference Voltage (VCC)
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10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA6416A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 38 and Figure 39.
VCC
Ramp-Up
Ramp-Down
Re-Ramp-Up
VCC_TRR_GND
Time
VCC_RT
VCC_FT
Time to Re-Ramp
VCC_RT
Figure 38. VCC is Lowered Below 0.2 V or 0 V and Then Ramped up to VCC
VCC
Ramp-Up
Ramp-Down
VCC_TRR_VPOR50
VIN drops below POR levels
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 39. VCC is Lowered Below the POR Threshold, Then Ramped Back up to VCC
Table 11 specifies the performance of the power-on reset feature for TCA6416A for both types of power-on reset.
Table 11. Recommended Supply Sequencing and Ramp Rates (1)
PARAMETER
(2)
MAX
UNIT
tFT
Fall rate
See Figure 38
0.1
2000
ms
tRT
Rise rate
See Figure 38
0.1
2000
ms
tTRR_GND
Time to re-ramp (when VCC drops to GND)
See Figure 38
1
μs
tTRR_POR50
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
See Figure 39
1
μs
VCC_GH
Level that VCCP can glitch down to, but not cause a functional
disruption when VCCX_GW = 1 μs
See Figure 40
1.2
V
tGW
Glitch width that will not cause a functional disruption when
VCCX_GH = 0.5 × VCCx
See Figure 40
10
μs
VPORF
Voltage trip point of POR on falling VCC
VPORR
Voltage trip point of POR on fising VCC
(1)
(2)
MIN
TYP
0.7
V
1.4
V
TA = 25°C (unless otherwise noted).
Not tested. Specified by design.
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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 40 and Table 11 provide more
information on how to measure these specifications.
VCC
VCC_GH
Time
VCC_GW
Figure 40. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 41 and Table 11 provide more details on this specification.
VCC
VPOR
VPORF
Time
POR
Time
Figure 41. VPOR
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11 Layout
11.1 Layout Guidelines
For printed circuit board (PCB) layout of the TCA6416A, common PCB layout practices should be followed
but additional concerns related to high-speed data transfer such as matched impedances and differential
pairs are not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away
from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry
higher amounts of current that commonly pass through power and ground traces. By-pass and de-coupling
capacitors are commonly used to control the voltage on the VCCP pin, using a larger capacitor to provide
additional power in the event of a short power supply glitch and a smaller capacitor to filter out highfrequency ripple. These capacitors should be placed as close to the TCA6416A as possible. These best
practices are shown in Figure 42.
For the layout example provided in Figure 42, it would be possible to fabricate a PCB with only 2 layers by
using the top layer for signal routing and the bottom layer as a split plane for power (VCCI and VCCP) and
ground (GND). However, a 4 layer board is preferable for boards with higher density signal routing. On a 4
layer PCB, it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground
plane, and dedicate the other internal layer to a power plane. In a board layout using planes or split planes
for power and ground, vias are placed directly next to the surface mount component pad which needs to
attach to VCCI, VCCP, or GND and the via is connected electrically to the internal layer or the other side of the
board. Vias are also used when a signal trace needs to be routed to the opposite side of the board, but this
technique is not demonstrated in Figure 42.
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11.2 Layout Example
LEGEND
Partial view of plane
(inner layer)
Via to power plane
Via to GND plane
VC
I
C
C
INT
VCCP
16
2
VCCI
SDA
15
3
RESET
SCL
14
4
P00
ADDR
13
5
P01
P17
16
6
P02
P16
15
7
P03
P15
14
8
P04
P14
13
9
P05
P13
16
10
P06
P12
15
11
P07
P11
14
12
GND
P10
13
GN
D
PW package
TCA6416A
1
To I/Os
To I/Os
P
To processor
VC
Bypass/decoupling
capacitors
Figure 42. TCA6416A Layout
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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21-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TCA6416APWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PH416A
TCA6416ARTWR
ACTIVE
WQFN
RTW
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PH416A
TCA6416AZQSR
LIFEBUY
BGA
MICROSTAR
JUNIOR
ZQS
24
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
PH416A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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21-May-2019
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TCA6416APWR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
TCA6416ARTWR
WQFN
RTW
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
TCA6416AZQSR
BGA MI
CROSTA
R JUNI
OR
ZQS
24
2500
330.0
12.4
3.3
3.3
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TCA6416APWR
TSSOP
PW
24
2000
367.0
367.0
38.0
TCA6416ARTWR
WQFN
RTW
24
3000
367.0
367.0
35.0
TCA6416AZQSR
BGA MICROSTAR
JUNIOR
ZQS
24
2500
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
13
B
0.30
0.19
0.1
C A B
24X
4.5
4.3
NOTE 4
1.2 MAX
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
13
12
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
WQFN - 0.8 mm max height
RTW0024B
PLASTIC QUAD FLATPACK-NO LEAD
4.1
3.9
B
A
4.1
3.9
PIN 1 INDEX AREA
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 2.5
EXPOSED
THERMAL PAD
12
7
(0.2) TYP
20X 0.5
6
2X
2.5
13
25
SYMM
2.45±0.1
1
PIN 1 ID
(OPTIONAL)
18
19
24
SYMM
24X 0.5
0.3
24X 0.34
0.24
0.1
0.05
C A B
C
4219135/A 11/2016
NOTES:
1.
2.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
RTW0024B
PLASTIC QUAD FLATPACK-NO LEAD
(
2.45)
SYMM
24
19
24X (0.6)
24X (0.24)
1
18
(0.97)
SYMM
25
(3.8)
20X (0.5)
(R0.05)
TYP
13
6
(Ø0.2) TYP
VIA
7
(0.97)
12
(3.8)
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOTES: (continued)
3.
For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
www.ti.com
4219135/A 11/2016
EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
RTW0024B
PLASTIC QUAD FLATPACK-NO LEAD
4X(
1.08)
(0.64) TYP
(R0.05) TYP
24
19
24X (0.6)
25
1
18
(0.64)
TYP
24X (0.24)
SYMM
20X (0.5)
(3.8)
13
6
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25:
78% PRINTED COVERAGE BY AREA UNDER PACKAGE
SCALE: 20X
4219135/A 11/2016
NOTES: (continued)
4.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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