Texas Instruments | DS90UH926Q-Q1 720p, 24-Bit Color FPD-Link III Deserializer With HDCP (Rev. M) | Datasheet | Texas Instruments DS90UH926Q-Q1 720p, 24-Bit Color FPD-Link III Deserializer With HDCP (Rev. M) Datasheet

Texas Instruments DS90UH926Q-Q1 720p, 24-Bit Color FPD-Link III Deserializer With HDCP (Rev. M) Datasheet
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DS90UH926Q-Q1
SNLS337M – OCTOBER 2010 – REVISED AUGUST 2017
DS90UH926Q-Q1 720p, 24-Bit Color FPD-Link III Deserializer With HDCP
1 Features
3 Description
•
The DS90UH926Q-Q1 deserializer, in conjunction
with the DS90UH925Q-Q1 serializer, provides a
solution for secure distribution of content-protected
digital video within automotive entertainment
systems. This chipset translates a parallel RGB video
interface into a single-pair high-speed serialized
interface. The digital video data is protected using the
industry standard HDCP copy protection scheme.
The serial bus scheme, FPD-Link III, supports full
duplex of high-speed forward data transmission and
low-speed backchannel communication over a single
differential link. Consolidation of video data and
control over a single differential pair reduces the
interconnect size and weight, while also eliminating
skew issues and simplifying system design.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications
– Device Temperature Grade 2: –40°C to
+105°C Ambient Operating Temperature
– Device HBM ESD Classification Level 3B
– Device CDM ESD Classification Level C6
– Device MM ESD Classification Level M3
Integrated HDCP Cipher Engine With On-Chip
Key Storage
Bidirectional Control Interface Channel Interface
With I2C Compatible Serial Control Bus
Supports High-Definition (720p) Digital Video
Format
RGB888 + VS, HS, DE and I2S Audio Supported
5- to 85-MHz PCLK Supported
Single 3.3-V Operation With 1.8-V or 3.3-V
Compatible LVCMOS I/O Interface
AC-Coupled STP Interconnect up to 10 Meters
Parallel LVCMOS Video Outputs
DC-Balanced and Scrambled Data With
Embedded Clock
Adaptive Cable Equalization
Supports HDCP Repeater Application
Image Enhancement (White Balance and
Dithering) and Internal Pattern Generation
EMI Minimization (SSCG and EPTO)
Low Power Modes Minimize Power Dissipation
Backward-Compatible Modes
An adaptive equalizer optimizes the maximum cable
reach. EMI is minimized by output SSC generation
(SSCG) and enhanced progressive turnon (EPTO)
features.
The HDCP cipher engine is implemented in both the
serializer and deserializer. HDCP keys are stored in
on-chip memory.
Device Information(1)
PART NUMBER
2 Applications
•
•
The DS90UH926Q-Q1 deserializer has a 31-bit
parallel LVCMOS output interface to accommodate
the RGB, video control, and audio data. The device
extracts the clock from a high-speed serial stream.
An output LOCK pin provides the link status if the
incoming data stream is locked, without the use of a
training sequence or special SYNC patterns, as well
as a reference clock.
PACKAGE
DS90UH926Q-Q1
Automotive Display for Navigation
Rear Seat Entertainment Systems
WQFN (60)
BODY SIZE (NOM)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Diagram
HOST
Graphics
Processor
RGB Digital Display Interface
VDD33
VDDIO
(1.8V or 3.3V) (3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
SCL
SDA
IDx
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
FPD-Link III
1 Pair / AC Coupled
0.1 PF
0.1 PF
DOUT+
RIN+
DOUT-
PDB
I2S AUDIO
(STEREO)
VDDIO
VDD33
(3.3V) (1.8V or 3.3V)
3
/
DS90UH925Q
Serializer
0.1 PF
100 ohm STP Cable
MODE_SEL
INTB
DAP
0.1 PF
PDB
OSS_SEL
OEN
MODE_SEL
RINDS90UH926Q
Deserializer
SCL
SDA
IDx
LOCK
PASS
3
/
INTB_IN
RGB Display
720p
24-bit color depth
I2S AUDIO
(STEREO)
MCLK
DAP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UH926Q-Q1
SNLS337M – OCTOBER 2010 – REVISED AUGUST 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
7
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Absolute Maximum Ratings ..................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
DC Electrical Characteristics .................................... 8
AC Electrical Characteristics................................... 10
DC and AC Serial Control Bus Characteristics....... 10
Recommended Timing Requirements for the Serial
Control Bus .............................................................. 11
6.9 Switching Characteristics ........................................ 11
6.10 Timing Diagrams ................................................... 12
6.11 Typical Characteristics .......................................... 15
7
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3
7.4
7.5
7.6
8
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
16
28
32
33
Application and Implementation ........................ 47
8.1 Application Information............................................ 47
8.2 Typical Application .................................................. 47
9
Power Supply Recommendations...................... 50
9.1 Power-Up Requirements and PDB Pin ................... 50
10 Layout................................................................... 51
10.1 Layout Guidelines ................................................. 51
10.2 Layout Examples................................................... 53
11 Device and Documentation Support ................. 54
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
54
54
54
54
54
54
12 Mechanical, Packaging, and Orderable
Information ........................................................... 54
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (February 2017) to Revision M
Page
•
Reverted all previous MLCK content changes made in Revision L back to Revision K ........................................................ 1
•
Removed disable jitter cleaner note ....................................................................................................................................... 5
Changes from Revision K (January 2015) to Revision L
Page
•
Changed top view pin out diagram ........................................................................................................................................ 4
•
Changed CLK to RES2 .......................................................................................................................................................... 5
•
Added note to disable jitter cleaner ....................................................................................................................................... 5
•
Changed MCLK to RES2 ....................................................................................................................................................... 5
•
Deleted reference to MCLK in this section ............................................................................................................................ 8
•
Deleted reference to MCLK in this section .......................................................................................................................... 11
•
Deleted reference to MCLK ................................................................................................................................................. 25
•
Deleted I2S Jitter Cleaning section ..................................................................................................................................... 25
•
Deleted MCLK section ......................................................................................................................................................... 25
•
Deleted MCLK columns in the Audio Interface Frequencies table....................................................................................... 26
•
Changed values in columns 2 to 5 of Configuration Select (MODE_SEL) table.................................................................. 29
•
Changed values in columns 2 to 5 of IDx table ................................................................................................................... 32
•
Changed Removed register reference to MCLK .................................................................................................................. 42
•
Changed Typical Display System Diagram (removed MCLK) ............................................................................................. 47
•
Changed Power-Up Requirements and PDB pin description and added Power-Up Sequence graphic. ........................... 50
2
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SNLS337M – OCTOBER 2010 – REVISED AUGUST 2017
Changes from Revision J (April 2013) to Revision K
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision I (August 2012) to Revision J
•
Page
Changed layout of National Semiconductor data sheet to TI format...................................................................................... 1
Changes from Revision H (March 2012) to Revision I
•
Page
: Configuration Select (MODE_SEL) #6 I2S Channel B (18–bit Mode) from L to H, corrected typo in table “DC and
AC Serial Control Bus Characteristics” from VDDIO to VDD33, added Recommended FRC settings table, added
“When backward compatible mode = ON, set LFMODE = 0” under Functional Description. Reformatted table 9 and
added clarification to notes. Added clarification to notes on Serial Control Bus Registers, address 0x02[3:0]
(backwards compatible and LFMODE registers), added “Note: Do not enable SSCG feature if PCLK source into the
SER has an SSC clock already.” under Functional Description, EMI REDUCTION FEATURES, Spread Spectrum
Clock Generation (SSCG) ...................................................................................................................................................... 1
Changes from Revision G (February 2012) to Revision H
•
Page
Deleted “DC Electrical Characteristics” PDB VDDIO = 1.71 to 1.89 V, added under “SUPPLY CURRENT IDDZ, DDIOZ,
IDDIOZMax = 10 mA, added under “CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS” EW Min = 0.3 UI AND
EH Min = 200 mV, added “INTERRUPT PIN — FUNCTIONAL DESCRIPTION AND USAGE (INTB)” under
Functional Description section, updated "POWER DOWN (PDB) description under Functional Description from
VDDIO to VDDIO = 3 to 3.6 V or VDD33, updated Figure 24 .................................................................................................. 1
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5 Pin Configuration and Functions
OSS_SEL
R6
R7
LOCK
OEN
32
31
R5
35
33
R4
36
34
R3
40
37
R1/GPIO1
41
38
R0/GPIO0
42
R2
PASS
43
VDDIO
RES1
44
39
I2S_DA/GPO_REG6
BISTEN
45
NKB Package
60 Pin WQFN With Exposed Thermal Pad
Top View
30
I2S_WC/GPO_REG7
47
29
VDD33_B
48
28
G0/GPIO2
49
27
G1/GPIO3
50
26
G2
CMF
51
25
G3
CMLOUTP
52
24
VDDIO
RES0
VDD33_A
RIN+
RIN-
46
DS90UH926Q-Q1
CMLOUTN
53
TOP VIEW
NC
54
DAP = GND
CAPR12
55
21
23
G4
22
G5
G6
15
14
B3
MODE_SEL
11
B5
12
10
B6
13
9
B4
8
B7
VDDIO
7
VS
BISTC/INTB_IN
HS
16
DE
60
6
MCLK
5
B2
PCLK
B1/I2S_DB/GPO_REG5
17
4
18
59
3
58
PDB
SCL
CAPI2S
CAPL12
B0/GPO_REG4
2
G7
19
1
20
57
SDA
56
I2S_CLK/GPO_REG8
IDx
CAPP12
Pin Functions
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
R[7:0]
33, 34, 35, 36,
37, 39, 40, 41
RED Parallel Interface Data Output Pins
O, LVCMOS
Leave open if unused
with pulldown
R0 can optionally be used as GPIO0 and R1 can optionally be used as GPIO1
G[7:0]
20, 21, 22, 23,
25, 26, 27, 28
GREEN Parallel Interface Data Output Pins
O, LVCMOS
Leave open if unused
with pulldown
G0 can optionally be used as GPIO2 and G1 can optionally be used as GPIO3.
B[7:0]
9, 10, 11, 12,
14, 17, 18, 19
BLUE Parallel Interface Data Output Pins
O, LVCMOS Leave open if unused
with pulldown B0 can optionally be used as GPO_REG4 and B1 can optionally be used as I2S_DB or
GPO_REG5.
8
Horizontal Sync Output Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
O, LVCMOS
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
with pulldown
when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs. See Table 11
HS
4
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Pin Functions (continued)
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
7
Vertical Sync Output Pin
O, LVCMOS
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse
with pulldown
width is 130 PCLKs.
DE
6
Data Enable Output Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
O, LVCMOS
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
with pulldown
when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs. See Table 11
PCLK
5
O, LVCMOS
Pixel Clock Output Pin. Strobe edge set by RFB configuration register. See Table 11
with pulldown
1, 30, 45
Digital Audio Interface Data Output Pins
O, LVCMOS Leave open if unused
with pulldown I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as
GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
VS
I2S_CLK,
I2S_WC,
I2S_DA
MCLK
60
O, LVCMOS I2S Master Clock Output
with pulldown x1, x2, or x4 of I2S_CLK Frequency
OPTIONAL PARALLEL INTERFACE
I2S_DB
18
Second Channel Digital Audio Interface Data Output pin at 18–bit color mode and set by
O, LVCMOS MODE_SEL or configuration register
with pulldown Leave open if unused
I2S_B can optionally be used as BI or GPO_REG5.
GPIO[3:0]
27, 28, 40, 41
Standard General Purpose IOs.
Available only in 18-bit color mode, and set by MODE_SEL or configuration register.
I/O, LVCMOS
See Table 11
with pulldown
Leave open if unused
Shared with G1, G0, R1 and R0.
GPO_REG[8:
4]
1, 30, 45, 18,
19
O, LVCMOS General Purpose Outputs and set by configuration register. See Table 11
with pulldown Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0.
16
Input,
Interrupt Input
LVCMOS
Shared with BISTC
with pulldown
PDB
59
Power-down Mode Input Pin
PDB = H, device is enabled (normal operation)
I, LVCMOS Refer to Power Supply Recommendations.
with pulldown PDB = L, device is powered down.
When the device is in the POWER DOWN state, the LVCMOS Outputs are in TRI-STATE,
the PLL is shutdown and IDD is minimized.
OEN
31
Input,
Output Enable Pin.
LVCMOS
See Table 8
with pulldown
OSS_SEL
46
Input,
Output Sleep State Select Pin.
LVCMOS
See Table 8
with pulldown
MODE_SEL
15
BISTEN
44
BIST Enable Pin.
I, LVCMOS
0: BIST Mode is disabled.
with pulldown
1: BIST Mode is enabled.
BISTC
16
BIST Clock Select.
I, LVCMOS
Shared with INTB_IN
with pulldown
0: PCLK; 1: 33 MHz
INTB_IN
CONTROL
I, Analog
Device Configuration Select. See Table 9
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Pin Functions (continued)
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
I2C
I, Analog
I2C Serial Control Bus Device ID Address Select
External pull-up to VDD33 is required under all conditions, DO NOT FLOAT.
Connect to external pullup and pulldown resistor to create a voltage divider.
See Figure 23
IDx
56
SCL
3
I2C Clock Input / Output Interface
I/O, LVCMOS
Must have an external pullup to VDD33, DO NOT FLOAT.
Open-Drain
Recommended pullup: 4.7 kΩ.
SDA
2
I2C Data Input / Output Interface
I/O, LVCMOS
Must have an external pullup to VDD33, DO NOT FLOAT.
Open-Drain
Recommended pullup: 4.7 kΩ.
LOCK
32
LOCK Status Output Pin
O, LVCMOS 0: PLL is unlocked, RGB[7:0], I2S[2:0], HS, VS, DE and PCLK output states are controlled
with pulldown by OEN. May be used as Link Status or Display Enable
1: PLL is Locked, outputs are active
PASS
42
PASS Output Pin
O, LVCMOS 0: One or more errors were detected in the received payload
with pulldown 1: ERROR FREE Transmission
Leave Open if unused. Route to test point (pad) recommended
STATUS
FPD-LINK III SERIAL INTERFACE
RIN+
49
I, LVDS
True Input.
The interconnection should be AC-coupled to this pin with a 0.1 μF capacitor.
RIN–
50
I, LVDS
Inverting Input.
The interconnection should be AC-coupled to this pin with a 0.1 μF capacitor.
CMLOUTP
52
O, LVDS
True CML Output
Monitor point for equalized differential signal
CMLOUTN
53
O, LVDS
Inverting CML Output
Monitor point for equalized differential signal
CMF
51
Analog
Common Mode Filter. Connect 0.1-μF capacitor to GND.
48, 29
Power
Power to on-chip regulator 3 V – 3.6 V. Requires 4.7 uF to GND at each VDD pin.
VDDIO
13, 24, 38
Power
LVCMOS I/O Power 1.8 V ±5% OR 3 V – 3.6 V. Requires 4.7 uF to GND at each VDDIO
pin.
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
POWER (1) AND GROUND
VDD33_A,
VDD33_B
REGULATOR CAPACITOR
CAPR12
55
CAPP12
57
CAPI2S
58
CAPL12
4
CAP
Decoupling capacitor connection for on-chip regulator. Requires a 4.7-µF to GND at each
CAP pin.
CAP
Decoupling capacitor connection for on-chip regulator. Requires two 4.7-µF to GND at this
CAP pin.
OTHERS
NC
RES[1:0]
(1)
6
54
NC
43.47
GND
No connect. This pin may be left open or tied to any level.
Reserved - tie to Ground
The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
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6 Specifications
6.1 Absolute Maximum Ratings
See
(1) (2) (3)
MIN
MAX
UNIT
Supply voltage – VDD33
−0.3
4
V
Supply voltage – VDDIO
−0.3
4
V
LVCMOS I/O voltage
−0.3
(VDDIO + 0.3)
V
Deserializer input voltage
−0.3
2.75
V
Junction temperature
60-pin WQFN Package
Maximum power dissipation
capacity at 25°C
Derate above 25 °C
150
°C
1/ RθJA
°C/W
31
°C/W
2.4
°C/W
150
°C
RθJA
RθJC
−65
Storage temperature, Tstg
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
For soldering specifications, see product folder at www.ti.com and Absolute Maximum Ratings for Soldering (SNOA549).
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002
V(ESD)
(1)
Electrostatic
discharge
(1)
UNIT
±8000
Charged-device model (CDM), per AEC Q100-011
±1250
Machine model, all pins
±250
(IEC, powered-up only)
RD = 330 Ω, CS = 150 pF
Air Discharge (Pin 49 and 50)
Contact Discharge (Pin 49 and 50)
±15000
±8000
(ISO10605)
RD = 330 Ω, CS = 150 pF
Air Discharge (Pin 49 and 50)
±15000
Contact Discharge (Pin 49 and 50)
±8000
(ISO10605)
RD = 2 kΩ, CS = 150 & 330 pF
Air Discharge (Pin 49 and 50)
±15000
Contact Discharge (Pin 49 and 50)
±8000
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
3
3.3
3.6
V
Connect VDDIO to 3.3 V and use 3.3-V IOs
3
3.3
3.6
V
Connect VDDIO to 1.8 V and use 1.8-V IOs
1.71
1.8
1.89
V
−40
25
105
°C
Supply voltage (VDD33)
LVCMOS supply voltage (VDDIO)
Operating free air temperature (TA)
PCLK frequency
5
Supply noise (1)
(1)
UNIT
85
MHz
100
mVP-P
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDD33 and VDDIO supplies
with amplitude = 100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the
Des with 10-meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows
no error when the noise frequency is less than 50 MHz.
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6.4 Thermal Information
DS90UH926Q-Q1
THERMAL METRIC (1)
NKB (WQFN)
UNIT
60 PINS
RθJA
Junction-to-ambient thermal resistance
26.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
8.1
°C/W
RθJB
Junction-to-board thermal resistance
5.2
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
5.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.1
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.5 DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
2
VDDIO
V
GND
0.8
V
10
μA
2
VDDIO
V
0.65 ×
VDDIO
VDDIO
V
GND
0.8
V
GND
0.35 ×
VDDIO
V
LVCMOS I/O DC SPECIFICATIONS
VIH
High Level Input
Voltage
VDDIO = 3 to 3.6 V
VIL
Low Level Input
Voltage
VDDIO = 3 to 3.6 V
IIN
Input Current
VIN = 0 V or VDDIO = 3 to 3.6 V
VIH
High Level Input
Voltage
VIL
Low Level Input
Voltage
IIN
VOH
Input Current
High Level Output
Voltage
PDB
VDDIO = 3 to 3.6 V
VDDIO = 1.71 to 1.89 V
VDDIO = 3 to 3.6 V
OEN, OSS_SEL,
BISTEN, BISTC /
INTB_IN, GPIO[3:0]
VDDIO = 1.71 to 1.89 V
VIN = 0 V or VDDIO
−10
±1
10
μA
VDDIO = 1.7
to 1.89 V
−10
±1
10
μA
VDDIO = 3 to 3.6 V
IOH = −4 mA
VDDIO = 1.7
to 1.89 V
VDDIO = 3 to 3.6 V
Low Level Output
Voltage
IOL = 4 mA
IOS
Output Short-Circuit
Current
VOUT = 0 V
IOZ
Tri-state Output Current VOUT = 0 V or VDDIO, PDB = L
(2)
(3)
8
±1
VDDIO = 3
to 3.6 V
VOL
(1)
−10
VDDIO = 1.7
to 1.89 V
R[7:0], G[7:0], B[7:0],
HS, VS, DE, PCLK,
LOCK, PASS, MCLK,
I2S_CLK, I2S_WC,
I2S_DA, I2S_DB,
GPO_REG[8:4]
2.4
VDDIO
V
VDDIO0.45
VDDIO
V
GND
0.4
V
GND
0.35
V
−60
−10
mA
10
μA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the electrical characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25 °C, and at Recommended Operating Conditions at the
time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
FPD-LINK III CML RECEIVER INPUT DC SPECIFICATIONS
VTH
Differential Threshold
High Voltage
VTL
Differential Threshold
Low Voltage
VCM
Differential Commonmode Voltage
RT
Internal Termination
Resistor - Differential
50
VCM = 2.5 V
(Internal VBIAS)
−50
mV
mV
RIN+, RIN–
1.8
80
100
V
120
Ω
CML MONITOR DRIVER OUTPUT DC SPECIFICATIONS
VODp-p
Differential Output
Voltage
CMLOUTP,
CMLOUTN
RL = 100 Ω
360
mVp-p
SUPPLY CURRENT
IDD1
IDDIO1
IDD2
IDDIO2
CL = 12 pF,
Checker Board Pattern
Figure 1
Supply Current
(includes load current)
f = 85 MHz
VDD33 = 3.6 V
CL = 4 pF
Checker Board Pattern, VDDIO = 3.6 V
Figure 1
VDDIO = 1.89 V
Supply Current Sleep
Mode
Without Input Serial
Stream
IDDS
IDDIOS
VDDIO= 3.6 V
VDDIO = 1.89 V
VDD33 = 3.6 V
VDDIO = 3.6 V
VDDIO = 1.89 V
IDDZ
IDDIOZ
VDD33= 3.6 V
Supply Current
(includes load current)
f = 85 MHz
Supply Current Power
Down
PDB = L, All LVCMOS
inputs are floating or
tied to GND
VDD33 = 3.6 V
VDDIO = 3.6 V
VDDIO = 1.89 V
VDD33
VDDIO
VDD33
VDDIO
VDD33
VDDIO
VDD33
VDDIO
125
145
110
118
60
75
125
145
75
85
50
65
90
115
3
5
2
3
2
10
0.05
10
0.05
10
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mA
mA
mA
mA
mA
mA
mA
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6.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
GPIO BIT RATE
Forward Channel Bit Rate
BR
See (4)
Back Channel Bit Rate
(5)
f = 5 – 85
MHz,
GPIO[3:0]
0.25 × f
Mbps
> 50
> 75
kbps
0.3
0.4
UI
200
300
mV
800
ns
CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS
EW
Differential Output Eye Opening
Width (6)
EH
Differential Output Eye Height
RL = 100 Ω,
Jitter Freq > f / 40
Figure 2 (4) (5)
CMLOUTP,
CMLOUTN,
f = 85 MHz
BIST MODE
tPASS
BIST PASS Valid Time
BISTEN = H
Figure 8 (4) (5)
PASS
SSCG MODE
fDEV
Spread Spectrum Clocking
Deviation Frequency
fMOD
Spread Spectrum Clocking
Modulation Frequency
(1)
(2)
(3)
(4)
(5)
(6)
SeeFigure 14, Table 1 and
Table 2 (4) (5)
±0.5%
±2.5%
8
100
f = 85 MHz,
SSCG = ON
kHz
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the electrical characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25 °C, and at Recommended Operating Conditions at the
time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
Specification is ensured by characterization and is not tested in production.
Specification is ensured by design and is not tested in production.
UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 35 × PCLK). The UI scales with PCLK frequency.
6.7 DC and AC Serial Control Bus Characteristics
Over 3.3-V supply and temperature ranges unless otherwise specified. (1)
PARAMETER
(2) (3)
TEST CONDITIONS
MIN
VIH
Input High Level
SDA and SCL
0.7 × VDD33
VIL
Input Low Level Voltage
SDA and SCL
GND
VHY
Input Hysteresis
VOL
SDA or SCL, VIN = VDD33 or GND
tR
SDA Rise Time – READ
tF
SDA Fall Time – READ
tSU;DAT
Setup Time — READ
tHD;DAT
Holdup Time — READ
tSP
Input Filter
CIN
Input Capacitance
(1)
(2)
(3)
10
MAX
UNIT
VDD33
V
0.3 × VDD33
> 50
SDA, IOL = 1.25 mA
IIN
TYP
0
–10
V
mV
0.36
V
10
µA
430
ns
20
ns
SeeFigure 9
560
ns
SeeFigure 9
615
ns
SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 9
SDA or SCL
50
ns
<5
pF
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the electrical characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25 °C, and at Recommended Operating Conditions at the
time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
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6.8 Recommended Timing Requirements for the Serial Control Bus
Over 3.3-V supply and temperature ranges unless otherwise specified.
MIN
fSCL
tLOW
tHIGH
tHD;STA
tSU:STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
tr
tf
SCL Clock Frequency
SCL Low Period
SCL High Period
NOM
MAX
UNIT
Standard Mode
0
100
kHz
Fast Mode
0
400
kHz
Standard Mode
4.7
µs
Fast Mode
1.3
µs
Standard Mode
Fast Mode
4
µs
0.6
µs
4
µs
Hold time for a start or a
repeated start condition
Figure 9
Standard Mode
Fast Mode
0.6
µs
Setup time for a start or a
repeated start condition
Figure 9
Standard Mode
4.7
µs
Fast Mode
0.6
µs
Data Hold Time
Figure 9
Standard Mode
0
3.45
µs
Fast Mode
0
0.9
µs
Data Setup Time
Figure 9
Standard Mode
250
Fast Mode
100
ns
Setup Time for STOP
Condition, Figure 9
Standard Mode
4
µs
Fast Mode
0.6
µs
Bus Free Time
Between STOP and START,
Figure 9
Standard Mode
4.7
µs
Fast Mode
1.3
µs
SCL and SDA Rise Time,
Figure 9
Standard Mode
1000
ns
Fast Mode
300
ns
SCL and SDA Fall Time,
Figure 9
Standard Mode
300
ns
Fast mode
300
ns
ns
6.9 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tRCP
PCLK Output Period
tRDC
PCLK Output Duty Cycle
tCLH
tCHL
tROS
tROH
LVCMOS Low-to-High Transition
Time
Figure 3
LVCMOS High-to-Low Transition
Time
Figure 3
TEST CONDITIONS
tRCP = tTCP
PIN/FREQ.
PCLK
MIN
TYP
MAX
UNIT
11.76
T
200
ns
45%
50%
55%
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
2
3
ns
VDDIO = 3 to 3.6 V,
CL = 12 pF
2
3
ns
2
3
ns
2
3
ns
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
VDDIO = 3 to 3.6 V,
CL = 12 pF
Data Valid before PCLK – Setup
Time
SSCG = OFF
Figure 6
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
Data Valid after PCLK – Hold
Time
SSCG = OFF
Figure 6
R[7:0], G[7:0],
B[7:0], HS,
VS, DE,
PCLK, LOCK,
PASS, MCLK,
I2S_CLK,
I2S_WC,
I2S_DA,
I2S_DB
2.2
ns
2.2
ns
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
3
ns
VDDIO = 3 to 3.6 V,
CL = 12 pF
3
ns
VDDIO = 3 to 3.6 V,
CL = 12 pF
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Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Active to OFF Delay
Figure 5 (1) (2)
tXZR
tDDLT
Lock Time
Figure 5 (1) (2) (3)
tDD
Delay – Latency (1) (2)
tDCCJ
tONS
tONH
tSES
tSEH
(1)
(2)
(3)
TEST CONDITIONS
OEN = L, OSS_SEL = H
SSCG = OFF
Cycle-to-Cycle Jitter (1) (2)
UNIT
R[7:0], G[7:0],
B[7:0]
10
ns
HS, VS, DE,
PCLK, LOCK,
PASS
15
ns
MCLK,I2S_CL
K, I2S_WC,
I2S_DA,
I2S_DB
60
ns
f = 5 – 85 MHz
5
f = 5 – 85 MHz
40
ms
0.5
ns
f = 15 to 85
MHz
0.2
ns
I2S_CLK = 1
to 12.28 MHz
±2
ns
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
50
ns
VDDIO = 3 to 3.6 V,
CL = 12 pF
50
ns
50
ns
50
ns
5
ns
5
ns
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
5
ns
VDDIO = 3 to 3.6 V,
CL = 12 pF
5
ns
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
VDDIO = 3 to 3.6 V,
CL = 12 pF
Data to Low after OSS_SEL = L
Setup Time
Figure 7 (1) (2)
MAX
ns
VDDIO = 3 to 3.6 V,
CL = 12 pF
Data Tri-State after OSS_ SEL =
H, Setup Time
Figure 7 (1) (2)
TYP
147 × T
VDDIO = 1.71 to 1.89 V,
CL = 12 pF
Data Tri-State After OEN = L
SetupTime
Figure 7 (1) (2)
MIN
f = 5 to <15
MHz
SSCG = OFF
Data Valid After OEN = H
SetupTime
Figure 7 (1) (2)
PIN/FREQ.
R[7:0], G[7:0],
B[7:0], HS,
VS, DE,
PCLK,
MCLK,I2S_CL
K, I2S_WC,
I2S_DA,
I2S_DB
Specification is ensured by characterization and is not tested in production.
Specification is ensured by design and is not tested in production.
tDDLT is the time required by the device to obtain lock when exiting power-down state with an active serial stream.
6.10 Timing Diagrams
VDDIO
PCLK
GND
VDDIO
RGB[n] (odd),
VS, HS
GND
VDDIO
RGB[n] (even),
DE
GND
Figure 1. Checker Board Data Pattern
12
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Timing Diagrams (continued)
EW
VOD (+)
CMLOUT
(Diff.)
EH
0V
EH
VOD (-)
tBIT (1 UI)
Figure 2. CML Output Driver
VDDIO
80%
20%
GND
tCLH
tCHL
Figure 3. LVCMOS Transition Times
START
BIT
STOP
BIT
START
BIT
STOP
BIT
RIN
0
(Diff.)
1
2
33
SYMBOL N
0
1
2
33
SYMBOL N+1
tDD
PCLK
(RFB = L)
RGB[7:0],
I2S[2:0],
HS, VS, DE
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 4. Delay - Latency
PDB
2.0V
0.8V
RIN
(Diff.)
}v[š
Œ
tDDLT
LOCK
TRI-STATE
or LOW
Z or L
tXZR
RGB[7:0],
HS, VS, DE,
I2S
TRI-STATE or LOW or Pulled Up
PCLK
(RFB = L)
Z or L or PU
TRI-STATE or LOW
OFF
IN LOCK TIME
Z or L
ACTIVE
OFF
Figure 5. PLL Lock Times and PDB Tri-State Delay
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Timing Diagrams (continued)
VDDIO
PCLK
w/RFB = H
1/2 VDDIO
GND
RGB[7:0],
VS, HS, DE,
I2S
VDDIO
VOHmin
VOLmax
GND
tROH
tROS
Figure 6. Output Data Valid (Setup and Hold) Times With SSCG = OFF
PDB = H
OSS_SEL
VIH
VIL
VIH
OEN
VIL
RIN
(Diff.)
}v[š
Œ
tSEH
tSES
tONH
tONS
TRI-STATE
LOCK
(HIGH)
PASS
ACTIVE
HIGH
RGB[7:0],
HS, VS, DE,
I2S[2:0]
LOW
TRI-STATE
PCLK
(RFB = L)
LOW
TRI-STATE
HIGH
ACTIVE
ACTIVE
TRI-STATE
LOW
TRI-STATE
LOW
Figure 7. Output State (Setup and Hold) Times
BISTEN
1/2 VDDIO
tPASS
PASS
(w/errors)
1/2 VDDIO
Prior BIST Result
Current BIST Test - Toggle on Error
Result Held
Figure 8. BIST PASS Waveform
14
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Timing Diagrams (continued)
SDA
tf
tHD;STA
tLOW
tr
tf
tr
tBUF
tSP
SCL
tSU;STA
tHD;STA
tHIGH
tHD;DAT
START
tSU;STO
tSU;DAT
STOP
REPEATED
START
START
Figure 9. Serial Control Bus Timing Diagram
CML Serializer Data Throughput
(200 mV/DIV)
6.11 Typical Characteristics
78 MHz TX
Pixel Clock
Input
(2 V/DIV)
78 MHz RX
Pixel Clock
Output
(2 V/DIV)
Time (1.25 ns/DIV)
Time (10 ns/DIV)
NOTE: On the rising edge of each clock period, the CML driver
outputs a low stop bit, high start bit, and 33 DC-scrambled data
bits.
Figure 10. Serializer CML Driver Output
With 78-MHZ TX Pixel Clock
Figure 11. Comparison of Deserializer LVCMOS RX PCLK
Output Locked to a 78-MHz TX PCLK
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7 Detailed Description
7.1 Overview
The DS90UH926Q-Q1 deserializer receives a 35 bits symbol over a single serial FPD-Link III pair operating up to
a 2.975 Gbps application payload. The serial stream contains an embedded clock, video control signals and the
DC-balanced video data and audio data which enhance signal quality to support AC coupling.
The DS90UH926Q-Q1 deserializer attains lock to a data stream without the use of a separate reference clock
source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the
serializer regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the
incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers
the clock and data by extracting the embedded clock information, validating then deserializing the incoming data
stream. It also applies decryption through a High-Bandwidth Digital Content Protection (HDCP) Cipher to this
video and audio data stream following reception of the data from the FPD-Link III decoder. The decrypted parallel
LVCMOS video bus is provided to the display. The deserializer is intended for use with the DS90UH925Q
serializer, but is also backward-compatible with DS90UR905Q or DS90UR907Q FPD-Link II serializer.
7.2 Functional Block Diagram
REGULATOR
SSCG
CMF
24
RGB [7:0]
HS
VS
DE
I2S_CLK
I2S_WC
I2S_DA
MCLK
RIN+
RIN4
CMLOUTP
CMLOUTN
BISTEN
BISTC
PDB
SCL
SCA
IDx
MODE_SEL
Error
Detector
Timing and
Control
PASS
Clock and
Data
Recovery
PCLK
LOCK
7.3 Feature Description
7.3.1 High-Speed Forward Channel Data Transfer
The high-speed forward channel (HS_FC) is composed of 35 bits of data containing RGB data, sync signals,
HDCP, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 12 illustrates the serial stream per
PCLK cycle. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized,
balanced and scrambled.
C1
C0
Figure 12. FPD-Link III Serial Stream
16
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Feature Description (continued)
The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975-Gbps
maximum (175 Mbps minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps minimum.
7.3.2 Low-Speed Back Channel Data Transfer
The low-speed backward channel (LS_BC) of the DS90UH926Q-Q1 provides bidirectional communication
between the display and host processor. The information is carried back from the Deserializer to the Serializer
per serial symbol. The back channel control data is transferred over the single serial link along with the highspeed forward data, DC balance coding, and embedded clock information. This architecture provides a backward
path across the serial link together with a high-speed forward channel. The back channel contains the I2C,
HDCP, CRC and 4 bits of standard GPIO information with 10-Mbps line rate.
7.3.3 Backward Compatible Mode
The DS90UH926Q-Q1 is also backward-compatible to DS90UR905Q and DS90UR907Q FPD Link II serializers
with 15- to 65-MHz pixel clock frequencies supported. It receives 28 bits of data over a single serial FPD-Link II
pair operating at the line rate of 420 Mbps to 1.82 Gbps. This backward-compatible mode is provided through the
MODE_SEL pin (Table 9) or the configuration register (Table 11). When backward-compatible mode = ON, set
LFMODE = 0.
7.3.4 Input Equalization Gain
FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces the
medium-induced deterministic jitter. It equalizes up to 10 meter STP cables with 3 connection breaks at
maximum serialized stream payload rate of 2.975 Gbps.
7.3.5 Common-Mode Filter Pin (CMF)
The deserializer provides access to the center tap of the internal termination. A capacitor must be placed on this
pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1-μF capacitor has to be connected to this pin to Ground.
7.3.6 Video Control Signal Filter
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, the transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, no restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low-frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high-frequency
noise on the control signals. See Figure 13.
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Feature Description (continued)
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
HS/VS/DE
OUT
Pulses 1 or 2
PCLKs wide
Filetered OUT
Figure 13. Video Control Signal Filter Waveform
7.3.7 EMI Reduction Features
7.3.7.1 Spread Spectrum Clock Generation (SSCG)
The DS90UH926Q-Q1 provides an internally-generated spread spectrum clock (SSCG) to modulate its outputs.
Both clock and data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.5%
(5% total) at up to 100-kHz modulations are available. This feature may be controlled by register. See Table 1,
Table 2 and Table 11. Do not enable the SSCG feature if the source PCLK into the SER has a clock with spread
spectrum already.
Frequency
fdev(max)
FPCLK+
FPCLK
FPCLK-
fdev(min)
Time
1/fmod
Figure 14. SSCG Waveform
Table 1. SSCG Configuration
LFMODE = L (15 to 85 MHz)
SSCG CONFIGURATION (0x2C) LFMODE = L (15 to 85 MHz)
18
SSC[2]
SSC[1]
L
L
SPREAD SPECTRUM OUTPUT
SSC[0]
Fdev (%)
Fmod (kHz)
L
L
±0.9
PCLK / 2168
L
H
±1.2
L
H
L
±1.9
L
H
H
±2.5
H
L
L
±0.7
H
L
H
±1.3
H
H
L
±2.0
H
H
H
±2.5
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Table 2. SSCG Configuration
LFMODE = H (5 to < 15 MHz)
SSCG CONFIGURATION (0x2C) LFMODE = H (5 to <15 MHz)
SPREAD SPECTRUM OUTPUT
SSC[2]
SSC[1]
SSC[0]
Fdev (%)
Fmod (kHz)
L
L
L
±0.5
PCLK / 628
L
L
H
±1.3
L
H
L
±1.8
L
H
H
±2.5
H
L
L
±0.7
H
L
H
±1.2
H
H
L
±2
H
H
H
±2.5
PCLK / 388
7.3.8 Enhanced Progressive Turnon (EPTO)
The deserializer LVCMOS parallel outputs timing are delayed. Groups of 8-bit R, G and B outputs switch in a
different time. This minimizes the number of outputs switching simultaneously and helps to reduce supply noise.
In addition it spreads the noise spectrum out reducing overall EMI.
7.3.9 LVCMOS VDDIO Option
The deserializer parallel bus can operate with 1.8 V or 3.3 V levels (VDDIO) for target (Display) compatibility.
The 1.8 V levels will offer a lower noise (EMI) and also a system power savings.
7.3.10 Power Down (PDB)
The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the
host or through the VDDIO, where VDDIO = 3 to 3.6 V or VDD33. To save power disable the link when the display is
not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after VDD33 and VDDIO have
reached final levels; no external components are required. In the case of driven by the VDDIO = 3 to 3.6 V or
VDD33 directly, a 10 kΩ resistor to the VDDIO = 3 to 3.6 V or VDD33 , and a > 10 µF capacitor to the ground are
required (See Figure 24).
7.3.11 Stop Stream Sleep
The deserializer enters a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer will
then lock to the incoming signal and recover the data.
NOTE
In STOP STREAM SLEEP, the Serial Control Bus Registers values are retained.
7.3.12 Serial Link Fault Detect
The serial link fault detection is able to detect any of following 7 conditions
1. cable open
2. + to - short
3. + short to GND
4. - short to GND
5. + short to battery
6. - short to battery
7. Cable is linked incorrectly
If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on the Serial Control
Bus Register bit 0 of address 0x1C Table 11. The link errors can be monitored though Link Error Count of the
Serial Control Bus Register bit [4:0] of address 0x41 Table 11.
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7.3.13 Oscillator Output
The deserializer provides an optional PCLK output when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature is controlled by
register Address 0x02, bit 5 (OSC Clock Enable). See Table 11.
7.3.14 Pixel Clock Edge Select (RFB)
The RFB determines the edge that the data is strobed on. If RFB is High (‘1’), output data is strobed on the
Rising edge of the PCLK. If RFB is Low (‘0’), data is strobed on the Falling edge of the PCLK. This allows for
inter-operability with downstream devices. The deserializer output does not need to use the same edge as the
Ser input. This feature may be controlled by register. See Table 11.
7.3.15 Built In Self Test (BIST)
An optional At-Speed, Built-In Self Test (BIST) feature supports the testing of the high speed serial link and the
low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for
system diagnostics. The BIST is not available in backwards-compatible mode.
7.3.15.1 BIST Configuration and Status
The BIST mode is enabled at the deserializer by the Pin select (Pin 44 BISTEN and Pin 16 BISTC) or
configuration register (Table 11) through the deserializer. When LFMODE = 0, the pin based configuration
defaults to external PCLK or 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user
can select the desired OSC frequency (default 33 MHz or 25 MHz) through the register bit. When LFMODE = 1,
the pin based configuration defaults to external PCLK or 12.5 MHz MHz internal Oscillator clock (OSC)
frequency.
When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the
Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1- to
35-bit errors.
The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset
(new BIST test or Power Down). A High on PASS indicates NO ERRORS were detected. A Low on PASS
indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to
the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the
connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the
deserializer is locked or unlocked, the lock status can be read in the register. See Table 11.
7.3.15.1.1 Sample BIST Sequence
See Figure 15 for the BIST mode flow diagram.
1. For the DS90UH925Q-Q1 and DS90UH926Q-Q1 FPD-Link III chipset, BIST Mode is enabled through the
BISTEN pin of DS90UH926Q-Q1 FPD-Link III deserializer. The desired clock source is selected through
BISTC pin.
2. The DS90UH925Q-Q1 serializer is woken up through the back channel if it is not already on. The all zero
pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the
deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high
and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will
switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and
counted to determine the payload error rate.
3. To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the data.
The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there
was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new
BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of
the BISTEN signal.
4. The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 16 shows the waveform
diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors.
In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission
etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect, reducing
20
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signal condition enhancements ( Rx Equalization).
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal Mode check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 15. BIST Mode Flow Diagram
7.3.15.2 Forward-Channel and Back-Channel Error Checking
While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero
pattern. The internal all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to
the deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with allzeroes and records any errors in status registers and dynamically indicates the status on PASS pin. The
deserializer then outputs a SSO pattern on the RGB output pins.
The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as
indicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The
register is cleared when the serializer enters the BIST mode. As soon as the serializer exits BIST mode, the
functional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active in
BIST mode only and keeps the record of last BIST run until it clears or enters BIST mode again.
DES Outputs
BISTEN
(DES)
Case 1 - Pass
PCLK
(RFB = L)
ROUT[23:0]
HS, VS, DE
DATA
(internal)
PASS
Prior Result
PASS
PASS
X
X
X
FAIL
Prior Result
Normal
SSO
Case 2 - Fail
X = bit error(s)
DATA
(internal)
BIST Test
BIST Duration
BIST
Result
Held
Normal
Figure 16. BIST Waveforms
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7.3.16 Image Enhancement Features
Several image enhancement features are provided. White balance LUTs allow the user to define and target the
color temperature of the display. Adaptive Hi-FRC dithering enables the presentation of “true-color” images on an
18–bit color display.
7.3.16.1 White Balance
The White Balance feature enables similar display appearance when using LCDs from different vendors. It
compensates for native color temperature of the display, and adjusts relative intensities of R, G, B to maintain
specified color temperature. Programmable control registers are used to define the contents of three LUTs (8-bit
color value for Red, Green and Blue) for the white balance feature. The LUTs map input RGB values to new
output RGB values. There are three LUTs, one LUT for each color. Each LUT contains 256 entries, 8 bits per
entry with a total size of 6144 bits (3 x 256 x 8). All entries are readable and writable. Calibrated values are
loaded into registers through the I2C interface (deserializer is a slave device). This feature may also be applied
to lower color depth applications such as 18–bit (666) and 16–bit (565). White balance is enabled and configured
through that serial control bus register.
7.3.16.1.1 LUT Contents
The user must define and load the contents of the LUT for each color (R,G,B). Regardless of the color depth
being driven (888, 666, 656), the user must always provide contents for 3 complete LUTs - 256 colors x 8 bits x 3
tables. Unused bits - LSBs -shall be set to 0 by the user.
When 24-bit (888) input data is being driven to a 24-bit display, each LUT (R, G and B) must contain 256 unique
8-bit entries. The 8-bit white balanced data is then available at the output of the DS90UH926Q-Q1 deserializer,
and driven to the display.
When 18-bit (666) input data is being driven to an 18-bit display, the white balance feature may be used in one of
two ways. First, simply load each LUT with 256, 8-bit entries. Each 8-bit entry is a 6-bit value (6 MSBs) with the 2
LSBs set to 00. Thus as total of 64 unique 6-bit white balance output values are available for each color (R, G
and B). The 6-bit white balanced data is available at the output of the DS90UH926Q-Q1 deserializer, and driven
directly to the display.
Alternatively, with 6-bit input data the user may choose to load complete 8-bit values into each LUT. This mode
of operation provides the user with finer resolution at the LUT output to more closely achieve the desired white
point of the calibrated display. Although 8-bit data is loaded, only 64 unique 8-bit white balance output values are
available for each color (R, G and B). The result is 8-bit white balanced data. Before driving to the output of the
deserializer, the 8-bit data must be reduced to 6-bit with an FRC dithering function. To operate in this mode, the
user must configure the DS90UH926Q-Q1 to enable the FRC2 function.
Examples of the three types of LUT configurations described are shown in Figure 17
7.3.16.1.2 Enabling White Balance
The user must load all 3 LUTs prior to enabling the white balance feature. The following sequence must be
followed by the user.
To initialize white balance after power-on (Table 3):
1. Load contents of all 3 LUTs . This requires a sequential loading of LUTs - first RED, second GREEN, third
BLUE. 256, 8-bit entries must be loaded to each LUT. Page registers must be set to select each LUT.
2. Enable white balance.
By default, the LUT data may not be reloaded after initialization at power-on.
An option does exist to allow LUT reloading after power-on and initial LUT loading (as described above). This
option may only be used after enabling the white balance reload feature through the associated serial control bus
register. In this mode the LUTs may be reloaded by the master controller through the I2C. This provides the user
with the flexibility to refresh LUTs periodically , or upon system requirements to change to a new set of LUT
values. The host controller loads the updated LUT values through the serial bus interface. There is no need to
disable the white balance feature while reloading the LUT data. Refreshing the white balance to the new set of
LUT data will be seamless - no interruption of displayed data.
It is important to note that initial loading of LUT values requires that all three LUTs be loaded sequentially. When
reloading, partial LUT updates may be made.
22
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8-bit in / 8 bit out
Gray level
Entry
Data Out
(8-bits)
248
249
250
251
252
253
254
255
11111000b
N/A
N/A
N/A
11111100b
N/A
N/A
N/A
«
«
00000000b
N/A
N/A
N/A
00000100b
N/A
N/A
N/A
00001000b
N/A
N/A
N/A
0
1
2
3
4
5
6
7
8
9
10
11
00000001b
N/A
N/A
N/A
00000110b
N/A
N/A
N/A
00001011b
N/A
N/A
N/A
248
249
250
251
252
253
254
255
11111010b
N/A
N/A
N/A
11111111b
N/A
N/A
N/A
«
11111010b
11111010b
11111011b
11111011b
11111110b
11111101b
11111101b
11111111b
0
1
2
3
4
5
6
7
8
9
10
11
Data Out
(8-bits)
«
248
249
250
251
252
253
254
255
Data Out
(8-bits)
«
00000000b
00000001b
00000011b
00000011b
00000110b
00000110b
00000111b
00000111b
00001000b
00001010b
00001001b
00001011b
6-bit in / 8 bit out
Gray level
Entry
«
0
1
2
3
4
5
6
7
8
9
10
11
6-bit in / 6 bit out
Gray level
Entry
Figure 17. White Balance LUT Configurations
Table 3. White Balance Register Table
PAGE
0
ADD
(dec)
42
ADD
(hex)
0x2A
REGISTER NAME BITS ACCESS
White Balance
Control
7:6
RW
5
RW
4
RW
DEFAU
LT
(hex)
FUNCTION
Page Setting
0x00
White Balance
Enable
DESCRIPTION
00: Configuration Registers
01: Red LUT
10: Green LUT
11: Blue LUT
0: White Balance Disable
1: White Balance Enable
0: Reload Disable
1: Reload Enable
3:0
Reserved
1
0–
255
00 – FF
White Balance Red
LUT
FF:0
RW
N/A
Red LUT
2
0–
255
00 – FF
White Balance
Green LUT
FF:0
RW
N/A
Green LUT
3
0–
255
00 – FF
White Balance
Blue LUT
FF:0
RW
N/A
Blue LUT
256 8–bit entries to be applied to the Red
subpixel data
256 8–bit entries to be applied to the Green
subpixel data
256 8–bit entries to be applied to the Blue
subpixel data
7.3.16.2 Adaptive HI-FRC Dithering
The Adaptive FRC Dithering Feature delivers product-differentiating image quality. It reduces 24-bit RGB (8 bits
per subpixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color gradients, and allowing the flexibility to use
lower cost 18-bit displays. FRC (Frame Rate Control) dithering is a method to emulate “missing” colors on a
lower color depth LCD display by changing the pixel color slightly with every frame. FRC is achieved by
controlling on and off pixels over multiple frames (Temporal). Static dithering regulates the number of on and off
pixels in a small defined pixel group (Spatial). The FRC module includes both Temporal and Spatial methods and
also Hi-FRC. Conventional FRC can display only 16,194,277 colors with 6-bit RGB source. “Hi-FRC” enables full
(16,777,216) color on an 18-bit LCD panel. The “adaptive” FRC module also includes input pixel detection to
apply specific Spatial dithering methods for smoother gray level transitions. When enabled, the lower LSBs of
each RGB output are not active; only 18 bit data (6 bits per R,G and B) are driven to the display. This feature is
enabled through the serial control bus register.
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Two FRC functional blocks are available, and may be independently enabled. FRC1 precedes the white balance
LUT, and is intended to be used when 24-bit data is being driven to an 18-bit display with a white balance LUT
that is calibrated for an 18-bit data source. The second FRC block, FRC2, follows the white balance block and is
intended to be used when fine adjustment of color temperature is required on an 18-bit color display, or when a
24-bit source drives an 18-bit display with a white balance LUT calibrated for 24-bit source data.
For proper operation of the FRC dithering feature, the user must provide a description of the display timing
control signals. The timing mode, “sync mode” (HS, VS) or “DE only” must be specified, along with the active
polarity of the timing control signals. All this information is entered to DS90UH926Q-Q1 control registers through
the serial bus interface.
Adaptive Hi-FRC dithering consists of several components. Initially, the incoming 8-bit data is expanded to 9-bit
data. This allows the effective dithered result to support a total of 16.7 million colors. The incoming 9-bit data is
evaluated, and one of four possible algorithms is selected. The majority of incoming data sequences are
supported by the default dithering algorithm. Certain incoming data patterns (black/white pixel, full on/off subpixel) require special algorithms designed to eliminate visual artifacts associated with these specific gray level
transitions. Three algorithms are defined to support these critical transitions.
An example of the default dithering algorithm is illustrated in Figure 18. The 1 or 0 value shown in the table
describes whether the 6-bit value is increased by 1 (1) or left unchanged (0). In this case, the 3 truncated LSBs
are 001.
Frame = 0, Line = 0
F0L0
Pixel Index
PD1
Pixel Data one
Cell Value 010
R[7:2]+0, G[7:2]+1, B[7:2]+0
LSB=001
three lsb of 9 bit data (8 to 9 for Hi-Frc)
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
F0L0
010
000
000
000
000
000
010
000
F0L1
101
000
000
000
101
000
000
000
R = 4/32
F0L2
000
000
010
000
010
000
000
000
G = 4/32
F0L3
000
000
101
000
000
000
101
000
B = 4/32
F1L0
000
000
000
000
000
000
000
000
F1L1
000
111
000
000
000
111
000
000
R = 4/32
F1L2
000
000
000
000
000
000
000
000
G = 4/32
F1L3
000
000
000
111
000
000
000
111
B = 4/32
F2L0
000
000
010
000
010
000
000
000
F2L1
000
000
101
000
000
000
101
000
R = 4/32
F2L2
010
000
000
000
000
000
010
000
G = 4/32
F2L3
101
000
000
000
101
000
000
000
B = 4/32
F3L0
000
000
000
000
000
000
000
000
F3L1
000
000
000
111
000
000
000
111
R = 4/32
F3L2
000
000
000
000
000
000
000
000
G = 4/32
F3L3
000
111
000
000
000
111
000
000
B = 4/32
LSB=001
LSB = 001
Figure 18. Default FRC Algorithm
24
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Table 4. Recommended FRC Settings
SOURCE
WHITE BALANCE LUT
DISPLAY
FRC1
FRC2
24–bit
24–bit
24–bit
Disabled
Disabled
24–bit
24–bit
18–bit
Disabled
Enabled
24–bit
18–bit
18–bit
Enabled
Disabled
18–bit
24–bit
24–bit
Disabled
Disabled
18–bit
24–bit
18–bit
Disabled
Enabled
18–bit
18–bit
18–bit
Disabled
Disabled
7.3.17 Internal Pattern Generation
The DS90UH926Q-Q1 serializer supports the internal pattern generation feature. It allows basic testing and
debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual
verification of panel operation. As long as the device is not in power down mode, the test pattern will be
displayed even if no parallel input is applied. If no PCLK is received, the test pattern can be configured to use a
programmed oscillator frequency. For detailed information, refer to AN-2198 Exploring the Internal Test Pattern
Generation Feature of 720p FPD-Link III Devices (SNLA132).
7.3.18 I2S Receiving
In normal 24-bit RGB operation mode, the DS90UH926Q-Q1 provides up to 3-bit of I2S. They are I2S_CLK,
I2S_WC and I2S_DA, as well as the Master I2S Clock (MCLK). The audio is received through the forward video
frame, or can be configured to receive during video blanking periods. A jitter cleaning feature reduces I2S_CLK
output jitter to +/- 2ns. The encrypted and packetized audio information is received during the video blanking
periods along with specific information about the clock frequency. The bit rates of any I2S input bits must
maintain one fourth of the PCLK rate. The audio decryption is supported per HDCP v1.3.
7.3.18.1 I2S Jitter Cleaning
In 18-bit RGB operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio
channel in additional to the 3–bit of I2S. The I2S_DB is synchronized to the I2S_CLK. To enable this
synchronization feature on this bit, set the MODE_SEL (Table 9) or program through the register bit ()
7.3.18.2 Secondary I2S Channel
In 18-bit RGB operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio
channel in additional to the 3–bit of I2S. The I2S_DB is synchronized to the I2S_CLK. To enable this
synchronization feature on this bit, set the MODE_SEL (Table 9) or program through the register bit (Table 11).
7.3.18.2.1 MCLK
The deserializer has an I2S Master Clock Output. It supports x1, x2, or x4 of I2S CLK Frequency. When the I2S
PLL is disabled, the MCLK output is off. Table 5 below covers the range of I2S sample rates and MCLK
frequencies. By default, all the MCLK output frequencies are x2 of the I2S CLK frequencies. The MCLK
frequencies can also be enabled through the register bit [7:4] (I2S MCLK Output) of 0x3A shown in Table 11. To
select desired MCLK frequency, write bit 7 (0x3A) = 1, then write to bit [6:4] accordingly.
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Table 5. Audio Interface Frequencies
SAMPLE RATE
(kHz)
I2S DATA WORD SIZE
(BITS)
32
1.024
44.1
48
1.4112
16
96
6.144
32
1.536
44.1
2.117
24
96
9.216
32
2.048
44.1
2.8224
32
96
192
26
2.304
4.608
192
48
1.536
3.072
192
48
I2S CLK
(MHz)
3.072
6.144
12.288
MCLK OUTPUT
(MHz)
REGISTER 0x3A[6:4]'b
I2S_CLK x1
000
I2S_CLK x2
001
I2S_CLK x4
010
I2S_CLK x1
000
I2S_CLK x2
001
I2S_CLK x4
010
I2S_CLK x1
000
I2S_CLK x2
001
I2S_CLK x4
010
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
010
I2S_CLK x2
011
I2S_CLK x4
100
I2S_CLK x1
000
I2S_CLK x2
001
I2S_CLK x4
010
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
010
I2S_CLK x2
011
I2S_CLK x4
100
I2S_CLK x1
011
I2S_CLK x2
100
I2S_CLK x4
101
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
010
I2S_CLK x2
011
I2S_CLK x4
100
I2S_CLK x1
011
I2S_CLK x2
100
I2S_CLK x4
110
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7.3.19 Interrupt Pin: Functional Description and Usage (INTB)
1. On DS90UH925Q-Q1, set register 0xC6[5] = 1 and 0xC6[0] = 1
2. DS90UH926Q-Q1 deserializer INTB_IN (pin 16) is set LOW by some downstream device.
3. DS90UH925Q-Q1 serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an
interrupt condition.
4. External controller detects INTB = LOW; to determine interrupt source, read HDCP_ISR register .
5. A read to HDCP_ISR will clear the interrupt at the DS90UH925, releasing INTB.
6. The external controller typically must then access the remote device to determine downstream interrupt
source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the
INTB_IN (pin 16) on the DS90UH926Q-Q1. The system is now ready to return to step (1) at next falling edge
of INTB_IN.
7.3.20 GPIO[3:0] and GPO_REG[8:4]
In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UH926Q-Q1 can be used as the
general purpose IOs GPIO[3:0] in either forward channel (Outputs) or back channel (Inputs) application.
7.3.20.1 GPIO[3:0] Enable Sequence
See Table 6 for the GPIO enable sequencing.
1. Enable the 18-bit mode either through the configuration register bit Table 11 on DS90UH925Q-Q1 only.
DS90UH926Q-Q1 is automatically configured as in the 18-bit mode.
2. To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UH925Q-Q1, then write 0x05 to
address 0x1F on DS90UH926Q-Q1.
Table 6. GPIO Enable Sequencing Table
NO.
DESCRIPTION
DEVICE
FORWARD CHANNEL
BACK CHANNEL
1
Enable 18-bit mode
DS90UH925Q-Q1
0x12 = 0x04
0x12 = 0x04
DS90UH926Q-Q1
Auto Load from DS90UH925Q-Q1
Auto Load from DS90UH925Q-Q1
2
GPIO3
DS90UH925Q-Q1
0x0F = 0x03
0x0F = 0x05
DS90UH926Q-Q1
0x1F = 0x05
0x1F = 0x03
DS90UH925Q-Q1
0x0E = 0x30
0x0E = 0x50
DS90UH926Q-Q1
0x1E = 0x50
0x1E = 0x30
DS90UH925Q-Q1
0x0E = 0x03
0x0E = 0x05
3
GPIO2
4
GPIO1
5
GPIO0
DS90UH926Q-Q1
0x1E = 0x05
0x0E = 0x05
DS90UH925Q-Q1
0x0D = 0x93
0x0D = 0x95
DS90UH926Q-Q1
0x1D = 0x95
0x1D = 0x93
7.3.20.2 GPO_REG[8:4] Enable Sequence
GPO_REG[8:4] are the outputs only pins. They must be programmed through the local register bits. See
Table 11 for the GPO_REG enable sequencing.
1. Enable the 18-bit mode either through the configuration register bit Table 11 on DS90UH925Q-Q1 only.
DS90UH926Q-Q1 is automatically configured as in the 18-bit mode.
2. To enable GPO_REG8 outputs a 1, write 0x90 to address 0x11 on DS90UH925Q.
Table 7. GPO_REG Enable Sequencing Table
NO.
DESCRIPTION
DEVICE
LOCAL ACCESS
1
Enable 18-bit mode
DS90UH926Q-Q1
0x12 = 0x04
(on DS90UH925Q-Q1)
2
GPO_REG8
DS90UH926Q-Q1
0x21 = 0x90
1
0x21 = 0x10
0
0x21 = 0x09
1
0x21 = 0x01
0
3
GPO_REG7
DS90UH926Q-Q1
LOCAL OUTPUT VALUE
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Table 7. GPO_REG Enable Sequencing Table (continued)
NO.
DESCRIPTION
DEVICE
LOCAL ACCESS
LOCAL OUTPUT VALUE
4
GPO_REG6
DS90UH926Q-Q1
0x20 = 0x90
1
0x20 = 0x10
0
5
GPO_REG5
DS90UH926Q-Q1
0x20 = 0x09
1
0x20 = 0x01
0
0x1F = 0x90
1
0x1F = 0x10
0
6
GPO_REG4
DS90UH926Q-Q1
7.4 Device Functional Modes
7.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN), and Output State Select
(OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is TRI-STATE or LOW
(depending on the value of the OEN setting). After the DS90UH926Q-Q1 completes its lock sequence to the
input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input
is available on the parallel bus and PCLK outputs. The State of the outputs are based on the OEN and
OSS_SEL setting (Table 8) or register bit (Table 11). See Figure 7.
Table 8. Output States
INPUTS
OUTPUTS
Serial
input
PDB
OEN
OSS_SEL
X
0
X
X
1
0
X
1
0
Lock
Pass
Data, GPIO, I2S
CLK
X
Z
Z
Z
Z
0
L or H
L
L
L
1
L or H
Z
Z
Z
Static
1
1
0
L
L
L
L/OSC (Register bit
enable)
Static
1
1
1
L
Previous Status
L
L
Active
1
1
0
H
L
L
L
Active
1
1
1
H
Valid
Valid
Valid
7.4.2 Low Frequency Optimization (LFMODE)
The LFMODE is set through a register (Table 11) or MODE_SEL Pin 24 (Table 9). It controls the operating
frequency of the deserializer. If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz.
If LFMODE is High, the PCLK frequency is between 5 MHz and <15 MHz. Please note: when the device
LFMODE is changed, a PDB reset is required.
7.4.3 Configuration Select (MODE_SEL)
Configuration of the device may be done through the MODE_SEL input pin, or through the configuration register
bit. A pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of the
MODE_SEL input (VR4) and VDD33 to select one of the other 10 possible selected modes. See Figure 19 and
Table 9.
VDD33
R3
MODE_SEL
VR4
R4
DES
Figure 19. MODE_SEL Connection Diagram
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Table 9. Configuration Select (MODE_SEL)
NO.
(1)
(2)
(3)
(4)
IDEAL
RATIO
VR4/VDD33
IDEAL VR4
(V)
SUGGESTED SUGGESTED
RESISTOR R3 RESISTOR R4 LFMODE (1)
kΩ (1% tol)
kΩ (1% tol)
REPEATER (2)
BACKWARD
COMPATIBLE (3)
I2S CHANNEL B
(18–bit MODE) (4)
1
0
0
Open
40.2
L
L
L
L
2
0.123
0.407
115
16.2
L
L
L
H
3
0.167
0.552
121
24.3
L
H
L
L
4
0.227
0.748
162
47.5
L
H
L
H
5
0.291
0.960
137
56.2
H
L
L
L
6
0.366
1.209
107
61.9
H
L
L
H
7
0.458
1.510
113
95.3
H
H
L
L
8
0.542
1.790
95.3
113
H
H
L
H
9
0.611
2.016
73.2
115
L
L
H
L
LFMODE:
L = frequency range is 15 MHz to 85 MHz (Default)
H = frequency range is 5 to < 15 MHz
Repeater:
L = Repeater mode is OFF (Default)
H = Repeater mode is ON
Backward Compatible:
L = Backward Compatible mode is OFF (Default)
H = Backward Compatible mode is ON; SER = DS90UR905Q or DS90UR907Q
– frequency range = 15 to 65 MHz, set LFMODE = L
I2S Channel B:
L = I2S Channel B mode is OFF, normal 24-bit RGB Mode (Default)
H = I2S Channel B mode is ON, 18-bit RGB Mode with I2S_DB Enabled. Note: use of GPIO(s) on unused inputs must be enabled by
register.
7.4.4 HDCP Repeater
When DS90UH925Q-Q1 and DS90UH926Q-Q1 are configured as the HDCP Repeater application, it provides a
mechanism to extend HDCP transmission over multiple links to multiple display devices. This repeater
application provides a mechanism to authenticate all HDCP Receivers in the system and distribute protected
content to the HDCP Receivers using the encryption mechanisms provided in the HDCP specification.
In this document, the DS90UH925Q-Q1 is referred to as the HDCP Transmitter or transmit port (TX), and the
DS90UH926Q-Q1 is referred to as the HDCP Receiver (RX). Figure 20 shows the maximum configuration
supported for HDCP Repeater implementations using the DS90UH925Q-Q1 (TX) and DS90UH926Q-Q1 (RX).
Two levels of HDCP Repeaters are supported with a maximum of three HDCP Transmitters per HDCP Receiver.
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1:3 Repeater
1:3 Repeater
TX
Source
TX
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
RX
RX
TX
TX
1:3 Repeater
RX
1:3 Repeater
RX
Figure 20. HDCP Maximum Repeater Application
To support HDCP Repeater operation, the DS90UH926Q-Q1 Deserializer includes the ability to control the
downstream authentication process, assemble the KSV list for downstream HDCP Receivers, and pass the KSV
list to the upstream HDCP Transmitter. An I2C master within the DS90UH926Q-Q1 communicates with the I2C
slave within the DS90UH925Q-Q1 Serializer. The DS90UH925Q-Q1 Serializer handles authenticating with a
downstream HDCP Receiver and makes status available through the I2C interface. The DS90UH926Q-Q1
monitors the transmit port status for each DS90UH925Q-Q1 and reads downstream KSV and KSV list values
from the DS90UH925Q-Q1.
In addition to the I2C interface used to control the authentication process, the HDCP Repeater implementation
includes two other interfaces. A parallel LVCMOS interface provides the unencrypted video data in 24-bit RGB
format and includes the DE/VS/HS control signals. In addition to providing the RGB video data, the parallel
LVCMOS interface communicates control information and packetized audio data during video blanking intervals.
A separate I2S audio interface may optionally be used to send I2S audio data between the HDCP Receiver and
HDCP Transmitter in place of using the packetized audio over the parallel LVCMOS interface. All audio and
video data is decrypted at the output of the HDCP Receiver and is re-encrypted by the HDCP Transmitter.
Figure 21 provides more detailed block diagram of a 1:2 HDCP repeater configuration.
30
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HDCP Transmitter
DS90UH925Q-Q1
I2C
Master
upstream
Transmitter
downstream
Receiver
or
Repeater
I2C
Slave
I2C
Parallel
LVCMOS
HDCP Receiver
DS90UH926Q-Q1
HDCP Transmitter
DS90UH925Q-Q1
I2S Audio
downstream
Receiver
or
Repeater
I2C
Slave
FPD-Link III interfaces
Figure 21. HDCP 1:2 Repeater Configuration
7.4.4.1 Repeater Connections
The HDCP Repeater requires the following connections between the HDCP Receiver and each HDCP
Transmitter Figure 22.
1. Video Data – Connect PCLK, RGB and control signals (DE, VS, HS).
2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to VDD33 with 4.7-kΩ resistors
3. Audio – Connect I2S_CLK, I2S_WC, and I2S_DA signals.
4. IDx pin – Each HDCP Transmitter and Receiver must have an unique I2C address.
5. MODE_SEL pin – All HDCP Transmitter and Receiver must be set into the Repeater Mode.
6. Interrupt pin– Connect DS90UH926Q-Q1 INTB_IN pin to DS90UH925Q-Q1 INTB pin. The signal must be
pulled up to VDDIO.
DS90UH925Q-Q1
DS90UH926Q-Q1
VDD33
R[7:0]
R[7:0]
G[7:0]
G[7:0]
B[7:0]
B[7:0]
DE
DE
VS
VS
HS
HS
I2S_CLK
I2S_CLK
I2S_WC
I2S_WC
I2S_DA
I2S_DA
Optional
MODE_SEL
VDD33
MODE_SEL
VDDIO
INTB_IN
INTB
VDD33
VDD33
ID[x]
VDD33
SDA
SDA
SCL
SCL
ID[x]
Figure 22. HDCP Repeater Connection Diagram
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7.5 Programming
7.5.1 Serial Control Bus
The DS90UH926Q-Q1 is configured by the use of a serial control bus that is I2C protocol compatible. . Multiple
deserializer devices may share the serial control bus since 16 device addresses are supported. Device address
is set through the R1 and R2 values on IDx pin. See Figure 23.
The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input /
Output. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external
pull-up resistor to VDD33. For most applications a 4.7 kΩ pull-up resistor to VDD33 may be used. The resistor value
may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven
Low.
VDD33
R1
VDD33
IDx
VR2
HOST
or
Salve
4.7k
4.7k
R2
SCL
SCL
SDA
SDA
SER
or
DES
To other
Devices
Figure 23. Serial Control Bus Connection
The configuration pin is the IDx pin. This pin sets one of 16 possible device addresses. A pull-up resistor and a
pull-down resistor of suggested values may be used to set the voltage ratio of the IDx input (VR2) and VDD33 to
select one of the other 16 possible addresses. See Table 10
Table 10. Serial Control Bus Addresses for IDx
NO.
IDEAL RATIO
VR2 / VDD33
IDEAL VR2
(V)
SUGGESTED
RESISTOR R1 kΩ
(1% tol)
SUGGESTED
RESISTOR R2 kΩ
(1% tol)
ADDRESS 7'b
ADDRESS 8'b
APPENDED
1
0
0
Open
40.2
0x2C
0x58
2
0.123
0.406
124
17.4
0x2D
0x5A
3
0.151
0.500
107
19.1
0x2E
0x5C
4
0.181
0.597
133
29.4
0x2F
0x5E
5
0.210
0.694
113
30.1
0x30
0x60
6
0.240
0.791
137
43.2
0x31
0x62
7
0.268
0.885
102
37.4
0x32
0x64
8
0.303
0.999
115
49.9
0x33
0x66
9
0.344
1.137
102
53.6
0x34
0x68
10
0.389
1.284
115
73.2
0x35
0x6A
11
0.430
1.418
115
86.6
0x36
0x6C
12
0.476
1.572
56.2
51.1
0x37
0x6E
13
0.523
1.725
93.1
102
0x38
0x70
14
0.565
1.863
82.5
107
0x39
0x72
15
0.611
2.016
73.2
115
0x3A
0x74
16
0.677
2.236
57.6
121
0x3B
0x76
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7.6 Register Maps
Table 11. Serial Control Bus Registers
ADD
(dec)
ADD
(hex)
Register
Name
0
0x00
I2C Device ID
1
0x01
Reset
Bit(s)
Register
Type
Default Function
(hex)
7:1
RW
Device ID
7–bit address of Deserializer
See Table 9
0
RW
ID Setting
I2C ID Setting
1: Register I2C Device ID (Overrides IDx pin)
0: Device ID is from IDx pin
7
RW
Remote
Auto Power
Down
Remote Auto Power Down
1: Power down when no forward channel link is detected
0: Do not power down when no forward channel link is
detected
0x04
6:3
2
0x02
Configuration
[0]
Descriptions
Reserved.
2
RW
BC Enable
Back channel enable
1: Enable
0: Disable
1
RW
Digital
RESET1
Reset the entire digital block including registers
This bit is self-clearing.
1: Reset
0: Normal operation
0
RW
Digital
RESET0
Reset the entire digital block except registers
This bit is self-clearing
1: Reset
0: Normal operation
7
RW
Output
Enable
LVCMOS Output Enable.
1: Enable
0: Disable. Tri-state Outputs
6
RW
OEN and
OSS_SEL
Override
Overrides Output Enable Pin and Output State pin
1: Enable override
0: Disable - no override
5
RW
OSC Clock
Enable
OSC Clock Output Enable
If loss of lock OSC clock is output onto PCLK
0: Disable
1: Enable
4
RW
Output
Sleep State
Select
(OSS_SEL)
OSS Select to Control Output State during Lock Low
Period
1: Enable
0: Disable
3
RW
Backward
Compatible
select by
pin or
register
control
Backward Compatible (BC) mode set by MODE_SEL pin
or register.
1: BC is set by register bit. Use register bit reg_0x02[2] to
set BC Mode
0: Use MODE_SEL pin.
2
RW
Backward
Compatible
Mode
Select
Backward compatible (BC) mode to DS90UR905Q or
DS90UR907Q, if reg_0x02[3] = 1
1: Backward compatible with DS90UR905Q or
DS90UR907Q
(Set LFMODE = 0)
0: Backward Compatible is OFF (default)
1
RW
LFMODE
select by
pin or
register
control
Frequency range is set by MODE_SEL pin or register
1: Frequency range is set by register. Use register
bitreg_0x02[0] to set LFMODE
0: Frequency range is set by MODE_SEL pin.
0
RW
LFMODE
Frequency range select
1: PCLK range = 5 to <15 MHz, if reg_0x02[1] = 1
0: PCLK range = 15 to 85 MHz (default)
0x00
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Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
3
0x03
Configuration
[1]
Bit(s)
Register
Type
7
6
Default Function
(hex)
0xF0
Reserved.
RW
CRC
Generator
Enable
4
RW
Filter
Enable
HS, VS, DE two clock filter When enabled, pulses less
than two full PCLK cycles on the DE, HS, and VS inputs
will be rejected
1: Filtering enable
0: Filtering disable
3
RW
I2C Passthrough
I2C Pass-Through Mode
1: Pass-Through Enabled
0: Pass-Through Disabled
2
RW
Auto ACK
ACK Select
1: Auto ACK enable
0: Self ACK
0
RW
RRFB
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
7:1
RW
BCC
Watchdog
Timer
The watchdog timer allows termination of a control channel
transaction, if it fails to complete within a programmed
amount of time. This field sets the Bidirectional Control
Channel Watchdog Timeout value in units of 2
milliseconds.
This field should not be set to 0
0
RW
BCC
Watchdog
Timer
Disable
Disable Bidirectional Control Channel Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation"
7
RW
I2C Pass
Through All
I2C Pass-Through All Transactions
1: Enabled
0: Disabled
6:4
RW
I2C SDA
Hold Time
Internal I2C SDA Hold Time
It configures the amount of internal hold time provided for
the SDA input relative to the SCL input. Units are 50 ns.
3:0
RW
I2C Filter
Depth
I2C Glitch Filter Depth
It configures the maximum width of glitch pulses on the
SCL and SDA inputs that will be rejected. Units are 5 ns.
5
5
34
0x04
0x05
BCC
Watchdog
Control
I2C Control [1]
CRC Generator Enable (Back Channel)
1: Enable
0: Disable
Reserved
1
4
Descriptions
Reserved
0xFE
0x2E
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Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
6
0x06
I2C Control [2]
Bit(s)
Register
Type
7
R
6
RW
Default Function
(hex)
0x00
Forward
Channel
Sequence
Error
Control Channel Sequence Error Detected It indicates a
sequence error has been detected in forward control
channel. It this bit is set, an error may have occurred in the
control channel operation.
Clear
Sequence
Error
It clears the Sequence Error Detect bit
This bit is not self-clearing.
5
7
8
0x07
0x08
Remote
Device ID
SlaveID[0]
Reserved
4:3
RW
SDA Output SDA Output Delay
Delay
This field configures output delay on the SDA output.
Setting this value will increase output delay in units of 50
ns. Nominal output delay values for SCL to SDA are:
00 : 250 ns
01: 300 ns
10: 350 ns
11: 400 ns
2
RW
Local Write
Disable Remote Writes to Local Registers through
Serializer (Does not affect remote access to I2C slaves at
Deserializer)
1: Stop remote write to local device registers
0: remote write to local device registers
1
RW
I2C Bus
Timer
Speed
Speed up I2C Bus Watchdog Timer
1: Timer expires after approximately 50 ms
0: Timer expires after approximately 1 s
0
RW
I2C Bus
Timer
Disable
Disable I2C Bus Timer When the I2C Timer may be used
to detect when the I2C bus is free or hung up following an
invalid termination of a transaction. If SDA is high and no
signalling occurs for approximately 1 s, the I2C bus is
assumed to be free. If SDA is low and no signaling occurs,
the device will try to clear the bus by driving 9 clocks on
SCL
7:1
RW
Remote ID
Remote ID
Configures the I2C Slave ID of the remote Serializer. A
value of 0 in this field disables I2C access to remote
Serializer. This field is automatically configured through the
Serializer Forward Channel. Software may overwrite this
value, but should also set the FREEZE DEVICE ID bit to
prevent overwriting by the Forward Channel.
0
RW
Freeze
Device ID
Freeze Serializer Device ID
1: Prevent auto-loading of the Serializer Device ID from the
Forward Channel. The ID will be frozen at the value
written.
0: Update
7:1
RW
Target
Slave
Device ID0
7-bit Remote Slave Device ID 0
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID0, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
0x18
0x00
0
9
0x09
SlaveID[1]
Descriptions
7:1
Reserved
RW
0
0x00
Target
Slave
Device ID1
7-bit Remote Slave Device ID 1
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID1, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
Reserved
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Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
10
0x0A
SlaveID[2]
Bit(s)
Register
Type
7:1
RW
Default Function
(hex)
0x00
Target
Slave
Device ID2
0
11
0x0B
SlaveID[3]
7:1
0x0C
SlaveID[4]
7:1
RW
0x00
Target
Slave
Device ID3
0x0D
SlaveID[5]
7:1
14
0x0E
SlaveID[6]
7:1
15
0x0F
SlaveID[7]
7:1
16
0x10
SlaveAlias[0]
7:1
RW
0x00
Target
Slave
Device ID4
RW
0x00
Target
Slave
Device ID5
RW
0x00
Target
Slave
Device ID6
RW
0x00
Target
Slave
Device ID7
RW
0x00
ID[0] Match
7-bit Remote Slave Device ID 5
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID5, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
Reserved
0
7-bit Remote Slave Device ID 6
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID6, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
Reserved
0
36
7-bit Remote Slave Device ID 4
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID4, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
Reserved
0
0
7-bit Remote Slave Device ID 3
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID3, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
Reserved
0
13
7-bit Remote Slave Device ID 2
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID2, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
Reserved
0
12
Descriptions
7-bit Remote Slave Device ID 7
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID7, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
Reserved
7-bit Remote Slave Device Alias ID 0
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID0 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
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Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
17
0x11
SlaveAlias[1]
Bit(s)
Register
Type
7:1
RW
Default Function
(hex)
0x00
ID[1] Match
0
18
0x12
SlaveAlias[2]
7:1
0x13
SlaveAlias[3]
7:1
RW
0x00
ID[2] Match
0x14
SlaveAlias[4]
7:1
21
0x15
SlaveAlias[5]
7:1
22
0x16
SlaveAlias[6]
23
0x17
SlaveAlias[7]
7-bit Remote Slave Device Alias ID 2
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID2 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
RW
0x10
ID[3] Match
0
20
7-bit Remote Slave Device Alias ID 1
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID1 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
0
19
Descriptions
7-bit Remote Slave Device Alias ID 3
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID3 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
RW
0x00
ID[4] Match
RW
0x00
ID[5] Match
7:1
RW
0x00
ID[6] Match
0
RW
7:1
RW
0x00
ID[7] Match
0
7-bit Remote Slave Device Alias ID 4
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID4 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
0
7-bit Remote Slave Device Alias ID 5
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID5 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
0
7-bit Remote Slave Device Alias ID 6
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID6 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
7-bit Remote Slave Device Alias ID 7
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID7 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
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Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
28
0x1C
General Status
Bit(s)
Register
Type
Default Function
(hex)
7:4
RW
3
R
I2S Locked
1
R
Signal
Detect
Signal Detect
1: Serial input detected
0: Serial input not detected
0
R
Lock
Deserializer CDR, PLL's clock to recovered clock
frequency
1: Deserializer locked to recovered clock
0: Deserializer not locked
0x00
Reserved
2
29
30
38
0x1D
0x1E
GPIO0 Config
GPIO2 and
GPIO1 Config
Descriptions
I2S Lock Status
0: I2S PLL controller not locked
1: I2S PLL controller locked to input I2S clock
Reserved
7:4
R
Rev-ID
Revision ID: 1010: Production Device
3
RW
0xA0
GPIO0
Output
Value
Local GPIO Output Value
This value is output on the GPIO pin when the GPIO
function is enabled, the local GPIO direction is Output, and
remote GPIO control is disabled.
2
RW
GPIO0
Remote
Enable
Remote GPIO0 Control
1: Enable GPIO control from remote Serializer. The GPIO
pin will be an output, and the value is received from the
remote Deserializer.
0: Disable GPIO control from remote Serializer
1
RW
GPIO0
Direction
Local GPIO Direction
1: Input
0: Output
0
RW
GPIO0
Enable
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
7
RW
GPIO2
Output
Value
Local GPIO Output Value
This value is output on the GPIO when the GPIO function
is enabled, the local GPIO direction is Output, and remote
GPIO control is disabled.
6
RW
GPIO2
Remote
Enable
Remote GPIO2 Control
1: Enable GPIO control from remote Serializer. The GPIO
pin will be an output, and the value is received from the
remote Deserializer.
0: Disable GPIO control from remote Serializer.
5
RW
GPIO2
Direction
Local GPIO Direction
1: Input
0: Output
4
RW
GPIO2
Enable
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
3
RW
GPIO1
Output
Value
Local GPIO Output Value
This value is output on the GPIO when the GPIO function
is enabled, the local GPIO direction is Output, and remote
GPIO control is disabled.
2
RW
GPIO1
Remote
Enable
Remote GPIO1 Control
1: Enable GPIO control from remote Serializer. The GPIO
pin will be an output, and the value is received from the
remote Deserializer.
0: Disable GPIO control from remote Serializer.
1
RW
GPIO1
Direction
Local GPIO Direction
1: Input
0: Output
0
RW
GPIO1
Enable
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
0x00
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Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
31
0x1F
GPO_REG4
and GPO3
Config
Bit(s)
Register
Type
7
RW
Default Function
(hex)
0x00
GPO_REG4 Local GPO_REG4 Output Value
Output
This value is output on the GPO when the GPO function is
Value
enabled, the local GPO direction is Output, and remote
GPO control is disabled.
6:5
32
0x20
GPO_REG6
and
GPO_REG5
Config
Reserved
4
RW
GPO_REG4 GPO_REG4 Function Enable
Enable
1: Enable GPO operation
0: Enable normal operation
3
RW
GPIO3
Output
Value
Local GPIO Output Value This value is output on the GPIO
when the GPIO function is enabled, the local GPIO
direction is Output, and remote GPIO control is disabled.
2
RW
GPIO3
Remote
Enable
Remote GPIO3 Control
1: Enable GPIO control from remote Serializer. The GPIO
pin will be an output, and the value is received from the
remote Deserializer.
0: Disable GPIO control from remote Serializer.
1
RW
GPIO3
Direction
Local GPIO Direction
1: Input
0: Output
0
RW
GPIO3
Enable
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
7
RW
0x00
6:5
0x21
GPO8 and
GPO7 Config
GPO_REG6 Local GPO_REG6 Output Value
Output
This value is output on the GPO when the GPO function is
Value
enabled, the local GPO direction is Output, and remote
GPO control is disabled.
Reserved
4
RW
GPO_REG6 GPO_REG6 Function Enable
Enable
1: Enable GPO operation
0: Enable normal operation
3
RW
GPO_REG5 Local GPO_REG5 Output Value
Output
This value is output on the GPO when the GPO function is
Value
enabled, the local GPO direction is Output, and remote
GPO control is disabled.
0
RW
GPO_REG5 GPO_REG5 Function Enable
Enable
1: Enable GPO operation
0: Enable normal operation
7
RW
2:1
33
Descriptions
Reserved
6:5
0x00
GPO_REG8 Local GPO_REG8 Output Value
Output
This value is output on the GPO when the GPO function is
Value
enabled, the local GPO direction is Output, and remote
GPO control is disabled.
Reserved
4
RW
GPO_REG8 GPO_REG8 Function Enable
Enable
1: Enable GPO operation
0: Enable normal operation
3
RW
GPO_REG7 Local GPO_REG7 Output Value
Output
This value is output on the GPO when the GPO function is
Value
enabled, the local GPO direction is Output, and remote
GPO control is disabled.
RW
GPO_REG7 GPO_REG7 Function Enable
Enable
1: Enable GPO operation
0: Enable normal operation
2:1
0
Reserved
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Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
Bit(s)
Register
Type
34
0x22
Data Path
Control
7
RW
6
RW
Pass RGB
Setting this bit causes RGB data to be sent independent of
DE. This allows operation in systems which may not use
DE to frame video data or send other data when DE is
deasserted. Note that setting this bit prevents HDCP
operation and blocks packetized audio. This bit does not
need to be set in DS90UB925 or in Backward Compatible
mode.
1: Pass RGB independent of DE
0: Normal operation
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
5
RW
DE Polarity
This bit indicates the polarity of the DE (Data Enable)
signal.
1: DE is inverted (active low, idle high)
0: DE is positive (active high, idle low)
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
4
RW
I2S_Gen
This bit controls whether the HDCP Receiver outputs
packetized Auxiliary/Audio data on the RGB video output
pins.
1: Don't output packetized audio data on RGB video output
pins
0: Output packetized audio on RGB video output pins.
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
3
RW
I2S Channel 1: Set I2S Channel B Enable from reg_0x22[0]
B Enable
0: Set I2S Channel B Enable from MODE_SEL pin
Override
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
2
RW
18-bit Video 1: Select 18-bit video mode
Select
Note: use of GPIO(s) on unused inputs must be enabled
by register.
0: Select 24-bit video mode
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
1
RW
I2S
Transport
Select
0
RW
I2S Channel I2S Channel B Enable
B Enable
1: Enable I2S Channel B on B1 output
0: I2S Channel B disabled
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
7
RW
35
0x23
General
Purpose
Control
Default Function
(hex)
0x00
0x10
Override FC 1: Disable loading of this register from the forward channel,
Config
keeping locally written values intact
0: Allow forward channel loading of this register
Rx RGB
Checksum
6:5
Mode Status
40
Descriptions
1: Enable I2S Data Forward Channel Frame Transport
0: Enable I2S Data Island Transport
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
RX RGB Checksum Enable Setting this bit enables the
Receiver to validate a one-byte checksum following each
video line. Checksum failures are reported in the
HDCP_STS register
Reserved
4
R
Mode_Sel
Mode Select is Done
3
R
LFMODE
Low Frequency Mode Status
2
R
Repeater
Repeater Mode Status
1
R
Backward
Backward Compatible Mode Status
0
R
I2S Channel I2S Channel B Status
B
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Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
36
0x24
BIST Control
Bit(s)
Register
Type
7:4
Default Function
(hex)
0x08
Descriptions
Reserved
3
RW
BIST Pin
Config
BIST Configured through Pin
1: BIST configured through pin
0: BIST configured through register bit
2:1
RW
BIST Clock
Source
BIST Clock Source
00: External Pixel Clock
01: 33 MHz Oscillator
10: Reserved
11: 25 MHz Oscillator
0
RW
BIST
Enable
BIST Control
1: Enabled
0: Disabled
37
0x25
BIST Error
7:0
R
0x00
BIST Error
Count
BIST Error Count
38
0x26
SCL High
Time
7:0
RW
0x83
SCL High
Time
I2C Master SCL High Time
This field configures the high pulse width of the SCL output
when the Deserializer is the Master on the local I2C bus.
Units are 50 ns for the nominal oscillator clock frequency.
The default value is set to provide a minimum 5 us SCL
high time with the internal oscillator clock running at 26
MHz rather than the nominal 20 MHz.
39
0x27
SCL Low Time
7:0
RW
0x84
SCL Low
Time
I2C SCL Low Time
This field configures the low pulse width of the SCL output
when the De-Serializer is the Master on the local I2C bus.
This value is also used as the SDA setup time by the I2C
Slave for providing data prior to releasing SCL during
accesses over the Bidirectional Control Channel. Units are
50 ns for the nominal oscillator clock frequency. The
default value is set to provide a minimum 5 us SCL low
time with the internal oscillator clock running at 26 MHz
rather than the nominal 20 MHz.
41
0x29
FRC Control
7
RW
0x00
Timing
Mode
Select
Select display timing mode
0: DE only Mode
1: Sync Mode (VS,HS)
6
RW
VS Polarity
0: Active High
1: Active Low
5
RW
HS Polarity
0: Active High
1: Active Low
4
RW
DE Polarity
0: Active High
1: Active Low
3
RW
FRC2
Enable
0: FRC2 Disable
1: FRC2 Enable
2
RW
FRC1
Enable
0: FRC1 Disable
1: FRC1 Enable
1
RW
Hi-FRC 2
Disable
0: Hi-FRC2 Enable
1: Hi-FRC2 Disable
0
RW
Hi-FRC 1
Disable
0: Hi-FRC1 Enable
1: Hi-FRC1 Disable
7:6
RW
Page
Setting
00: Configuration Registers
01: Red LUT
10: Green LUT
11: Blue LUT
5
RW
White
Balance
Enable
0: White Balance Disable
1: White Balance Enable
4
RW
LUT Reload 0: Reload Disable
Enable
1: Reload Enable
42
0x2A
White Balance
Control
3:0
0x00
Reserved
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Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
43
0x2B
I2S Control
Bit(s)
Register
Type
7
RW
Default Function
(hex)
0x00
I2S PLL
6:1
0
44
58
0x2C
0x3A
SSCG Control
I2S DIVSEL
42
0x41
Link Error
Count
I2S PLL Control
0: I2S PLL is ON for I2S data jitter cleaning
1: I2S PLL is OFF. No jitter cleaning
Reserved
RW
7:4
I2S Clock
Edge
0x00
I2S Clock Edge Select
0: I2S Data is strobed on the Rising Clock Edge
1: I2S Data is strobed on the Falling Clock Edge
Reserved
3
RW
SSCG
Enable
Enable Spread Spectrum Clock Generator
0: Disable
1: Enable
2:0
RW
SSCG
Selection
SSCG Frequency Deviation:
When LFMODE = H
fdev fmod
000: ±0.7 CLK / 628
001: ±1.3
010: ±1.8
011: ±2.5
100: ±0.7 CLK / 388
101: ±1.2
110: ±2.0
111: ±2.5
When LFMODE = L
fdev fmod
000: ±0.9 CLK / 2168
001: ±1.2
010: ±1.9
011: ±2.5
100: ±0.7 CLK / 1300
101: ±1.3
110: ±2.0
111: ±2.5
7
RW
MCLK Div
Override
0: No override for MCLK divider (default)
1: Override divider select for MCLK
6:4
RW
MCLK Div
See Table 5
0x00
3:0
65
Descriptions
Reserved
7:5
0x03
Reserved
4
RW
Link Error
Count
Enable
Enable serial link data integrity error count
1: Enable error count
0: Disable
3:0
RW
Link Error
Count
Link error count threshold.
Counter is pixel clock based. clk0, clk1 and DCA are
monitored for link errors, if error count is enabled,
deserializer loose lock once error count reaches threshold.
If disabled deserilizer loose lock with one error.
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Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
68
0x44
Equalization
Bit(s)
Register
Type
7:5
RW
Default Function
(hex)
0x60
EQ Stage 1
Select
4
86
0x56
CML Output
Reserved
RW
EQ Stage 2
Select
EQ select value.
Used if adaptive EQ is bypassed.
000 Min EQ 2nd Stage
001
010
011
100
101
110
111 Max EQ 2nd Stage
0
RW
Adaptive
EQ
1: Disable adaptive EQ (to write EQ select values)
0: Enable adaptive EQ
7:4
0x08
RW
Reserved
CMLOUT+/- 1: Disabled (Default)
Enable
0: Enabled
2:0
0x64
Pattern
Generator
Control
EQ select value.
Used if adaptive EQ is bypassed.
000 Min EQ 1st Stage
001
010
011
100
101
110
111 Max EQ 1st Stage
3:1
3
100
Descriptions
7:4
Reserved
RW
0x10
Pattern
Generator
Select
3:1
0
Fixed Pattern Select
This field selects the pattern to output when in Fixed
Pattern Mode. Scaled patterns are evenly distributed
across the horizontal or vertical active regions. This field is
ignored when Auto-Scrolling Mode is enabled. The
following table shows the color selections in non-inverted
followed by inverted color mode
0000: Reserved 0001: White/Black
0010: Black/White
0011: Red/Cyan
0100: Green/Magenta
0101: Blue/Yellow
0110: Horizontally Scaled Black to White/White to Black
0111: Horizontally Scaled Black to Red/Cyan to White
1000: Horizontally Scaled Black to Green/Magenta to
White
1001: Horizontally Scaled Black to Blue/Yellow to White
1010: Vertically Scaled Black to White/White to Black
1011: Vertically Scaled Black to Red/Cyan to White
1100: Vertically Scaled Black to Green/Magenta to White
1101: Vertically Scaled Black to Blue/Yellow to White
1110: Custom color (or its inversion) configured in PGRS,
PGGS, PGBS registers
1111: Reserved
Reserved
RW
Pattern
Generator
Enable
Pattern Generator Enable
1: Enable Pattern Generator
0: Disable Pattern Generator
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Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
101
0x65
Pattern
Generator
Configuration
Bit(s)
Register
Type
7:5
Default Function
(hex)
0x00
Descriptions
Reserved
4
RW
Pattern
Generator
18 Bits
18-bit Mode Select
1: Enable 18-bit color pattern generation. Scaled patterns
will have 64 levels of brightness and the R, G, and B
outputs use the six most significant color bits.
0: Enable 24-bit pattern generation. Scaled patterns use
256 levels of brightness.
3
RW
Pattern
Generator
External
Clock
Select External Clock Source
1: Selects the external pixel clock when using internal
timing.
0: Selects the internal divided clock when using internal
timing
This bit has no effect in external timing mode
(PATGEN_TSEL = 0).
2
RW
Pattern
Generator
Timing
Select
Timing Select Control
1: The Pattern Generator creates its own video timing as
configured in the Pattern Generator Total Frame Size,
Active Frame Size. Horizontal Sync Width, Vertical Sync
Width, Horizontal Back Porch, Vertical Back Porch, and
Sync Configuration registers.
0: the Pattern Generator uses external video timing from
the pixel clock, Data Enable, Horizontal Sync, and Vertical
Sync signals.
1
RW
Pattern
Generator
Color Invert
Enable Inverted Color Patterns
1: Invert the color output.
0: Do not invert the color output.
0
RW
Pattern
Generator
Auto-Scroll
Enable
Auto-Scroll Enable:
1: The Pattern Generator will automatically move to the
next enabled pattern after the number of frames specified
in the Pattern Generator Frame Time (PGFT) register.
0: The Pattern Generator retains the current pattern.
102
0x66
Pattern
Generator
Indirect
Address
7:0
RW
0x00
Indirect
Address
This 8-bit field sets the indirect address for accesses to
indirectly-mapped registers. It should be written prior to
reading or writing the Pattern Generator Indirect Data
register.
See AN-2198 Exploring Int Test Patt Gen Feat of 720p
FPD-Link III Devices (SNLA132)
103
0x67
Pattern
Generator
Indirect Data
7:0
RW
0x00
Indirect
Data
When writing to indirect registers, this register contains the
data to be written. When reading from indirect registers,
this register contains the read back value.
See AN-2198 Exploring Int Test Patt Gen Feat of 720p
FPD-Link III Devices (SNLA132)
128
0x80
RX_BKSV0
7:0
R
0x00
RX BKSV0
BKSV0: Value of byte 0 of the Deserializer KSV
129
0x81
RX_BKSV1
7:0
R
0x00
RX BKSV1
BKSV1: Value of byte 1 of the Deserializer KSV
130
0x82
RX_BKSV2
7:0
R
0x00
RX BKSV2
BKSV2: Value of byte 2 of the Deserializer KSV
131
0x83
RX_BKSV3
7:0
R
0x00
RX BKSV3
BKSV3: Value of byte 3 of the Deserializer KSV.
132
0x84
RX_BKSV4
7:0
R
0x00
RX BKSV4
BKSV4: Value of byte 4 of the Deserializer KSV.
144
0x90
TX_KSV0
7:0
R
0x00
TX KSV0
KSV0: Value of byte 0 of the Serializer KSV.
145
0x91
TX_KSV1
7:0
R
0x00
TX KSV1
KSV1: Value of byte 1 of the Serializer KSV.
146
0x92
TX_KSV2
7:0
R
0x00
TX KSV2
KSV2: Value of byte 2 of the Serializer KSV.
147
0x93
TX_KSV3
7:0
R
0x00
TX KSV3
KSV3: Value of byte 3 of the Serializer KSV.
148
0x94
TX_KSV4
7:0
R
0x00
TX KSV4
KSV4: Value of byte 4 of the Serializer KSV.
44
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Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
192
0xC0
HDCP_DBG
193
0xC1
HDCP_DBG2
Bit(s)
Register
Type
7:4
Default Function
(hex)
0x00
Reserved
3
R
RGB_CHK
SUM_EN
Enable RBG video line checksum.
1: Enables sending of ones-complement checksum for
each 8-bit RBG data channel following end of each video
data line.
0: Checksum disabled
Set via the HDCP_DBG register in the HDCP Transmitter.
2
R
FC_TEST
MODE
Frame Counter Testmode:
1: Speeds up frame counter used for Pj and Ri verification.
When set to a 1, Pj is computed every 2 frames and Ri is
computed every 16 frames.
0: Pj is computed every 16 frames and Ri is computed
every 128 frames.
Set via the HDCP_DBG register in the HDCP Transmitter.
1
R
TMR_
SPEEDUP
Timer Speedup:
1: Speed up HDCP authentication timers.
0: Standard authentication timing
Set via the HDCP_DBG register in the HDCP Transmitter.
0
R
HDCP_I2C
_FAST
HDCP I2C Fast mode Enable:
1: Enable the HDCP I2C Master in the HDCP Receiver to
operation with Fast mode timing.
0:Tthe I2C Master will operate with Standard mode timing.
Set via the HDCP_DBG register in the HDCP Transmitter.
7:2
1
0x00
RW
Reserved
NO_
DECRYPT
0
196
224
225
226
0xC4
0xE0
0xE1
0xE2
HDCP Status
RPTR TX0
RPTR TX1
RPTR TX2
Descriptions
No Decrypt:
1: The HDCP Receiver outputs the encrypted data on the
RGB pins. All other functions will work normally. This
provides a simple way of showing that the link is
encrypted.
0: Normal Operation
Reserved
7:2
0x00
Reserved
1
R
RGB_CHK
SUM_ERR
RGB Checksum Error Detected:
If RGB Checksum in enabled through the HDCP
Transmitter HDCP_DBG register, this bit will indicate if a
checksum error is detected. This register may be cleared
by writing any value to this register.
0
R
HDCP
Status
HDCP Authenticated:
Indicates the HDCP authentication has completed
successfully. The controller may now send video data
requiring content protection. This bit will be cleared if
authentication is lost or if the controller restarts
authentication.
7:1
R
Serializer Port 0 I2C Address:
Indicates the I2C address for the Repeater Serializer Port.
0
R
HDCP
Serializer
Port 0
Address
7:1
R
Serializer Port 1 I2C Address: Indicates the I2C address
for the Repeater Serializer Port.
0
R
HDCP
Serializer
Port 1
Address
HDCP
Serializer
Port 2
Address
Serializer Port 2 I2C Address: Indicates the I2C address
for the Repeater Serializer Port.
7:1
0
0x0
0x00
0x00
R
Serializer Port 0 Valid:
Indicates that the HDCP Repeater has a Serializer port at
the I2C Address identified by upper 7 bits of this register.
Serializer Port 1 Valid: Indicates that the HDCP Repeater
has a Serializer port at the I2C Address identified by upper
7 bits of this register.
Serializer Port 2 Valid: Indicates that the HDCP Repeater
has a Serializer port at the I2C Address identified by upper
7 bits of this register.
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Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
227
0xE3
RPTR TX3
Register
Type
7:1
R
0
R
Default Function
(hex)
0x00
Descriptions
HDCP
Serializer
Port 3
Address
Serializer Port 3 I2C Address: Indicates the I2C address
for the Repeater Serializer Port.
Serializer Port 3 Valid: Indicates that the HDCP Repeater
has a Serializer port at the I2C Address identified by upper
7 bits of this register
240
0xF0
7:0
R
0x5F
ID0
First byte ID code: _
241
0xF1
7:0
R
0x55
ID1
Second byte of ID code: U
242
0xF2
7:0
R
0x48
ID2
Third byte of ID code, Value will be either ‘B’ or ‘H’. ‘H’
indicates an HDCP capable device.
243
0xF3
7:0
R
0x39
ID3
Fourth byte of ID code: 9
244
0xF4
7:0
R
0x32
ID4
Fifth byte of ID code: 2
245
0xF5
7:0
R
0x36
ID5
Sixth byte of ID code: 6
46
HDCP RX ID
Bit(s)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DS90UH926Q-Q1, in conjunction with the DS90UH925Q-Q1, is intended for interface between a HDCP
compliant host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888) and high definition
(720p) digital video format. It allows to receive a three 8-bit RGB stream with a pixel rate up to 85 MHz together
with three control bits (VS, HS and DE) and three I2S-bus audio stream with an audio sampling rate up to 192
kHz. The included HDCP 1.3 compliant cipher block allows the authentication of the DS90UH926Q, which
decrypts both video and audio contents. The keys are pre-loaded by TI into non-volatile memory (NVM) for
maximum security.
8.1.1 Display Application
The deserializer is expected to be located close to its target device. The interconnect between the deserializer
and the target device is typically in the 1-inch to 3-inch separation range. The input capacitance of the target
device is expected to be in the 5-pF to 10-pF range. Take care of the PCLK output trace as this signal is edgesensitive and strobes the data. It is also assumed that the fanout of the deserializer is up to three in the repeater
mode. If additional loads need to be driven, a logic buffer or mux device is recommended.
8.2 Typical Application
Figure 24 shows a typical application of the DS90UH926Q-Q1 deserializer for an 85 MHz 24-bit color display
application. Inputs utilize 0.1-μF coupling capacitors to the line and the deserializer provides internal termination.
Bypass capacitors are placed near the power supply pins. At a minimum, seven 0.1-μF capacitors and two 4.7μF capacitors should be used for local device bypassing. Ferrite beads are placed on the power lines for effective
noise suppression. Because the device in the Pin/STRAP mode, two 10 kΩ pull-up resistors are used on the
parallel output bus to select the desired device features.
The interface to the target display is with 3.3-V LVCMOS levels, thus the VDDIO pins are connected to the 3.3-V
rail. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
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Typical Application (continued)
3.3V/1.8V
DS90UH926Q-Q1
3.3V
VDDIO
VDD33_A
FB1
C6
FB2
C4
VDDIO
VDD33_B
C7
C5
VDDIO
C8
CAPP12
C9
CAPR12
C13
CAPI2S
PASS
C10
LOCK
CAPL12
C11
C12
C1
Serial
FPD-Link III
Interface
RIN+
RIN-
C2
CMF
C3
CMLOUTP
100:
VDD33_B*
CMLOUTN
R5
OSS_SEL
OEN
BISTEN
BISTC / INTB_IN
PDB
Host Control
C14
4.7k
4.7k
VDD33_B
VDD33_B
FB1 ± FB2: Impedance = 1 k: @ 100 MHz,
Low DC resistance (<1:)
C1 ± C3 = 0.1 PF (50 WV; C1, C2: 0402; C3: 0603)
C4 ± C13 = 4.7 PF
C14 =>10 PF
R1 and R2 (see IDx Resistor Values Table 8)
SDA
SCL
ID[X]
VDD33_B
R3
MODE_SEL
R3 and R4 (see MODE_SEL Resistor Values Table 4)
R5 = 10 k:
* or VDDIO = 3.3V+0.3V
G7
G6
G5
G4
G3
G2
G1
G0
LVCMOS
Parallel
Video / Audio
Interface
B7
B6
B5
B4
B3
B2
B1
B0
HS
VS
DE
PCLK
R1
R2
R7
R6
R5
R4
R3
R2
R1
R0
R4
I2S_CLK
I2S_WC
I2S_DA
MCLK
NC
RES
2
DAP (GND)
Figure 24. Typical Connection Diagram
48
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Typical Application (continued)
HOST
Graphics
Processor
RGB Digital Display Interface
VDD33
VDDIO
(1.8V or 3.3V) (3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
FPD-Link III
1 Pair / AC Coupled
0.1 PF
0.1 PF
DOUT+
RIN+
DOUT-
PDB
I2S AUDIO
(STEREO)
VDDIO
VDD33
(3.3V) (1.8V or 3.3V)
3
/
DS90UH925Q
Serializer
0.1 PF
MODE_SEL
INTB
SCL
SDA
IDx
RIN-
100 ohm STP Cable
0.1 PF
PDB
OSS_SEL
OEN
MODE_SEL
DS90UH926Q
Deserializer
SCL
SDA
IDx
DAP
LOCK
PASS
3
/
INTB_IN
RGB Display
720p
24-bit color depth
I2S AUDIO
(STEREO)
MCLK
DAP
Figure 25. Typical Display System Diagram
8.2.1 Design Requirements
For the typical design application, use the following as input parameters:
Table 12. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VDDIO
1.8 V or 3.3 V
VDD33
3.3 V
AC-Coupling Capacitor for RIN±
100 nF
PCLK Frequency
78 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Transmission Media
The DS90UH925Q-Q1 and DS90UH926Q-Q1 chipset is intended to be used in a point-to-point configuration
through a shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize
impedance discontinuities. The interconnect (cable and connector) between the serializer and deserializer should
have a differential impedance of 100 Ω. The maximum length of cable that can be used is dependant on the
quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical
environment (for example, power stability, ground noise, input clock jitter, PCLK frequency, etc.) and the
application environment.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define
the acceptable data eye opening width and eye opening height. A differential probe should be used to measure
across the termination resistor at the CMLOUT± pin Figure 2.
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78 MHz TX Pixel Clock Input
(500 mV/DIV)
Magnitude (80 mV/DIV)
CML Serializer Data Throughput
(200 mV/DIV)
8.2.3 Application Curves
Time (100 ps/DIV)
Time (2.5 ns/DIV)
Figure 26. Deserializer CMLOUT Eye Diagram With 78-MHz
TX Pixel Clock
Figure 27. Deserializer FPD-Link III Input With 78-MHz TX
Pixel Clock
9 Power Supply Recommendations
9.1 Power-Up Requirements and PDB Pin
When VDDIO and VDD33_X are powered separately, the VDDIO supply (1.8 V or 3.3 V) ramps up 100 µs before
the other supply (VDD33_X) begins to ramp. If VDDIO is tied with VDD33_X, both supplies may ramp at the
same time. The VDDs (VDD33_X and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise.
Use a large capacitor on the PDB pin to ensure PDB arrives after all the VDDs have settled to the recommended
operating voltage. When PDB pin is pulled to VDDIO = 3 V to 3.6 V or VDD33_X, TI recommends using a 10-kΩ
pullup and a > 10-µF cap to GND to delay the PDB input signal.
All inputs must not be driven until VDD33_X and VDDIO has reached its steady-state value.
< 1.5 ms
1.8 V or 3.3 V
VDDIO
100 µs
3.3 V
VDD33_X
< 1.5 ms
3.3 V
PDB
PDB starts to ramp after all supplies have settled
Figure 28. Power-Up Sequence of DS90UH926Q-Q1
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10 Layout
10.1 Layout Guidelines
Design the circuit board layout and stack-up for the FPD-Link III devices to provide low-noise power feed to the
device. Good layout practice also separates high-frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback, and interference. Power system performance may be greatly improved
by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range. Voltage rating of the
tantalum capacitors should be at least 5× the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50 µF to 100 µF range and will smooth low-frequency switching noise. TI
recommends connecting the power and ground pins directly to the power and ground planes with bypass
capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the path.
TI recommends a small body size X7R chip capacitor, such as 0603 or 0402, for external bypass. Its small body
size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML
lines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ω are
typically recommended for CML interconnect. The closely coupled lines help to ensure that coupled noise will
appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less.
Information on the WQFN style package is provided in AN-1187 Leadless Leadframe Package (LLP)
(SNOA401).
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in Table 13:
Table 13. No Pullback WQFN Stencil Aperture Summary
DEVICE
PIN
COUNT
MKT Dwg
PCB I/O
Pad Size
(mm)
PCB PITCH
(mm)
PCB DAP SIZE
(mm)
STENCIL I/O
APERTURE (mm)
STENCIL DAP
Aperture (mm)
NUMBER of DAP
APERTURE
OPENINGS
DS90UH926Q-Q1
60
NKB0060B
0.25 × 0.6
0.5
6.3 × 6.3
0.25 × 0.8
6.3 × 6.3
1
Figure 29 shows the PCB layout example derived from the layout design of the DS90UH926QSEVB Evaluation
Board. The graphic and layout description are used to determine both proper routing and proper solder
techniques when designing the Serializer board.
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10.1.1 CML Interconnect Guidelines
See AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and AN-905 Transmission
Line RAPIDESIGNER® Operation and Applications Guide (SNLA035) for full details.
• Use 100-Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500 Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: www.ti.com/lvds.
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10.2 Layout Examples
Length-Matched RGB
Output Traces
AC Capacitors
NKB0060B
High-Speed Traces
Figure 29. DS90UH926Q-Q1 Deserializer Example Layout
Figure 30. 60-Pin WQFN Stencil Example of Via and Opening Placement
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
• AN-2198 Exploring the Internal Test Pattern Generation Feature of 720p FPD-Link III Devices (SNLA132)
• AN-1187 Leadless Leadframe Package (LLP) (SNOA401)
• AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008)
• AN-905 Transmission Line RAPIDESIGNER® Operation and Applications Guide (SNLA035)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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3-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS90UH926QSQ/NOPB
ACTIVE
WQFN
NKB
60
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UH926QSQ
DS90UH926QSQE/NOPB
ACTIVE
WQFN
NKB
60
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UH926QSQ
DS90UH926QSQX/NOPB
ACTIVE
WQFN
NKB
60
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UH926QSQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-Aug-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Dec-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DS90UH926QSQ/NOPB
Package Package Pins
Type Drawing
WQFN
NKB
60
DS90UH926QSQE/NOPB WQFN
NKB
DS90UH926QSQX/NOPB WQFN
NKB
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
330.0
16.4
9.3
9.3
1.3
12.0
16.0
Q1
60
250
178.0
16.4
9.3
9.3
1.3
12.0
16.0
Q1
60
2000
330.0
16.4
9.3
9.3
1.3
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Dec-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90UH926QSQ/NOPB
WQFN
NKB
60
1000
367.0
367.0
38.0
DS90UH926QSQE/NOPB
WQFN
NKB
60
250
210.0
185.0
35.0
DS90UH926QSQX/NOPB
WQFN
NKB
60
2000
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
NKB0060B
VQFN - 0.8 mm max height
SCALE 1.500
PLASTIC QUAD FLATPACK - NO LEAD
9.1
8.9
B
A
PIN 1 INDEX AREA
9.1
8.9
0.8
0.7
C
SEATING PLANE
0.05
0.00
0.08 C
2X 7
6.3 0.1
EXPOSED
THERMAL PAD
SYMM
16
15
31
SYMM
61
2X 7
1
56X 0.5
PIN 1 ID
(0.1) TYP
30
45
60
46
0.7
60X
0.5
60X
0.3
0.2
0.1
0.05
C A B
4214995/A 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NKB0060B
VQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 6.3)
SYMM
60X (0.8)
46
60
SEE SOLDER MASK
DETAIL
60X (0.25)
1
45
56X (0.5)
(1.1) TYP
(1.2) TYP
(R0.05) TYP
( 0.2) TYP
VIA
SYMM
61
(0.6) TYP
15
(8.6)
31
16
30
(0.6) TYP
(1.2) TYP
(1.1) TYP
(8.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK DEFINED
SOLDER MASK DETAILS
4214995/A 03/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
NKB0060B
VQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
25X ( 1)
(1.2) TYP
60X (0.8)
60
46
60X (0.25)
1
45
56X (0.5)
(R0.05) TYP
(1.2) TYP
61
SYMM
(8.6)
15
31
30
16
SYMM
(8.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 8X
EXPOSED PAD 61
63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4214995/A 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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