Texas Instruments | TPD2S701-Q1 Automotive USB 2-Channel Data Line Short-to-VBUS and IEC ESD Protection (Rev. A) | Datasheet | Texas Instruments TPD2S701-Q1 Automotive USB 2-Channel Data Line Short-to-VBUS and IEC ESD Protection (Rev. A) Datasheet

Texas Instruments TPD2S701-Q1 Automotive USB 2-Channel Data Line Short-to-VBUS and IEC ESD Protection (Rev. A) Datasheet
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TPD2S701-Q1
SLLSEY0A – APRIL 2017 – REVISED JULY 2017
TPD2S701-Q1 Automotive USB 2-Channel Data Line Short-to-VBUS and IEC ESD Protection
1 Features
•
1
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified
– –40°C to 125°C Operating Temperature Range
Short-to-VBUS Protection on VD+ and VD–
ESD Performance VD+, VD–
– ±8-kV Contact Discharge (IEC 61000-4-2 and
ISO 10605 330 pF, 330 Ω)
– ±15-kV Air-Gap Discharge (IEC 61000-4-2 and
ISO 10605 330 pF, 330 Ω)
High Speed Data Switches (1-GHz Bandwidth)
Only Requires 5-V Power Supply
Adjustable OVP Threshold
Fast Overvoltage Response Time (200 ns typical)
Thermal Shutdown Feature
Integrated Input Enable and Fault Output Signal
Flow-through Routing for Data Integrity
– 10-pin VSSOP Package (3 mm × 3 mm)
– 10-pin QFN Package (2.5 mm × 2.5 mm)
On these pins, this device can handle overvoltage
protection up to 7-V DC. This provides sufficient
protection for shorting the data lines to the USB VBUS
rail. The overvoltage protection circuit provides the
most reliable short to VBUS isolation in the industry,
shutting off the data switches in 200 ns and
protecting the upstream circuitry from harmful voltage
and current spikes.
Additionally, the TPD2S701-Q1 only requires a single
power supply of 5 V in order to optimize power tree
size and cost. The OVP threshold and clamping
circuit can be adjusted by a resistor divider network to
provide a simple, cost effective way to optimize
system protection for any transceiver. The
TPD2S701-Q1 also includes a FLT pin which
provides an indication when the device sees an
overvoltage condition and automatically resets when
the overvoltage condition is removed.
The TPD2S701-Q1 also integrates system level IEC
61000-4-2 and ISO 10605 ESD clamps on the VD+
and VD– pins, thus eliminating the need for external
high voltage, low capacitance TVS clamp circuits in
the application.
2 Applications
•
•
End Equipment
– Head Unit
– Rear Seat Entertainment
– Telematics
– USB Hubs
– Navigation Modules
– Media Interface
Interfaces
– USB 2.0
– USB 3.0
Device Information(1)
PART NUMBER
TPD2S701-Q1
PACKAGE
3.00 mm × 3.00 mm
QFN (10)
2.50 mm × 2.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
VPWR
VREF
MODE
3 Description
The TPD2S701-Q1 is a 2-Channel Data Line Shortto-VBUS and IEC61000-4-2 ESD protection device for
automotive high-speed interfaces like USB 2.0. The
TPD2S701-Q1 contains two data line nFET switches
which ensure safe data communication by providing
best in class bandwidth for minimal signal
degradation while simultaneously protecting the
internal system circuits from any overvoltage
conditions at the VD+ and VD– pins.
BODY SIZE (NOM)
VSSOP (10)
Control Logic
FLT
EN
Overvoltage
Protection
D+
VD+
ESD
Clamps
D-
VD-
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD2S701-Q1
SLLSEY0A – APRIL 2017 – REVISED JULY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Absolute Maximum Ratings ...................................... 4
ESD Ratings—AEC Specification ............................. 4
ESD Ratings—IEC Specification .............................. 4
ESD Ratings—ISO Specification .............................. 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Power Supply and Supply Current Consumption
Chracteristics ............................................................. 7
6.9 Timing Requirements ................................................ 8
6.10 Typical Characteristics .......................................... 10
7
8
Parameter Measurement Information ................ 14
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 17
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 18
10 Power Supply Recommendations ..................... 21
10.1 VPWR Path ............................................................. 21
10.2 VREF Pin ................................................................ 21
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 22
12 Device and Documentation Support ................. 23
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Original (April 2017) to Revision A
•
2
Page
Updated Figure 19 ............................................................................................................................................................... 14
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5 Pin Configuration and Functions
DGS Package
10-Pin SSOP
Top View
DSK Package
10-Pin QFN
Top View
VD-
1
10
D-
VD-
1
10
D-
VD+
2
9
D+
VD+
2
9
D+
GND
3
8
VREF
GND
4
7
VPWR
FLT
3 Thermal 8
Pad
4
7
VREF
FLT
EN
5
6
MODE
EN
5
MODE
6
VPWR
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
VD–
I/O
High voltage D– USB data line, connect to USB connector D+, D– IEC61000-4-2 ESD
protection
2
VD+
I/O
High voltage D+ USB data line, connect to USB connector D+, D– IEC61000-4-2 ESD
protection
3
GND
Ground
4
FLT
O
Open-drain fault pin. See Table 1
5
EN
I
Enable active-low input. Drive EN low to enable the switches. Drive EN high to disable the
switches. See Table 1 for mode selection
6
MODE
I
Selects between device modes. See the Detailed Description section. Acts as LDO reference
voltage for mode 1
7
VPWR
I
5-V DC supply input for internal circuits. Connect to internal power rail on PCB
8
VREF
I/O
Pin to set OVP threshold. See the Detailed Description section for instructions on how to set
OVP threshold
9
D+
I/O
I/O protected low voltage D+ USB data line, connects to transceiver
10
D–
I/O
Protected low voltage D– USB data line, connects to transceiver
Ground pin for internal circuits and IEC ESD clamps
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
UNIT
VPWR
5-V DC supply voltage for internal circuitry
–0.3
7.7
V
VREF
Pin to set OVP threshold
–0.3
6
V
VD+,
VD–
Voltage range from connector-side USB data lines
–0.3
7.7
V
D+, D–
Voltage range for internal USB data lines
–0.3
VREF + 0.3
V
VMODE
Voltage on MODE pin
–0.3
7.7
V
VFLT
Voltage on FLT pin
–0.3
7.7
V
VEN
Voltage on enable pin
–0.3
7.7
V
TA
Operating free air temperature (3)
–40
125
°C
TSTG
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
Thermal limits and power dissipation limits must be observed.
6.2 ESD Ratings—AEC Specification
VALUE
Human-body model (HBM), per AEC Q100-002
V(ESD)
(1)
Electrostatic discharge
(1)
All pins
All pins besides
Charged-device model (CDM), per AEC Q100-011 corners
Corner pins
UNIT
±2000
±500
V
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC Specification
VALUE
V(ESD)
(1)
Electrostatic discharge
IEC 61000-4-2 contact discharge
VD+, VD– pins (1)
±8000
IEC 61000-4-2 air-gap discharge
VD+, VD– pins (1)
±15000
UNIT
V
See Figure 19 for details on system level ESD testing setup.
6.4 ESD Ratings—ISO Specification
VALUE
VESD
(1)
(2)
4
(1)
Electrostatic discharge
ISO 10605 (330 pF, 330 Ω) contact discharge
(10 strikes)
VD+, VD– pins
±8000
ISO 10605 (330 pF, 330 Ω) air-gap discharge
(10 strikes)
VD+, VD– pins
±15000
ISO 10605 (150 pF, 330 Ω) contact discharge
(10 strikes)
VD+, VD– pins
±8000
ISO 10605 (150 pF, 330 Ω) air-gap discharge
(10 strikes)
VD+, VD– pins
±15000
ISO 10605 (330 pF, 2 kΩ) contact discharge (10
stikes) (2)
VD+, VD– pins
±8000
ISO 10605 (330 pF, 2 kΩ) air-gap discharge (10
strikes)
VD+, VD– pins
±15000
ISO 10605 (150 pF, 2 kΩ) air-gap discharge (10
discharges)
VD+, VD– pins
±25000
UNIT
V
See Figure 19 for details on system level ESD testing setup.
VREF > 3 V.
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6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
VPWR
5-V DC supply voltage for internal circuitry
4.5
7
V
VREF
Mode 0. Voltage range for VREF pin (for setting OVP threshold)
3
3.6
V
VREF
Mode 1. Voltage range for VREF pin (for setting OVP threshold)
0.63
3.8
V
VD+, VD–
Voltage range from connector-side USB data lines
0
3.6
V
D+, D–
Voltage range for internal USB data lines
0
3.6
V
VEN
Voltage range for enable
0
7
V
VFLT
Voltage range for FLT
0
7
V
IFLT
Current into open drain FLT pin FET
0
3
mA
CVPWR
VPWR capacitance (1)
External Capacitor on VPWR pin
1
10
CVREF
VREF capacitance
External Capacitor on VREF pin
0.3
1
3
CMODE
Allowed parasitic capacitance on mode pin from PCB and mode 1 external resistors
20
pF
RMODE_0
Resistance to GND to set to mode 0
2
2.6
kΩ
RMODE_1
Resistance to GND to set to mode 1 (calculate parallel combination of RTOP and RBOT)
(1)
14
µF
20
µF
kΩ
For recommended values for capacitors and resistors, the typical values assume a component placed on the board near the pin.
Minimum and maximum values listed are inclusive of manufacturing tolerances, voltage derating, board capacitance, and temperature
variation. The effective value presented should be within the minimum and maximums listed in the table.
6.6 Thermal Information
TPD2S701-Q1
THERMAL METRIC (1)
DGS (VSSOP)
DSK (WSON)
10 PINS
10 PINS
UNIT
θJA
Junction-to-ambient thermal resistance
167.3
61.5
°C/W
θJCtop
Junction-to-case (top) thermal resistance
56.9
51.3
°C/W
θJB
Junction-to-board thermal resistance
87.6
34
°C/W
ψJT
Junction-to-top characterization parameter
7.7
1.3
°C/W
ψJB
Junction-to-board characterization parameter
86.2
34.3
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
7.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.47
0.5
0.53
V
50
200
nA
MODE 1 ADJUSTABLE VREF
VMODE_CMP
Mode 1 VREF feedback
regulator voltage
VMODE
Standard mode 1 set-up. EN = 0 V. Once
VREF = 3.3 V, measure voltage on mode pin
IMODE_LEAK
Mode pin mode 1 leakage
current
IMODE
Standard mode 1. Remove RTOP and RBOT.
Power up device and wait until start-up time has
passed. Then force 0.53 V on the MODE pin
and measure current into pin
VREF_ACCURACY
VREF accuracy
VREF
Informative, test parameters below; accuracy
with RTOP and RBOT as ±1% resistors
–8%
VREF_3.3V
Mode 1 VREF set to 3.3 V
VREF
Standard mode 1 set-up. RTOP = 140 kΩ ± 1%,
RBOT = 24.9 kΩ ± 1%. EN = 0. Measure value
of VREF once it settles
3.04
3.31
3.58
V
VREF_0.66V
Mode 1 VREF set to 0.66 V
VREF
Standard mode 1 set-up. RTOP = 47.5 kΩ ± 1%,
RBOT = 150 kΩ ± 1%.EN = 0. Measure value of
VREF once it settles
0.6
0.66
0.72
V
VREF_3.8V
Mode 1 VREF set to 3.8 V
VREF
Standard mode 1 set-up. RTOP = 165 kΩ ± 1%,
RBOT = 24.9 kΩ ± 1%. EN = 0. Measure value
of VREF once it settles
3.5
3.81
4.12
V
Mode 0. Connect VPWR = 5 V; VREF = 3.3 V;
VD+ = 3.3 V; Set VIH(EN) = 0 V; Sweep VIH
from 0 V to 1.4 V; Measure when D+ drops low
(less than or equal to 5% of 3.3 V) from 3.3 V
1.2
8%
EN, FLT PINS
High-level input voltage
VIH
EN
Low-level input voltage
V
Mode 0. Connect VPWR = 5 V; VREF = 3.3 V;
VD+ = 3.3 V. Set VIH(EN) = 3.3 V; Sweep VIH
from 3.3 V to 0.5 V; Measure when D+ rise to
95% of 3.3 V from 0 V
0.8
1
IIL
Input leakage current
EN
Mode 0. VPWR = 5 V; VREF = 3.3 V; VI (EN) =
3.3 V ; Measure current into EN pin
VOL
Low-level output voltage
FLT
Mode 0. Drive the TPS2S701-Q1 in OVP to
assert FLT pin. Source IOL = 1 mA into FLT pin
and measure voltage on FLT pin when asserted
TSD_RISING
The rising over temperature
protection shutdown threshold
VPWR = 5 V, ENZ = 0 V, TA stepped up until
FLTZ is asserted
140
150
165
℃
TSD_FALLING
The falling over temperature
protection shutdown threshold
VPWR = 5 V, ENZ = 0 V, TA stepped down
from TSD_RISING until FLTZ is cleared
125
138
150
℃
TSD_HYST
The over temperature
protection shutdown threshold
hysteresis
TSD_RISING – TSD_FALLING
10
12
15
℃
VD±
Mode 1. Set VPWR = 5 V; EN = 0 V; RTOP = 165
kΩ, RBOT = 24.9 kΩ. Connect D± to 40-Ω load.
Increase VD+ or VD– from 4.1 V to 4.9 V.
Measure the value at which FLTZ is asserted
4.3
4.5
4.7
V
1.19
×
VREF
1.25
×
VREF
1.31 ×
VREF
V
µA
V
0.4
OVP CIRCUIT—VD±
VOVP_RISING
Input overvoltage protection
threshold, VREF > 3.6 V
VOVP_RISING
Input overvoltage protection
threshold
VD±
Mode 1. Set VPWR = 5 V; EN = 0 V; RTOP = 140
kΩ, RBOT = 24.9 kΩ. Increase VD+ or VD– from
3.6 V to 4.6 V. Measure the value at which
FLTZ is asserted. Repeat for RTOP = 39 kΩ,
RBOT = 150 kΩ. Increase VD+ or VD– from 0.6
V to 0.9 V. Measure the value at which FLTZ is
asserted. See the resultant values meet the
equation, and make sure to observe data
switches turnoff.
Also check for mode 0 when VREF = 3.3 V
VHYS_OVP
Hysteresis on OVP
VD±
Difference between rising and falling OVP
thresholds on VD±
VD±
After collecting each rising OVP threshold,
lower the VD± voltage until you see FLT
deassert. This gives the falling OVP threshold.
Use this value to calculate VHYS_OVP
VOVP_FALLING
Input overvoltage protection
threshold
IVD_LEAK_0
Leakage current on VD±
during normal operation
6
V
VD±
Standard mode 0 or mode 1. Set VD± = 0 V. D±
= floating. Measure current flowing into VD±
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25
mV
VOV
P_RI
SING
–
VHYS
_OVP
–0.1
V
0.1
µA
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
IVD_LEAK_3.6V
Leakage current on VD±
during normal operation
VOVP_3.3V
Input overvoltage threshold
for VREF = 3.3 V
VOVP_0.66V
Input overvoltage threshold
for VREF = 0.66 V
TEST CONDITIONS
MIN
VD±
Standard mode 0 or mode 1. Set VD± = 3.6 V.
D± = floating. Measure current flowing into VD±
VD±
Standard mode 1. RTOP = 140 kΩ ± 1%, RBOT =
24.9 kΩ ± 1%. Connect D± to 40-Ω load.
Measure the value at which FLTZ is asserted
Standard mode 1. RTOP = 47.5 kΩ ± 1%, RBOT =
150 kΩ ± 1%. Connect D± to 40-Ω load.
Measure the value at which FLTZ is asserted
VD±
TYP
MAX
UNIT
2.5
4
3.61
4.14
4.67
0.72
0.83
0.94
4
6.5
Ω
1
Ω
µA
V
V
DATA LINE SWITCHES – VD+ to D+ or VD– to D–
On resistance
Mode 0 or 1. Set VPWR = 5 V; VREF = 3.3 V; EN
= 0 V; Measure resistance between D+ and
VD+ or D– and VD–, voltage between 0 and 0.4
V
RON(Flat)
On resistance flatness
Mode 0 or 1. Set VPWR = 5 V; VREF = 3.3 V; EN
= 0 V; Measure resistance between D+ and
VD+ or D– and VD–, sweep voltage between 0
and 0.4 V. Take difference of resistance at 0.4V and 0-V VD± bias
BWON
On bandwidth (–3-dB)
Mode 0 or 1. Set VPWR = 5 V; VREF = 3.3 V; EN
= 0 V; Measure S21 bandwidth from D+ to VD+
or D– to VD– with voltage swing = 400 mVpp,
Vcm = 0.2 V
RON
960
MHz
6.8 Power Supply and Supply Current Consumption Chracteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VUVLO_RISING_
VPWR
VUVLO_HYST_V
TEST CONDITIONS
MIN
TYP
MAX
VPWR rising UVLO threshold
Use standard mode 0 set-up. Set EN = 0 V, load D+ to 45
Ω, VD+ = 3.3 V. Set VPWR = 3.5 V, and step up VPWR until
90% of VD+ appears on D+
3.7
3.95
4.2
V
VPWR UVLO hysteresis
Use standard mode 0 set up. Set EN = 0 V, load D+ to 45
Ω, VD+ = 3.3 V. Set VPWR = 4.3 V, and step down
VPWR until D+ falls to 10% of VD+. This gives
VUVLO_FALLING_VPWR. VUVLO_RISING_VPWR –
VUVLO_FALLING_VPWR = VUVLO_HYST_VPWR for this unit
250
300
400
mV
Use standard mode 0 set up. Set EN = 0V, load D+ to 45
Ω, VD+ = 3.3 V. Set VREF = 2.5 V, and step up
VREF until 90% of VD+ appears on D+
2.6
2.7
2.9
V
Use standard mode 0 set up. Set EN = 0 V, load D+ to 45
Ω, VD+ = 3.3 V. Set VREF = 3 V, and step down
VREF until D+ falls to 10% of VD+. This gives
VUVLO_FALLING_VREF. VUVLO_RISING_VREF
–VUVLO_FALLING_VREF = VUVLO_HYST_VREF for this unit
75
125
200
mV
PWR
VUVLO_RISING_ VREF rising UVLO threshold
in mode 0
VREF
VUVLO_HYST_V
VREF UVLO hysteresis
REF
UNIT
IVPWR_DISABLE VPWR disabled current
consumption
D_MODE0
Use standard mode 0. EN = 5 V . Measure current into
VPWR
110
µA
IVPWR_DISABLE VPWR disabled current
consumption
D_MODE1
Use standard mode 1. EN = 5 V. Measure current into
VPWR
110
µA
IVREF_DISABLE
VREF disabled current
consumption mode 0
Use standard mode 0. EN = 5 V. Measure current into
VREF
10
µA
IVPWR_MODE0
VPWR pperating current
consumption
Use standard mode 0. EN = 0 V. Measure current into
VPWR
250
µA
IVPWR_MODE1
VPWR operating current
consumption
Use standard mode 1. EN = 0 V. Measure current into
VPWR
350
µA
IVREF
VREF operating current
consumption mode 0
Use standard mode 0. EN = 0 V. Measure current into
VREF
12
20
µA
VREF fast charge current
Standard mode 1. 0.1 µF < CVREF < 3 µF. Set-up for
charging to 3.3 V. Use a high voltage capacitor that does
not derate capacitance up the 3.3 V. Measure slope to
calculate the current when CVREF cap is being
charged. Test to check this OPEN LOOP method
22
D
ICHG_VREF
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Power Supply and Supply Current Consumption Chracteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ID_OFF_LEAK_S
TB
ID_ON_LEAK_ST
B
IVD_OFF_LEAK_
STB
IVD_ON_LEAK_S
TB
MIN
TYP
MAX
Mode 0. Measured flowing into D+ or D– supply, VPWR = 0
V, VD+ or VD– = 18 V, EN = 0 V, VREF = 0 V, D± = 0 V
–1
1
Mode 0. Measured flowing into D+ or D– supply, VPWR = 5
V, VD+ or VD– = 18 V, EN = 0 V, VREF = 3.3 V, D± = 0 V
–1
1
UNIT
µA
µA
Mode 0. Measured flowing out of VD+ or VD– supply,
VPWR = 0 V, VD+ or VD– = 18 V, EN = 0 V, VREF = 0 V,
D± = 0 V
120
Mode 0. Measured flowing out of VD+ or VD– supply,
VPWR = 5 V, VD+ or VD– = 18 V, EN = 0 V, VREF = 3.3 V,
D± = 0 V
120
µA
IVPWR_TO_VRE Leakage from VPWR to
VREF
F_LEAK
Use standard mode 0. Set VREF = 0 V. Measured
current flowing out of VREF pin
1
µA
IVREF_TO_VPW
Use standard mode 0. Set VPWR = 0 V. Measured as
current flowing out of VPWR pin
1
µA
R_LEAK
Leakage from VREF to
VPWR
6.9 Timing Requirements
over operating free-air temperature range (unless otherwise noted)
MIN
NOM MAX
UNIT
ENABLE PIN AND VREF FAST CHARGE
Time between when 5 V is applied to VPWR, and VREF
reaches VVREF_FAST_CHG. Needs to happen before or at
same time tON_STARTUP completes
TVREF_CHG
VREF fast charge time
TON_STARTU
Mode 0. EN = 0 V, measured from VPWR and VREF =
UVLO+ to data FET ON, VPWR comes to UVLO+ second.
Device turnon time from UVLO
Place 3.3 V on VD±. Ramp VREF to 3.3 V, then VPWR
mode 0
to 5 V and measure the time it takes for D± to reach 90%
of VD±
P_MODE0
TON_STARTU
P_MODE1
Informative. mode 1. EN = 0 V, measured from VPWR =
Device turnon time from UVLO
UVLO+ to data FET ON
mode 1
0.5
1
ms
0.5
1
ms
0.5 +
TCHG_C
ms
VREF
Mode 1. EN = 0 V, measured from VPWR = UVLO+ to
Device turnon time from UVLO
data FET ON, CVREF = 1 µF, VREF_FINAL = 3.3 V.
mode 1
Measure the time it takes for D± to reach 90% of VD±
0.6
Device turnon time mode 0
Mode 0. VPWR = 5 V, VREF = 3.3 V, time from EN is
asserted until data FET is ON. Place 3.3 V on VD±,
measure the time it takes for D± to reach 90% of VD±
150
µs
Device turnon time mode 1
Mode 1. VPWR = 5 V, VREF_INITIAL = 0 V, time from EN is
asserted until data FET is ON. Place 3.3 V on VD±,
measure the time it takes for D± to reach 90% of VD±
150 +
TCHG_V
µs
Mode 1. VPWR = 5 V, VREF_INITIAL = 0 V, time from EN is
TON_EN_MOD Device turnon time mode 1 for asserted until data FET is ON. Place 3.3 V on VD±,
VREF = 3.3 V
measure the time it takes for D± to reach 90% of
E1_3.3V
VD±. CVREF = 1 µF, VREF_FINAL = 3.3 V
300
µs
Mode 0 or 1. VPWR = 5 V, VREF = 3.3 V, time from EN is
deasserted until data FET is off. Place 3.3 V on VD±,
measure the time it takes for D± to fall to 10% of
VD±, RD± = 45 Ω
5
µs
TON_STARTU
P_MODE1_3.3V
TON_EN_MOD
E0
TON_EN_MOD
E1
TOFF_EN
Device turnoff time
Informative. Mode 1. Time from VREF = 0 V to 80% ×
VREF_FINAL after EN transitions from high to low
TCHG_CVREF
Time to charge CVREF
1
ms
REF
(CVREF
× 0.8
(VREF_FI
NAL)/(IC
s
HG_VREF
)
TCHG_CVREF
_3.3V
8
Time to charge CVREF
Mode 1. Time from VREF = 0 V to 90% × 3.3 V after EN
to 3.3 V
transitions from high to low, CVREF = 1 µF
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Timing Requirements (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
TCHG_CVREF
_0.66V
Time to charge CVREF to 0.66
V
NOM MAX
UNIT
Mode 1. Time from VREF = 0 V to 90% × 0.63 V after EN
transitions from high to low, CVREF = 1 µF. RTOP = 47.5
kΩ ± 1%, RBOT = 150 kΩ ± 1%
26
µs
Mode 0 or 1. Measured from OVP condition to FET turn
off . Short VD± to 5 V and measure the time it takes D±
voltage to reach 0.1 × VD±_CLAMP_MAX from the time the 5V hot-plug is applied. RLOAD_D± = 45 Ω. (1) (2)
2
µs
OVERVOLTAGE PROTECTION
tOVP_response
OVP response time to VBUS
_VBUS
tOVP_response OVP response time
Mode 0 or 1. Measured from OVP condition to FET turn
off . Short VD± to 18 V and measure the time it takes D±
voltage to reach 0.1 × VD±_CLAMP_MAX from the time the
18-V hot-plug is applied. RLOAD_D± = 45 Ω (1) (2)
0.1
tOVP_Recov
Recovery time FLT pin
Measured from OVP clear to FLT deassertion (1)
32
ms
Measured from OVP clear until FET turns back on. Drop
VD+ from 16 V to 3.3 V with VREF = 3.3 V, measure time
it takes for D+ to reach 90% of 3.3 V
32
ms
_FET
Recovery time for data FET to
turn back on
tOVP_ASSERT
FLT assertion time
Measured from OVP on VD+ or VD– to FLT assertion
1
µs
_FLT
tOVP_Recov
(1)
(2)
12.6
18
23.4
ms
Shown in Figure 1.
Specified by design, not production tested.
VOVP
VD+/-
/EN
tOVP_OFF
tOVP_Recov
D+/tOVP_/FLT_ON
tOVP_/FLT_OFF
/FLT
(1)
OVP Operation – VD+, VD–
Figure 1. TPD2S701-Q1 Timing Diagram
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6.10 Typical Characteristics
100
60
VD
D
80
VD
D
40
60
Voltage (V)
Voltage (V)
20
40
20
0
-20
0
-40
-20
-40
-10
0
10
20
30
40 50
Time (ns)
60
70
80
90
-60
-10
100
0
10
20
30
Fig1
Figure 2. 8-kV IEC 61400-4-2 Contact Waveform
40 50
Time (ns)
60
70
80
90
100
Fig2
Figure 3. –8-kV IEC 61400-4-2 Contact Waveform
80
40
VD
D
60
VD
D
20
40
Voltage (V)
Voltage (V)
0
20
0
-40
-20
-60
-40
-60
-10
-20
0
10
20
30
40 50
Time (ns)
60
70
80
90
-80
-10
100
0
10
20
30
Fig3
Figure 4. 8-kV ISO 10605 (330-pF, 330-Ω) Contact Waveform
40 50
Time (ns)
60
70
80
90
100
Fig4
Figure 5. –8-kV ISO 10605 (330-pF, 330-Ω) Contact
Waveform
6
1
0.8
5
0.6
4
Voltage (V)
Current (mA)
0.4
0.2
0
-0.2
3
2
-0.4
-0.6
1
-0.8
-1
-5
0
5
10
Voltage (V)
15
20
25
0
-600
/EN
VDr
Dr
/FLT
-400
Fig5
Figure 6. Data Line I-V Curve
10
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-200
0
Time (Ps)
200
400
600
Fig6
Figure 7. Data Switch Turnon Time
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Typical Characteristics (continued)
200
200
Diabled
Enabled
180
VPWR Operating Current (PA)
180
160
Current (PA)
140
120
100
80
60
40
160
140
120
100
80
60
40
Disabled
Enabled
20
20
0
-40
0
3
3.5
4
4.5
Bias Voltage (V)
5
5.5
Figure 8. VPWR Operating Current vs Bias Voltage
6
4.5
5.5
4
20
40
60
80
Temperature (qC)
100
120
140
Fig8
3.5
Data Switch RON (:)
On Resistance (:)
0
Figure 9. VPWR Operating Current vs Temperature
(VPWR = 5 V)
5
4.5
4
3.5
3
3
2.5
2
1.5
1
2.5
-40qC
25qC
85qC
125qC
0.5
0
2
0
0.5
1
1.5
2
Bias Voltage (V)
2.5
3
0
3.5
7.5
6.5
7.5
5.5
6
4.5
4.5
3.5
3
2.5
1.5
1.5
0
0.5
-1.5
0.5
1
1.5
2
2.5
Time (us)
3
3.5
4
1.5
2
Bias Voltage (V)
2.5
3
3.5
Fig1
7
VDr
/FLT
6
5
-3
4.5
Voltage (V)
8.5
0
1
Figure 11. Data Switch RON vs Bias Voltage
13.5
VD+ V
12
VD+ I
D+ V
10.5
/FLT
9
9.5
D + &/FLT (V)
10.5
-0.5
-0.5
0.5
D010
Figure 10. VD± Leakage Current at 7 V Across Temperature
(Enabled)
Voltage (V) or Current (A)
-20
Fig7
4
3
2
1
0
0
5
D011
Figure 12. Data Switch Short-to-5 V Response Waveform
10
15
20
25
Time (ms)
30
35
40
Fig1
Figure 13. FLT Assertion Time During OVP
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Typical Characteristics (continued)
0
7
VDr
/FLT
6
-1
Insertion Loss (dB)
Voltage (V)
5
4
3
2
1
-2
-3
-4
-5
-6
0
0
10
20
30
40
50
60
Time (ms)
70
80
90
100
-7
1E+5
1E+6
Fig1
1E+7
1E+8
Frequency (Hz)
1E+9
5E+9
D015
D001
Figure 15. Data Switch Differential Bandwidth
Figure 14. FLT Recover Time After OVP Clear
0
Insertion Loss (dB)
-1
-2
-3
-4
-5
-6
-7
1E+5
1E+6
1E+7
1E+8
Frequency (Hz)
1E+9
5E+9
D016
Figure 16. Data Switch Single-Ended Bandwidth
Figure 17. USB2.0 Eye Diagram (No TPD2S701-Q1)
12
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Typical Characteristics (continued)
Figure 18. USB2.0 Eye Diagram (With TPD2S701-Q1)
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ESD Strike Points
7 Parameter Measurement Information
USB 2.0
CMC
10 nH
VD-
D-
VD+
D+
45 Ÿ
10 nH
CCLAMP
TPD2S701-Q1
5V
GND
VREF
FLT
VPWR
RTOP
45 Ÿ
5V
CPWR
EN
MODE
RBOT
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Figure 19. ESD Setup
14
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8 Detailed Description
8.1 Overview
The TPD2S701-Q1 is a 2-Channel Data Line Short-to-VBUS and IEC61000-4-2 ESD protection device for
automotive high-speed interfaces like USB2.0. The TPD2S701-Q1 contains two data line nFET switches which
ensure safe data communication while protecting the internal system circuits from any overvoltage conditions at
the VD+ and VD– pins. On these pins, this device can handle overvoltage protection up to 7-V DC. This provides
sufficient protection for shorting the data lines to the USB VBUS rail.
Additionally, the TPD2S701-Q1 has a FLT pin which provides an indication when the device sees an overvoltage
condition and automatically resets when the overvoltage condition is removed. The TPD2S701-Q1 also
integrates IEC ESD clamps on the VD+ and VD– pins, thus eliminating the need for external TVS clamp circuits
in the application.
The TPD2S701-Q1 has an internal oscillator and charge pump that controls the turnon of the internal nFET
switches. The internal oscillator controls the timers that enable the charge pump and resets the open-drain FLT
output. If VD+ and VD– are less than VOVP, the internal charge pump is enabled. After an internal delay, the
charge-pump starts-up, turning on the internal nFET switches. At any time, if VD+ or VD– rises above VOVP,
TPD2S701-Q1 asserts FLT pin LOW and the nFET switches are turned off.
8.2 Functional Block Diagram
VPWR
VREF
MODE
Control Logic
FLT
EN
Overvoltage
Protection
D+
VD+
ESD
Clamps
D-
VD-
GND
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8.3 Feature Description
8.3.1 OVP Operation
When the VD+, or VD– voltages rise above VOVP, the internal nFET switches are turned off, protecting the
transceiver from overvoltage conditions. The response is very rapid, with the FET switches turning off in less
than 1 µs. Before the OVP condition, the FLT pin is High-Z, and is pulled HIGH via an external resistor to
indicate there is no fault. Once the OVP condition occurs, the FLT pin is asserted LOW. When the VD+, or VD–
voltages returns below VOVP – VHYS-OVP, the nFET switches are turned on again. When the OVP condition is
cleared and the nFETs are completely turned on, the FLT is reset to high-Z.
8.3.2 OVP Threshold
5.0 V
4.5 V
4.5
1.875 V
0.9 V
4.0 V
0.375 V
VOVP = 0.75 V
1 / Ratio = 1.25
3.6 V
0.15 V
VREF = 0.6 V
1.5 V
Figure 20. OVP Threshold
The OVP Threshold VOVP is set by VREF according to Equation 1, Equation 2 and Equation 3.
VOVP
1.25 u VREF
(1)
VREF d 3.6 V
(2)
VOVP = 4.5 V for VREF > 3.6 V
(3)
Equation 1, Equation 2 and Equation 3 yield the typical VOVP values. See the parametric tables for the minimum
and maximum values that include variation over temperature and process. Figure 20 gives a graphical
representation of the relationship between VOVP and VREF.
VREF can be set either by an external regulator (Mode 0) or an internal adjustable regulator (Mode 1). See the
VREF Operation section for more details on how to operate VREF in Mode 0 and Mode 1.
8.3.3 D± Clamping Voltage
The TPD2S701-Q1 provides a differentiated device architecture which allows the system designer to control the
clamping voltage the protected transceiver sees from the D+ and D– pins. This architecture allows the system
designer to minimize the amount of stress the transceiver sees during ESD events. The clamping voltage that
appears on the D+ and D– lines during an ESD event obeys Equation 4.
VCLAMP _ DP / M VREF VBR IRDYN
(4)
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Feature Description (continued)
Where VBR approximately = 0.7 V, IRDYN approximately = 1 V. By adjusting VREF, the clamping voltage of the D+
and D– lines can be adjusted. As VREF also controls the OVP threshold, take care to insure that the VREF setting
both satisfies the OVP threshold requirements while simultaneously optimizing system protection on the D+ and
D– lines.
The size of the capacitor used on the VREF pin also influences the clamping voltage as transient currents during
ESD events flow into the VREF capacitor. This causes the VREF voltage to increase, and likewise the clamping
voltage on D± according to Equation 4. The larger capacitor that is used, the better the clamping performance of
the device is going to be. See the parametric tables for the clamping performance of the TPD2S701-Q1 with a 1µF capacitor.
8.4 Device Functional Modes
The TPD2S701-Q1 has two modes of operation which vary the way the VREF pin functions. In Mode 0, the
VREF pin is connected to an external regulator which sets the voltage on the VREF pin. In Mode 1, the
TPD2S701-Q1 uses an adjustable internal regulator to set the VREF voltage. Mode 1 enables the system
designer to operate the TPD2S701-Q1 with a single power supply, and have the flexibility to easily set the VREF
voltage to any voltage between 0.6 V and 3.8 V with two external resistors.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPD2S701-Q1 offers 2-channels of short-to-VBUS protection and IEC ESD protection for automotive high
speed interfaces such as USB 2.0. For the overvoltage protection (OVP), this device integrates N-channel FET’s
which quickly isolate (200 ns) the protected circuitry in the event of an overvoltage condition on the VD+ and
VD– lines. With respect to the ESD protection, the TPD2S701-Q1 has an internal clamping diode on each data
line (VD+ and VD–) which provides 8-kV contact ESD protection and 15-kV air-gap ESD protection. More details
on the internal components of the TPD2S701-Q1 can be found in the Overview section.
The TPD2S701-Q1 also has the ability to vary the OVP threshold based on the configuration of the Mode pin and
the voltage present on the VREF pin (0.6 V-4.5 V). This functionality is discussed in greater depth in the OVP
Threshold section. Once the VREF threshold is crossed, a fault is detectable to the user through the FLT pin,
where 5 V on the pin indicates no fault is detected, and 0 V-0.4 V represents a fault condition. Figure 21 shows
the TPD2S701-Q1 in a typical application, interfacing between the protected internal circuitry and the connector
side, where ESD vulnerability is at its highest.
9.2 Typical Application
VBAT
DC/DC
SW
VOUT
RSENSE
VIN
FB
Sens+
VBUS
D±
Sens-
TPD2S701-Q1
D-
VD-
Transciever
D+
VD+
D+
GND
VREF
/FLT
VPWR
/EN
MODE
CCLAMP
GND
RTOP
CPWR
DSK Package
(2.5mm x 2.5mm x 0.75mm)
5V
RBOT
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Figure 21. USB 2.0 Port With Short-to-VBUS and IEC ESD Protection
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Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Device Operation
Table 1 gives the complete device functionality in response to the EN pin, to overvoltage conditions at the
connector (VD± pins), to thermal shutdown, and to the conditions of the VPWR, VREF, and MODE pins.
Table 1. Device Operation Table
Functional Mode EN
MODE
VREF
VPWR
VD±
TJ
FLT
Comments
NORMAL OPERATION
Mode 0
unpowered 1
X
Rbot ≤ 2.6 kΩ
X
X
X
X
H
Device unpowered, data
switches open
Mode 0
unpowered 2
X
Rbot ≤ 2.6 kΩ
X
X
X
X
H
Device unpowered, data
switches open
Mode 1
unpowered
X
Rtop | | Rbot > 14 kΩ
X
X
X
X
H
Device unpowered, data
switches open
Mode 0 disabled
H
Rbot ≤ 2.6 kΩ
>UVLO
>UVLO
X
<TSD
H
Device disabled, data switches
open
Mode 1 disabled
H
Rtop | | Rbot > 14 kΩ
Set by Rtop
and Rbot
>UVLO
X
<TSD
H
Device disabled, data switches
open, VREF is disabled
Mode 0 enabled
L
Rbot ≤ 2.6 kΩ
>UVLO
>UVLO
<OVP
<TSD
H
Device enabled, data switches
closed, VREF is the value set
by the power supply on VREF
Mode 1 enabled
L
Rtop | | Rbot > 14 kΩ
Set by Rtop
and Rbot
>UVLO
<OVP
<TSD
H
Device enabled, data switches
closed, VREF is the value set
by the Rtop and Rbot resistor
divider
FAULT CONDITIONS
Mode 0 thermal
shutdown
X
Rbot ≤ 2.6 kΩ
X
>UVLO
X
>TSD
L
Thermal shutdown, data
switches opened, FLT pin
asserted
Mode 1 thermal
shutdown
X
Rtop | | Rbot > 14 kΩ
Set by Rtop
and Rbot
>UVLO
X
>TSD
L
Thermal shutdown, data
switches opened, VREF is
disabled, FLT pin asserted
L
Data line overvoltage
protection mode. OVP is set
relative to the voltage on VREF.
Data switches opened, FLT
pin asserted
L
Data line overvoltage
protection mode. OVP is set
relative to the voltage on VREF.
Data switches opened, fault
pin asserted
Mode 0 OVP fault
Mode 1 OVP fault
Rbot ≤ 2.6 kΩ
>UVLO
Rtop | | Rbot > 14 kΩ
Set by Rtop
and Rbot
L
L
>UVLO
>UVLO
>OVP
>OVP
<TSD
<TSD
9.2.2 Detailed Design Procedure
9.2.2.1 VREF Operation
The TPD2S701-Q1 has two modes of operation which vary the way the VREF pin functions. In Mode 0, the VREF
pin is connected to an external regulator which sets the voltage on the VREF pin. In Mode 1, the TPD2S701-Q1
uses an adjustable internal regulator to set the VREF voltage. Mode 1 enables the system designer to operate the
TPD2S701-Q1 with a single power supply, and have the flexibility to easily set the VREF voltage to any voltage
between 0.6 V and 3.8 V with two external resistors.
9.2.2.1.1 Mode 0
To set the device into Mode 0, ensure that Rbot, resistance between the MODE pin and ground, is less than 2.6
kΩ. The easiest way to implement Mode 0 is to directly connect the mode pin to GND on your PCB. With this
resistance condition met, connect VREF to an external regulator to set the VREF voltage.
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9.2.2.1.2 Mode 1
To operate in Mode 1, ensure that Rtop || Rbot, resistance between the MODE pin and ground, is greater than 14
kΩ. This is accomplished by insuring Rtop || Rbot > 14 kΩ because when the device is initially powered up, VREF is
at ground until the internal circuitry recognizes if the device is in Mode 1 or Mode 2.
In Mode 1, VREF is set by using an internal regulator to set the voltage. Using a resistor divider off of a feedback
comparator is how to set VREF, similar to a standard LDO or DC/DC. VREF is set in Mode 1 according to
Equation 5.
VMODE RTOP RBOT
VREF
RBOT
(5)
Equation 5 yields the typical value for VREF. When using ±1% resistors RTOP and RBOT, VREF accuracy is going to
be ±5%. Therefore, the minimum and maximum values for VREF can be calculated off of the typical VREF. The
parametric tables above give example RTOP and RBOT resistors to use for standard output VREF voltages for Mode
1.
9.2.2.2 Mode 1 Enable Timing
In Mode 1, when the TPD2S701-Q1 is disabled, the output regulator is disabled, leading VREF to discharge to 0 V
through RTOP and RBOT. It is desired for VREF to be at 0 V when the device is disabled to minimize the clamping
voltage during a power disabled ESD event. If VREF is at 0 V, this holds D± near ground during these fault
events.
When enabling the TPD2S701-Q1, VREF is quickly charged up to insure a quick turnon time of the Data FETs.
Data FET turnon is gated by VREF reaching 80% of its final voltage plus 150 µs to insure a proper OVP threshold
is set before passing data. This prevents false OVPs due to normal operation. Because Data FET turnon is gated
by charging the VREF clamping capacitor, the size of the capacitor influences the turnon time of the Data
switches. The TPD2S701-Q1’s internal regulator uses a constant current source to quickly charge the VREF
clamping capacitor, so the charging time of CVREF can easily be calculated with Equation 6.
CVREF u 0.8 VREFFINAL
tCHG _ CVREF
ICHG _ VREF
(6)
Where CVREF is the clamping capacitance on VREF, VREFFINAL is the final value VREF is set to, and ICHG_VREF = 22
mA (typical). If VREF = 1 V, 0.8 is used in the above equation because 80% of VREF is the amount of time that
gates the turnon of the Data FETs. Once tCHG_CVREF is calculated, the typical turnon time of the Data FETs can
be calculated from Equation 7.
tON_EN_MODE1 = tCHG_CVREF + 150 Ps
20
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(7)
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Product Folder Links: TPD2S701-Q1
TPD2S701-Q1
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SLLSEY0A – APRIL 2017 – REVISED JULY 2017
9.2.3 Application Curves
Figure 22. USB2.0 Eye Diagram (Board Only, Through
Path)
Figure 23. USB2.0 Eye Diagram (System from Typical
Application Schematic)
10 Power Supply Recommendations
10.1 VPWR Path
The VPWR pin provides power to the TPD2S701-Q1. A 10-μF capacitor is recommended on VPWR as close to the
pin as possible for localized decoupling of transients. A supply voltage above the UVLO threshold for VPWR must
be supplied for the device to power on.
10.2 VREF Pin
The VREF pin provides a voltage reference for the data switch OVP level as well as a bypass for ESD clamping. A
1-μF capacitor must be placed as close to the pin as possible and the supply must be set to be above the UVLO
threshold for VREF.
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21
TPD2S701-Q1
SLLSEY0A – APRIL 2017 – REVISED JULY 2017
www.ti.com
11 Layout
11.1 Layout Guidelines
Proper routing and placement maintains signal integrity for high-speed signals. The following guidelines apply to
the TPD2S701-Q1:
• Place the bypass capacitors as close as possible to the VPWR and VREF pins. Capacitors must be attached
to a solid ground. This minimizes voltage disturbances during transient events such as ESD or overcurrent
conditions.
• High speed traces (data switch path) must be routed as straight as possible and any sharp bends must be
minimized.
Standard ESD recommendations apply to the VD+, VD- pins as well:
• The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
11.2 Layout Example
TPS2S701-Q1
Figure 24. TPD2S701-Q1 Layout
22
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TPD2S701-Q1
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SLLSEY0A – APRIL 2017 – REVISED JULY 2017
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
TPD2S701-Q1 Evaluation Module User's Guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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TPD2S701-Q1
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www.ti.com
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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Product Folder Links: TPD2S701-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPD2S701QDGSRQ1
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
15R
TPD2S701QDSKRQ1
ACTIVE
SON
DSK
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
14H
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2017
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-May-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPD2S701QDGSRQ1
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TPD2S701QDSKRQ1
SON
DSK
10
3000
180.0
8.4
2.8
2.8
1.0
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-May-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD2S701QDGSRQ1
VSSOP
DGS
10
2500
366.0
364.0
50.0
TPD2S701QDSKRQ1
SON
DSK
10
3000
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
SCALE 3.200
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
10
1
3.1
2.9
NOTE 3
8X 0.5
2X
2
5
6
B
10X
3.1
2.9
NOTE 4
SEE DETAIL A
0.27
0.17
0.1
C A
1.1 MAX
B
0.23
TYP
0.13
0.25
GAGE PLANE
0 -8
0.15
0.05
0.7
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (0.3)
10X (1.45)
(R0.05)
TYP
SYMM
1
10
SYMM
8X (0.5)
6
5
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
10X (0.3)
SYMM
1
(R0.05) TYP
10
SYMM
8X (0.5)
6
5
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DSK 10
2.5 x 2.5 mm, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225304/A
PACKAGE OUTLINE
DSK0010A
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
2.6
2.4
B
A
PIN 1 INDEX AREA
2.6
2.4
C
0.8 MAX
SEATING PLANE
0.08 C
(0.2) TYP
EXPOSED
THERMAL PAD
0.05
0.00
1.2 0.1
6
5
2X
2
11
2 0.1
1
10
8X 0.5
PIN 1 ID
(OPTIONAL)
10X
0.45
0.35
10X
0.3
0.2
0.1
0.05
C A B
C
4218903/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSK0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.6)
(1.2)
10
1
10X (0.25)
SYMM
11
(2)
8X (0.5)
(R0.05) TYP
(0.75)
5
6
(0.35)
( 0.2) VIA
TYP
SYMM
(2.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218903/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DSK0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.6)
SYMM
10
1
METAL
TYP
10X (0.25)
SYMM
11
8X (0.5)
(0.89)
(R0.05) TYP
5
6
(1.13)
(2.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4218903/A 01/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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