Texas Instruments | TPD5S115 HDMI Companion Chip With Step-Up DC-DC Converter, Level-Shifter, and ESD Clamp (Rev. D) | Datasheet | Texas Instruments TPD5S115 HDMI Companion Chip With Step-Up DC-DC Converter, Level-Shifter, and ESD Clamp (Rev. D) Datasheet

Texas Instruments TPD5S115 HDMI Companion Chip With Step-Up DC-DC Converter, Level-Shifter, and ESD Clamp (Rev. D) Datasheet
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TPD5S115
SLVSBL2D – OCTOBER 2012 – REVISED JUNE 2017
TPD5S115 HDMI Companion Chip With Step-Up DC-DC Converter,
Level-Shifter, and ESD Clamp
1 Features
3 Description
•
The TPD5S115 device is an integrated HDMI
companion chip solution. The device provides a
regulated 5-V output (5VOUT) for sourcing the HDMI
power line. The regulated 5-V output supplies up to
55 mA to the HDMI receiver with a current limiting
function. The TPD5S115 features two control signals:
EN and LS_OE. The control of 5VOUT and the hot
plug detect (HPD) circuitry is independent of the
LS_OE control signal and is controlled by the EN pin.
The EN pin allows the detection scheme (5VOUT +
HPD) to be active before turning on the whole HDMI
link. The LS_OE activates the internal LDO, CEC,
SCL, and SDA buffers only when EN is also
activated. This dual stage enable scheme ensures
optimized power saving for portable applications.
1
•
•
•
•
•
•
•
Conforms to HDMI Compliance Tests Without Any
External Components
Supports HDMI 2.0, HDMI 1.4, and HDMI 1.3
Standards
Matches HDMI Connector Pin Mapping
Internal DC-DC Converter to Generate 5 V From a
Battery Voltage as Low as 2.3 V
Auto-Direction Sensing, Level Shifting, and
Buffering in the CEC, SDA, and SCL Paths
IEC 61000-4-2 (Level 4) System Level ESD
Compliance
Reverse Current Blocking and Short-Circuit
Protection to Protect Against Fault Conditions
Industrial Temperature Range: –40°C to 85°C
2 Applications
•
•
•
•
•
•
Set-Top Boxes
TVs
Smart Phones
Digital Camcorders
Portable Game Consoles
Digital Still Cameras
There are three noninverting, bidirectional, voltage
level translation circuits for the SDA, SCL, and CEC
lines. Each have a common power rail (VCCA) on the
A side from 1.1 V to 3.6 V. On the B side, the SCL_B
and SDA_B each have an internal 1.75-kΩ pullup
connected to the regulated 5-V rail (5VOUT). The
DDC (SCL_B and SDA_B) pins meet the I2C
specification and drive up to 750-pF loads with the
buffers. The CEC_B pin has an internal 27-kΩ pullup
to an internal 3.3-V supply. The TPD5S115 exceeds
the IEC61000-4-2 (Level 4) ESD protection level. This
device features a space saving, 1.72-mm × 1.72-mm,
YFF package with 0.4-mm pitch.
Device Information(1)
PART NUMBER
TPD5S115
PACKAGE
DSBGA (16)
BODY SIZE (NOM)
1.72 mm × 1.72 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical System Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD5S115
SLVSBL2D – OCTOBER 2012 – REVISED JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
Electrical Characteristics – I/O Capacitances ........... 7
Switching Characteristics – VCCA = 1.2 V ................. 7
Switching Characteristics – VCCA = 1.5 V ................. 8
Switching Characteristics – VCCA = 1.8 V ................. 8
Switching Characteristics – VCCA = 2.5 V ............... 9
Switching Characteristics – VCCA = 3.3 V ............. 10
Typical Characteristics .......................................... 11
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
13
15
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Applications ................................................ 16
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2016) to Revision D
•
Page
Updated Pinout image ........................................................................................................................................................... 3
Changes from Revision B (March 2013) to Revision C
Page
•
Added Device Information table, Pin Configuration and Functions section, Specifications section, ESD Ratings table,
Detailed Description section, Application and Implementation section, Power Supply Recommendations section,
Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section .................................................................................................................................................................................... 1
•
Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
•
Added Thermal Information table ........................................................................................................................................... 5
•
Moved the passive components parameters from Recommended Operating Conditions table to the Output
Capacitor section .................................................................................................................................................................. 18
Changes from Revision A (February 2013) to Revision B
•
2
Page
Changed Board Layout section ............................................................................................................................................ 21
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SLVSBL2D – OCTOBER 2012 – REVISED JUNE 2017
5 Pin Configuration and Functions
YFF Package
16-Pin DSBGA
Top View
A
B
C
D
1
2
3
4
SCL_B
GND
HPD_B
VCCA
CEC_B
SDA_B
LS_OE
HPD_A
5VOUT
SW
EN
SDA_A
PGND
VBAT
CEC_A
SCL_A
Not to scale
Pin Functions
PIN
TYPE (1)
DESCRIPTION
C1
O
DC-DC output. The 5-V power pin can supply a 55-mA regulated current to the HDMI receiver. A
separate DC-DC converter control pin (EN) disables the DC-DC converter when operating at lowpower mode
CEC_A
D3
I/O
LS system side CEC bus I/O. This pin is bidirectional and referenced to VCCA
CEC_B
B1
I/O
LS HDMI connector side CEC bus I/O. This pin is bidirectional and referenced to the 3.3-V internal
supply
EN
C3
C
DC-DC enable. Enables the DC-DC converter and HPD circuitry when EN is HIGH. The EN is
referenced based off VCCA
GND
A2
G
Device ground
HPD_A
B4
O
System side output for the hot plug detect. This pin is unidirectional and is referenced to VCCA
HPD_B
A3
I
HDMI side input for the hot plug detect. This pin is unidirectional and is referenced to 5VOUT
LS_OE
B3
C
Level shifter enable. This pin is referenced to VCCA. Enables level shifters and LDO when EN is
HIGH and LS_OE is HIGH
PGND
D1
G
DC-DC converter ground. These pins are isolated from the GND pins. This pin should be tied to
system GND
SCL_A,
SDA_A
D4, C4
I/O
LS system side input and output for I2C Bus. These pins are bidirectional and referenced to VCCA
SCL_B,
SDA_B
A1, B2
I/O
LS HDMI side connector side input and output for I2C Bus. These pins are bidirectional and
referenced to 5VOUT
SW
C2
I
Switch input. This pin is the inductor input for the DC-DC converter
VBAT
D2
P
Battery supply. This voltage is typically 2.3 V to 5.5 V
VCCA
A4
P
System side supply. This voltage is typically 1.2 V to 3.3 V from the core microcontroller
NAME
NO.
5VOUT
(1)
C = Control, G = Ground, I = Input, O = Output, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VCCA
Supply voltage
MAX
UNIT
4
V
V
VBAT
–0.3
6
SCL_A, SDA_A, CEC_A
–0.3
4
SCL_B, SDA_B, CEC_B, HPD_B
–0.3
6
EN, LS_OE
–0.3
4
SCL_A, SDA_A, CEC_A
–0.3
4
SCL_B, SDA_B, CEC_B
–0.3
6
SCL_A, SDA_A, CEC_A
–0.3
VCCA + 0.3
SCL_B, SDA_B, CEC_B
–0.3
5VOUT +
0.3
V
–50
mA
Output clamp current (VO < 0)
–50
mA
Continuous current through 5VOUT, or GND
±100
mA
150
°C
Input voltage, VI (2)
Voltage applied to any output in the high-impedance or
power‑off state, VO (2)
Voltage applied to any output in the high or low state, VO (2)
Input clamp current (IV < 0)
Storage temperature, Tstg
(1)
(2)
–65
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
6.2 ESD Ratings
VALUE
All pins except pins 4A, B3, C3,
C4, D3, and D4
500
Pins 4A, B3, C3, C4, D3, and D4
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
(1)
(2)
Electrostatic discharge
IEC 61000-4-2 Contact Discharge
Pins A1, A3, B1, B2, and C1
±14000
IEC 61000-4-2 Air-gap Discharge
Pins A1, A3, B1, B2, and C1
±16000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCCA
Supply voltage, VCCA
VBAT
Supply voltage, VBAT
1.2
VCCA = 1.2 V to 3.6 V
High-level input voltage
(1)
4
3.6
V
V
2.3
5.5
0.7 × VCCA
VCCA
CEC_A
0.7 × VCCA
VCCA
1
VCCA
0.7 ×
5VOUT
5VOUT
CEC_B
0.7 × 3.3 V
(internal) (1)
3.3 V
(internal) (1)
HPD_B
2
SCL_B, SDA_B
5VOUT = 5 V
MAX UNIT
SCL_A, SDA_A
EN, LS_OE
VIH
NOM
V
3.3 V (internal) is an internally generated voltage node for the CEC_B output buffer supply reference. An LDO generates this 3.3 V from
5VOUT when LS_OE and EN are HIGH.
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
VCCA = 1.2 V to 3.6 V
VIL
Low-Level input voltage
5VOUT = 5 V
VILC
Low-level input voltage
VOL – VILC
Delta between VOL and VILC (VIO = 2.5 V)
TA
Operating free-air temperature
NOM
MAX UNIT
SCL_A, SDA_A
–0.5
0.082 × VCCA
CEC_A
–0.5
0.082 × VCCA
EN, LS_OE
–0.5
0.4
SCL_B, SDA_B
–0.5
0.3 × 5VOUT
CEC_B
–0.5
0.3 × 3.3
(internal) (1)
HPD_B
0
0.8
–0.5
V
0.065 × VCCA
V
85
°C
0.1 × VCCA
V
–40
6.4 Thermal Information
TPD5S115
THERMAL METRIC (1)
YFF (DSBGA)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
78.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.6
°C/W
RθJB
Junction-to-board thermal resistance
13.2
°C/W
ψJT
Junction-to-top characterization parameter
2.5
°C/W
ψJB
Junction-to-board characterization parameter
13
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOHA
IOH = –10 µA, VI = VIH, VCCA = 1.2 V to 3.6 V
VOLA
IOL = 10 µA, VI = VIL, VCCA = 1.2 V to 3.6 V
VOHB
IOH = –10 µA, VI = VIH
VOLB
IOL = 3 mA, VI = VIL
SCL_A, SDA_A
Pullup connected to VCCA rail
MIN
TYP
V
10
SCL_B, SDA_B
Pullup connected to 5-V rail
1.75
IPULLUPAC
Transient boosted
pullup current
SCL_B, SDA_B
(rise-time accelerator)
Pullup connected to 5-V rail
15
IOFF
Leakage current
Bus load capacitance
V
0.4
Internal pullup
CL
UNIT
V
VCCA × 0.16
RPU
IOZ
MAX
VCCA × 0.8
V
kΩ
mA
A port
VCCA = 0 V, VI or VO = 0 to 3.6 V, VCCA = 0 V
±5
B port
5VOUT = 0 V, VI or VO = 0 to 5.5 V, VCCA = 0 V to 3.6
V
±5
A port
VO = VCCO or GND, VCCA = 1.2 V to 3.6 V
±5
B port
VI = VCCI or GND, VCCA = 1.2 V to 3.6 V
µA
±5
A port
15
B port
750
pF
SUPPLY CURRENT
ICCA
ICCB
VCCA supply current
VBAT supply current
Standby
I/Os = HIGH
2
µA
Active
I/Os = HIGH
15
µA
Standby
EN = LOW, LS_OE = LOW
0.5
DC-DC and
HPD active
EN = HIGH, LS_OE = LOW
30
50
µA
DC-DC, HPD,
DDC, CEC Active
EN = HIGH, LS_OE = LOW, I/Os = HIGH
225
300
µA
µA
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Electrical Characteristics (continued)
TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC-DC CONVERTER
VBAT
Input voltage
2.3
5.5
V
VOUT
Total DC output voltage (1)
4.9
5
5.13
V
TOVA
Total output voltage accuracy (2)
4.8
5
5.3
V
IO = 65 mA
50.6
VIO_Ripple
Output voltage ripple, loaded
fCLK
Internal operating frequency
VBAT = 2.3 V to 5.5 V
3.5
MHz
tSTART
Start-up time
From EN input to 5-V power output 90% point
187
µs
Output current
VBAT = 2.3 V to 5.5 V
Reverse leakage current, VO
EN = LOW, VO = 5.5 V
Leakage current from battery to VO
EN = LOW
IO
IO = 150 mA
mVPP
16
55
mA
2.5
µA
5
µA
Falling
2
V
Rising
2.1
V
Line transient response
VBAT = 3.4 V, IO = 20 mA to 65 mA, A 217 Hz,
600 mVPP square wave pulse
17.1
mVpk
Load transient response
VBAT = 3.4 V, IO = 5 mA to 65 mA, 10-µs pulse,
tRISE = tFALL = 0.1 µs
63.5
mVpk
IINRUSH
Inrush current, average over tSTART
VBAT = 2.3 V to 5.5 V, IOUT = 65 mA
168
mA
ISC
Short-circuit current limit from output
90
mA
VBATUV
Undervoltage lockout threshold
VOLTAGE LEVEL SHIFTER CEC LINE (x_A & x_B PORTS)
VOHA
IOH = –10 µA, VI = VIH, VCCA = 1.2 V to 3.6 V
VOLA
IOL = 10 µA, VI = VIL, VCCA = 1.2 V to 3.6 V
VOHB
IOH = –20 µA, VI = VIH
VOLB
IOL = 3 mA, VI = VIL
RPU
Internal pullup
RPD
Internal pulldown
IOFF
IOZ
VCCA × 0.8
V
VCCA × 0.16
V
VCCA × 0.8
V
0.4
CEC_A
Pullup connected to VCCA rail
10
CEC_B
Pullup connected to 3.3 V rail
CEC_B
Pullup connected to GND
A port
VCCA = 0 V, VI or VO = 0 to 3.6 V, VCCA = 0 V
B port
5VOUT = 0 V, VI or VO = 0 to 5.5 V, VCCA = 0 V to 3.6
V
A port
VO = VCCO or GND, VCCA = 1.2 V to 3.6 V
±5
B port
VI = VCCI or GND, VCCA = 1.2 V to 3.6 V
±5
22
26
30
14
V
kΩ
MΩ
±5
±1.8
µA
VOLTAGE LEVEL SHIFTER - HPD LINE (X_A & x_B)
VOHA
IOH = –3 mA, VI = VIH, VCCA = 1.2 V to 3.6 V
VOLA
IOL = 3 mA, VI = VIL, VCCA = 1.2 V to 3.6 V
RPD
Internal pulldown
IOZ
HPD_B
Pullup connected to GND
A port
VI = VCCI or GND, VCCA = 3.6 V
VCCA × 0.7
V
0.4
100
V
kΩ
±5
µA
LS_OE, EN
II
VI = VCCA or GND, VCCA = 1.2 V to 3.6 V
(1)
(2)
Includes voltage references, DC load and line regulations, process and temperature.
Includes voltage references, DC load and line regulations, transient load and line regulations, ripple, process, and temperature.
6
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6.6 Electrical Characteristics – I/O Capacitances
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
EN, LS_OE
SCL_A, SDA_A, CEC_A
VBIAS = 1.8 V, f = 1 MHz,
30-mVPP AC signal
HPD_A, HPD_B
Capacitance
SCL_B, SDA_B
CEC_B
CEC_B
MIN
VCCA = 3.6 V, VBAT = 5 V
VBIAS = 2.5 V, f = 100 kHz,
3.5-VPP AC signal
VBIAS = 1.65 V, f = 100 kHz,
2.5-VPP AC signal
TYP
MAX
7.1
9.5
UNIT
pF
VCCA = 3.6 V, VBAT = 5 V, EN = LOW
7
pF
VCCA = 3.6 V, VBAT = 5 V, EN = LOW
4
pF
VCCA = 3.6 V, VBAT = 5 V, EN = LOW,
LS_OE = HIGH
10
pF
VCCA = 3.6 V, VBAT = 5 V, EN = LOW,
LS_OE = HIGH
7
pF
VCCA = 0 V, 5V_IN = 0 V
7
pF
6.7 Switching Characteristics – VCCA = 1.2 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SCL and SDA LINES (x_A & x_B PORTS)
tPHL
High-to-low propagation delay
tPLH
Low-to-high propagation delay
tFALL
Fall time
tRISE
Rise time
fMAX
Maximum switching frequency
A to B
DDC channels enabled
394
B to A
DDC channels enabled
347
A to B
DDC channels enabled
504
B to A
DDC channels enabled
171
A port
DDC channels enabled
146
B port
DCC channels enabled
135
A port
DCC channels enabled
190
B port
DCC channels enabled
93
DCC channels enabled
400
ns
ns
ns
ns
kHz
CEC LINE (x_A & x_B PORTS)
tPHL
High-to-low propagation delay
tPLH
Low-to-high propagation delay
tFALL
Fall time
tRISE
Rise time
A to B
CEC channels enabled
550
B to A
CEC channels enabled
350
A to B
CEC channels enabled
13
µs
B to A
CEC channels enabled
290
ns
A port
CEC channels enabled
146
B port
CEC channels enabled
200
A port
CEC channels enabled
190
ns
B port
CEC channels enabled
16.4
µs
ns
ns
HPD LINE (x_A & x_B PORTS)
tPHL
Propagation delay
B to A
CEC channels enabled
10.4
ns
tPLH
Low-to-high propagation delay
B to A
CEC channels enabled
9.9
ns
tFALL
Fall time
A port
CEC channels enabled
0.7
ns
tRISE
Rise time
A port
CEC channels enabled
0.8
ns
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6.8 Switching Characteristics – VCCA = 1.5 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SCL, SDA LINES (x_A & x_B PORTS)
tPHL
High-to-low propagation delay
tPLH
Low-to-high propagation delay
tFALL
Fall time
tRISE
Rise time
fMAX
Maximum switching frequency
A to B
DDC channels enabled
375
B to A
DDC channels enabled
272
A to B
DDC channels enabled
488
B to A
DDC channels enabled
166
A port
DDC channels enabled
114
B port
DCC channels enabled
135
A port
DCC channels enabled
186
B port
DCC channels enabled
93
DCC channels enabled
ns
ns
ns
ns
400
kHz
CEC Line (x_A & x_B Ports)
tPHL
High-to-low propagation delay
tPLH
Low-to-high propagation delay
tFALL
Fall time
tRISE
Rise time
A to B
CEC channels enabled
536
B to A
CEC channels enabled
272
A to B
CEC channels enabled
13
µs
B to A
CEC channels enabled
285
ns
A port
CEC channels enabled
113
B port
CEC channels enabled
201
A port
CEC channels enabled
187
ns
B port
CEC channels enabled
16
µs
ns
ns
HPD LINE (x_A & x_B PORTS)
tPHL
High-to-low propagation delay
B to A
CEC channels enabled
10
ns
tPLH
Low-to-high propagation delay
B to A
CEC channels enabled
10
ns
tFALL
Fall time
A port
CEC channels enabled
0.46
ns
tRISE
Rise time
A port
CEC channels enabled
0.5
ns
6.9 Switching Characteristics – VCCA = 1.8 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SCL, SDA LINES (x_A & x_B PORTS)
tPHL
High-to-low propagation delay
tPLH
Low-to-high propagation delay
tFALL
Fall time
tRISE
Rise time
fMAX
Maximum switching frequency
A to B
DDC channels enabled
370
B to A
DDC channels enabled
230
A to B
DDC channels enabled
480
B to A
DDC channels enabled
163
A port
DDC channels enabled
100
B port
DCC channels enabled
135
A port
DCC channels enabled
180
B port
DCC channels enabled
93
DCC channels enabled
400
ns
ns
ns
ns
kHz
CEC LINE (x_A & x_B PORTS)
tPHL
High-to-low propagation delay
tPLH
Low-to-high propagation delay
tFALL
8
Fall time
A to B
CEC channels enabled
530
B to A
CEC channels enabled
230
A to B
CEC channels enabled
13
µs
B to A
CEC channels enabled
280
ns
A port
CEC channels enabled
98
B port
CEC channels enabled
200
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ns
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Switching Characteristics – VCCA = 1.8 V (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tRISE
Rise time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
A port
CEC channels enabled
180
ns
B port
CEC channels enabled
16
µs
HPD LINE (x_A & x_B PORTS)
tPHL
High-to-low propagation delay
B to A
CEC channels enabled
10
ns
tPLH
Low-to-high propagation delay
B to A
CEC channels enabled
10
ns
tFALL
Fall time
A port
CEC channels enabled
0.41
ns
tRISE
Rise time
A port
CEC channels enabled
0.41
ns
6.10 Switching Characteristics – VCCA = 2.5 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SCL, SDA LINES (x_A & x_B PORTS)
tPHL
High-to-low propagation delay
tPLH
Low-to-high propagation delay
tFALL
Fall time
tRISE
Rise time
fMAX
Maximum switching frequency
A to B
DDC channels enabled
370
B to A
DDC channels enabled
185
A to B
DDC channels enabled
467
B to A
DDC channels enabled
160
A port
DDC channels enabled
80
B port
DCC channels enabled
135
A port
DCC channels enabled
179
B port
DCC channels enabled
93
DCC channels enabled
400
ns
ns
ns
ns
kHz
CEC LINE (x_A & x_B PORTS)
tPHL
High-to-low propagation delay
tPLH
Low-to-high propagation delay
tFALL
Fall time
tRISE
Rise time
A to B
CEC channels enabled
530
B to A
CEC channels enabled
185
A to B
CEC channels enabled
13
µs
B to A
CEC channels enabled
275
ns
A port
CEC channels enabled
80
B port
CEC channels enabled
200
A port
CEC channels enabled
180
ns
B port
CEC channels enabled
16
µs
ns
ns
HPD LINE (x_A & x_B PORTS)
tPHL
High-to-low propagation delay
B to A
CEC channels enabled
10
ns
tPLH
Low-to-high propagation delay
B to A
CEC channels enabled
10
ns
tFALL
Fall time
A port
CEC channels enabled
0.35
ns
tRISE
Rise time
A port
CEC channels enabled
0.35
ns
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6.11 Switching Characteristics – VCCA = 3.3 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SCL, SDA LINES (x_A & x_B PORTS)
tPHL
High-to-low propagation delay
tPLH
Low-to-high propagation delay
tFALL
Fall time
tRISE
Rise time
fMAX
Maximum switching frequency
A to B
DDC channels enabled
370
B to A
DDC channels enabled
160
A to B
DDC channels enabled
460
B to A
DDC channels enabled
155
A port
DDC channels enabled
75
B port
DCC channels enabled
135
A port
DCC channels enabled
180
B port
DCC channels enabled
93
DCC channels enabled
400
ns
ns
ns
ns
kHz
CEC LINE (x_A & x_B PORTS)
tPHL
High-to-low propagation delay
tPLH
Low-to-high propagation delay
tFALL
Fall time
tRISE
Rise time
A to B
CEC channels enabled
530
B to A
CEC channels enabled
160
A to B
CEC channels enabled
13
µs
B to A
CEC channels enabled
275
ns
A port
CEC channels enabled
73
B port
CEC channels enabled
200
A port
CEC channels enabled
180
ns
B port
CEC channels enabled
16
µs
ns
ns
HPD LINE (x_A & x_B PORTS)
tPHL
High-to-low propagation delay
B to A
CEC channels enabled
10
ns
tPLH
Low-to-high propagation delay
B to A
CEC channels enabled
10
ns
tFALL
Fall time
A port
CEC channels enabled
0.34
ns
tRISE
Rise time
A port
CEC channels enabled
0.36
ns
10
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6.12 Typical Characteristics
6
6
EN
5VOUT @ 55mA
5VOUT @ 65mA
5
4
4
Voltage (V)
3
2
1
3
2
1
0
0
VCCA = VIH = 2.5V, VBAT = 3.6V
VCCA = VIH = 2.5V, VBAT = 3.6V
±1
±1
0
500
1000
1500
2000
2500
3000
3500
Time ( s)
4000
±50
0
6
8
10
12
14
16
18
VBAT Voltage (V)
V5VOUT Voltage (mA)
I5VOUT Current (mA)
V5VOUT
4
200
250
300
C002
4.0
5.04
3.9
5.02
3.8
5.00
3.7
4.98
3.6
4.96
3.5
4.94
3.4
4.92
3.3
4.90
3.2
4.88
3.1
4.86
VBAT
3.0
4.84
5VOUT (20mA)
2.9
4.82
5VOUT (65mA)
2.8
20
Time( s)
0
4.80
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time ( s)
C003
Figure 3. Current vs Time
C004
Figure 4. Voltage vs Time
5.0
5.16
4.5
5.12
Iout = 65mA
V5VOUT Output Voltage (V)
4.0
Frequency (MHz)
150
Figure 2. Voltage vs Time
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
I5VOUT
2
100
Time ( s)
Figure 1. Voltage vs Time
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
0
50
C001
5VOUT Voltage (V)
Voltage (V)
EN
5VOUT @ 55mA
5VOUT @ 65mA
5
3.5
3.0
2.5
2.0
1.5
1.0
VBAT = 3V
0.5
100
150
200
5.04
5.00
4.96
4.92
4.88
4.84
VBAT = 4V
0.0
Iout = 100mA
5.08
4.80
250
300
350
400
450
Output Current (mA)
500
2.3
2.6
Figure 5. Frequency vs Output Current
2.9
3.2
3.5
3.8
4.1
4.4
4.7
5.0
VBAT Input Voltage (V)
C005
5.3
C006
Figure 6. Output Voltage vs Input Voltage
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Typical Characteristics (continued)
VEN
6
T = 25ƒC
0.40
0.30
0.25
0.20
0.15
VCCA = VIH = 1.8V
VBAT = 3.6V
TA = 25ƒC
V5VOUT (V)
5
T = 85ƒC
0.35
Voltage (V)
Supply Current (mA)
0.7
7
T = ±40ƒC
0.45
0.6
0.5
I5VOUT (A)
4
0.4
3
0.3
2
0.2
1
0.1
0
0.0
Current (A)
0.50
0.10
0.05
±0.1
±1
0.00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Supply Voltage (V)
±50
6.0
0
5.00
150
200
250
300
350
400
450
Time ( s)
C008
Figure 8. Voltage and Current vs Time
100
VBAT = 2.3V
VBAT = 3.0V
VBAT = 3.6V
VBAT = 4.2V
90
80
70
Efficiency (%)
Output Voltage (V)
5.02
100
C007
Figure 7. Supply Current vs Supply Voltage
5.04
50
4.98
4.96
60
50
40
30
4.94
20
4.92
Iout = 10mA
10
4.90
Iout = 100mA
0
1m
10m
Output Current (A)
100m
2.3
2.8
3.3
3.8
4.3
4.8
Input Voltage (V)
C009
Figure 9. Output Voltage vs Output Current
5.3
C010
Figure 10. Efficiency vs Input Voltage
100
90
80
Efficiency (%)
70
60
50
40
30
VBAT = 2.3V
VBAT = 3.0V
VBAT = 3.6V
VBAT = 4.2V
20
10
0
1m
10m
100m
Output Current (A)
1
C011
Figure 11. Efficiency vs Output Current
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7 Detailed Description
7.1 Overview
The TPD5S115 is an integrated interface solution that covers HDMI versions' 2.0, 1.4, and 1.3 need for power
supply voltage management and control line level translation. On the power supply line, it has a DC-DC
converter that takes the internal power supply from 2.3 V to 5.5 V, and outputs a regulated and current-limited,
5‑V voltage to the connector. The drivers support level translation on HPD, ECE, SCL, and SDA lines in both
transmission directions. Moreover, the rise-time acceleration feature helps drive the high capacitive load on the
cable side. Every channel comes with robust ESD protection with ±14-kV contact and ±16-kV air-gap
IEC61000‑4-2 capability.
7.2 Functional Block Diagram
(1)
3.3 V (internal) is an internal 3.3-V supply rail which is generated from 5VOUT when EN and LS_OE are HIGH.
(2)
LS_OE_INT is an internal control signal generated from EN and LS_OE signals. LS_OE_INT is active when both EN
and LS_OE are HIGH.
7.3 Feature Description
7.3.1 Rise-Time Accelerators
The HDMI cable side of the DDC lines incorporates rise-time accelerators to support the high capacitive load on
the HDMI cable side. The rise-time accelerator boosts the cable-side DDC signal, independent of which side of
the bus is releasing the signal.
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Feature Description (continued)
TPD5S115
Copyright © 2016, Texas Instruments Incorporated
Figure 12. Receiving and Transmitting Interaction
7.3.2 Hot Plug Detect
After the TPD5S115’s DC-DC converter and HPD block are enabled through the EN pin, the TPD5S115 is ready
for continual HDMI receiver detection. After a HDMI cable connects a receiving and transmitting device together,
the 5-V signal from the DC-DC output flows through the receiving device’s internal resistor and into HPD’s input.
The HPD buffer’s output then goes high, indicating to the transmitter that a receiving device is connected. To
save power, periodic detection can be done by turning on and off the DC-DC converter before a receiving device
is connected.
NOTE
Ground offset between the TPD5S115 ground and the ground of devices on port A of the
TPD5S115 must be avoided. A CMOS or NMOS open-drain capable of sinking 3 mA of
current at 0.4 V has an output resistance of 133 Ω or less (R = E / I). Such a driver shares
enough current with the port A output pulldown of the TPD5S115 to be detected as a LOW
while the ground offset is zero. If the ground offset is greater than 0 V, then the driver
resistance must be less. Because VILC can be as low as 90 mV at cold temperatures and
the low end of the current distribution, the maximum ground offset should not exceed 50
mV. Bus repeaters that use an output offset are not interoperable with the port A of the
TPD5S115 as their output LOW levels are not recognized by the TPD5S115 as a LOW. If
the TPD5S115 is placed in an application where the VIL of port A of the TPD5S115 does
not go below its VILC it will pull port B LOW initially when port A input transitions LOW but
the port B will return HIGH, so it does not reproduce the port A input on port B. Such
applications must be avoided. Port B is interoperable with all I2C-bus slaves, masters, and
repeaters.
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Feature Description (continued)
7.3.3 CEC Level Shift Operation
The CEC level shift function operates in the same manner as the DDC lines except that the CEC line does not
need the rise time accelerator function.
7.3.4 Pullup Resistor
The system is designed to work properly with no external pullup resistors on the DDC, CEC, and HPD lines.
7.3.5 Undervoltage Lockout
The undervoltage-lockout circuit prevents the DC-DC converter from malfunctioning at low input voltages and
from excessive discharge of the battery. It disables the output stage of the converter once the falling VIN trips the
undervoltage-lockout threshold (VBATUV). The undervoltage-lockout threshold for falling VIN is typically 2 V. The
device starts operation once the rising VIN trips the under-voltage-lockout threshold again at 2.1 V (typical).
7.3.6 Soft Start
The DC-DC converter has an internal soft-start circuit that controls the ramp-up of the output voltage. The output
voltage reaches its nominal value within 250 µs (typical) after EN has been pulled high. The output voltage
ramps up from 5% to its nominal value within 300 µs (typical). This limits the in-rush current in the converter
during start-up and prevents possible input voltage drops when a battery or high impedance power source is
used. During soft start, the switch current limit is reduced to 300 mA until the output voltage reaches VIN. Once
the output voltage trips this threshold, the device operates with its nominal current limit.
7.4 Device Functional Modes
7.4.1 Power-Save Mode
The TPD5S115 integrates a power-save mode to improve efficiency at light loads. In power-save mode, the
converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output
voltage with several pulses and goes into power-save mode once the output voltage exceeds the set threshold
voltage. The PFM mode is ended and PWM mode begins in case the output current can no longer be supported
in PFM mode.
7.4.2 Enable
The DC-DC converter is enabled when the EN is set to high. At first, the internal reference is activated and the
internal analog circuits are settled. Afterwards, the soft start is activated and the output voltage is ramped up.
The output voltage reaches its nominal value in 250 µs (typical) after the device has been enabled. The EN input
can be used to control power sequencing in a system with various DC-DC converters. The EN pin can be
connected to the output of another converter to drive the EN pin high and create a sequencing of supply rails.
When EN = GND, the converter enters shutdown mode.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPD5S115 is an integrated solution for HDMI 2.0, 1.3, and 1.4 interfaces. The device has a boost converter
on the power supply, signal conditioning circuits on CEC, SCL, SDA, and HPD lines, and ESD protection on all
the connector-facing lines.
8.2 Typical Applications
8.2.1 DDC or CEC Level Shifter
The TPD5S115 enables DDC translation from VCCA (system side) voltage levels to 5-V (HDMI cable side)
voltage levels without degradation of system performance. The TPD5S115 contains 2 bidirectional, open-drain
buffers specifically designed to support up and down-translation between the low voltage, VCCA side DDC-bus
and the 5-V DDC-bus. The port B I/Os are overvoltage tolerant to 5.5 V, even when the device is shutdown. After
power up and with the LS_OE and EN pins HIGH, a LOW level on port A (below VILC = 0.08 × VCCA) turns the
corresponding port B driver (either SDA or SCL) on and drives port B down to VOLB. When port A rises above
approximately 0.10 × VCCA, the port B pulldown driver is turned off and the internal pullup resistor pulls the pin
HIGH. When port B falls first and goes below 0.3 × VOUT, a CMOS hysteresis input buffer detects the falling
edge, turns on the port A driver, and pulls port A down to approximately VOLA = 0.16 × VCCA. The port B pulldown
is not enabled unless the port A voltage goes below VILC. If the port A low voltage goes below VILC, the port B
pulldown driver is enabled until port A rises above (VILC + ΔVT-HYSTA), then port B, if not externally driven LOW,
continues to rise being pulled up by the internal pullup resistor.
5VOUT
VCCA
CMP2
IACCEL
CMP1
ACCEL
RPUA
700mV
RPUB
150mV
Port A
GLITCH
FILTER
Port B
DDC
Lines
Only
l
300mV
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Figure 13. DDC or CEC Level Shifter Block Diagram
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Typical Applications (continued)
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
PARAMETER
VALUE
5VOUT DC current
55 mA
CEC_A, HPD_A, SCL_A, SDA_A voltage level
VCCA
HDMI 2.0 data rate per TMDS signal pair
6 Gbps
Required IEC 61000-4-2 ESD Protection
±8-kV contact
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 DDC or CEC Level Shifter Operational Notes for VCCA = 1.8 V
•
•
•
•
•
•
•
•
The threshold of CMP1 is approximately 150 mV ± the 40 mV of total hysteresis
The comparator trips for a falling waveform at approximately 130 mV
The comparator trips for a rising waveform at approximately 170 mV
To be recognized as a zero, the level at port A must first go below 130 mV (VILC in spec) and then stay below
170 mV (VILA in spec)
To be recognized as a one, the level at A must first go above 170 mV and then stay above 130 mV
VILC is specified as 110 mV in Electrical Characteristics to give some margin to the 130 mV
VILA is specified as 140 mV in Electrical Characteristics to give some margin to the 170 mV
VIHA is specified as 70% of VCCA to be consistent with standard CMOS levels
8.2.1.2.2 Input Capacitor
Due to the nature of the boost converter having a pulsating input current, a low-ESR input capacitor is required to
prevent large voltage transients that can cause poor performance of the device or interference with other circuits
in the system. TI recommends a 1.2-µF (minimum) input capacitor to improve transient behavior of the regulator
and EMI behavior of the total power-supply circuit. TI recommends placing a ceramic capacitor (4.7 µF) as close
as possible to the VIN and GND pins to improve the input noise filtering.
8.2.1.2.3 Output Capacitor
TI recommends using a small ceramic capacitors placed as close as possible to the VOUT and GND pins of the
IC. If the application requires the use of large capacitors which can not be placed close to the IC, TI recommends
using a smaller ceramic capacitor in parallel to the large capacitor. This small capacitor must be placed as close
as possible to the VOUT and GND pins of the IC. Use Equation 1 to estimate the recommended minimum output
capacitance.
Cmin =
IOUT ´ (VOUT - VIN )
f ´ DV ´ VOUT
where
•
•
f is the switching frequency
ΔV is the maximum allowed ripple
(1)
If a ripple voltage of 10 mV is chosen, a minimum effective capacitance of 2.7 µF is needed. The total ripple is
larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using
Equation 2.
DVESR = IOUT ´ RESR
(2)
To maintain control loop stability, a capacitor with a value in the range of the calculated minimum must be used.
There are no additional requirements regarding minimum ESR. There is no upper limit for the output capacitance
value. Larger capacitors cause lower output voltage ripple as well as lower output voltage drop during load
transients.
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Ceramic capacitors have a DC-bias effect, which has a strong influence on the final effective capacitance
needed. Therefore the appropriate capacitor value must be chosen very carefully. Package size, voltage rating,
and material are responsible for differences between the rated capacitor value and the effective capacitance. The
minimum effective capacitance value is 1.2 µF, but the recommended value is 4.7 µF.
Table 2. Passive Components: Recommended
Effective Values
COMPONENT
MIN
TYP
MAX
CIN
1.2
4.7
6.5
COUT
1.2
4.7
10
µF
LIN
0.7
1
1.3
µH
CVCCA
0.1
UNIT
µF
µF
8.2.1.3 Application Curve
B Port
A Port
Figure 14. DDC Level Shifter Operation (B to A Direction)
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8.2.2 Other Application Circuits
Figure 15 and Figure 16 show application examples using the TPD5S115 devices. Customers must fully validate
and test any circuit before implementing a design based on an example in this section. Unless otherwise noted,
the design procedures in DDC or CEC Level Shifter are applicable.
Figure 15. Application Schematic for HDMI Controllers With One GPIO for HDMI Interface Control
Some HDMI controllers may have only one GPIO to control the HDMI interface, thus, the HDMI driver chip
controls the TPD5S115 through only one control line (EN). In this mode the HPD_A to LS_OE pins are
connected to each other (see Figure 15).
Figure 16. Application Schematic for HDMI Controllers With Two GPIOs for HDMI Interface Control
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Some HDMI driver chips may have two GPIOs to control the HDMI interface chip. In this case a flexible power
saving mode can be implemented. The LS_OE and EN are active-high enable pins. They control the TPD5S115
power-saving options according to Table 3 and Table 4.
Table 3. Device Status – Part 1
LS_OE
EN
VCCA
VBAT
5VOUT
A-SIDE PULLUPS
DCC, B-SIDE PULLUPS
CEC, B-SIDE PULLUPS
L
L
1.8 V
5V
Off
Off
Off
Off
L
H
1.8 V
5V
On
On
On
Off
H
L
1.8 V
5V
Off
Off
Off
Off
H
H
1.8 V
5V
On
On
On
On
X
X
0V
0V
High-Z
High-Z
High-Z
High-Z
X
X
1.8 V
0V
Low
Low
High-Z
High-Z
X
X
0V
5V
High-Z
High-Z
High-Z
High-Z
Table 4. Device Status – Part 2
LS_OE
EN
CEC LDO
DC-DC AND HPD
DDC OR CEC VLTS
ICCA TYP
ICC VBAT TYP
COMMENT
L
L
Off
Off
OFF and High-Z
1 µA
1 µA
Fully disabled
L
H
Off
On
OFF and High-Z
1 µA
30 µA
DC-DC (30 µA) ON
H
L
Off
Off
OFF and High-Z
1 µA
1 µA
Not valid state
H
H
On
On
ON
13 µA
225 µA
Fully ON
X
X
Off
Off
High-Z
0 µA
0 µA
Power down
X
X
Off
Off
High-Z
0 µA
0 µA
Power down
X
X
Off
Off
High-Z
0 µA
0 µA
Power down
9 Power Supply Recommendations
To keep the normal function of TPD5S115, the designer needs to make sure that both VBAT and VCCA are
within the recommended operating range. See Detailed Design Procedure for power supply recommendations.
20
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Copyright © 2012–2017, Texas Instruments Incorporated
Product Folder Links: TPD5S115
TPD5S115
www.ti.com
SLVSBL2D – OCTOBER 2012 – REVISED JUNE 2017
10 Layout
10.1 Layout Guidelines
For proper operation, follow these layout and design guidelines:
• Place the TPD5S115 as close to the connector as possible. This allows it to remove the energy associated
with ESD strike before it reaches the internal circuitry of the system board.
• Place power line capacitors and inductors close to the pins with wide traces to allow enough current to flow
through with less trace parasitics. Ensure that there is enough metallization for the GND pad. A sufficient
current path enables safe discharge of all the energy associated with the ESD strike.
10.2 Layout Example
Figure 17. Board Layout With DC-DC Components (Top View)
Submit Documentation Feedback
Copyright © 2012–2017, Texas Instruments Incorporated
Product Folder Links: TPD5S115
21
TPD5S115
SLVSBL2D – OCTOBER 2012 – REVISED JUNE 2017
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Reading and Understanding an ESD Protection Datasheet
• ESD Layout Guide
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
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Copyright © 2012–2017, Texas Instruments Incorporated
Product Folder Links: TPD5S115
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPD5S115YFFR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
DSBGA
YFF
16
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
RE115
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPD5S115YFFR
Package Package Pins
Type Drawing
SPQ
DSBGA
3000
YFF
16
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
8.4
Pack Materials-Page 1
1.84
B0
(mm)
K0
(mm)
P1
(mm)
1.84
0.69
4.0
W
Pin1
(mm) Quadrant
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD5S115YFFR
DSBGA
YFF
16
3000
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0016
DSBGA - 0.625 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
0.625 MAX
C
SEATING PLANE
0.30
0.12
BALL TYP
0.05 C
1.2 TYP
D
C
1.2
TYP
SYMM
D: Max = 1.768 mm, Min =1.708 mm
B
E: Max = 1.768 mm, Min =1.708 mm
0.4 TYP
A
16X
0.015
0.3
0.2
C A B
1
3
2
4
SYMM
0.4 TYP
4219386/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0016
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
16X ( 0.23)
1
4
3
2
A
(0.4) TYP
B
SYMM
C
D
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MAX
( 0.23)
METAL
METAL UNDER
SOLDER MASK
0.05 MIN
( 0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219386/A 05/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0016
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
16X ( 0.25)
1
2
3
4
A
(0.4) TYP
B
SYMM
METAL
TYP
C
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4219386/A 05/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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