Texas Instruments | TCAN1051 Fault Protected CAN Transceiver with CAN FD (Rev. D) | Datasheet | Texas Instruments TCAN1051 Fault Protected CAN Transceiver with CAN FD (Rev. D) Datasheet

Texas Instruments TCAN1051 Fault Protected CAN Transceiver with CAN FD (Rev. D) Datasheet
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TCAN1051, TCAN1051G, TCAN1051GV
TCAN1051H, TCAN1051HV, TCAN1051HG
TCAN1051HGV, TCAN1051V
SLLSES8D – MARCH 2016 – REVISED MAY 2017
TCAN1051 Fault Protected CAN Transceiver with CAN FD
1 Features
•
1
•
•
•
•
•
•
•
•
Meets the ISO 11898-2:2016 and
ISO 11898-5:2007 Physical Layer Standards
'Turbo' CAN:
– All Devices Support Classic CAN and 2 Mbps
CAN FD (Flexible Data Rate) and "G" Options
Support 5 Mbps
– Short and Symmetrical Propagation Delay
Times and Fast Loop Times for Enhanced
Timing Margin
– Higher Data Rates in Loaded CAN Networks
I/O Voltage Range Supports 3.3 V and 5 V MCUs
Ideal Passive Behavior When Unpowered
– Bus and Logic Terminals are High Impedance
(no load)
– Power Up/Down With Glitch Free Operation
On Bus and RXD Output
Protection Features
– HBM ESD Protection: ±16 kV
– IEC ESD Protection up to ±15 kV
– Bus Fault Protection: ±58 V (non-H variants)
and ±70 V (H variants)
– Undervoltage Protection on VCC and VIO (V
variants only) Supply Terminals
– Driver Dominant Time Out (TXD DTO) - Data
rates down to 10 kbps
– Thermal Shutdown Protection (TSD)
Receiver Common Mode Input Voltage: ±30 V
Typical Loop Delay: 110 ns
Junction Temperatures from –55°C to 150°C
Available in SOIC(8) Package and Leadless
VSON(8) Package (3.0 mm x 3.0 mm) with
Improved Automated Optical Inspection (AOI)
Capability
•
CAN Bus Standards Such as CANopen,
DeviceNet, NMEA2000, ARNIC825, ISO11783,
CANaerospace
3 Description
This CAN transceiver family meets the ISO11898-2
(2016) High Speed CAN (Controller Area Network)
physical layer standard. All devices are designed for
use in CAN FD networks up to 2 Mbps (megabits per
second). Devices with part numbers that include the
"G" suffix are designed for data rates up to 5 Mbps,
and versions with the "V" have a secondary power
supply input for I/O level shifting the input pin
thresholds and RXD output level. This family of
devices comes with silent mode which is also
commonly referred to as listen-only mode.
Additionally, all devices include many protection
features to enhance device and network robustness.
Device Information
ORDER NUMBER
TCAN1051x
•
•
•
All devices support highly loaded CAN networks
Heavy Machinery ISOBUS Applications –
ISO 11783
Industrial Automation, Control, Sensors and Drive
Systems
Building, Security and Climate Control Automation
Telecom Base Station Status and Control
BODY SIZE
SOIC (8)
4.90 mm × 3.91 mm
VSON (8)
3.00 mm x 3.00 mm
Functional Block Diagram
NC or VIO
VCC
5
3
VCC or VIO
TXD
1
S
8
TSD
7
CANH
Dominant
time-out
6
CANL
Mode
Select
UVP
2 Applications
•
•
PACKAGE
VCC or VIO
RXD
4
Logic
Output
2
GND
Copyright © 2016, Texas Instruments Incorporated
A.
Terminal 5 function is device dependent;
NC on devices without the "V" suffix, and
VIO for I/O level shifting for devices with the
"V" suffix.
B.
RXD logic output is driven to VCC on
devices without the "V" suffix, and VIO for
devices with the "V" suffix.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCAN1051, TCAN1051G, TCAN1051GV
TCAN1051H, TCAN1051HV, TCAN1051HG
TCAN1051HGV, TCAN1051V
SLLSES8D – MARCH 2016 – REVISED MAY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configurations and Functions .......................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
9
1
1
1
2
4
4
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Power Rating............................................................. 6
Electrical Characteristics........................................... 7
Switching Characteristics ........................................ 10
Typical Characteristics ............................................ 11
Parameter Measurement Information ................ 12
Detailed Description ............................................ 15
9.1 Overview ................................................................. 15
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 16
9.4 Device Functional Modes........................................ 19
10 Application and Implementation........................ 21
10.1 Application Information.......................................... 21
10.2 Typical Applications .............................................. 21
11 Power Supply Requirements ............................. 25
12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 26
12.2 Layout Example .................................................... 26
13 Device and Documentation Support ................. 27
13.1
13.2
13.3
13.4
13.5
13.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
14 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
Changes from Revision C (August 2016) to Revision D
Page
•
Deleted Feature "Meets the December 17th, 2015 Draft of ISO 11898-2 Physical Layer Update" ....................................... 1
•
Changed Feature From: "Meets the Released ISO 11898-2:2007 and ISO 11898-2:2003 Physical Layer Standards"
To: "Meets the ISO 11898-2:2016 and ISO 11898-5:2007 Physical Layer Standards" ......................................................... 1
•
Changed Feature From: "All devices support 2 Mbps CAN FD.." To: "All Devices Support Classic CAN and 2 Mbps
CAN FD.." ............................................................................................................................................................................... 1
•
Changed the Functional Block Diagram, removed the Dominant time-out box ..................................................................... 1
•
Added Storage temperature range to the Absolute Maximum Ratings table ......................................................................... 5
•
Changed Human Body Model (HBM) From: ±10000 To: ±16000 in the ESD table............................................................... 5
•
Changed Charged Device Model (CDM) From: ±750 To: ±1500 in the ESD table................................................................ 5
•
Changed TBD to values for the DRB (VSON) Package in the ESD table ............................................................................. 5
•
Changed VSYM in the DRIVER ELECTRICAL CHARACTERISTICS table............................................................................. 8
•
Changed VSYM_DC in the DRIVER ELECTRICAL CHARACTERISTICS table ........................................................................ 8
•
Deleted "VI = 0.4 sin (4E6 π t) + 2.5 V" from the Test Condition of CI in the RECEIVER ELECTRICAL
CHARACTERISTICS table ..................................................................................................................................................... 9
•
Deleted "VI = 0.4 sin (4E6 π t)" from the Test Condition of CID in the RECEIVER ELECTRICAL CHARACTERISTICS
table ........................................................................................................................................................................................ 9
•
Added "-30 V ≤ VCM ≤ +30" to the Test Condition of RID and RIN in the RECEIVER ELECTRICAL
CHARACTERISTICS table ..................................................................................................................................................... 9
•
Changed the Functional Block Diagram, removed the Dominant time-out box ................................................................... 15
•
Changed Table 3, BUS OUTPUT colum .............................................................................................................................. 17
Changes from Revision B (May 2016) to Revision C
Page
•
Added devices: TCAN1051, TCAN1051G, TCAN1051GV, and TCAN1051V ...................................................................... 1
•
Changed Feature From: AddeBus Fault Protection: ±70 V To: Bus Fault Protection: ±58 V (non-H variants) and ±70
V (H variants).......................................................................................................................................................................... 1
•
Added Feature "Available in SOIC(8) package and leadless VSON(8) package..." .............................................................. 1
2
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Product Folder Links: TCAN1051 TCAN1051G TCAN1051GV TCAN1051H TCAN1051HV TCAN1051HG
TCAN1051HGV TCAN1051V
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TCAN1051H, TCAN1051HV, TCAN1051HG
TCAN1051HGV, TCAN1051V
www.ti.com
•
SLLSES8D – MARCH 2016 – REVISED MAY 2017
Updated Absolute Maximum Ratings with new devices ........................................................................................................ 5
Changes from Revision A (April 2016) to Revision B
Page
•
Added the VSON (8) pin package to the Device Information table........................................................................................ 1
•
Added the VSON (8) pin package to the Pin Configurations and Functions.......................................................................... 4
•
Added V(Diff) to the Absolute Maximum Ratings (1)
•
Added the DRB package to the Thermal Information table ................................................................................................... 6
(2)
table .................................................................................................... 5
Changes from Original (March 2016) to Revision A
•
Page
Changed the device status From: Product Preview To: Production ...................................................................................... 1
Copyright © 2016–2017, Texas Instruments Incorporated
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TCAN1051HGV TCAN1051V
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TCAN1051, TCAN1051G, TCAN1051GV
TCAN1051H, TCAN1051HV, TCAN1051HG
TCAN1051HGV, TCAN1051V
SLLSES8D – MARCH 2016 – REVISED MAY 2017
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5 Device Comparison Table
DEVICE
NUMBER
BUS FAULT PROTECTION
5-Mbps FLEXIBLE DATA
RATE
TCAN1051 (Base)
±58 V
TCAN1051G
±58 V
X
TCAN1051GV
±58 V
X
TCAN1051V
±58 V
TCAN1051H
±70 V
3-V LEVEL SHIFTER
INTEGRATED
PIN 8 MODE SELECTION
X
X
TCAN1051HG
±70 V
X
TCAN1051HGV
±70 V
X
TCAN1051HV
±70 V
Silent Mode
X
X
6 Pin Configurations and Functions
D Package for Base, (H), (G) and (HG) Devices
8 PIN (SOIC)
Top View
TXD
1
8
S
GND
2
7
CANH
VCC
3
6
CANL
RXD
4
5
NC
D Package for (V), (GV), (HV) and (HGV) Devices
8 PIN (SOIC)
Top View
DRB Package for Base, (H), (G), and (HG) Devices
8 PIN (VSON)
Top View
TXD
1
8 S
GND
2
7 CANH
VCC
3
6 CANL
RXD
4
5
TXD
1
8
S
GND
2
7
CANH
VCC
3
6
CANL
RXD
4
5
VIO
DRB Package for (V), (GV), (HV) and (HGV) Devices
8 PIN (VSON)
Top View
NC
TXD
1
8 S
GND
2
7 CANH
VCC
3
6 CANL
RXD
4
5
VIO
Pin Functions
PINS
(H), (G), (HG)
(V), (GV), (HV),
(HGV)
TYPE
TXD
1
1
DIGITAL INPUT
GND
2
2
GND
VCC
3
3
POWER
RXD
4
4
DIGITAL OUTPUT
NC
5
—
—
VIO
—
5
POWER
Transceiver I/O level shifting supply voltage (Devices with "V" suffix only)
CANL
6
6
BUS I/O
Low level CAN bus input/output line
CANH
7
7
BUS I/O
High level CAN bus lnput/output line
S
8
8
DIGITAL INPUT
NAME
4
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DESCRIPTION
CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
Ground connection
Transceiver 5-V supply voltage
CAN receive data output (LOW for dominant and HIGH for recessive bus states)
No Connect
Silent Mode control input (active high)
Copyright © 2016–2017, Texas Instruments Incorporated
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TCAN1051HGV TCAN1051V
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TCAN1051H, TCAN1051HV, TCAN1051HG
TCAN1051HGV, TCAN1051V
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SLLSES8D – MARCH 2016 – REVISED MAY 2017
7 Specifications
7.1 Absolute Maximum Ratings (1)
(2)
MIN
MAX
UNIT
VCC
5-V Bus Supply Voltage Range
All Devices
–0.3
7
V
VIO
I/O Level-Shifting Voltage Range
Devices with the "V" Suffix
–0.3
7
V
VBUS
CAN Bus I/O voltage range (CANH,
CANL)
Devices without the "H" Suffix
–58
58
V
V(Diff)
Max differential voltage between
CANH and CANL
Devices without the “H” suffix
–58
58
V
VBUS
CAN Bus I/O voltage range (CANH,
CANL)
Devices with the "H" Suffix
-70
70
V
V(Diff)
Max differential voltage between
CANH and CANL
Devices with the “H” suffix
–70
70
V
V(Logic_Input)
Logic input terminal voltage range (TXD,
S)
–0.3
+7 and VI ≤ VIO + 0.3
V
V(Logic_Output)
Logic output terminal voltage range
(RXD)
–0.3
+7 and VI ≤ VIO + 0.3
V
IO(RXD)
RXD (Receiver) output current
–8
8
mA
TJ
Virtual junction temperature range (see Thermal Information)
–55
150
°C
TSTG
Storage temperature range (see Thermal Information)
–65
150
°C
(1)
(2)
All Devices
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated condition for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to ground terminal.
7.2 ESD Ratings
TEST CONDITIONS
VALUE
UNIT
D (SOIC) Package
All terminals (1)
±6000
CAN bus terminals (CANH, CANL) to GND (2)
±16000
Charged Device Model (CDM) ESD stress voltage
All terminals (3)
±1500
V
Machine Model
All terminals (4)
±200
V
Human Body Model (HBM) ESD stress voltage
System Level Electro-Static Discharge (ESD)
System Level Electrical fast transient (EFT)
CAN bus terminals
(CANH, CANL) to GND
CAN bus terminals
(CANH, CANL) to GND
IEC 61000-4-2: Unpowered
Contact Discharge
±15000
IEC 61000-4-2: Powered Contact
Discharge
±8000
IEC 61000-4-4: Criteria A
±4000
V
V
V
DRB (VSON) Package
Human Body Model (HBM) ESD stress voltage
All terminals (1)
±6000
CAN bus terminals (CANH, CANL) to GND (2)
±16000
(3)
Charged Device Model (CDM) ESD stress voltage
All terminals
Machine Model
All terminals (4)
System Level Electro-Static Discharge (ESD)
System Level Electrical fast transient (EFT)
(1)
(2)
(3)
(4)
CAN bus terminals
(CANH, CANL) to GND
CAN bus terminals
(CANH, CANL) to GND
V
±1500
V
±200
V
IEC 61000-4-2: Unpowered
Contact Discharge
±14000
IEC 61000-4-2: Powered Contact
Discharge
±8000
IEC 61000-4 Criteria A
±4000
V
V
Tested in accordance to JEDEC Standard 22, Test Method A114.
Test method based upon JEDEC Standard 22 Test Method A114, CAN bus is stressed with respect to GND.
Tested in accordance to JEDEC Standard 22, Test Method C101.
Tested in accordance to JEDEC Standard 22, Test Method A115.
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7.3 Recommended Operating Conditions
MIN
MAX
VCC
5-V Bus Supply Voltage Range
4.5
5.5
VIO
I/O Level-Shifting Voltage Range
2.8
5.5
IOH(RXD)
RXD terminal HIGH level output current
–2
IOL(RXD)
RXD terminal LOW level output current
2
UNIT
V
mA
7.4 Thermal Information
TCAN1051
THERMAL METRIC (1)
TEST CONDITIONS
High-K thermal resistance (2)
D (SOIC)
DRB (VSON)
8 Pins
8 Pins
105.8
UNIT
RθJA
Junction-to-air thermal resistance
40.2
°C/W
RθJB
Junction-to-board thermal resistance (3)
46.8
49.7
°C/W
RθJC(TOP)
Junction-to-case (top) thermal resistance (4)
48.3
15.7
°C/W
ΨJT
Junction-to-top characterization parameter (5)
8.7
0.6
°C/W
ΨJB
Junction-to-board characterization parameter (6)
46.2
15.9
°C/W
TTSD
Thermal shutdown temperature
170
170
°C
TTSD_HYS
Thermal shutdown hysteresis
5
5
°C
(1)
(2)
(3)
(4)
(5)
(6)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
7.5 Power Rating
PARAMETER
PD
6
Average power dissipation
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TEST CONDITIONS
POWER DISSIPATION
UNIT
VCC = 5 V, VIO = 5 V (if applicable), TJ = 27°C, RL = 60 Ω, S at 0
V, Input to TXD at 250 kHz, CL_RXD = 15 pF. Typical CAN
operating conditions at 500 kbps with 25% transmission
(dominant) rate.
52
mW
VCC = 5.5 V, VIO = 5.5 V (if applicable), TJ = 150°C, RL = 50 Ω,
S at 0 V, Input to TXD at 500 kHz, CL_RXD = 15 pF. Typical high
load CAN operating conditions at 1 Mbps with 50% transmission
(dominant) rate and loaded network.
124
mW
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SLLSES8D – MARCH 2016 – REVISED MAY 2017
7.6 Electrical Characteristics
Over recommended operating conditions, TA = –55°C to 125°C (unless otherwise noted).
PARAMETER
TYP (1)
MAX
See Figure 5, TXD = 0 V, RL = 60 Ω, CL =
open, RCM = open, S = 0V
40
70
See Figure 5, TXD = 0 V, RL = 50 Ω, CL =
open, RCM = open, S = 0V
45
80
TEST CONDITIONS
MIN
UNIT
SUPPLY CHARACTERISTICS
Normal mode
(dominant)
ICC
5-V Supply current
IIO
I/O supply current
UVVCC
Normal mode
(dominant – bus fault)
See Figure 5, TXD = 0 V, S = 0V, CANH =
-12V, RL = open, CL = open, RCM = open
Normal mode
(recessive)
See Figure 5, TXD = VCC, RL = 50 Ω, CL =
open, RCM = open,
S = 0V
1.5
2.5
Silent mode
See Figure 5, TXD = VCC, RL = 50 Ω,CL =
open, RCM = open,
S = VCC
1.5
2.5
Normal and Silent
modes
RXD Floating, TXD = S = 0 or 5.5 V
90
300
4.2
4.4
4.0
4.25
180
mA
Rising undervoltage detection on VCC for
protected mode
Falling undervoltage detection on VCC for
protected mode
VHYS(UVVCC)
Hysteresis voltage on UVVCC
UVVIO
Undervoltage detection on VIO for protected
mode
VHYS(UVVIO)
Hysteresis voltage on UVVIO for protected mode
All devices
V
3.8
200
Devices with the "V" Suffix (I/O levelshifting)
µA
mV
1.3
2.75
80
V
mV
S TERMINAL (MODE SELECT INPUT)
VIH
High-level input voltage
Devices with the "V" suffix (I/O level-shifting)
Devices without the "V" suffix (5-V only)
0.7 x VIO
2
Devices with the "V" suffix (I/O level-shifting)
0.3 x VIO
VIL
Low-level input voltage
IIH
High-level input leakage current
S = VCC or VIO = 5.5 V
IIL
Low-level input leakage current
S = 0 V, VCC = VIO = 5.5 V
–2
Ilkg(OFF)
Unpowered leakage current
S = 5.5 V, VCC = VIO = 0 V
-1
Devices without the "V" suffix (5-V only)
V
0.8
30
0
2
µA
1
TXD TERMINAL (CAN TRANSMIT DATA INPUT)
VIH
High-level input voltage
Devices with the "V" suffix (I/O level-shifting)
Devices without the "V" suffix (5-V only)
0.7 x VIO
2
Devices with the "V" suffix (I/O level-shifting)
0.3 x VIO
VIL
Low-level input voltage
IIH
High-level input leakage current
TXD = VCC = VIO = 5.5 V
–2.5
0
1
IIL
Low-level input leakage current
TXD = 0 V, VCC = VIO = 5.5 V
–100
-25
–7
Ilkg(OFF)
Unpowered leakage current
TXD = 5.5 V, VCC = VIO = 0 V
–1
0
1
CI
Input capacitance
VIN = 0.4 * sin(4E6 * π * t) + 2.5 V
(1)
Devices without the "V" suffix (5-V only)
V
0.8
5
µA
pF
All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 5 V, RL = 60 Ω.
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Electrical Characteristics (continued)
Over recommended operating conditions, TA = –55°C to 125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
RXD TERMINAL (CAN RECEIVE DATA OUTPUT)
VOH
Devices with the "V" suffix (I/O levelshifting), See Figure 6, IO = –2 mA
High-level output voltage
VOL
Devices without the "V" suffix (5-V only),
See Figure 6, IO = –2 mA
4
4.6
V
Devices with the "V" suffix (I/O levelshifting), See Figure 6, IO = +2 mA
Low-level output voltage
Ilkg(OFF)
0.8 × VIO
0.2 x VIO
Devices without the "V" suffix (5-V only),
See Figure 6, IO = +2 mA
Unpowered leakage current
RXD = 5.5 V, VCC = 0 V, VIO = 0 V
–1
0.2
0.4
0
1
µA
DRIVER ELECTRICAL CHARACTERISTICS
VO(DOM)
Bus output voltage
(dominant
VO(REC)
Bus output voltage
(recessive)
VOD(DOM)
Differential output
voltage (dominant)
Differential output
voltage (recessive)
VOD(REC)
CANH
CANL
CANH and CANL
CANH - CANL
CANH - CANL
See Figure 13 and Figure 5, TXD = 0 V, S =
0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM =
open
2.75
4.5
0.5
2.25
See Figure 13 and Figure 5, TXD = VCC, VIO
= VCC, S = VCC or 0 V (2), RL = open (no
load), RCM = open
2
See Figure 13 and Figure 5, TXD = 0 V, S =
0 V, 45 Ω ≤ RL < 50 Ω, CL = open, RCM =
open
1.4
3
See Figure 13 and Figure 5, TXD = 0 V, S =
0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM =
open
1.5
3
See Figure 13 and Figure 5, TXD = 0 V, S =
0 V, RL = 2240 Ω, CL = open, RCM = open
1.5
5
See Figure 13 and Figure 5, TXD = VCC, S
= 0 V, RL = 60 Ω, CL = open, RCM = open
–120
12
See Figure 13 and Figure 5, TXD = VCC, S
= 0 V, RL = open (no load), CL = open, RCM
= open
–50
50
0.9
1.1
V/V
0.4
V
Transient symmetry (dominant or recessive)
( VO(CANH) + VO(CANL)) / VCC
See Figure 5 and Figure 15, S at 0 V, Rterm
= 60 Ω, Csplit = 4.7 nF, CL = open,
RCM = open, TXD = 250 kHz, 1 MHz
VSYM_DC
DC Output symmetry (dominant or recessive)
(VCC – VO(CANH) – VO(CANL))
See Figure 5 and , S = 0 V,
RL = 60 Ω, CL = open, RCM = open
–0.4
See Figure 13 and Figure 11, Figure 11, S
at 0 V, VCANH = -5 V to 40 V, CANH = open,
TXD = 0 V
–100
IOS(SS_DOM)
IOS(SS_REC)
(2)
8
Short-circuit steady-state output current,
recessive
V
mA
See Figure 13 and Figure 11, S at 0 V,
VCANL = -5 V to 40 V, CANH = open,
TXD = 0 V
See Figure 13 and Figure 11, –27 V ≤ VBUS
≤ 32 V, Where VBUS = CANH = CANL, TXD
= VCC, all modes
3
mV
VSYM
Short-circuit steady-state output current,
dominant
0.5 × VCC
100
–5
5
mA
For the bus output voltage (recessive) will be the same if the device is in Normal mode with S terminal LOW or if the device is in Silent
mode with the S terminal is HIGH.
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Electrical Characteristics (continued)
Over recommended operating conditions, TA = –55°C to 125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
+30
V
RECEIVER ELECTRICAL CHARACTERISTICS
See Figure 6, Table 6 and Table 1, S = 0 or
VCC or VIO
VCM
Common mode range, normal mode
VIT+
Positive-going input threshold voltage, all modes
VIT–
Negative-going input threshold voltage, all
modes
VIT+
Positive-going input threshold voltage, all modes
VIT–
Negative-going input threshold voltage, all
modes
VHYS
Hysteresis voltage (VIT+ - VIT–)
See Figure 6, Table 6 and Table 1, S = 0 or
VCC or VIO
Ilkg(IOFF)
Power-off (unpowered) bus input leakage current
CANH = CANL = 5 V, VCC = VIO = 0 V
CI
Input capacitance to ground (CANH or CANL)
TXD = VCC, VIO = VCC
CID
Differential input capacitance
TXD = VCC, VIO = VCC
RID
Differential input resistance
RIN
Input resistance (CANH or CANL)
TXD = VCC = VIO = 5 V, S = 0 V,
-30 V ≤ VCM ≤ +30 V
RIN(M)
Input resistance matching:
[1 – RIN(CANH) / RIN(CANL)] × 100%
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See Figure 6, Table 6 and Table 1, S = 0 or
VCC or VIO, -20 V ≤ VCM ≤ +20 V
See Figure 6, Table 6 and Table 1, S = 0 or
VCC or VIO, -30 V ≤ VCM ≤ +30 V
VCANH = VCANL = 5 V
-30
900
500
1000
mV
400
120
mV
4.8
µA
24
30
pF
12
15
pF
30
80
kΩ
15
40
kΩ
–2%
+2%
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7.7 Switching Characteristics
Over recommended operating conditions with TA = -55°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1) MAX UNIT
DEVICE SWITCHING CHARACTERISTICS
tPROP(LOOP1)
Total loop delay, driver input (TXD) to receiver
output (RXD), recessive to dominant
tPROP(LOOP2)
Total loop delay, driver input (TXD) to receiver
output (RXD), dominant to recessive
tMODE
Mode change time, from Normal to Silent or
from Silent to Normal
See Figure 8, S = 0 V,
RL = 60 Ω,
CL = 100 pF, CL(RXD) = 15 pF
100
160
110
175
1
10
ns
See Figure 7
µs
DRIVER SWITCHING CHARACTERISTICS
tpHR
Propagation delay time, high TXD to driver
recessive (dominant to recessive)
tpLD
Propagation delay time, low TXD to driver
dominant (recessive to dominant)
tsk(p)
Pulse skew (|tpHR - tpLD|)
tR
Differential output signal rise time
45
tF
Differential output signal fall time
45
tTXD_DTO
Dominant timeout
75
See Figure 5, S = 0 V,
RL = 60 Ω,
CL = 100 pF, RCM = open
See Figure 10, S = 0 V,
RL = 60 Ω, CL = open
55
ns
20
1.2
3.8
ms
RECEIVER SWITCHING CHARACTERISTICS
tpRH
Propagation delay time, bus recessive input to
high output (Dominant to Recessive)
tpDL
Propagation delay time, bus dominant input to
low output (Recessive to Dominant)
tR
tF
65
ns
50
ns
RXD Output signal rise time
10
ns
RXD Output signal fall time
10
ns
See Figure 6, S = 0 V,
CL(RXD) = 15 pF
FD Timing Parameters
tBIT(BUS)
tBIT(RXD)
ΔtREC
(1)
10
Bit time on CAN bus output pins with tBIT(TXD) =
500 ns, all devices
435
530
Bit time on CAN bus output pins with tBIT(TXD) =
200 ns, G device variants only
155
210
400
550
120
220
Receiver timing symmetry with tBIT(TXD) = 500
ns, all devices
-65
40
Receiver timing symmetry with tBIT(TXD) = 200
ns, G device variants only
-45
15
Bit time on RXD output pins with tBIT(TXD) = 500 See Figure 9 , S = 0 V,
ns, all devices
RL = 60 Ω, CL = 100 pF,
Bit time on RXD output pins with tBIT(TXD) = 200 CL(RXD) = 15 pF,
ΔtREC = tBIT(RXD) - tBIT(BUS)
ns, G device variants only
ns
All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 5 V, RL = 60 Ω.
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3
3
2.5
2.5
2
2
VOD(D) (V)
VOD(D) (V)
7.8 Typical Characteristics
1.5
1.5
1
1
0.5
0.5
0
-55
-35
-15
5
VCC = 5 V
CL = Open
25
45
65
Temperature (°C)
85
105
0
4.5
125
4.6
4.7
VIO = 3.3 V
RCM = Open
RL = 60 Ω
S=0V
4.9
VIO = 5 V
CL = Open
Figure 1. VOD(D) over Temperature
5
5.1
VCC (V)
5.2
5.3
5.4
5.5
D002
S=0V
RCM = Open
RL = 60 Ω
Temp = 25°C
Figure 2. VOD(D) over VCC
1.48
150
1.47
125
Total Loop Delay (ns)
ICC Recessive (mA)
4.8
D001
1.46
1.45
1.44
1.43
100
75
50
25
1.42
1.41
-55
-35
-15
VCC = 5 V
CL = Open
5
25
45
65
Temperature (°C)
VIO = 3.3 V
RCM = Open
85
105
0
-55
-35
-15
D003
RL = 60 Ω
S=0V
Figure 3. ICC Recessive over Temperature
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125
VCC = 5 V
CL = 100 pF
5
25
45
65
Temperature (°C)
85
VIO = 3.3 V
CL_RXD = 15 pF
105
125
D004
RL = 60 Ω
S=0V
Figure 4. Total Loop Delay over Temperature
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8 Parameter Measurement Information
RCM
CANH
VCC
50%
TXD
TXD
RL
CL
VOD
0V
VCM
VO(CANH)
CANL
50%
tpHR
tpLD
90%
RCM
VO(CANL)
0.9V
VOD
0.5V
10%
tR
tF
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Figure 5. Driver Test Circuit and Measurement
CANH
VID
IO
RXD
1.5V
0.9V
0.5V
0V
VID
CL_RXD
CANL
tpDL
tpRH
VO
VOH
90%
VO(RXD)
50%
10%
VOL
tF
tR
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Figure 6. Receiver Test Circuit and Measurement
Table 1. Receiver Differential Input Voltage Threshold Test (See Figure 6)
INPUT
12
OUTPUT
VCANH
VCANL
|VID|
-29.5 V
-30.5 V
1000 mV
L
30.5 V
29.5 V
1000 mV
L
-19.55 V
-20.45 V
900 mV
L
20.45 V
19.55 V
900 mV
L
-19.75 V
-20.25 V
500 mV
H
20.25 V
19.75 V
500 mV
H
-29.8 V
-30.2 V
400 mV
H
30.2 V
29.8 V
400 mV
H
Open
Open
X
H
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RXD
VOL
VOH
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CANH
VIH
TXD
0V
CL
RL
S
50%
CANL
VI
S
0V
tMODE
RXD
VO
VOH
CL_RXD
RXD
50%
VOL
Copyright © 2016, Texas Instruments Incorporated
Figure 7. tMODE Test Circuit and Measurement
CANH
VIH
TXD
0V
CL
RL
S
50%
CANL
VI
S
0V
tMODE
RXD
VO
VOH
CL_RXD
RXD
50%
VOL
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Figure 8. TPROP(LOOP) Test Circuit and Measurement
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VI
70%
TXD
CANH
30%
30%
0V
TXD
VI
RL
5 x tBIT
CL
tBIT(TXD)
CANL
0V
tBIT(BUS)
S
900mV
VDIFF
RXD
VO
500mV
CL_RXD
VOH
70%
RXD
30%
tBIT(RXD)
VOL
Figure 9. CAN FD Timing Parameter Measurement
CANH
VIH
TXD
TXD
RL
CL
0V
VOD
VOD(D)
CANL
0.9V
VOD
0.5V
tTXD_DTO
0V
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Figure 10. TXD Dominant Timeout Test Circuit and Measurement
CANH
200 s
IOS
TXD
VBUS
IOS
CANL
VBUS
VBUS
0V
or
0V
VBUS
VBUS
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Figure 11. Driver Short Circuit Current Test and Measurement
14
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9 Detailed Description
9.1 Overview
These CAN transceivers meet the ISO11898-2 (2016) High Speed CAN (Controller Area Network) physical layer
standard. They are designed for data rates in excess of 1 Mbps for CAN FD and enhanced timing margin /
higher data rates in long and highly-loaded networks. These devices provide many protection features to
enhance device and CAN robustness.
9.2 Functional Block Diagram
NC or VIO
VCC
5
3
VCC or VIO
TXD
1
S
8
TSD
7
CANH
Dominant
time-out
6
CANL
Mode
Select
UVP
VCC or VIO
RXD
4
Logic
Output
2
GND
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9.3 Feature Description
9.3.1 TXD Dominant Timeout (DTO)
During normal mode (the only mode where the CAN driver is active), the TXD DTO circuit prevents the
transceiver from blocking network communication in the event of a hardware or software failure where TXD is
held dominant longer than the timeout period tTXD_DTO. The DTO circuit timer starts on a falling edge on TXD.
The DTO circuit disables the CAN bus driver if no rising edge is seen before the timeout period expires. This
frees the bus for communication between other nodes on the network. The CAN driver is re-activated when a
recessive signal is seen on the TXD terminal, thus clearing the TXD DTO condition. The receiver and RXD
terminal still reflect activity on the CAN bus, and the bus terminals are biased to the recessive level during a TXD
dominant timeout.
TXD fault stuck dominant: example PCB
failure or bad software
TXD
(driver)
tTXD_DTO
Fault is repaired & transmission
capability restored
Driver disabled freeing bus for other nodes
%XV ZRXOG EH ³VWXFN GRPLQDQW´ EORFNLQJ FRPPXQLFDWLRQ IRU WKH
whole network but TXD DTO prevents this and frees the bus for
communication after the time tTXD_DTO.
Normal CAN
communication
CAN
Bus
Signal
tTXD_DTO
Communication from
other bus node(s)
Communication from
repaired node
Communication from
other bus node(s)
Communication from
repaired local node
RXD
(receiver)
Communication from
local node
Figure 12. Example Timing Diagram for TXD DTO
NOTE
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum
possible transmitted data rate of the device. The CAN protocol allows a maximum of
eleven successive dominant bits (on TXD) for the worst case, where five successive
dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO
minimum, limits the minimum data rate. Calculate the minimum transmitted data rate by:
Minimum Data Rate = 11 / tTXD_DTO.
9.3.2 Thermal Shutdown (TSD)
If the junction temperature of the device exceeds the thermal shutdown threshold (TTSD), the device turns off the
CAN driver circuits thus blocking the TXD-to-bus transmission path. The CAN bus terminals are biased to the
recessive level during a thermal shutdown, and the receiver-to-RXD path remains operational. The shutdown
condition is cleared when the junction temperature drops at least the thermal shutdown hysteresis temperature
(TTSD_HYS) below the thermal shutdown temperature (TTSD) of the device.
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Feature Description (continued)
9.3.3 Undervoltage Lockout
The supply terminals have undervoltage detection that places the device in protected mode. This protects the
bus during an undervoltage event on either the VCC or VIO supply terminals.
Table 2. Undervoltage Lockout 5 V Only Devices (Devices without the "V" Suffix) (1)
(1)
(2)
VCC
DEVICE STATE
BUS OUTPUT
RXD
> UVVCC
Normal
Per TXD
Mirrors Bus (2)
< UVVCC
Protected
High Impedance
High Impedance
See the VIT section of the Electrical Characteristics.
Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.
Table 3. Undervoltage Lockout I/O Level Shifting Devices (Devices with the "V" Suffix)
(1)
VCC
VIO
DEVICE STATE
BUS OUTPUT
RXD
> UVVCC
> UVVIO
Normal
Per TXD
Mirrors Bus (1)
< UVVCC
> UVVIO
Protected
High Impedance
High (Recessive)
> UVVCC
< UVVIO
Protected
High Impedance
High Impedance
< UVVCC
< UVVIO
Protected
High Impedance
High Impedance
Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.
NOTE
After an undervoltage condition is cleared and the supplies have returned to valid levels,
the device typically resumes normal operation within 50 µs.
9.3.4 Unpowered Device
The device is designed to be 'ideal passive' or 'no load' to the CAN bus if it is unpowered. The bus terminals
(CANH, CANL) have extremely low leakage currents when the device is unpowered to avoid loading down the
bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains in
operation. The logic terminals also have extremely low leakage currents when the device is unpowered to avoid
loading down other circuits that may remain powered.
9.3.5 Floating Terminals
These devices have internal pull ups on critical terminals to place the device into known states if the terminals
float. The TXD terminal is pulled up to VCC or VIO to force a recessive input level if the terminal floats. The S
terminal is also pulled down to force the device into Normal mode if the terminal floats.
9.3.6 CAN Bus Short Circuit Current Limiting
The device has two protection features that limit the short circuit current when a CAN bus line is short-circuit fault
condition: driver current limiting (both dominant and recessive states) and TXD dominant state time out to
prevent permanent higher short circuit current of the dominant state during a system fault. During CAN
communication the bus switches between dominant and recessive states, thus the short circuit current may be
viewed either as the instantaneous current during each bus state or as an average current of the two states. For
system current (power supply) and power considerations in the termination resistors and common-mode choke
ratings, use the average short circuit current. Determine the ratio of dominant and recessive bits by the data in
the CAN frame plus the following factors of the protocol and PHY that force either recessive or dominant at
certain times:
• Control fields with set bits
• Bit stuffing
• Interframe space
• TXD dominant time out (fault case limiting)
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These ensure a minimum recessive amount of time on the bus even if the data field contains a high percentage
of dominant bits. The short circuit current of the bus depends on the ratio of recessive to dominant bits and their
respective short circuit currents. The average short circuit current may be calculated with the following formula:
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC]
(1)
Where:
• IOS(AVG) is the average short circuit current
• %Transmit is the percentage the node is transmitting CAN messages
• %Receive is the percentage the node is receiving CAN messages
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
• IOS(SS)_REC is the recessive steady state short circuit current
• IOS(SS)_DOM is the dominant steady state short circuit current
NOTE
Consider the short circuit current and possible fault cases of the network when sizing the
power ratings of the termination resistance and other network components.
9.3.7 Digital Inputs and Outputs
9.3.7.1 5-V VCC Only Devices (Devices without the "V" Suffix):
The 5-V VCC only devices are supplied by a single 5-V rail. The digital inputs have TTL input thresholds and are
therefore 5 V and 3.3 V compatible. The RXD outputs on these devices are driven to the VCC rail for logic high
output. Additionally, the TXD pin is internally pulled up to VCC, and the S pin is pulled low to GND. The internal
bias of the mode pins may only place the device into a known state if the terminals float, they may not be
adequate for system-level biasing during transients or noisy enviroments.
NOTE
TXD pull up strength and CAN bit timing require special consideration when these devices
are used with CAN controllers with an open-drain TXD output. An adequate external pull
up resistor must be used to ensure that the CAN controller output of the micrcontroller
maintains adequate bit timing to the TXD input.
9.3.7.2 5 V VCC with VIO I/O Level Shifting (Devices with the "V" Suffix):
These devices use a 5 V VCC power supply for the CAN driver and high speed receiver blocks. These
transceivers have a second power supply for I/O level-shifting (VIO). This supply is used to set the CMOS input
thresholds of the TXD and S pins and the RXD high level output voltage. Additionally, the TXD pin is internally
pulled up to VIO, and the S pin is pulled low to GND.
18
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9.4 Device Functional Modes
The device has two main operating modes: Normal mode and Silent mode. Operating mode selection is made
via the S input terminal.
Table 4. Operating Modes
(1)
S Terminal
MODE
DRIVER
RECEIVER
RXD Terminal
LOW
Normal Mode
Enabled (ON)
Enabled (ON)
Mirrors Bus State (1)
HIGH
Silent Mode
Disabled (OFF)
Enabled (ON)
Mirrors Bus State (1)
Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.
9.4.1 CAN Bus States
The CAN bus has two states during powered operation of the device: dominant and recessive. A dominant bus
state is when the bus is driven differentially, corresponding to a logic low on the TXD and RXD terminal. A
recessive bus state is when the bus is biased to VCC / 2 via the high-resistance internal input resistors RIN of the
receiver, corresponding to a logic high on the TXD and RXD terminals.
Typical Bus Voltage (V)
Normal and Silent Mode
4
CANH
3
Vdiff(D)
2
Vdiff(R)
CANL
1
Time, t
Recessive
Logic H
Dominant
Logic L
Recessive
Logic H
Figure 13. Bus States (Physical Bit Representation)
9.4.2 Normal Mode
Select the Normal mode of device operation by setting S terminal low. The CAN driver and receiver are fully
operational and CAN communication is bi-directional. The driver translates a digital input on TXD to a differential
output on CANH and CANL. The receiver translates the differential signal from CANH and CANL to a digital
output on RXD.
9.4.3 Silent Mode
Activate Silent mode by setting S terminal high. The CAN driver is disabled, preventing communication from the
TXD pin to the CAN bus. The high speed receiver remains active so that CAN bus communication continues to
be relayed to the RXD output pin.
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9.4.4 Driver and Receiver Function Tables
Table 5. Driver Function Table
DEVICE
All Devices
INPUTS
S
(1)
L or open
H
(1)
(2)
OUTPUTS
TXD
(1) (2)
CANH
(1)
CANL (1)
DRIVEN BUS
STATE
L
H
L
Dominant
H or Open
Z
Z
Recessive
X
Z
Z
Recessive
H = high level, L = low level, X = irrelevant, Z = common mode (recessive) bias to VCC / 2. See
Figure 13 and for bus state and common mode bias information.
Devices have an internal pull up to VCC or VIO on TXD terminal. If the TXD terminal is open the
terminal will be pulled high and the transmitter will remain in recessive (non-driven) state.
Table 6. Receiver Function Table
DEVICE MODE
Normal or Silent
(1)
(2)
20
CAN DIFFERENTIAL INPUTS
VID = VCANH – VCANL
BUS STATE
RXD
TERMINAL (1)
VID ≥ VIT+(MAX)
Dominant
L (2)
VIT-(MIN) < VID < VIT+(MAX)
?
? (2)
VID ≤ VIT-(MIN)
Recessive
H (2)
Open (VID ≈ 0 V)
Open
H
H = high level, L = low level, ? = indeterminate.
See Receiver Electrical Characteristics section for input thresholds.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
These CAN transceivers are typically used in applications with a host microprocessor or FPGA that includes the
data link layer portion of the CAN protocol. Below are typical application configurations for both 5 V and 3.3 V
microprocessor applications. The bus termination is shown for illustrative purposes.
10.2 Typical Applications
Node n
Node 1
Node 2
Node 3
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
(with termination)
MCU or DSP
CAN
Controller
CAN
Transceiver
RTERM
RTERM
Figure 14. Typical CAN Bus Application
10.2.1 Design Requirements
10.2.1.1 Bus Loading, Length and Number of Nodes
The ISO 11898-2 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus.
A large number of nodes requires transceivers with high input impedance such as the TCAN1051 family of
transceivers.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2. They have made system-level trade-offs for data rate, cable length, and parasitic loading of the bus.
Examples of some of these specifications are ARINC825, CANopen, DeviceNet and NMEA2000.
The TCAN1051 family is specified to meet the 1.5 V requirement with a 50Ω load, incorporating the worst case
including parallel transceivers. The differential input resistance of the TCAN1051 family is a minimum of 30 kΩ. If
100 TCAN1051 family transceivers are in parallel on a bus, this is equivalent to a 300Ω differential load worst
case. That transceiver load of 300 Ω in parallel with the 60Ω gives an equivalent loading of 50 Ω. Therefore, the
TCAN1051 family theoretically supports up to 100 transceivers on a single bus segment. However, for CAN
network design margin must be given for signal loss across the system and cabling, parasitic loadings, network
imbalances, ground offsets and signal integrity thus a practical maximum number of nodes is typically much
lower. Bus length may also be extended beyond the original ISO 11898 standard of 40 m by careful system
design and datarate tradeoffs. For example CANopen network design guidelines allow the network to be up to 1
km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
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Typical Applications (continued)
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. In using this flexibility comes the
responsibility of good network design and balancing these tradeoffs.
10.2.2 Detailed Design Procedures
10.2.2.1 CAN Termination
The ISO 11898 standard specifies the interconnect to be a twisted pair cable (shielded or unshielded) with 120-Ω
characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used to
terminate both ends of the cable to prevent signal reflections. Unterminated drop lines (stubs) connecting nodes
to the bus should be kept as short as possible to minimize signal reflections. The termination may be on the
cable or in a node, but if nodes may be removed from the bus, the termination must be carefully placed so that
two terminations always exist on the network.
Termination may be a single 120-Ω resistor at the end of the bus, either on the cable or in a terminating node. If
filtering and stabilization of the common mode voltage of the bus is desired, then split termination may be used.
(See Figure 15). Split termination improves the electromagnetic emissions behavior of the network by eliminating
fluctuations in the bus common-mode voltages at the start and end of message transmissions.
Standard Termination
CANH
Split Termination
CANH
RTERM/2
CAN
Transceiver
RTERM
CAN
Transceiver
CSPLIT
RTERM/2
CANL
CANL
Copyright © 2016, Texas Instruments Incorporated
Figure 15. CAN Bus Termination Concepts
The TCAN1051 family of transceivers have variants for both 5-V only applications and applications where level
shifting is needed for a 3.3-V micrcontroller.
22
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Typical Applications (continued)
Figure 16. Typical CAN Bus Application Using 5 V CAN Controller
Figure 17. Typical CAN Bus Application Using 3.3 V CAN Controller
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Typical Applications (continued)
10.2.3 Application Curves
50
ICC Dominant (mA)
40
30
20
10
0
4.5
4.6
4.7
4.8
VCC = 4.5 V to 5.5
V
4.9
5
5.1
VCC (V)
5.2
VIO = 3.3 V
5.3
5.4
5.5
D005
RL = 60 Ω
CL = Open
Temp = 25°C
S=0V
Figure 18. ICC Dominant Current over VCC Supply Voltage
24
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11 Power Supply Requirements
These devices are designed to operate from a VCC input supply voltage range between 4.5 V and 5.5 V. Some
devices have an output level shifting supply input, VIO, designed for a range between 3.0 V and 5.5 V. Both
supply inputs must be well regulated. A bulk capacitance, typically 4.7 μF, should be placed near the CAN
transceiver's main VCC supply output, and in addition a bypass capacitor, typically 0.1 μF, should be placed as
close to the device's VCC and VIO supply terminals. This helps to reduce supply voltaeg ripple present on the
outputs of the switched-mode power supplies and also helps to compensate for the resistance and inductance of
the PCB power planes and traces.
12 Layout
Robust and reliable bus node design often requires the use of external transient protection device in order to
protect against EFT and surge transients that may occur in industrial enviroments. Because ESD and transients
have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-frequency layout techniques must
be applied during PCB design. The TCAN1051 family comes with high on-chip IEC ESD protection, but if higher
levels of system level immunity are desired external TVS diodes can be used. TVS diodes and bus filtering
capacitors should be placed as close to the on-board connectors as possible to prevent noisy transient events
from propagating further into the PCB and system.
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12.1 Layout Guidelines
•
•
•
Place the protection and filtering circuitry as close to the bus connector, J1, to prevent transients, ESD and
noise from propagating onto the board. In this layout example a transient voltage suppression (TVS) device,
D1, has been used for added protection. The production solution can be either bi-directional TVS diode or
varistor with ratings matching the application requirements. This example also shows optional bus filter
capacitors C4 and C5. Additionally (not shown) a series common mode choke (CMC) can be placed on the
CANH and CANL lines between the transceiver U1 and connector J1.
Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device.
Use supply (VCC) and ground planes to provide low inductance.
NOTE
High-frequency currents follows the path of least impedance and not the path of least
resistance.
•
•
•
•
•
•
•
Use at least two vias for supply (VCC) and ground connections of bypass capacitors and protection devices to
minimize trace and via inductance.
Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver,
examples are C1, C2 on the VCC supply and C6 and C7 on the VIO supply.
Bus termination: this layout example shows split termination. This is where the termination is split into two
resistors, R6 and R7, with the center or split tap of the termination connected to ground via capacitor C3. Split
termination provides common mode filtering for the bus. When bus termination is placed on the board instead
of directly on the bus, additional care must be taken to ensure the terminating node is not removed from the
bus thus also removing the termination. See the application section for information on power ratings needed
for the termination resistor(s).
To limit current of digital lines, serial resistors may be used. Examples are R2, R3, and R4. These are not
required.
Terminal 1: R1 is shown optionally for the TXD input of the device. If an open drain host processor is used,
this is mandatory to ensure the bit timing into the device is met.
Terminal 5: For "V" variants of the TCAN1051 family, bypass capacitors should be placed as close to the pin
as possible (example C6 and C7). For device options without VIO I/O level shifting, this pin is not internally
connected and can be left floating or tied to any existing net, for example a split pin connection.
Terminal 8: is shown assuming the mode terminal, S, will be used. If the device will only be used in normal
mode, R4 is not needed and R5 could be used for the pull down resistor to GND.
12.2 Layout Example
R5
R1
R2
TXD
R6
7
4
5
R7
C5
6
C6
C7
3
J1
C3
GND
D1
U1
U1
C2
C1
R3
C4
2
VCC
GND
8
1
GND
RXD
R4
S
VCC or VIO
GND
VIO
GND
26
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13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 7. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TCAN1051
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Click here
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TCAN1051G
Click here
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Click here
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TCAN1051GV
Click here
Click here
Click here
Click here
Click here
TCAN1051H
Click here
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Click here
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TCAN1051HV
Click here
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Click here
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TCAN1051HG
Click here
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TCAN1051HGV
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TCAN1051V
Click here
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Click here
Click here
Click here
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SOIC
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4
5
B
.150-.157
[3.81-3.98]
NOTE 4
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[ 0.11 -0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
.041
[1.04]
TYPICAL
4221445/B 04/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
SEE
DETAILS
SYMM
8X (.055)
[1.4]
SEE
DETAILS
SYMM
1
1
8
8X (.024)
[0.6]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
SYMM
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
.0028 MAX
[0.07]
ALL AROUND
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/B 04/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
SYMM
5
4
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/B 04/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OUTLINE
DRB0008F
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.05)
SECTION A-A
SECTION A-A
SCALE 30.000
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
EXPOSED
THERMAL PAD
1.6 0.05
(0.2) TYP
4
5
A
A
2X
1.95
2.4 0.05
8
1
6X 0.65
8X
PIN 1 ID
(OPTIONAL)
8X
0.5
0.3
0.35
0.25
0.1
0.05
C A B
C
4222121/C 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRB0008F
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.55)
( 0.2) VIA
TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222121/C 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRB0008F
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
8X (0.6)
METAL
TYP
1
8
8X (0.3)
(0.635)
SYMM
(1.07)
6X (0.65)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4222121/C 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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33
PACKAGE OPTION ADDENDUM
www.ti.com
16-Feb-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TCAN1051HD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
1051
TCAN1051HDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
1051
TCAN1051HGD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
1051
TCAN1051HGDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
1051
TCAN1051HGVD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
1051V
TCAN1051HGVDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
1051V
TCAN1051HVD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
1051V
TCAN1051HVDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
1051V
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
16-Feb-2017
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TCAN1051H, TCAN1051HG, TCAN1051HGV, TCAN1051HV :
• Automotive: TCAN1051H-Q1, TCAN1051HG-Q1, TCAN1051HGV-Q1, TCAN1051HV-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
IMPORTANT NOTICE
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Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
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Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
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