Texas Instruments | TLIN1028-Q1 Automotive Local Interconnect Network (LIN) Transceiver with Integrated Voltage Regulator | Datasheet | Texas Instruments TLIN1028-Q1 Automotive Local Interconnect Network (LIN) Transceiver with Integrated Voltage Regulator Datasheet

Texas Instruments TLIN1028-Q1 Automotive Local Interconnect Network (LIN) Transceiver with Integrated Voltage Regulator Datasheet
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TLIN1028-Q1
SLLSEX4 – AUGUST 2019
TLIN1028-Q1 Automotive Local Interconnect Network (LIN) Transceiver with Integrated
Voltage Regulator
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
AEC Q100 (Grade 1): Qualified for automotive
applications
Local interconnect network (LIN) physical layer
specification ISO/DIS 17987–4.2 compliant and
conforms to SAE J2602 recommended practice
for LIN
Supports 12 V applications
Wide Operating Ranges
– ±58 V LIN bus fault protection
– LDO output supporting 3.3 V or 5 V
– Sleep mode: ultra-low current
consumption allows wake up event from:
– LIN bus or local wake through EN pin
– Power up and down glitch-free operation
Protection Features:
– ESD protection
– Under voltage protection on VSUP
– TXD dominant time out (DTO) protection
– Thermal shutdown protection
– Unpowered node or ground disconnection
failsafe at system level
VCC sources 125 mA with DRB and DDA package
Available in SOIC (8) and HSOIC (8) package and
Leadless VSON (8) package with improved
automated optical inspection (AOI) capability
Body electronics and lighting
Hybrid, electric & powertrain systems
Automotive infotainment and cluster
Appliances
3 Description
The TLIN1028-Q1 is a local interconnect network
(LIN) physical layer transceiver, compliant to LIN 2.2A
ISO/DIS 17987–4.2 standards, with an integrated low
dropout (LDO) voltage regulator.
LIN is a single-wire bidirectional bus typically used for
low speed in-vehicle networks using data rates up to
20 kbps. The LIN receiver supports data rates up to
100 kbps for end-of-line programming. The
TLIN1028-Q1 converts the LIN protocol data stream
on the TXD input into a LIN bus signal. The receiver
converts the data stream to logic level signals that
are sent to the microprocessor through the opendrain RXD pin. The TLIN1028-Q1 reduces system
complexity by providing a 3.3 V or 5 V rail with up to
70 mA (D) and 125 mA (DRB and DDA) of current to
power microprocessors, sensors or other devices.
The TLIN1028-Q1 has an optimized current-limited
wave-shaping driver which reduces electromagnetic
emissions (EME).
Device Information(1)
PART NUMBER
PACKAGE
TLIN1028-Q1
BODY SIZE (NOM)
SOIC (8)
4.90 mm x 3.91 mm
HSOIC (8)
4.90 mm x 3.91 mm
VSON (8)
3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematics, Master Mode
Simplified Schematics, Slave Mode
MASTER
NODE
VBAT
VBAT
Slave Node
10 µF
10 µF
EN
2
100 nF
1
8
I/O
MCU w/o
pullup
Low
Power
MCU
Master Node
Pullup
5
LIN Bus
Low
Power
MCU
6
7
nRTS
LIN
200 pF
RXD
TXD
EN
1
8
100 nF
VDD I/O
4
LIN Controller
Or
SCI/UART
5
GND
LIN
LIN Bus
200 pF
RXD
TXD
3,PAD
2
I/O
1 kQ
4
GND
VDD
MCU w/o
pullup
VDD I/O
LIN Controller
Or
SCI/UART
VSUP
Vcc
VSUP
Vcc
VDD
6
7
3,PAD
nRTS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
1
TLIN1028-Q1
SLLSEX4 – AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
5
6
8
ABSOLUTE MAXIMUM RATINGS ...........................
ESD RATINGS..........................................................
ESD RATINGS, IEC SPECIFICATION .....................
RECOMMENDED OPERATING CONDITIONS .......
THERMAL INFORMATION.......................................
POWER SUPPLY CHARACTERISTICS ..................
ELECTRICAL CHARACTERISTICS .........................
AC SWITCHING CHARACTERISTICS.....................
8
Parameter Measurement Information .................. 9
9
Detailed Description ............................................ 19
9.2 Functional Block Diagram ....................................... 19
9.3 Feature Description................................................. 19
9.4 Device Functional Modes........................................ 22
10 Application and Implementation........................ 26
10.1 Application Information.......................................... 26
10.2 Typical Application ............................................... 26
11 Power Supply Recommendations ..................... 27
12 Layout................................................................... 28
12.1 Layout Guidelines ................................................. 28
12.2 Layout Example .................................................... 29
13 Device and Documentation Support ................. 30
13.1
13.2
13.3
13.4
13.5
13.6
13.7
8.1 Test Circuit: Diagrams and Waveforms .................... 9
ADVANCE INFORMATION
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
31
31
31
31
14 Mechanical, Packaging, and Orderable
Information ........................................................... 31
9.1 Overview ................................................................. 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
August 2019
*
Initial release.
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5 Description (continued)
Ultra-low current consumption is possible using the sleep mode which allows wake up via LIN bus or pin. The
LIN bus has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In the
recessive state, the LIN bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode. No external
pull-up components are required for slave applications. Master applications require an external pull-up resistor (1
kΩ) plus a series diode per the LIN specification.
6 Pin Configuration and Functions
D Package
8-Pin (SOIC)
Top View
VSUP
1
8
VCC
EN
2
7
nRST
GND
3
6
TX D
LIN
4
5
RX D
VSUP
1
EN
2
GND
3
LIN
4
No t to scale
Th ermal
Pad
8
VCC
7
nRST
6
TX D
5
RX D
ADVANCE INFORMATION
DRB Package
8-Pin (VSON)
Top View
No t to scale
DDA Package
8-Pin (HSOIC)
Top View
VSUP
1
EN
2
8
VCC
7
nRST
6
TX D
5
RX D
Th ermal
GND
3
LIN
4
Pad
No t to scale
Pin Functions
PIN
NO.
(1)
(2)
NAME
TYPE (1)
DESCRIPTION
1
VSUP
2
EN
HV Supply In Device supply voltage (connected to battery in series with external reverse blocking diode)
3
GND
4
LIN
HV I/O
5
RXD
DO
RXD output (open-drain) interface reporting state of LIN bus voltage
6
TXD
DI
TXD input interface to control state of LIN output
7
nRST
DO
Reset output (active low)
8
VCC
DI
GND
Supply Out
Enable input
Ground
(2)
LIN bus single-wire transmitter and receiver
Output voltage from integrated LDO
HV - High Voltage, DI - Digital Input, DO - Digital Output, HV I/O - High Voltage Input/Output
When the thermal pad is present, it must be soldered to ground plane.
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7 Specifications
7.1 ABSOLUTE MAXIMUM RATINGS
MIN
MAX
VSUP
Supply voltage range (ISO/DIS 17987)
–0.3
42
V
VLIN
LIN Bus input voltage (ISO/DIS 17987)
–58
58
V
VCC50
Regulated 5 V Output Supply
–0.3
6
V
VCC33
Regulated 3.3 V Output Supply
–0.3
4.5
V
VnRST
Reset output voltage
–0.3
VCC + 0.3
V
VLOGIC_INPUT
Logic input voltage
–0.3
6
V
VLOGIC_OUTPUT
Logic output voltage
–0.3
IVCC
VCC supply current
IO
Digital pin output current
IO(nRST)
Reset output current
TJ
Tstg
(1)
6
UNIT
V
300
mA
–8
8
mA
–5
5
mA
Junction temperature
–40
165
°C
Storage temperature range
–65
150
°C
ADVANCE INFORMATION
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD RATINGS
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM) classification level H2: VSUP, LIN, and WAKE with
respect to ground
±8000
Human body model (HBM) classification level 3A: all other pins, per AEC Q100002 (1)
±4000
Charged device model (CDM) classification level
All pins
C5, per AEC Q100-011
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 ESD RATINGS, IEC SPECIFICATION
V(ESD)
V(ESD)
Powered electrostatic discharge SAEJ2962-1 (3)
, LIN, VSUP terminal to
Transient
ISO7637-2 and IEC 62215-3 Transients
according to IBEE LIN EMC test spec (4)
Transient
ISO7637 Slow Transients Pulse
(1)
(2)
(3)
(4)
(5)
VALUE
UNIT
IEC 61000-4-2 contact discharge
±8000
V
SAEJ2962-1 contact discharge
±8000
SAEJ2962-1 air discharge
±15000
(1)
Electrostatic discharge
GND (2)
Pulse 1
-100
Pulse 2a
75
Pulse 3a
-150
Pulse 3b
100
SAEJ2962-1 (5) test spec and IBEE Zwickau
85
V
V
V
IEC 61000-4-2 is a system-level ESD test. Results given here are specific to the IBEE LIN EMC Test specification conditions. Different
system-level configurations may lead to different results
Testing performed at 3rd party IBEE Zwickau test house, test report available upon request.
SAEJ2962-1 Testing performed at 3rd party US3 approved EMC test facility, test report available upon request.
ISO7637 is a system-level transient test. Results given here are specific to the IBEE LIN EMC Test specification conditions. Different
system-level configurations may lead to different results.
ISO7637 is a system-level transient test. Results given here are specific to the SAEJ2962-1 Test specification conditions. Different
system-level configurations may lead to different results
7.4 RECOMMENDED OPERATING CONDITIONS
MIN
VSUP
Supply voltage
VLIN
VLOGIC5
4
NOM
MAX
UNIT
5.5
28
V
LIN bus input voltage
0
28
V
Logic pin voltage
0
5.25
V
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RECOMMENDED OPERATING CONDITIONS (continued)
MIN
NOM
0
MAX
UNIT
3.465
V
VLOGIC33
Logic pin voltage
IOH(DO)
Digital terminal HIGH level output current
IOL(DO)
Digital terminal LOW level output current
C(VSUP)
VSUP supply capacitor
100
nF
C(VCC)
VCC supply capacitor
10
µF
ESRCO
Output ESR requirements
-2
mA
2
0.001
mA
2
Ω
7.5 THERMAL INFORMATION
TLIN1028x
D
DRB
DDA
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
119.4
45.7
40.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.5
49.2
60.5
°C/W
RθJB
Junction-to-board thermal resistance
64.9
18.9
15.6
°C/W
ψJT
Junction-to-top characterization parameter
9.6
0.7
4.0
°C/W
ψJB
Junction-to-board characterization parameter
63.7
18.8
15.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
2.7
4.6
°C/W
(1)
ADVANCE INFORMATION
THERMAL METRIC (1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 POWER SUPPLY CHARACTERISTICS
parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND CURRENT
Device is operational beyond the LIN
defined nominal supply voltage range. See
Figure 1 and Figure 2
5.5
36
V
Normal and Standby Modes: Ramp VSUP
while LIN signal is a 10 kHz square wave
with 50 % duty cycle and swing between 5.5
V ≤ VLIN ≤ 28 V. See Figure 1 and Figure 2
5.5
28
V
Sleep Mode
5.5
VSUP
Operational supply voltage (ISO/DIS 17987
Param 10)
VSUP
Nominal supply voltage (ISO/DIS 17987
Param 10):
UVSUPR
Under voltage VSUP threshold
Ramp Up
UVSUPF
Under voltage VSUP threshold
Ramp Down
UVHYS
Delta hysteresis voltage for VSUP under
voltage threshold
ISUP
Transceiver and LDO supply current (D
Package)
Transceiver normal mode dominant plus
LDO output
80
mA
ISUP
Transceiver and LDO supply current (DRB
and DDA Packages)
Transceiver normal mode dominant plus
LDO output
135
mA
ISUPTRXDOM
Supply current transceiver only
1.8
Supply current transceiver only
V
2.1
2.5
V
V
Normal Mode: EN = VCC, bus dominant: total
bus load where RLIN ≥ 500 Ω and CLIN ≤ 10
nF
1.2
7.5
mA
Standby Mode: EN = 0 V, bus dominant:
total bus load where RLIN ≥ 500 Ω and CLIN ≤
10 nF
1
2.1
mA
450
775
µA
38
55
Standby Mode: EN = 0 V, LIN = recessive =
VSUP, IOZH from processor ≤ 1 µA
Added Standby Mode current through the
RXD pull-up resistor with a value of 100 kΩ:
EN = 0 V, LIN = recessive = VSUP, RXD =
GND (1)
(1)
V
4.2
1.5
Normal Mode: EN = VCC,
Bus recessive: LIN = VSUP,
ISUPTRXREC
28
3.5
µA
55
RXD pin is an open drain output. In standby mode RXD is pulled low which has the device pulling current through VSUP through the
pull-up resisitor to VCC. The value of the pull-up resistor impacts the standby mode current. A 10 kΩ resistor value can add as much at
500 µA of current.
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POWER SUPPLY CHARACTERISTICS (continued)
parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted)
PARAMETER
ISUPTRXSLP
TEST CONDITIONS
Sleep mode supply current transceiver only
MIN
5.5 V < VSUP ≤ 28 V, LIN = VSUP, EN = 0 V,
TXD and RXD floating
TYP
MAX
UNIT
11
27
µA
%
REGULATED OUTPUT VCC
ADVANCE INFORMATION
VCC
Regulated output (D package)
VSUP = 5.5 to 28 V, ICC = 1 to 70 mA
–2
2
VCC
Regulated output (DRB and DDA package)
VSUP = 5.5 to 28 V, ICC = 1 to 125 mA
–2
2
%
∆VCC(∆VSUP)
Line regulation
VSUP = 5.5 to 28 V, ΔVCC, ICC = 10 mA
50
mV
∆VCC(∆VSUPL)
Load regulation (DRB and DDA package)
ICC = 1 to 125 mA, VSUP = 14 V, ΔVCC
50
mV
∆VCC(∆VSUPL)
Load regulation (D package)
ICC = 1 to 70 mA, VSUP = 14 V, ΔVCC
50
mV
VDROP
Dropout voltage (5 V LDO) (DRB and DDA
package)
VSUP – VCC, ICC = 125 mA;
300
600
mV
VDROP
Dropout voltage (5 V LDO) (D package)
VSUP – VCC, ICC = 70 mA;
300
600
mV
VDROP
Dropout voltage (3.3 V LDO) (DRB and DDA
package)
VSUP – VCC, ICC = 125 mA;
350
700
mV
VDROP
Dropout voltage (3.3 V LDO) (D package)
VSUP – VCC, ICC = 70 mA;
350
700
mV
UVCC5R
Under voltage 5 V VCC threshold
Ramp Up
4.7
4.86
V
UVCC5F
Under voltage 5 V VCC threshold
Ramp Down
UVCC33R
Under voltage 3.3 V VCC threshold
Ramp Up
UVCC33F
Under voltage 3.3 V VCC threshold
Ramp Down
tDET(UVCC)
VCC undervoltage deglitch time. An UVCC
event will not be recognized unless it last
longer than this.
CnRST = 20pF
1
ICCOUT
Output current (D Package)
VCC in regulation with 12 V VSUP
ICCOUT
Output current (DRB and DDA package)
VCC in regulation with 12 V VSUP
ICCOUTL
Output current limit
VCC short to ground
PSRR
Power supply rejection ripple rejection
VRIP = 0.5 VPP, Load = 10 mA, ƒ = 100 Hz,
CO = 10 μF
TSDR
Thermal shutdown temperature
Internal junction temperature - rising
TSDF
Thermal shutdown temperature
Internal junction temperature - falling
TSDHYS
Thermal shutdown hysteresis
4.2
4.45
2.9
2.5
V
3.1
2.75
V
V
15
µs
0
70
mA
0
125
mA
275
mA
60
dB
165
°C
150
10
°C
°C
7.7 ELECTRICAL CHARACTERISTICS
parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RXD OUTPUT TERMINAL (OPEN DRAIN)
VOL
Output low voltage
Based upon a 2 kΩ to 10 kΩ external pull-up
to VCC
IOL
Low level output current, open drain
LIN = 0 V, RXD = 0.4 V
1.5
ILKG
Leakage current, high-level
LIN = VSUP, RXD = VCC
–5
0.2
VCC
mA
0
5
µA
V
TXD INPUT TERMINAL
VIL
Low level input voltage
–0.3
0.8
VIH
High level input voltage
2
5.5
V
IIH
High level input leakage current
RTXD
Internal pull-up resistor value
TXD = high
–5
0
5
µA
125
350
800
kΩ
LIN TERMINAL (REFERENCED TO VSUP)
VOH
HIGH level output voltage
LIN recessive, TXD = high, IO = 0 mA, VSUP
= 5.5 V to 36 V
VOL
LOW level output voltage
LIN dominant, TXD = low, VSUP = 5.5 V to
36 V
VSUP_NON_OP
VSUP where impact of recessive LIN bus < 5%
(ISO/DIS 17987 Param 11)
TXD & RXD open, VLIN = 5.5 V to 42 V, Bus
Load = 60 kΩ + diode and 1.1 kΩ + diode
I BUS_LIM
Limiting current (ISO/DIS 17987 Param 12)
TXD = 0 V, VLIN = 36 V, RMEAS = 440 Ω,
VSUP = 36 V,
VBUSdom < 4.518 V; Figure 6
6
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0.85
VSUP
–0.3
40
90
0.2
VSUP
42
V
200
mA
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ELECTRICAL CHARACTERISTICS (continued)
parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I BUS_PAS_dom
VLIN = 0 V, VSUP = 12 V Driver off/recessive,
RMEAS = 499 Ω; Figure 7
I BUS_PAS_rec1
Receiver leakage current, recessive (ISO/DIS
17987 Param 14)
VLIN ≥ VSUP, 5.5 V ≤ VSUP ≤ 36 V Driver off,
RMEAS = 1 kΩ; Figure 8
I BUS_PAS_rec2
Receiver leakage current, recessive (ISO/DIS
17987 Param 14)
VLIN = VSUP, Driver off, RMEAS = 1 kΩ;
Figure 8
I BUS_NO_GND
Leakage current, loss of ground (ISO/DIS 17987
Param 15)
GND = VSUP, VSUP = 12 V, 0 V ≤ VLIN ≤ 28
V, RMEAS = 1 kΩ; Figure 9
IBUS_NO_BAT
Leakage current, loss of supply (ISO/DIS 17987
Param 16)
0 V ≤ VLIN ≤ 28 V, VSUP = GND, RMEAS = 10
kΩ; Figure 10
VBUSdom
Low level input voltage (ISO/DIS 17987 Param
17)
LIN dominant (including LIN dominant for
wake up); Figure 3, Figure 4
VBUSrec
High level input voltage (ISO/DIS 17987 Param
18)
LIN recessive; Figure 3, Figure 4
VBUS_CNT
Receiver center threshold (ISO/DIS 17987 Param
VBUS_CNT = (VIL + VIH)/2; Figure 3, Figure 4
19)
VHYS
Hysteresis voltage (ISO/DIS 17987 Param 20)
VHYS = (VIL - VIH); Figure 3, Figure 4
VSERIAL_DIODE
Serial diode LIN term pull-up path (ISO/DIS
17987 Param 21)
By design and characterization
0.4
0.7
1.0
V
RSLAVE
Pull-up resistor to VSUP (ISO/DIS 17987 Param
26)
Normal and Standby modes
20
45
60
kΩ
IRSLEEP
Pull-up current source to VSUP
Sleep mode, VSUP = 12 V, LIN = GND
–2
µA
CLIN,PIN
Capacitance of the LIN pin
55
pF
V
–1
mA
20
µA
–8
8
µA
–1
1
mA
8
µA
0.4
0.6
0.475
VSUP
VSUP
0.5
–20
0.525
VSUP
0.175
VSUP
ADVANCE INFORMATION
PARAMETER
Receiver leakage current, dominant (ISO/DIS
17987 Param 13)
EN INPUT TERMINAL
VIH
High level input voltage
2
5.5
VIL
Low level input voltage
–0.3
0.8
V
VHYS
Hysteresis voltage
By design and characterization
30
500
mV
IIL
Low level input current
EN = Low
REN
Internal pull-down resistor
–5
0
5
µA
125
350
800
kΩ
nRST TERMINAL (OPEN DRAIN OUTPUT)
ILKG
Leakage current, high-level
LIN = VSUP, nRST = VCC
VOL
Low-level output voltage
Based upon external pull up to VCC
IOL
Low-level output current, open drain
LIN = 0 V, nRST = 0.4 V
–5
5
µA
0.2
VCC
1.5
mA
DUTY CYCLE CHARACTERISTICS
D112V
D212V
D312V
D412V
Duty Cycle 1 (ISO/DIS 17987 Param 27)
THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP,
VSUP = 5.5 V to 18 V, tBIT = 50 µs (20 kbps),
D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 11,
Figure 12)
Duty Cycle 2 (ISO/DIS 17987 Param 28)
THREC(MIN) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP, VSUP = 5.5 V to
18 V,
tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x
tBIT) (See Figure 11, Figure 12)
Duty Cycle 3 (ISO/DIS 17987 Param 29)
THREC(MAX) = 0.778 x VSUP, THDOM(MAX) =
0.616 x VSUP,
VSUP = 5.5 V to 18 V, tBIT = 96 µs (10.4
kbps),
D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 11,
Figure 12)
Duty Cycle 4 (ISO/DIS 17987 Param 30)
THREC(MIN) = 0.389 x VSUP,
THDOM(MIN) = 0.251 x VSUP,
VSUP = 5.5 V to 18 V, tBIT = 96 µs (10.4
kbps),
D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 11,
Figure 12)
0.396
0.581
0.417
0.59
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7.8 AC SWITCHING CHARACTERISTICS
parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEVICE SWITCHING CHARACTERISTICS
trx_pdr
trx_pdf
Receiver rising/falling propagation delay time
(ISO/DIS 17987 Param 31)
RRXD = 2.4 kΩ, CRXD = 20 pF
(See Figure 13, Figure 14 and Figure 18)
trs_sym
Symmetry of receiver propagation delay time
Receiver rising propagation delay time (ISO/DIS
17987 Param 32)
Rising edge with respect to falling edge,
(trx_sym = trx_pdf – trx_pdr), RRXD = 2.4 kΩ, CRXD
= 20 pF (Figure 13, Figure 14 and Figure 18)
tLINBUS
LIN wakeup time (minimum dominant time on LIN
See Figure 17, Figure 21 and Figure 22
bus for wakeup)
tCLEAR
Time to clear false wakeup prevention logic if LIN
bus had a bus stuck dominant fault (recessive
See Figure 22
time on LIN bus to clear bus stuck dominant fault)
tDST
Dominant state time out
–2
6
µs
2
µs
25
100
150
µs
8
17
50
µs
20
34
80
ms
12
µs
ADVANCE INFORMATION
tEN
Enable pin deglitch time
Time enable pin state change before
initiating mode change or sampling TXD
pine: See Figure 15
tMODE_CHANGE
Mode change delay time sleep mode to normal
mode
Time to change from normal mode to sleep
or standby after TXD pin sampling after EN
pin set low: See Figure 15
20
µs
tMODE_CHANGE
Mode change delay time sleep mode to normal
mode
Time to change from sleep mode to normal
mode through EN pin and not due to a wake
event; RXD pulled up to VCC: See Figure 15
800
µs
tNOMINT
Normal mode initialization time
Time for normal mode to initialize and data
on RXD pin to be valid after tEN See
Figure 15
30
µs
tPWR
Power up time
Upon power up time it takes for valid data on
RXD
1.5
ms
8
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8 Parameter Measurement Information
8.1 Test Circuit: Diagrams and Waveforms
5
8
2
1
VSUP
EN
7
4
LIN
6
3
GND
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS
Pulse Generator
tR/tF: Square Wave: < 20 ns
:
tR/tF Triangle Wave: < 40ns
Frequency: 20 Hz
Jitter: < 25 ns
ADVANCE INFORMATION
VCC
RXD
VCC
Measurement Tools
O-scope:
DMM
Figure 1. Test System: Operating Voltage Range with RX and TX Access
Trigger Point
Delta t = + 5 µs (tBIT
= 50 µs)
RX
2 * tBIT = 100 µs (20 kBaud)
Figure 2. RX Response: Operating Voltage Range
Period T = 1/f
LIN Bus Input
Amplitude
(signal range)
Frequency: f = 20 Hz
Symmetry: 50%
Figure 3. LIN Bus Input Signal
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Test Circuit: Diagrams and Waveforms (continued)
5
VCC
RXD
8
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VCC
2
1
VPS
VSUP
EN
7
4
LIN
6
Pulse Generator
tR/tF: Square Wave: < 20 ns
:
tR/tF Triangle Wave: < 40ns
Frequency: 20 Hz
Jitter: < 25 ns
3
GND
ADVANCE INFORMATION
Measurement Tools
O-scope:
DMM
Figure 4. LIN Receiver Test with RX access
5
VCC
8
VCC
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
1
2
EN
VSUP
VPS1
D
3
6
4
LIN
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
3
GND
RBUS
VPS2
Measurement Tools
O-scope:
DMM
Figure 5. VSUP_NON_OP Test Circuit
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Test Circuit: Diagrams and Waveforms (continued)
5
VCC
1
VCC
2
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS
7
VSUP
EN
7
4
RMEAS =
440
LIN
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
T = 10 ms
Jitter: < 25 ns
6
3
TXD
GND
ADVANCE INFORMATION
Measurement Tools
O-scope:
DMM
Figure 6. Test Circuit for IBUS_LIM at Dominant State (Driver on)
5
VCC
8
VCC
2
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS
1
EN
VSUP
4
7
RMEAS = 499 Ÿ
LIN
3
6
GND
Measurement Tools
O-scope:
DMM
Figure 7. Test Circuit for IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V
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Test Circuit: Diagrams and Waveforms (continued)
5
VCC
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
8
VCC
VPS1
2
1
EN
VSUP
4
7
LIN
6
GND
RMEAS
=1 kŸ
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS2
VPS2 2 V/s ramp
[8 V Æ 36 V]
3
V Drop across resistor
< 20 mV
ADVANCE INFORMATION
Measurement Tools
O-scope:
DMM
Figure 8. Test Circuit for IBUS_PAS_rec
5
VCC
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
8
VCC
VPS1
2
EN
VSUP
1
4
7
LIN
6
GND
RMEAS
= 1 kŸ
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS2
3
VPS2 2 V/s ramp
[0 V Æ 36 V]
V Drop across resistor
< 1V
Measurement Tools
O-scope:
DMM
Figure 9. Test Circuit for IBUS_NO_GND Loss of GND
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Test Circuit: Diagrams and Waveforms (continued)
5
VCC
8
VCC
2
1
VSUP
EN
7
LIN
6
GND
Power Supply 2
Resolution: 10mV/ 1mA
VPS Accuracy: 0.2%
RMEAS =
10 kŸ
4
VPS 2 V/s ramp
[0 V Æ 36 V]
3
V Drop across resistor
< 1V
ADVANCE INFORMATION
Measurement Tools
O-scope:
DMM
Figure 10. Test Circuit for IBUS_NO_BAT Loss of Battery
5
VCC
8
VCC
2
EN
VSUP
VPS1
4
7
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
Jitter: < 25 ns
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
1
RMEAS
LIN
6
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
3
TXD
VPS2
GND
Measurement Tools
O-scope:
DMM
Figure 11. Test Circuit Slope Control and Duty Cycle
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Test Circuit: Diagrams and Waveforms (continued)
tBIT
tBIT
RECESSIVE
D=
0.5
TXD (Input)
DOMINANT
THREC(MAX)
Thresholds
RX Node 1
THDOM(MAX)
LIN Bus
Signal
VSUP
THREC(MIN)
Thresholds
RX Node 2
THDOM(MIN)
ADVANCE INFORMATION
tBUS_DOM(MAX)
tBUS_REC(MIN)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
D = tBUS_REC(MIN)/(2 x tBIT)
tBUS_DOM(MIN)
tBUS_REC(MAX)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
D = tBUS_REC(MIN)/(2 x tBIT)
Figure 12. Definition of Bus Timing
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Test Circuit: Diagrams and Waveforms (continued)
VCC
2.4 kŸ
5
VCC
RXD
8
VCC
2
1
VSUP
EN
VPS
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
4
7
LIN
3
6
GND
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
Jitter: < 25 ns
ADVANCE INFORMATION
20 pF
Measurement Tools
O-scope:
DMM
Figure 13. Propagation Delay Test Circuit
THREC(MAX)
LIN Bus
Signal
Thresholds
RX Node 1
THDOM(MAX)
VSUP
THREC(MIN)
Thresholds
RX Node 2
THDOM(MIN)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
trx_pdr(1)
trx_pdf(1)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
trx_pdr(2)
trx_pdf(2)
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Figure 14. Propagation Delay
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Test Circuit: Diagrams and Waveforms (continued)
Wake Event
tMODE_CHANGE
tMODE_CHANGE
tNOMINT
tEN
EN
tEN
Can be high or low
TXD
MODE
Normal
EN
Filter/TXD
Sampling
Window
Transition
Sleep
Standby
Enable
Filter
ADVANCE INFORMATION
RXD
Normal
Can be high or low
TXD
MODE
Transition
Normal
Mirrors Bus
EN
Filter/TXD
Sampling
Window
Transition
Indeterminate Ignore
Enable
Filter
Standby
¾
¾
Floating for sleep
Floating for normal Æ
standby
Wake Request
RXD = Low
Transition
Indeterminate Ignore
Normal
Mirrors
Bus
Figure 15. Mode Transitions
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Test Circuit: Diagrams and Waveforms (continued)
EN
tEN
Weak Internal Pullup
Weak Internal Pullup
VSUP
LIN
RXD
Floating
MODE
Sleep
tMODE_CHANGE
+
tNOMINIT
ADVANCE INFORMATION
TXD
Normal
Figure 16. Wakeup Through EN
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Test Circuit: Diagrams and Waveforms (continued)
0.6 x VSUP
LIN
0.6 x VSUP
VSUP
0.4 x VSUP
0.4 x VSUP
t < tLINBUS
TXD
tLINBUS
Weak Internal Pullup
ADVANCE INFORMATION
EN
RXD
MODE
Floating
Sleep
Standby
Normal
Figure 17. Wakeup through LIN
VSUP
100 nF
VCC
10 µF
10 µF
EN
RLIN
GND
nRST
TXD
RRXD
LIN
RXD
CLIN
CRXD
Figure 18. Test Circuit for AC Characteristics
18
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9 Detailed Description
9.1 Overview
The TLIN1028-Q1 LIN transceiver is a Local Interconnect Network (LIN) physical layer transceiver, compliant to
LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4.2 with integrated wake-up and protection features. The
LIN bus is a single-wire, bidirectional bus that typically is used in low speed in-vehicle networks with data rates
that range up to 20 kbps. The LIN receiver works up to 100 kbps supporting in-line programming. The device
converts the LIN protocol data stream on the TXD input into a LIN bus signal using a current-limited waveshaping driver which reduces electromagnetic emissions (EME). The receiver converts the data stream to logic
level signals that are sent to the microprocessor through the open-drain RXD pin. The LIN bus has two states:
dominant state (voltage near ground) and recessive state (voltage near battery). In the recessive state, the LIN
bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode.
Ultra-low current consumption is possible using the sleep mode. The TLIN1028 provides two methods to wake
up from sleep mode: EN pin and LIN bus. The device integrates a low dropout voltage regulator with a wide input
from VSUP providing 5 V ±2% or 3.3 V ±2% with up to 125 mA of current depending upon system implementation.
nRST is asserted high when VCC increases above UVCC and stays high as long as VCC is above this threshold.
VSUP
ADVANCE INFORMATION
9.2 Functional Block Diagram
VCC
5.0 V or 3.3 V LDO
UV
DET
POR
CNTL
VSUP
RXD
VSUP/2
Comp
VCC
250 kO
Filter
nRST
45 kQ
Control
EN
350 lQ
Fault
Detection
& Protection
VCC
350 lQ
Dominant
State
Timeout
TXD
DR/
Slope
CTL
LIN
GND
Figure 19. Functional Block Diagram
9.3 Feature Description
9.3.1 LIN (Local Interconnect Network) Bus
This high voltage input or output pin is a single wire LIN bus transmitter and receiver. The LIN pin can survive
transient voltages up to 58 V. Reverse currents from the LIN to supply (VSUP) are minimized with blocking diodes,
even in the event of a ground shift or loss of supply (VSUP).
9.3.1.1 LIN Transmitter Characteristics
The transmitter meets thresholds and AC parameters according to the LIN specification. The transmitter is a low
side transistor with internal current limitation and thermal shutdown. During a thermal shutdown condition, the
transmitter is disabled to protect the device. There is an internal pull-up resistor with a serial diode structure to
VSUP, so no external pull-up components are required for the LIN slave mode applications. An external pull-up
resistor and series diode to VSUP must be added when the device is used for a master node application.
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Feature Description (continued)
9.3.1.2 LIN Receiver Characteristics
The receiver characteristic thresholds are ratio-metric with the device supply pin according to the LIN
specification.
The receiver is capable of receiving higher data rates (> 100 kbps) than supported by LIN or SAEJ2602
specifications. This allows the TLIN1028-Q1 to be used for high speed downloads at the end-of-line production or
other applications. The actual data rate achievable depends on system time constants (bus capacitance and pullup resistance) and driver characteristics used in the system.
9.3.1.2.1 Termination
There is an internal pull-up resistor with a serial diode structure to VSUP, so no external pull-up components are
required for the LIN slave mode applications. An external pull-up resistor (1 kΩ) and a series diode to VSUP must
be added when the device is used for master node applications as per the LIN specification.
Figure 20 shows a master node configuration and how the voltage levels are defined
Simplified Transceiver
VLIN_Bus
ADVANCE INFORMATION
VSUP
VSUP/2
RXD
Voltage drop across the
diodes in the pullup path
VBAT
VBattery
VSUP
Receiver
VLIN_Recessive
Filter
1k
45 kŸ
LIN
LIN Bus
VCC
350 k
TXD
GND
Transmitter
with slope control
VLIN_Dominant
t
Figure 20. Master Node Configuration with Voltage Levels
9.3.2 TXD (Transmit Input and Output)
TXD is the interface to the node processors’s LIN protocol controller that is used to control the state of the LIN
output. When TXD is low, the LIN output is dominant (near ground). When TXD is high, the LIN output is
recessive (near VSUP). See Figure 20. The TXD input structure is compatible with processors with 3.3 V and 5 VI
and VO. TXD has an internal pull-up resistor. The LIN bus is protected from being stuck dominant through a
system failure driving TXD low through the dominant state time-out timer.
9.3.3 RXD (Receive Output)
RXD is the interface to the processors LIN protocol controller, which reports the state of the LIN bus voltage. LIN
recessive (near VSUP) is represented by a high level on the RXD and LIN dominant (near ground) is represented
by a low level on the RXD pin. The RXD output structure is an open-drain output stage. This allows the device to
be used with 3.3 V and 5 VI/O processors. If the processors RXD pin does not have an integrated pull-up, an
external pull-up resistor to the processors I and O supply voltage is required. In standby mode, the RXD pin is
driven low to indicate a wake up request from the LIN bus. When going from normal mode to standby mode the
RXD pin is released and pulled up to the voltage rail the external pull-up resistor is connected. It is pulled low if a
wake event takes place.
9.3.4 VSUP (Supply Voltage)
VSUP is the power supply pin. VSUP is connected to the battery through an external reverse battery-blocking
diode.
20
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Feature Description (continued)
The VSUP pin is a high-voltage-tolerant pin. Decoupling capacitor with a value of 100 nF is recommended to be
connected close to this pin to better the transient performance. If there is a loss of power at the ECU level, the
device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN
systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains
powered (battery supplied). When VSUP drops low enough the regulated output drops out of regulation. The LIN
bus works with a VSUP as low as 5.5 V, but at a lower voltage, the performance is indeterminate and not ensured.
If VSUP voltage level drops enough, it triggers the UVSUP, and if it keeps dropping, at some point it passes the
POR threshold.
9.3.5 GND (Ground)
GND is the device ground connection. The device can operate with a ground shift as long as the ground shift
does not reduce the VSUP below the minimum operating voltage. If there is a loss of ground at the ECU level, the
device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN
systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains
powered (battery supplied).
EN controls the operational modes of the device. When EN is high, the device is in normal operating mode
allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low, the device is put into sleep
mode and there are no transmission paths available. EN has an internal pull-down resistor to ensure the device
remains in low power mode even if EN is left floating. EN should be held low until VSUP reaches the expected
system voltage level.
9.3.7 nRST (Reset Output)
The VCC pin is monitored for under voltage events. This pin is internally pulled up to VCC and when an
undervoltage event takes place, this pin is pulled low. The pin returns to VCC once the voltage on VCC exceeds
the under voltage threshold. nRST is only dependent upon UVCC and not dependent upon the operational mode.
If UVCC takes place for longer than tDET(UVCC) nRST is pulled low. If a thermal shutdown event takes place, this
pin is pulled to ground.
9.3.8 VCC (Supply Output)
The VCC terminal can provide 5 V or 3.3 V with up to 125 mA to power up external devices when using high-k
boards and thermal management best practices in order to keep the virtual junction temperature below 150 °C.
9.3.9 Protection Features
The device has several protection features that are described as follows.
9.3.9.1 TXD Dominant Time Out (DTO)
During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application
failure, the LIN bus is protected by the dominant state time-out timer. This timer is triggered by a falling edge on
the TXD pin. If the low signal remains on TXD for longer than tDST, the transmitter is disabled, thus allowing the
LIN bus to return to recessive state and communication to resume on the bus. The protection is cleared and the
tDST timer is reset by a rising edge on TXD. The TXD pin has an internal pull-up to ensure the device fails to a
known recessive state if TXD is disconnected. During this fault, the transceiver remains in normal mode
(assuming no change of stated request on EN), the RXD pin reflects the LIN bus and the LIN bus pull-up
termination remains on.
9.3.9.2 Bus Stuck Dominant System Fault: False Wake Up Lockout
The device contains logic to detect bus stuck dominant system faults and prevents the device from waking up
falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus. If the bus
is dominant, the wake up logic is locked out until a valid recessive on the bus “clears” the bus stuck dominant,
preventing excessive current use. Figure 21 and Figure 22 show the behavior of this protection.
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ADVANCE INFORMATION
9.3.6 EN (Enable Input)
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Feature Description (continued)
EN
LIN Bus
< tLINBUS
< tLINBUS
tLINBUS
Figure 21. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wakeup
EN
ADVANCE INFORMATION
tLINBUS
tLINBUS
LIN Bus
tLINBUS
tCLEAR
< tCLEAR
Figure 22. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wakeup
9.3.9.3 Thermal Shutdown
The LIN transmitter is protected by current limiting circuit; however, if the junction temperature of the device
exceeds the thermal shutdown threshold, the device puts the LIN transmitter into the recessive state and turns
off the VCC regulator. The nRST pin is pulled to ground during a TSD event. Once the over-temperature fault
condition has been removed and the virtual junction temperature has cooled beyond the hysteresis temperature,
the transmitter is re-enabled. During this fault the device enters a TSD off mode. Once the junction temperature
cools, the device enters standby mode as per the state diagram.
9.3.9.4 Under Voltage on VSUP
The device contains a power-on reset circuit to avoid false bus messages during under voltage conditions when
VSUP is less than UVSUP.
9.3.9.5 Unpowered Device and LIN Bus
In automotive applications, some LIN nodes in a system can be unpowered (ignition supplied) while others in the
network remain powered by the battery. The device has extremely low unpowered leakage current from the bus,
so an unpowered node does not affect the network or load it down.
9.4 Device Functional Modes
The TLIN1028-Q1 has three functional modes of operation, normal, sleep, and standby. The next sections
describes these modes as well as how the device moves between the different modes. Figure 23 graphically
shows the relationship while Table 1 shows the state of pins.
Table 1. Operating Modes
Mode
EN
RXD
LIN BUS
Termination
Transmitter
nRST
Comment
Sleep
Low
Floating
Weak Current pullup
Off
Ground
nRST is internally connected to the LDO output which
in sleep mode is pulled to ground
22
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Device Functional Modes (continued)
Table 1. Operating Modes (continued)
Mode
EN
RXD
LIN BUS
Termination
Transmitter
nRST
Comment
Standby
Init
Low
Floating
45 kΩ (typical)
Off
Ramping
nRST is internally connected to the LDO output which
in standby init mode is pulled low until VCC raises
beyond UVCC threshold.
Standby
from
SLP
Low
Low
45 kΩ (typical)
Off
VCC
Wake up event detected, waiting on processors to set
EN
nRST comes on to VCC once thresholds are met.
Standby
from
Norm
Low
Floating
45 kΩ (typical)
Off
VCC
LDO is on and RXD is floating. If a wake event takes
place RXD is pulled low.
Normal
High
LIN Bus
Data
45 kΩ (typical)
On
VCC
LIN transmission up to 20 kbps
TSD Off
NA
Floating
45 kΩ (typical)
Off
Ground
nRST is pulled low as the LDO is turned off which
means UVCC threshold has been met.
Unpowered State
ADVANCE INFORMATION
VSUP < UVSUP
VSUP < UVSUP
VSUP • 89SUP
Standby Init Mode
EN = High
Transceiver: Off
WUP Receiver: Off
RXD: Floating
Termination: 45 NŸ
LDO: Ramping up
Any State
EN = Low
Tj > TSD
TSD Off Mode
Standby Mode
EN = Low > tEN
AND TXD = High
AND nRST = High
Transceiver: Off
WUP Receiver: On
RXD: Signals wake event
Termination: 45 NŸ
LDO: On
nRST: High
Tj < TSD
Transceiver: Off
WUP Receiver: On
RXD: Floating
Termination: 45 NŸ
LDO: Off
nRST: Low (Fault Condition)
VSUP < UVSUP
LIN Bus Wake up
Unpowered State
EN = High > tEN
nRST = High
Normal Mode
Transceiver: On
WUP Receiver: Off
RXD: LIN Bus Data
Termination: 45 NŸ
LDO: On
nRST: High
VSUP < UVSUP
VSUP < UVSUP
EN = Low > tEN
AND TXD = Low
AND nRST = High
EN = High > tEN
Sleep Mode
Transceiver: Off
WUP Receiver: On
RXD: Floating
Termination: Weak pullup
LDO: Off
nRST: Low
Figure 23. Operating State Diagram
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9.4.1 Normal Mode
If the EN pin is high after the device enters standby init mode it enters normal mode. If EN is low, it enters
standby mode. In normal operational mode, the receiver and transmitter are active and the LIN transmission up
to the LIN specified maximum of 20 kbps is supported. The receiver detects the data stream on the LIN bus and
outputs it on RXD for the LIN controller. A recessive signal on the LIN bus is a digital high and a dominant signal
on the LIN bus is a digital low. The driver transmits input data from TXD to the LIN bus. Normal mode is entered
as EN transitions high while the device is in sleep or standby mode for > tEN. Once EN has been high for tEN the
device enters normal mode after tMODE_CHANGE and tNOMINIT times.
9.4.2 Sleep Mode
Sleep Mode is the power saving mode for the TLIN1028-Q1. Even with extremely low current consumption in this
mode, the device can still wake up from the LIN bus through a wake-up signal or if EN is set high for > tEN. The
wake-up events must be active for the respective time periods (tLINBUS).
ADVANCE INFORMATION
While the device is in sleep mode, the following conditions exist:
• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if
LIN is short circuited to ground). However, the weak current pull-up is active to prevent false wake up events
in case an external connection to the LIN bus is lost.
• The normal receiver is disabled.
• EN input and LIN wake up receiver are active.
9.4.3 Standby Mode
Standby mode is entered either by a wake up event through LIN bus while the device is in sleep mode or by the
EN pin while in normal mode. From normal mode EN must be low for > tEN and TXD and nRST are high. RXD
pin in standby mode is dependent upon how standby mode was entered. If entered from normal mode or power
up, RXD floats until a wake event takes place at which time it is pulled low. If entered from sleep mode, RXD is
pulled low to indicate a wake event. See Standby Mode Application Note for more application information.
During power up, if EN is low the device goes into standby mode, and if EN is high, the device goes into normal
mode. EN has an internal pull-down resistor ensuring EN is pulled low if the pin is left floating in the system.
9.4.4 Wake Up Events
There are two ways to wake up from sleep mode:
• Remote wake up initiated by the falling edge of a recessive (high) to dominant (low) state transition on the
LIN bus where the dominant state is held for the tLINBUS filter time. After this tLINBUS filter time has been met
and a rising edge on the LIN bus going from dominant state to recessive state initiates a remote wake up
event eliminating false wake ups from disturbances on the LIN bus or if the bus is shorted to ground.
• Local wake up through EN being set high for longer than tEN.
9.4.4.1 Wake Up Request (RXD)
When the TLIN1028-Q1 encounters a wake up event from the LIN bus, RXD goes low and the device transitions
to standby mode until EN is reasserted high and the device enters normal mode. Once the device enters normal
mode, the RXD pin releases the wake up request signal and the RXD pin then reflects the receiver output from
the LIN bus.
9.4.5 Mode Transitions
When the device is transitioning between modes, the device needs the time tMODE_CHANGE and tNOMINT to allow
the change to fully propagate from the EN pin through the device into the new state.
9.4.6 Voltage Regulator
The device has an integrated high-voltage LDO that operates over a 5.5 V to 28 V input voltage range for both
3.3 V and 5 V VCC. The device has an output current capability of 125 mA and support fixed output voltages of
3.3 V (TLIN10283-Q1) or 5 V (TLIN10285-Q1). It features thermal shutdown and short-circuit protection to
prevent damage during over-temperature and over-current conditions
24
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9.4.6.1 VCC
The VCC pin is the regulated output based on the required voltage. The regulated voltage accuracy is ± 2%. The
output is current limited. In the event that the regulator drops out of regulation, the output tracks the input minus
a drop based on the load current. When the input voltage drops below the UVSUP threshold, the regulator shuts
down until the input voltage returns above the UVSUPR level. The device monitors situations where VCC may drop
below the UVCC level thus causing the nRST pin to be pulled low.
9.4.6.2 Output Capacitance Selection
For stable operation over the full temperature range and with load currents up to 125 mA on VCC a certain
capacitance is expected and depends upon the minimum load current. To support no load to full load a value of
10 µF and ESR smaller than 2 Ω is needed. For 500 µA to full load an 1 µF capacitance can be used. The low
ESR recommendation is to improve the load transient performance.
9.4.6.3 Low-Voltage Tracking
9.4.6.4 Power Supply Recommendation
The device is designed to operate from an input-voltage supply range between 5.5 V and 28 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the device. The recommended
minimum capacitance at the pin is 100 nF . The max voltage range is for the LIN functionality. Exceeding 24V for
the LDO reduces the effective current sourcing capability due to thermal considerations.
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ADVANCE INFORMATION
At low input voltages, the regulator drops out of regulation and the output voltage tracks input minus a voltage
based on the load current (IL) and switch resistor. This tracking allows for a smaller input capacitance and can
possibly eliminate the need for a boost converter during cold-crank conditions.
TLIN1028-Q1
SLLSEX4 – AUGUST 2019
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TLIN1028-Q1 can be used as both a slave device and a master device in a LIN network. The device comes
with the ability to support remote wake up request. It can provide the power to the local processor.
10.2 Typical Application
The device comes with an integrated 45 kΩ pull-up resistor and series diode for slave applications. For master
applications an external 1 kΩ pull-up resistor with series blocking diode can be used. Figure 24 shows the device
being used in both master and slave applications.
10 µF
Vcc VSUP
8
2
100 nF(4)
1
Master Node
Pullup(3)
MCU w/o
pullup(2)
VDD I/O
1 kQ
MCU
4
LIN Controller
Or
SCI/UART(1)
5
200 pF
RXD
6
TXD
GND
7
3
nRST
SLAVE
NODE
10 µF
Vcc
I/O
VDD
LIN
GND
EN
LIN Bus
I/O
VDD
VBAT
ADVANCE INFORMATION
MASTER
NODE
EN
2
8
VSUP
100 nF(4)
1
MCU w/o
pullup(2)
Slave Node(3)
VDD I/O
MCU
4
LIN Controller
Or
SCI/UART(1)
5
200 pF
RXD
TXD
GND
LIN
6
7
3
nRST
(1) If RXD on MCU or LIN slave has internal pullup; no external pullup resistor is needed.
(2) If RXD on MCU or LIN slave does not have an internal pullup requires external pullup resistor.
(3) Master node applications require and external 1 lQ ‰µooµ‰ Œ •]•š}Œ v • Œ] o ]} .
(4) Decoupling capacitor values are system dependent but usually have 100 nF, 1 R& v H10 µF
Figure 24. Typical LIN Bus
26
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Typical Application (continued)
10.2.1 Design Requirements
10.2.1.1 Normal Mode Application Note
When using the TLIN1028-Q1 in systems which are monitoring the RXD pin for a wake up request, special care
should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition period
between states as the receivers are switched. The application software should not look for an edge on the RXD
pin indicating a wake up request until tMODE_CHANGE. This is shown in When transitioning to normal mode there is
an initialization period shown as tNOMINIT.
10.2.1.2 Standby Mode Application Note
If the TLIN1028-Q1 detects an under voltage on VSUP, the RXD pin transitions low and would signal to the
software that the device is in standby mode and should be returned to sleep mode for the lowest power state.
The maximum dominant TXD time allowed by the TXD dominant state time out limits the minimum possible data
rate of the device. The LIN protocol has different constraints for master and slave applications; thus, there are
different maximum consecutive dominant bits for each application case and thus different minimum data rates.
10.2.2 Detailed Design Procedures
RXD on processors or LIN slave has internal pull-up; no external pull-up resistor is need. RXD on processors or
LIN slave without internal pull-up requires external pull-up resistor. Master node applications require and external
1 kΩ pull-up resistor and serial diode.
11 Power Supply Recommendations
The TLIN1028-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from 5.5 V
to 28 V . A 100 nF decoupling capacitor should be placed as close to the VSUP pin of the device as possible.
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ADVANCE INFORMATION
10.2.1.3 TXD Dominant State Timeout Application Note
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12 Layout
PCB design should start with design of the protection and filtering circuitry because ESD and EFT have a wide
frequency bandwidth from approximately 3 MHz to 3 GHz, high frequency layout techniques must be applied
during PCB design. Placement at the connector also prevents these noisy events from propagating further into
the PCB and system.
12.1 Layout Guidelines
•
•
•
•
ADVANCE INFORMATION
•
•
•
•
Pin 1 (VSUP): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed as close
to the device as possible.
Pin 2 (EN): EN is an input pin that is used to place the device in a low power sleep mode. If this feature is not
used, the pin should be pulled high to the regulated voltage supply of the microprocessor through a series
resistor, values between 1 kΩ and 10 kΩ. Additionally, a series resistor may be placed on the pin to limit
current on the digital lines in the event of an over voltage fault.
Pin 3 (GND): This is the ground connection for the device. This pin should be tied to the ground plane
through a short trace with the use of two vias to limit total return inductance.
Pin 4 (LIN): This pin connects to the LIN bus. For slave applications, a 200 pF capacitor to ground is
implemented. For master applications, an additional series resistor and blocking diode should be placed
between the LIN pin and the VSUP pin. See Figure 24
Pin 5 (RXD): The pin is an open drain output and requires and external pull-up resistor in the range of 1 kΩ
to 10 kΩ to function properly. If the microprocessor paired with the transceiver does not have an integrated
pull-up, an external pull-up resistor should be placed on RXD. If RXD is connected to the VCC pin a higher
pull-up resistor value can be used to reduce standby current.
Pin 6 (TXD): The TXD pin is the transmit input signal to the device from the processors. A series resistor can
be placed to limit the input current to the device in the event of an over voltage on this pin. A capacitor to
ground can be placed close to the input pin of the device to filter noise.
Pin 7 (nRST): This pin connects to the processors as a reset out.
Pin 8 (VCC): Output source, either 3.3 V or 5 V depending upon the version of the device.
NOTE
All ground and power connections should be made as short as possible and use at least
two vias to minimize the total loop inductance.
28
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12.2 Layout Example
VCC
VSUP
U1
VCC
8
VCC
D2
Only needed for
the Master node
VSUP
1
C4
C2
GND
J1
R7
R3
GND
EN
R2
2
EN
nRST
7
TXD
6
C3
LIN
GND
GND
3
GND
R4
TXD
C1
GND
ADVANCE INFORMATION
VCC
4
LIN
RXD
5
R1
GND
RXD
Figure 25. Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
ADVANCE INFORMATION
For related documentation see the following:
LIN Standards:
• ISO/DIS 17987-1.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and
use case definition
• ISO/DIS 17987-4.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer
(EPL) specification 12V/24V
• SAEJ2602-1: LIN Network for Vehicle Applications
• LIN2.0, LIN2.1, LIN2.2 and LIN2.2A specification
EMC requirements:
• SAEJ2962-2: TBD
• HW Requirements for CAN, LIN, FR V1.3: German OEM requirements for LIN
• ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge
• ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband
radiated electromagnetic energy - Part 4: Harness excitation methods
• ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1:
Definitions and general considerations
• ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical
transient transmission by capacitive and inductive coupling via lines other than supply lines
• IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz Part 4: Direct RF power injection method
• IEC 61000-4-2
• IEC 61967-4
• CISPR25
Conformance Test requirements:
• ISO/DIS 17987-7.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer
(EPL) conformance test specification
• SAEJ2602-2: LIN Network for Vehicle Applications Conformance Test
TLINx441 LDO Performance, SLLA427
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
30
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13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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ADVANCE INFORMATION
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
PACKAGE OPTION ADDENDUM
www.ti.com
23-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PTLIN10285DRBRQ1
ACTIVE
SON
DRB
8
3000
TBD
Call TI
Call TI
-40 to 125
PTLIN10285DRQ1
ACTIVE
SOIC
D
8
2500
TBD
Call TI
Call TI
-40 to 125
TLIN10285DRBRQ1
PREVIEW
SON
DRB
8
3000
TBD
Call TI
Call TI
-40 to 125
TLIN10285DRQ1
PREVIEW
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TL085
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Nov-2019
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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