Texas Instruments | P82B96 I2C Compatible Dual Bidirectional Bus Buffer (Rev. C) | Datasheet | Texas Instruments P82B96 I2C Compatible Dual Bidirectional Bus Buffer (Rev. C) Datasheet

Texas Instruments P82B96 I2C Compatible Dual Bidirectional Bus Buffer (Rev. C) Datasheet
Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
P82B96 I2C Compatible Dual Bidirectional Bus Buffer
1 Features
3 Description
•
The P82B96 device is a bus buffer that supports
bidirectional data transfer between an I2C bus and a
range of other bus configurations with different
voltage and current levels.
1
•
•
•
•
•
•
•
Operating Power-Supply Voltage Range
of 2 V to 15 V
Can Interface Between I2C Buses Operating at
Different Logic Levels (2 V to 15 V)
Longer Cables by allowing bus capacitance of
400 pF on Main Side (Sx/Sy) and 4000 pF on
Transmission Side (Tx/Ty)
Outputs on the Transmission Side (Tx/Ty) Have
High Current Sink Capability for Driving LowImpedance or High-Capacitive Buses
Interface With Optoelectrical Isolators and Similar
Devices That Need Unidirectional Input and
Output Signal Paths by Splitting I2C Bus Signals
Into Pairs of Forward (Tx/Ty) and Reverse (Rx/Ry)
Signals
400-kHz Fast I2C Bus Operation Over at Least
20 Meters of Wire
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
2 Applications
•
•
•
•
One of the advantages of the P82B96 is that it
supports longer cables/traces and allows for more
devices per I2C bus because it can isolate bus
capacitance such that the total loading (devices and
trace lengths) of the new bus or remote I2C nodes
are not apparent to other I2C buses (or nodes). The
restrictions on the number of I2C devices in a system
due to capacitance, or the physical separation
between them, are greatly improved.
The device is able to provide galvanic isolation
(optocoupling) or use balanced transmission lines
(twisted pairs), because separate directional Tx and
Rx signals are provided. The Tx and Rx signals may
be connected directly (without causing bus latching),
to provide an bidirectional signal line with I2C
properties (open-drain driver). Likewise, the Ty and
Ry signals may also be connected together to provide
an bidirectional signal line with I2C properties (opendrain driver). This allows for a simple communication
design, saving design time and costs.
Device Information(1)
HDMI DDC
Long I2C Communication
Galvanic I2C Isolation
Industrial Communications
PART NUMBER
PACKAGE
P82B96
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
PDIP (8)
9.81 mm × 6.35 mm
TSSOP (8)
3.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Long-Distance I2C Communications
Main Enclosure
Remote-Control Enclosure
12 V
12 V
3.3–5 V
3.3–5 V
Long Cables
SCL
SCL
3.3–5 V
12 V
3.3–5 V
SDA
SDA
P82B96
P82B96
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
1
1
1
2
3
4
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics: VCC = 2.3 V to 2.7 V ........ 6
Electrical Characteristics: VCC = 3 V to 3.6 V ........... 7
Electrical Characteristics: VCC = 4.5 V to 5.5 V ........ 8
Electrical Characteristics: VCC = 15 V....................... 9
Switching Characteristics ........................................ 10
Typical Characteristics .......................................... 11
Parameter Measurement Information ................ 12
9
Detailed Description ............................................ 13
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
14
14
10 Application and Implementation........................ 15
10.1 Application Information.......................................... 15
10.2 Typical Applications .............................................. 17
11 Power Supply Recommendations ..................... 21
12 Layout................................................................... 21
12.1 Layout Guidelines ................................................. 21
12.2 Layout Example .................................................... 21
13 Device and Documentation Support ................. 22
13.1
13.2
13.3
13.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
14 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Revision B (July 2007) to Revision C
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Changed VCC pins to VCC pins in pinout diagrams................................................................................................................ 4
2
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
P82B96
www.ti.com
SCPS144C – MAY 2006 – REVISED MAY 2015
5 Description (continued)
Two or more Sx or Sy I/Os must not be connected to each other on the same node. The P82B96 design does
not support this configuration. Bidirectional I2C signals do not have a direction control pin so, instead, slightly
different logic low-voltage levels are used at Sx/Sy to avoid latching of this buffer. A standard I2C low applied at
the Rx/Ry of a P82B96 is propagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special
buffered low is applied to the Sx/Sy of another P82B96, the second P82B96 does not recognize it as a standard
I2C bus low and does not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to
similar buffers that rely on special logic thresholds for their operation.
The Sx/Sy side of the P82B96 is intended for I2C logic voltage levels of I2C master and slave devices or Tx/Rx
signals of a second P82B96, if required. If Rx and Tx are connected, Sx can function as either the SDA or SCL
line. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are no
restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or
multi-point configuration (multiple P82B96 devices share the same Tx/Rx and Ty/Ry nodes) with the Tx/Rx and
Ty/Ry I/O pins on the common bus, and the Sx/Sy side connected to the line-card slave devices.
In any design, the Sx pins of different devices should never be linked, because the resulting system would be
very susceptible to induced noise and would not support all I2C operating modes.
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
3
P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
www.ti.com
6 Pin Configuration and Functions
P Package
8-Pin PDIP
(Top View)
D Package
8-Pin SOIC
(Top View)
Sx
1
8
VCC
Rx
2
7
Tx
3
GND
4
1
8
Sy
Sx
Rx
2
7
VCC
Sy
6
Ry
Tx
3
6
Ry
5
Ty
GND
4
5
Ty
DGK Package
8-Pin VSSOP
(Top View)
PW Package
8-Pin TSSOP
(Top View)
Sx
Rx
Tx
GND
8
7
6
5
1
2
3
4
Sx
Rx
Tx
GND
VCC
Sy
Ry
Ty
1
2
3
4
8
7
6
5
VCC
Sy
Ry
Ty
Pin Functions
PIN
NO.
NAME
I/O
Serial data bus or SDA. Connect to VCC of I2C master through a pullup resistor.
1
Sx
2
Rx
I
Receive signal. Connect to VCC of P82B96 through a pullup resistor.
3
Tx
O
Transmit signal. Connect to VCC of P82B96 through a pullup resistor.
4
GND
—
Ground
5
Ty
O
Transmit signal. Connect to VCC of P82B96 through a pullup resistor.
6
Ry
I
Receive signal. Connect to VCC of P82B96 through a pullup resistor.
7
Sy
I/O
8
VCC
I
4
I/O
DESCRIPTION
Serial clock bus or SCL. Connect to VCC of I2C master through a pullup resistor.
Supply voltage
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
P82B96
www.ti.com
SCPS144C – MAY 2006 – REVISED MAY 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.3
18
V
Sx or Sy (SDA or SCL)
–0.3
18
Rx or Ry
–0.3
18
Sx or Sy (SDA or SCL)
–0.3
18
Tx or Ty
–0.3
18
VCC
Supply voltage on VCC pin
VI
Voltage on buffered input
VO
Voltage on buffered output
IO
Continuous output current
ICC
Continuous current through VCC or GND
250
mA
TA
Operating free-air temperature
–40
85
°C
Tstg
Storage temperature
–55
125
°C
(1)
Sx or Sy
250
Tx or Ty
250
V
V
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3500
Charged-Device Model (CDM), per JEDEC specification JESD22C101 (2)
±1000
Machine Model (MM), per JEDEC specification JESD22-A115-A
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VCC
Supply voltage
IOL
Low-level output current
VIOmax
Maximum input/output voltage level
VILdiff
Low-level input voltage difference
TA
Operating free-air temperature
MIN
MAX
2
15
Sx, Sy
VSx, VSy = 1 V, VRx, VRy ≤ 0.42 V
3
Tx, Ty
VSx, VSy = 0.4 V, VTx, VTy = 0.4 V
30
Sx, Sy
VTx, VTy = 0.4 V
15
Tx, Ty
VSx, VSy = 0.4 V
15
Sx, Sy
UNIT
V
mA
V
0.4
V
85
°C
–40
7.4 Thermal Information
P82B96
THERMAL METRIC
RθJA
(1)
Junction-to-ambient thermal resistance
D (SOIC)
DGK (VSSOP)
P (PDIP)
PW (TSSOP)
8 PINS
8 PINS
8 PINS
8 PINS
UNIT
109.1
174.3
53.5
173.5
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
61.6
63
44.4
57.6
°C/W
RθJB
Junction-to-board thermal resistance
48.6
94.2
30.6
101.8
°C/W
ψJT
Junction-to-top characterization parameter
19.6
8.1
22.9
5.3
°C/W
ψJB
Junction-to-board characterization parameter
48.2
92.8
30.5
100.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
5
P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
www.ti.com
7.5 Electrical Characteristics: VCC = 2.3 V to 2.7 V
VCC = 2.3 V to 2.7 V, voltages are specified with respect to GND (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
ΔV/ΔTIN
Temperature coefficient of
input thresholds
Sx, Sy
VOL
Low-level output voltage
Sx, Sy
ΔV/ΔTOUT
Temperature coefficient of
output low levels (3)
Sx, Sy
ICC
Quiescent supply current
ΔICC
Additional supply current
per pin low
Dynamic output sink
capability on I2C bus
IIOS
Sx, Sy
Tx, Ty
Leakage current
on buffered bus
Input current
from buffered bus
II
Leakage current
on buffered bus input
Sx, Sy
Rx, Ry
VIT
ISx, ISy = 3 mA
ISx, ISy = 0.2 mA
0.8
0.67
ISx, ISy = 0.2 mA
VSx, VSy > 2 V,
VRx, VRy = low
7
VSx, VSy = 2.5 V,
VRx, VRy = high
VTx, VTy > 1 V,
VSx, VSy = low on
I2C bus = 0.4 V
0.88
0.73
MAX
mV/°C
1
0.79
See
(2)
See
(2)
V
mV/°C
1.8
2
mA
1.7
2.75
3
mA
18
0.1
60
5.5
1
mA
1
100
60
–1
1
Bus low, VRx,
VRy = 0.4 V
–1
1
1
1.5
Input logic level low
threshold (4)
on normal I2C bus
0.65
0.6
1
0.7
0.65
0.58 x
VCC
1
See
(2)
See
(2)
μA
mA
Bus low, VRx,
VRy = high
Input logic level high
threshold (4)
on normal I2C bus
UNIT
0.9
μA
μA
V
0.58 x
VCC
0.5 x
VCC
Input threshold
0.42 x
VCC
Input logic level low
VIOdiff
Input/output logic level
difference (5)
Sx, Sy
(VSx output low
at 3 mA) –
(VSx input high max)
for I2C applications
100
VIOrel
VCC voltage at which all
buses are released
Sx, Sy
Tx, Ty
Sx, Sy are low, VCC
ramping, voltage on
Tx, Ty lowered until
released
1
ΔV/ΔTREL
Temperature coefficient of release
voltage
–4
Cin
Input capacitance
2.5
6
MIN
0.1
Input logic level high
(1)
(2)
(3)
(4)
(5)
MAX
VTx, VTy = VCC =
2.5 V,
VSx, VSy = high
Input threshold
Rx, Ry
TA = –40°C to 85°C
–1.8
VRx, VRy = VCC
Sx, Sy
TYP
(1)
–2
Tx, Ty
IIOT
Input current from I2C bus
MIN
Sx = Sy = VCC
Leakage current on I2C bus
Dynamic output sink
capability on buffered bus
TA = 25°C
Rx, Ry
150
0.42 x
VCC
100
mV
1
V
mV/°C
4
4
pF
Typical value is at VCC = 2.5 V, TA = 25°C
See the Typical Characteristics section of this data sheet.
The output logic low depends on the sink current.
The input logic threshold is independent of the supply voltage.
The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for VSX output low always exceeds the
minimum VSx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.
While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications.
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
P82B96
www.ti.com
SCPS144C – MAY 2006 – REVISED MAY 2015
7.6 Electrical Characteristics: VCC = 3 V to 3.6 V
VCC = 3 V to 3.6 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ΔV/ΔTIN
Temperature
coefficient of
input thresholds
Sx, Sy
VOL
Low-level output
voltage
Sx, Sy
ΔV/ΔTOUT
Temperature
coefficient of
output low
levels (3)
Sx, Sy
ICC
Quiescent supply current
ΔICC
Additional supply
current per pin
low
Dynamic output
sink capability
on I2C bus
IIOS
IIOT
ISx, ISy = 0.2 mA
0.8
0.67
ISx, ISy = 0.2 mA
VSx, VSy > 2 V, VRx, VRy = low
Dynamic output
sink capability
on buffered bus
VTx, VTy > 1 V,
VSx, VSy = low on I2C bus =
0.4 V
Tx, Ty
Sx, Sy
MIN
0.88
0.73
7
UNIT
MAX
mV/°C
1
0.79
See
(2)
See
(2)
V
mV/°C
0.9
1.8
2
mA
1.7
2.75
3
mA
18
5.7
mA
0.1
60
1
μA
1
100
60
mA
VTx, VTy = VCC = 3.3 V,
VSx, VSy = high
0.1
Bus low, VRx, VRy = high
–1
1
Bus low, VRx, VRy = 0.4 V
–1
1
1
1.5
1
μA
1
μA
Rx, Ry
VRx, VRy = VCC
Sx, Sy
Input threshold
Input logic-level high
threshold (4) on normal I2C bus
Input logic-level low
threshold (4) on normal I2C bus
Input logic level high
Rx, Ry
0.65
0.6
0.7
0.65
0.58 x
VCC
Input threshold
See
(2)
See
(2)
V
0.58 x VCC
0.5 x VCC
0.42 x
VCC
Input logic level low
VIOdiff
Input/output logic
level difference (5)
Sx, Sy
(VSx output low at 3 mA) –
(VSx input high max) for I2C
applications
VIOrel
VCC voltage at
which all buses
are released
Sx, Sy
Tx, Ty
Sx, Sy are low, VCC ramping,
voltage on Tx, Ty lowered until
released
ΔV/ΔTREL
Temperature coefficient of
release voltage
–4
Cin
Input capacitance Rx, Ry
2.5
(1)
(2)
(3)
(4)
(5)
MAX
–1.8
Sx = Sy = VCC
VSx, VSy = 5 V,
VRx, VRy = high
Leakage current
on buffered bus
input
TYP
TA = –40°C to 85°C
Sx, Sy
Input current
from buffered bus
VIT
ISx, ISy = 3 mA
Tx, Ty
Leakage current
on buffered bus
II
MIN
(1)
–2
Leakage current
on I2C bus
Input current
from I2C bus
TA = 25°C
100
150
0.42 x
VCC
100
1
mV
1
V
mV/°C
4
4
pF
Typical value is at VCC = 3.3 V, TA = 25°C
See the Typical Characteristics section of this data sheet.
The output logic low depends on the sink current.
The input logic threshold is independent of the supply voltage.
The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for VSX output low always exceeds the
minimum VSx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.
While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications.
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
7
P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
www.ti.com
7.7 Electrical Characteristics: VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ΔV/ΔTIN
Temperature
coefficient of input Sx, Sy
thresholds
VOL
Low-level output
voltage
Sx, Sy
ΔV/ΔTOUT
Temperature
coefficient of
output low
levels (3)
Sx, Sy
ICC
Quiescent supply current
ΔICC
Additional supply
current
per pin low
Dynamic output
sink capability
on I2C bus
IIOS
IIOT
Sx, Sy
ISx, ISy = 0.2 mA
0.67
VSx, VSy > 2 V,
VRx, VRy = low
VTx, VTy > 1 V,
VSx, VSy = low on I2C bus =
0.4 V
Tx, Ty
Sx, Sy
TYP
MIN
MAX
0.88
0.73
7
1
0.79
See
(2)
See
(2)
V
mV/°C
0.9
1.8
2
mA
1.7
2.75
3
mA
18
0.1
60
UNIT
mV/°C
6
1
mA
1
100
60
0.1
Bus low, VRx, VRy = high
–1
1
Bus low, VRx, VRy = 0.4 V
–1
1
1
1.5
1
μA
mA
VTx, VTy = VCC = 5 V,
VSx, VSy = high
VRx, VRy = VCC
Input threshold
Input logic-level high
threshold (4)
on normal I2C bus
Input logic-level low
threshold (4)
on normal I2C bus
Input logic level high
Rx, Ry
0.65
0.6
1
μA
μA
Input/output logic
level difference (5)
Sx, Sy
(VSx output low at 3 mA) –
(VSx input high max) for I2C
applications
VIOrel
VCC voltage at
which all buses
are released
Sx, Sy
Tx, Ty
Sx, Sy are low, VCC
ramping, voltage on Tx, Ty
lowered until released
See
(2)
See
(2)
V
0.58 x
VCC
Input threshold
VIOdiff
0.7
0.65
0.58 x VCC
0.5 x VCC
0.42 x
VCC
Input logic level low
8
MAX
Rx, Ry
Sx, Sy
(1)
(2)
(3)
(4)
(5)
TA = –40°C to 85°C
–1.8
Sx = Sy = VCC
Dynamic output
sink capability
on buffered bus
Leakage current
on buffered bus
input
0.8
ISx, ISy = 0.2 mA
VSx, VSy = 5 V,
VRx, VRy = high
Input current
from buffered bus
VIT
ISx, ISy = 3 mA
Tx, Ty
Leakage current
on buffered bus
II
MIN
(1)
–2
Leakage current
on I2C bus
Input current
from I2C bus
TA = 25°C
100
1
150
0.42 x
VCC
100
1
mV
V
Typical value is at VCC = 5 V, TA = 25°C
See the Typical Characteristics section of this data sheet.
The output logic low depends on the sink current.
The input logic threshold is independent of the supply voltage.
The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for VSX output low always exceeds the
minimum VSx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.
While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications.
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
P82B96
www.ti.com
SCPS144C – MAY 2006 – REVISED MAY 2015
Electrical Characteristics: VCC = 4.5 V to 5.5 V (continued)
VCC = 4.5 V to 5.5 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
MIN
TYP
(1)
ΔV/ΔTREL
Temperature coefficient of
release voltage
–4
Cin
Input capacitance
2.5
Rx, Ry
TA = –40°C to 85°C
MAX
MIN
UNIT
MAX
mV/°C
4
4
pF
7.8 Electrical Characteristics: VCC = 15 V
VCC = 15 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ΔV/ΔTIN
Temperature
coefficient of
input thresholds
Sx, Sy
VOL
Low-level output
voltage
Sx, Sy
ΔV/ΔTOUT
Temperature
coefficient of
output low
levels (3)
Sx, Sy
ICC
Quiescent supply
current
ΔICC
Additional supply
current
per pin low
IIOS
IIOT
Dynamic output
sink capability
on I2C bus
0.67
ISx, ISy = 0.2 mA
VSx, VSy > 2 V,
VRx, VRy = low
VSx, VSy = 15 V,
VRx, VRy = high
Dynamic output
sink capability
on buffered bus
VTx, VTy > 1 V,
VSx, VSy = low on I2C bus
= 0.4 V
Tx, Ty
Sx, Sy
Input current
from buffered bus
Leakage current
on buffered bus
input
MIN
MAX
0.88
0.73
7
1
0.79
See
(2)
See
(2)
V
mV/°C
0.9
1.8
2
mA
1.7
2.75
3
mA
18
0.1
60
UNIT
mV/°C
–1.8
6.5
1
mA
1
100
60
0.1
Bus low, VRx, VRy = high
–1
1
Bus low, VRx, VRy = 0.4 V
–1
1
1
1.5
1
μA
mA
VTx, VTy = VCC = 15 V,
VSx, VSy = high
VRx, VRy = VCC
Input threshold
Rx, Ry
Input logic-level high
threshold (4)
on normal I2C bus
0.65
Input logic-level high
threshold (4)
on normal I2C bus
0.6
Input logic level high
0.58 x
VCC
1
μA
μA
0.7
0.65
See
(2)
See
(2)
V
Input threshold
Input logic level low
(1)
(2)
(3)
(4)
TA = –40°C to 85°C
MAX
Rx, Ry
Sx, Sy
VIT
ISx, ISy = 0.2 mA
0.8
Tx, Ty
Leakage current
on buffered bus
II
ISx, ISy = 3 mA
Sx = Sy = VCC
Sx, Sy
TYP (1)
–2
Leakage current
on I2C bus
Input current
from I2C bus
TA = 25°C
MIN
0.58 x VCC
0.5 x VCC
0.42 x
VCC
0.42 x
VCC
Typical value is at VCC = 15 V, TA = 25°C
See the Typical Characteristics section of this data sheet.
The output logic low depends on the sink current.
The input logic threshold is independent of the supply voltage.
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
9
P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
www.ti.com
Electrical Characteristics: VCC = 15 V (continued)
VCC = 15 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TA = 25°C
TEST CONDITIONS
MIN
TYP
VIOdiff
Input/output logic
level difference (5)
Sx, Sy
(VSx output low at 3 mA) –
(VSx input high max) for
I2C applications
VIOrel
VCC voltage at
which all buses
are released
Sx, Sy
Tx, Ty
Sx, Sy are low, VCC
ramping, voltage on Tx,
Ty lowered until released
ΔV/ΔTREL
Temperature coefficient of
release voltage
–4
Cin
Input capacitance Rx, Ry
2.5
(5)
100
TA = –40°C to 85°C
(1)
MAX
MIN
150
UNIT
MAX
100
1
mV
1
V
mV/°C
4
4
pF
The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for VSX output low always exceeds the
minimum VSx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.
While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications.
7.9 Switching Characteristics
VCC = 5 V, TA = 25°C, no capacitive loads, voltages are specified with respect to GND (unless otherwise noted)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
TEST CONDITIONS
TYP UNIT
tpzl
Buffer delay time on falling
input
VSx (or VSy) = input switching
threshold
VTx (or VTy) output falling
50% of VLOAD (1)
RTx pullup = 160 Ω,
CTx = 7 pF + board
trace capacitance
70
ns
tplz
Buffer delay time on rising
input
VSx (or VSy) = input switching
threshold
VTx (or VTy) output
reaching 50% of VLOAD
RTx pullup = 160 Ω,
CTx = 7 pF + board
trace capacitance
90
ns
tpzl
Buffer delay time on falling
input
VRx (or VRy) = input switching
threshold
VSx (or VSy) output falling
50% of VLOAD (3)
RSx pullup = 1500 Ω,
CTx = 7 pF + board
trace capacitance
250
ns
tplz
Buffer delay time on rising
input
VRx (or VRy) = input switching
threshold
VSx (or VSy) output
reaching 50% of VLOAD
RSx pullup = 1500 Ω,
CTx = 7 pF + board
trace capacitance
270
ns
(1)
(2)
(3)
(4)
10
The
The
The
The
(2)
(4)
fall time of VTx from 5 V to 2.5 V in the test is approximately 15 ns.
rise time of VTx from 0 V to 2.5 V in the test is approximately 20 ns.
fall time of VSx from 5 V to 2.5 V in the test is approximately 50 ns.
rise time of VSx from 0.9 V to 2.5 V in the test is approximately 70 ns.
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
P82B96
www.ti.com
SCPS144C – MAY 2006 – REVISED MAY 2015
7.10 Typical Characteristics
1200
800
600
Typical
0
25
Typical
800
600
Minimum
400
-50 –25
Maximum
1000
Maximum
VOL – mV
VOL – mV
1000
Minimum
400
-50 –25
50 75 100 125
0
Figure 2. VOL at Sx vs Junction Temperature, IOL = 3 mA
1000
1000
800
800
VIH(min) – mV
VIL(max) – mV
Figure 1. VOL at Sx vs Junction Temperature, IOL = 0.2 mA
600
400
0
50 75 100 125
Tj – °C
Tj – °C
200
-50 –25
25
600
400
200
-50 –25
25 50 75 100 125
Tj – °C
0
25 50 75 100 125
Tj – °C
Figure 4. VIH(min) at Sx vs Junction Temperature
Figure 3. VIL(max) at Sx vs Junction Temperature
1400
VCC(max) – mV
1200
1000
800
600
400
-50 –25
0
25 50 75 100 125
Tj – °C
Figure 5. VCC(max) vs Junction Temperature
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
11
P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
www.ti.com
8 Parameter Measurement Information
VCC
VIN
VCC
VOUT
PULSE
GENERATOR
RL = 160 to 1500 W
S1
DUT
GND
CL = Probe and jig capacitance
(see Note A)
RT
TEST
S1
tPLZ/tPZL
VCC
TEST CIRCUIT FOR OPEN-DRAIN OUTPUT
VCC
0.6 V
0V
Sx or Sy
tPZL
tPLZ
VCC
0.5 ´ VCC
Tx or Ty
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
Figure 6. Test Circuit and Voltage Waveforms
12
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
P82B96
www.ti.com
SCPS144C – MAY 2006 – REVISED MAY 2015
9 Detailed Description
9.1 Overview
The P82B96 is a bus buffer that supports bidirectional data transfer between an I2C bus and a range of other bus
configurations with different voltage and current levels.
One of the advantages of the P82B96 is that it supports longer cables/traces and allows for more devices per I2C
bus because it can isolate bus capacitance such that the total loading (devices and trace lengths) of the new bus
or remote I2C nodes are not apparent to other I2C buses (or nodes). The restrictions on the number of I2C
devices in a system due to capacitance, or the physical separation between them, are greatly improved.
The P82B96 is able to provide galvanic isolation (optocoupling) or use balanced transmission lines (twisted
pairs), because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be connected
directly (without causing bus latching), to provide an bidirectional signal line with I2C properties (open-drain
driver). Likewise, the Ty and Ry signals may also be connected together to provide an bidirectional signal line
with I2C properties (open-drain driver). This allows for a simple communication design, saving design time and
costs.
Two or more Sx or Sy I/Os must not be connected to each other on the same node. The P82B96 design does
not support this configuration. Bidirectional I2C signals do not have a direction control pin so, instead, slightly
different logic low-voltage levels are used at Sx/Sy to avoid latching of this buffer. A standard I2C low applied at
the Rx/Ry of a P82B96 is propagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special
buffered low is applied to the Sx/Sy of another P82B96, the second P82B96 does not recognize it as a standard
I2C bus low and does not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to
similar buffers that rely on special logic thresholds for their operation.
The Sx/Sy side of the P82B96 is intended for I2C logic voltage levels of I2C master and slave devices or Tx/Rx
signals of a second P82B96, if required. If Rx and Tx are connected, Sx can function as either the SDA or SCL
line. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are no
restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or
multi-point configuration (multiple P82B96 devices share the same Tx/Rx and Ty/Ry nodes) with the Tx/Rx and
Ty/Ry I/O pins on the common bus, and the Sx/Sy side connected to the line-card slave devices.
In any design, the Sx pins of different devices should never be linked, because the resulting system would be
very susceptible to induced noise and would not support all I2C operating modes.
9.2 Functional Block Diagram
VCC (2–15 V)
8
Sx (SDA)
3
1
2
Sy (SCL)
5
7
6
Tx (TxD, SDA)
Rx (RxD, SDA)
Ty (TxD, SCL)
Ry (RxD, SCL)
P82B96
4
GND
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
13
P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
www.ti.com
9.3 Feature Description
9.3.1 Sx and Sy
The I2C pins, Sx and Sy, are designed to interface directly with an I2C bus. The logic threshold-voltage levels on
the I2C bus are independent of the supply VCC. The maximum I2C bus supply voltage is 15 V, and the specified
static sink current is 3 mA.
Sx and Sy have two identical buffers. Each buffer is made up of two logic signal paths. The first one, named Tx
or Ty, is a forward path from the I2C interface pin, which drives the buffered bus. The second one, named Rx or
Ry, is a reverse signal path from the buffered bus input to drive the I2C bus interface.
There are two purposes for these paths: to sense the voltage state of the I2C pin (Sx or Sy) and transmit this
state to Tx or Ty, respectively, and to detect the state of the Rx or Ry and pull the I2C pin low when Rx or Ry is
low.
9.3.2 Tx and Ty
Tx and Ty are open-collector outputs without ESD protection diodes to VCC. Each pin may be connected through
a pullup resistor to a supply voltage in excess of VCC, as long as the 15-V rating is not exceeded. Tx and Ty have
a larger current-sinking capability than a standard I2C device and can sink a static current of greater than 30 mA.
They also have dynamic pulldown capability of 100-mA, typically.
A logic low is transmitted to Tx or Ty only when the voltage at the I2C pin (Sx or Sy) is less than 0.6 V. A logic
low at Rx or Ry causes the I2C bus (Sx or Sy) to be pulled to a logic low level in accordance with I2C
requirements (maximum 1.5 V in 5-V applications), but not low enough to be looped back to the Tx or Ty output
and cause the buffer to latch low.
The minimum low level that the P82B96 can achieve on the I2C bus by a low at Rx or Ry typically is 0.8 V.
If VCC fails, neither the I2C pins nor the Tx or Ty outputs are held low. Their open-collector configuration allows
them to be pulled up to the rated maximum of 15 V without VCC present. The input configuration on Sx, Sy, Rx,
and Ry also presents no loading of external signals when VCC is not present. This ensures that communication
on the main I2C bus can continue if the P82B96 has no supply.
The effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 4 pF for
all bus voltages and supply voltages, including VCC = 0 V.
9.3.3 Long Cable Length
The P82B96 supports 400 pF on the main I2C bus (Sx/Sy side) and up to 4000 pF on the transmission side
(Tx/Ty). This allows for longer cables to be used due to the significant increase in capacitance allowed by the
device.
9.4 Device Functional Modes
The P82B96 begins functioning once VCC reaches 2 V. When VCC is low, the P82B96 does not hold the Sx/Sy
pins low, which ensures I2C communication can continue between other devices on the bus while the VCC is low.
14
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
P82B96
www.ti.com
SCPS144C – MAY 2006 – REVISED MAY 2015
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Calculating System Delays and Bus-Clock Frequency for Fast Mode System
Figure 7 through Figure 9 show the P82B96 used to drive extended bus wiring, with relatively large capacitance
(up to 4000 pF), linking two Fast mode I2C bus nodes. It includes simplified expressions for making the relevant
timing calculations for 3.3-/5-V operation. It may be necessary to decrease the nominal SCL frequency below
400 kHz, because the buffers and the wiring introduce timing delays. In most cases, the actual bus frequency is
lower than the nominal master timing, due to bit-wise stretching of the clock periods.
Buffered Expansion Bus
Local Master Bus
Remote Slave Bus
VCCB
VCCM
MASTER
VCCS
Rb
Rm
SCL
Sx
I2C
P82B96
Tx/Rx
Rs
SCL
SLAVE
Sx
Tx/Rx
P82B96
Cb = Buffered Bus
Wiring Capacitance
Cm = Master Bus
Capacitance
Cs = Slave Bus
Capacitance
I2C
GND
Falling edge of SCL at master is delayed by the buffers and bus fall times.
9
Effective Delay of SCL at Slave = 255 + 17 VCCM + (2.5 + 4 × 10 Cb) VCCB (ns)
C = F, V = Volts
Figure 7. Linking Two I2C Bus Nodes Over a Long Cable, Master to Slave
Buffered Expansion Bus
Local Master Bus
VCCB
VCCM
MASTER
SCL
Rb
Rm
Sx
P82B96
Tx/Rx
Tx/Rx
2
IC
Cm = Master Bus
Capacitance
Cb = Buffered Bus
Wiring Capacitance
GND
Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times.
Effective delay of SCL at master = 270 + RmCm + 0.7RbCb (ns)
C = F, R = Ω
Figure 8. Master I2C Node Connection to P82B96
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
15
P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
www.ti.com
Application Information (continued)
Buffered Expansion Bus
Local Master Bus
VCCM
Remote Slave Bus
VCCS
VCCB
MASTER
SDA
Rm
Rs
Rb
Sx
P82B96
Tx/Rx
Tx/Rx
P82B96
SDA
SLAVE
Sx
I2C
I2C
Cm = Master Bus
Capacitance
Cb = Buffered Bus
Wiring Capacitance
Cs = Slave Bus
Capacitance
GND
Rising edge of SDA at slave is delayed by the buffers and bus rise times.
Effective delay of SDA at master = 270 + 0.2RsCs + 0.7(RbCb + RmCm) (ns)
C = F, R = Ω
Figure 9. Linking Two I2C Bus Nodes Over a Long Cable, Slave to Master
The delay factors involved in calculation of the allowed bus speed are:
• The propagation delay of the master signal through the buffers and wiring to the slave. The important delay is
that of the falling edge of SCL, because this edge requests the data or ACK from a slave.
• The effective stretching of the nominal low period of SCL at the master, caused by the buffer and bus rise
times.
• The propagation delay of the slave response signal through the buffers and wiring back to the master. The
important delay is that of a rising edge in the SDA signal. Rising edges always are slower and, therefore, are
delayed by a longer time than falling edges. (The rising edges are limited by the passive pullup, while falling
edges actively are driven.)
The timing requirement in any I2C system is that a slave’s data response (which is provided in response to a
falling edge of SCL) must be received at the master before the end of the corresponding low period of SCL as it
appears on the bus wiring at the master. Because all slaves, as a minimum, satisfy the worst-case timing
requirements of a 400-kHz part, they must provide their response within the minimum allowed clock low period of
1300 ns. Therefore, in systems that introduce additional delays, it is necessary only to extend that minimum clock
low period by any effective delay of the slave response. The effective delay of the slave's response equals the
total delays in SCL falling edge from the master reaching the slave (A) minus the effective delay (stretch) of the
SCL rising edge (B) plus total delays in the slave response data, carried on SDA, and reaching the master (C).
The master microcontroller should be programmed to produce a nominal SCL low period
of (1300 + A – B + C) ns and should be programmed to produce the nominal minimum SCL high period of
600 ns. Then, a check should be made to ensure the cycle time is not shorter than the minimum 2500 ns. If
found to be necessary, increase either clock period.
Due to clock stretching, the SCL cycle time always is longer than (600 + 1300 + A + C) ns.
10.1.1.1 Sample Calculations
The master bus has an RmCm product of 100 ns and VCCM = 5 V.
The buffered bus has a capacitance of 1 nF and a pullup resistor of 160 Ω to 5 V, giving an RbCb product of
160 ns. The slave bus also has an RsCs product of 100 ns.
The master low period should be programmed to be ≥(1300 + 372.5 – 482 + 472) ns, which calculates to
≥1662.5 ns.
The master high period may be programmed to the minimum 600 ns. The nominal master clock period is
≥(1662.5 + 600) ns = 2262.5 ns, equivalent to a frequency of 442 kHz.
The
actual
bus-clock
period,
including
the
482-ns
clock
stretch
effect,
is
(nominal + stretch) = (2262.5 + 482) ns or ≥2745 ns, equivalent to an allowable frequency of 364 kHz.
16
Submit Documentation Feedback
below
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
P82B96
www.ti.com
SCPS144C – MAY 2006 – REVISED MAY 2015
10.2 Typical Applications
10.2.1 Driving Ribbon or Flat Telephone Cables
+V Cable Drive
VCC1
R2
VCC2
R2
R2
VCC
SCL
Sx
2
IC
MASTER
SDA
Sy
R1
R1
R1
R1
Rx
Rx
Tx
Tx
Ty
Ty
Sx
SCL
2
IC
SLAVE(S)
Sy
Ry
Ry
R2
VCC
SDA
Cable
P82B96
C2
P82B96
Propagation
Delay = 5 ns/m
C2
C2
C2
GND
GND
BAT54A
BAT54A
Figure 10. Driving Ribbon or Flat Telephone Cables
10.2.1.1 Design Requirements
In this application, the P82B96 is used to drive a ribbon cable. The following are assumed to be true
• Sy/Sx side of I2C bus is at a known voltage from 3.3 V to 5 V
• Tx/Ty and Rx/Ry side of I2C bus is at a known voltage from 2 V to 15V
• SCL Clock Speed <= 400kHz
10.2.1.2 Detailed Design Procedure
Table 1. Bus Capabilities
VCC1
(V)
+V
CABLE
(V)
VCC2
(V)
R1
(Ω)
R2
(kΩ)
C2
(pF)
5
12
5
750
2.2
400
(1)
(2)
CABLE
CABLE
LENGTH
CAPACITANCE
(m)
CABLE
DELAY
(ns)
MASTER SCL
PULSE
DURATION
(ns)
BUS
CLOCK
SPEED
(kHz)
MAXIMUM
SLAVE
RESPONSE
DELAY
HIGH
LOW
250
(1)
1250
600
4000
120
(2)
(1)
500
600
2600
185
(2)
(2)
5
12
5
750
2.2
220
100
3.3
5
3.3
330
1
220
25
1 nF
125
600
1500
390
3.3
5
3.3
330
1
100
3
120 pF
15
600
1000
500
600 ns
Not applicable; calculations are delay based.
Normal 400-kHz bus specification
When the master SCL high and low periods can be programmed separately, the timings can allow for bus
delays. The low period should be programmed to achieve the minimum 1300 ns plus the net delay in the slave
response data signal caused by bus and buffer delays. The longest data delay is the sum of the delay of the
falling edge of SCL from master to slave and the delay of the rising edge of SDA from slave data to master. The
actual SCL frequency is lower than calculated from the programmed clock periods because the buffer stretches
the programmed SCL low period. In the example for the 25-m cable in Table 1, the clock is stretched 400 ns, the
falling edge of SCL is delayed 490 ns, and the SDA rising edge is delayed 570 ns. The required additional low
period is (490 + 570) = 1060 ns and the I2C bus specifications already include an allowance for a worst-case bus
rise time (0% to 70%) of 425 ns. The bus rise time can be 300 ns (30% to 70%), which means it can be 425 ns
(0% to 70%). The 25-m cable delay times include all rise and fall times. Therefore, the device only needs to be
programmed with an additional (1060 – 400 – 425) = 235 ns, making a total programmed low period 1535 ns.
The programmed low is stretched by 400 ns to yield an actual bus low time of 1935 ns, which, allowing the
minimum high period of 600 ns, yields a cycle period of 2535 ns or 394 kHz.
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
17
P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
www.ti.com
Note in both the 100-m and 250-m examples, the capacitive loading on the I2C buses at each end is within the
maximum allowed Standard mode loading of 400 pF, but exceeds the Fast mode limit. This is an example of a
hybrid mode, because it relies on the response delays of Fast mode parts, but uses (allowable) Standard mode
bus loadings with rise times that contribute significantly to the system delays. The cables cause large
propagation delays. Therefore, these systems must operate well below the 400-kHz limit, but illustrate how they
still can exceed the 100-kHz limit, provided all parts are capable of Fast mode operation. The fastest example
illustrates how the 400-kHz limit can be exceeded, provided master and slave parts have delay specifications
smaller than the maximum allowed. Many TI slaves have delays shorter than 600 ns, but none have that
specified.
10.2.1.3 Application Curve
6
Input
Output
Amplitude (V)
5
4
3
2
1
0
D001
Figure 11. Propagation Delay Through P82B96 With 400-KHz Data
10.2.2 Galvanic Isolation
Figure 12 shows how the P82B96 can be used to galvanically isolate an I2C bus. This is achieved with the use of
optocouplers to provide the isolation, and wiring the Rx/Ry and Tx/Ty pins to the appropriate diodes to allow for
bidirectional operation.
VCC1
VCC
R4
R2
R5
R3
2
IC
SDA
5V
Rx
(SDA)
R1
2
IC
SDA
Tx
(SDA)
1/2 P82B96
Figure 12. Galvanic Isolation of I2C Nodes
18
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
P82B96
www.ti.com
SCPS144C – MAY 2006 – REVISED MAY 2015
10.2.3 Long-Distance I2C
Figure 13 shows how the P82B96 can be used for long-distance I2C communications over a twisted pair. Tx and
Rx share the same node and connect to one wire of a twisted pair, and Ty and Ry share the same node and
connect to another twisted pair. One twisted pair should have 1 wire tied to VCC and the other twisted pair should
have one of the wires tied to GND.
Main Enclosure
Remote-Control Enclosure
12 V
12 V
3.3–5 V
3.3–5 V
Long Cables
SCL
SCL
3.3–5 V
12 V
3.3–5 V
SDA
SDA
P82B96
P82B96
Figure 13. Long-Distance I2C Communications
10.2.4 Extend I2C/DDC Bus With Short-Circuit Protection
Figure 14 shows how a master I2C bus can be protected against short circuits or failures in applications that
involve plug/socket connections and long cables that may become damaged. A simple circuit is added to monitor
the SDA bus and, if its low time exceeds the design value, disconnect the master bus. P82B96 frees all of its
I/Os if its supply is removed, so one option is to connect its VCC to the output of a logic gate from, for example,
the LVC family. The SDA and SCL lines could be timed, and VCC disabled through the gate, if a line exceeds a
design value of the low period. If the supply voltage of logic gates restricts the choice of VCC supply, the low-cost
discrete circuit in Figure 14 can be used. If the SDA line is held low, the 100-nF capacitor charges, and Ry is
pulled toward VCC. When it exceeds VCC/2, Ry sets Sy high, which effectively releases it.
In this example, the SCL line is made unidirectional by tying Rx to VCC. The state of the buffered SCL line cannot
affect the master clock line, which is allowed when clock stretching is not required. It is simple to add an
additional transistor or diode to control the Rx input in the same way as Ry, when necessary. The +V cable drive
can be any voltage up to 15 V, and the bus may be run at a lower impedance by selecting pullup resistors for a
static sink current up to 30 mA. VCC1 and VCC2 may be chosen to suit the connected devices. Because DDC uses
relatively low speeds (<100 kHz), the cable length is not restricted to 20 m by the I2C signaling, but it may be
limited by the video signaling.
Figure 10 and Table 1 show that P82B96 can achieve high clock rates over long cables. While calculating with
lumped wiring capacitance yields reasonable approximations to actual timing; even 25 m of cable is better
treated using transmission line theory. Flat ribbon cables connected as shown, with the bus signals on the outer
edge, have a characteristic impedance in the range 100–200 Ω. For simplicity, they cannot be terminated in their
characteristic impedance, but a practical compromise is to use the minimum pullup allowed for P82B96 and
place half this termination at each end of the cable. When each pullup is less than 330 Ω, the rising-edge
waveforms have their first voltage step level above the logic threshold at Rx, and cable timing calculations can
be based on the fast rise/fall times of resistive loading, plus simple one-way propagation delays. When the pullup
is larger, but less than 750 Ω, the threshold at Rx is crossed after one signal reflection. So, at the sending end, it
is crossed after two times the one-way propagation delay and, at the receiving end, after three times that
propagation delay. For flat cables with partial plastic dielectric insulation (by using outer cores) the one-way
propagation delays are about 5 ns/m. The 10% to 90% rise and fall times on the cable are from 20 ns and 50 ns,
so their delay contributions are small. There is ringing on falling edges that can be damped, if required, using
Schottky diodes.
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
19
P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
V
+V Cable Drive
100 kW
100 nF
VCC1
www.ti.com
VCC
Rx
SCL
Sx
+V Cable Drive
VCC2
VCC
BC
847B
3-m to 20-m Cables
Rx
Sx
Tx
Tx
SCL
2
Ty
2
I C/DDC
Master
4700 W
Ty
Ry
SDA
Sy
I C/DDC
Slave
Ry
2
I C/DDC
Sy
SDA
470 kW
BC
847B
P82B96
P82B96
470 kW
GND
Monitor/Flat TV
GND
PC/TV Receiver/Decoder Box
R
G
B
Video Signals
Figure 14. Extending DDC Bus
10.2.5 Voltage Translation
Figure 15 shows how the P82B96 can be used for I2C Voltage Translation.
VCC (2–15V)
5V
Tx
(SDA)
2
IC
SDA
R1
SDA
(New Levels)
Rx
(SDA)
1/2 P82B96
Figure 15. Interfacing I2C Bus With Different Logic Levels
20
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
P82B96
www.ti.com
SCPS144C – MAY 2006 – REVISED MAY 2015
11 Power Supply Recommendations
VCC accepts supply voltages from 2 V up to 15 V. The GND pin must be tied to ground. TI recommends that
decoupling capacitor with a value of approximately 100 nF be placed near VCC.
12 Layout
12.1 Layout Guidelines
The recommended decoupling capacitors should be placed as close to the VCC pin of the P82B96 as possible.
12.2 Layout Example
Figure 16 is an example layout for the typical application seen in the Long-Distance I2C section, using the DGK
package.
VCC
Local SCL
Local SDA
= VIA to GND Plane
0603 Cap
Sx
VCC
Rx
Sy
Tx
Ry
GND
Ty
Cable SCL
Cable SDA
Figure 16. Layout Example
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
21
P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
www.ti.com
13 Device and Documentation Support
13.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
Submit Documentation Feedback
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: P82B96
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
P82B96D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PG96
P82B96DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PG96
P82B96DGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
7DS
P82B96DGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
7DS
P82B96DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PG96
P82B96DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PG96
P82B96P
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
P82B96P
P82B96PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PG96
P82B96PWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PG96
P82B96PWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PG96
P82B96PWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PG96
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
P82B96DGKR
Package Package Pins
Type Drawing
VSSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
P82B96DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
P82B96PWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
P82B96DGKR
VSSOP
DGK
8
2500
358.0
335.0
35.0
P82B96DR
SOIC
D
8
2500
367.0
367.0
35.0
P82B96PWR
TSSOP
PW
8
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising