Texas Instruments | SN65HVD10x IO-Link PHY for Device Nodes (Rev. D) | Datasheet | Texas Instruments SN65HVD10x IO-Link PHY for Device Nodes (Rev. D) Datasheet

Texas Instruments SN65HVD10x IO-Link PHY for Device Nodes (Rev. D) Datasheet
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SN65HVD101, SN65HVD102
SLLSE84D – MAY 2011 – REVISED MAY 2017
SN65HVD10x IO-Link PHY for Device Nodes
1 Features
•
1
•
•
•
•
•
•
•
•
•
•
Configurable CQ Output: Push-Pull, High-Side, or
Low-Side for SIO Mode
Remote Wake-Up Indicator
Current Limit Indicator
Power-Good Indicator
Overtemperature Protection
Reverse Polarity Protection
Configurable Current Limits
9-V to 36-V Supply Range
Tolerant to 50-V Peak Line Voltage
3.3-V/5-V Configurable Integrated LDO
(SN65HVD101 ONLY)
20-pin QFN Package, 4 mm × 3.5 mm
2 Applications
•
Suitable for IO-Link Device Nodes
3 Description
The SN65HVD101 and ‘HVD102 IO-Link PHYs
implement the IO-Link interface for industrial point-topoint communication. When the device is connected
to an IO-Link master through a 3-wire interface, the
master can initiate communication and exchange
data with the remote node while the SN65HVD10X
acts as a complete physical layer for the
communication.
The IO-Link driver output (CQ) can be used in pushpull, high-side, or low-side configurations using the
EN and TX input pins. The PHY receiver converts the
24-V IO-Link signal on the CQ pin to standard logic
levels on the RX pin. A simple parallel interface is
used to receive and transmit data and status
information between the PHY and the local controller.
The SN65HVD101 and 'HVD102 implement
protection features for overcurrent, overvoltage and
overtemperature conditions. The IO-Link driver
current limit can be set using an external resistor. If a
short-circuit current fault occurs, the driver outputs
are internally limited, and the PHY generates an error
signal (SC). These devices also implement an
overtemperature shutdown feature that protects the
device from high-temperature faults.
The SN65HVD102 operates from a single external
3.3-V or 5-V local supply. The SN65HVD101
integrates a linear regulator that generates either 3.3
V or 5 V from the IO-Link L+ voltage for supplying
power to the PHY as well as a local controller and
additional circuits.
The SN65HVD101 and 'HVD102 are available in the
20-pin RGB package (4 mm × 3,5 mm QFN) for
space-constrained applications.
Device Information(1)
PART NUMBER
PACKAGE
SN65HVD101
BODY SIZE (NOM)
QFN (20)
SN65HVD102
4.00 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
1µF
RPU
Vcc
Sensor
MCU
IRQ
Vcc IN Vcc OUT Vcc SET
WAKE
GPIO1
PWR _OK
GPIO2
CUR _OK
GPIO3
GND
L+
SN65HVD101
RX
TXD
TX
RTS
EN
1
2
TEMP _OK
RXD
1µF
CQ
4
3
LILIM ADJ
GND
RSET
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD101, SN65HVD102
SLLSE84D – MAY 2011 – REVISED MAY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
5
5
6
7
8
Absolute Maximum Ratings .....................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement ....................................... 8
Detailed Description .............................................. 9
9.1 Overview ................................................................... 9
9.2 Functional Block Diagram ....................................... 10
9.3 Feature Description................................................. 10
9.4 Device Functional Modes........................................ 13
10 Application and Implementation........................ 14
10.1 Application Information.......................................... 14
10.2 Typical Application ............................................... 14
10.3 System Examples ................................................ 19
11 Power Supply Recommendations ..................... 20
12 Layout................................................................... 21
12.1 Layout Guidelines ................................................. 21
12.2 Layout Example .................................................... 21
13 Device and Documentation Support ................. 22
13.1
13.2
13.3
13.4
13.5
13.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
14 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (February 2017) to Revision D
•
Page
Changed From: 950 mW To: 950 W, and From: 475 mW To: 475 W in the TVS Evaluation section ................................ 16
Changes from Revision B (April 2015) to Revision C
•
Page
Changed pin 1 of the SN65HVD102 From: nc To: Vcc SET ................................................................................................. 3
Changes from Revision A (March 2013) to Revision B
Page
•
Added Device Information and ESD Rating tables, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
•
Changed front-page Simplified Schematic image. ................................................................................................................ 1
•
Changed Pin Functions table format ..................................................................................................................................... 4
•
Re-write detailed description section. .................................................................................................................................... 9
•
Re-write application information section. ............................................................................................................................. 14
Changes from Original (May 2011) to Revision A
•
2
Page
Changed the devices From: Product Preview To: Production................................................................................................ 1
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SLLSE84D – MAY 2011 – REVISED MAY 2017
5 Device Comparison Table
DEVICE
VOLTAGE REGULATOR
SN65HVD101
Yes
SN65HVD102
No
6 Pin Configuration and Functions
Vcc SET
1
15
CUR _OK
nc
2
14
L-
13
GND
19
WAKE
20
TX
16
RX
17
EN
18
TEMP _OK
WAKE
19
TX
20
RX
EN
TEMP _OK
RGB Package
20-Pin QFN with Thermal Pad
Top View
18
17
16
Vcc SET
1
15
CUR _OK
nc
2
14
L-
13
GND
GND
3
GND
3
ILIM_ADJ
4
12
CQ
ILIM_ADJ
4
12
CQ
PWR _OK
5
11
nc
PWR _OK
5
11
nc
GND
Vcc OUT
nc
L+
6
7
8
9
10
L+
10
nc
9
nc
8
GND
7
SN65HVD102
Vcc IN
6
Vcc IN
SN65HVD101
Pin Functions
PIN
NAME
NUMBER
DESCRIPTION
TYPE (1)
IO-Link Interface
L+
10
P
CQ
12
I/O
L–
14
P
IO-Link supply voltage (24V nominal)
IO-Link data signal (bi-directional)
IO-Link ground (connect to board ground)
Local Controller Interface
CUR_OK
15
OD
High-CQ-current fault indicator output signal from PHY to the microcontroller. Connect this pin via
pull-up resistor to Vcc OUT. A LOW level indicates over-current condition.
WAKE
16
OD
Wake up indicator from the PHY to the local controller Connect this pin via pull-up resistor to Vcc
OUT.
RX
17
O
PHY receive data output to the local controller
TX
18
I
PHY transmit data input from the local controller
EN
20
I
Driver enable input signal from the local controller
Power Supply Pins
VCC IN
7
A
Voltage supply input for SN65HVD102
Voltage sense feedback input for the voltage regulator of the SN65HVD101. Connect this pin to pin
8 either directly or through a current boost transistor.
VCC OUT
8
P
Not connected in SN65HVD102
Linear regulator output of SN65HVD101. Connect this pin to pin 7 either directly or through a
current boost transistor.
3, 6, 13
P
Logic ground potential
GND
(1)
Type definitions: I = Input, I/O = Input/Output, A = Analog, O - CMOS Output, OD = Open Drain Output, P = Power
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Pin Functions (continued)
PIN
NAME
NUMBER
DESCRIPTION
TYPE (1)
Special Connect Pins
VCC SET
1
I
Connect this pin to ground to make Vcc OUT = 3.3V. Leave this pin floating to make Vcc OUT =
5V.
ILIMADJ
4
A
Input for current limit adjustment. Connect resistor RSET between this pin and ground. For RSET
values see Figure 2.
PWR_OK
5
OD
Power-Good indicator. Connect this pin via pull-up resistor to Vcc OUT. A HIGH at this pin indicates
that L+ and Vcc OUT are at correct levels.
Temp_OK
19
OD
Temperature-Good indicator. Connect this pin via pull-up resistor to Vcc OUT. High-impedance at
this pin indicates that the internal temperature is at a safe level. A low at this pin indicates the
device is approaching thermal shutdown.
2, 9, 11
–
NC
No Connection. Leave these pins floating (open)
In normal operation, the PHY sets the output state of the CQ pin when the driver is enabled. During fault
conditions, the driver may be disabled by internal circuits.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
Steady state
–40
40 (2)
Transient pulse width <100 µs
–50
50
(3)
UNIT
V
Line voltage
L+, CQ
Voltage difference
|VL+ – VCQ|
Supply voltage
VCC
–0.3
6
V
Input voltage
TX, EN, VCC_SET, ILIMADJ,
–0.3
6
V
Output voltage
RX, CUR_OK, WAKE, PWR_OK
–0.3
6
V
Output current
RX, CUR_OK, WAKE, PWR_OK
–5
5
mA
–65
150
°C
180
°C
Storage temperature, Tstg
Junction temperature, TJ
(1)
(2)
(3)
V
40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with reference to the GND pin, unless otherwise specified.
GND pin and L– line should be at the same DC potential
7.2 ESD Ratings
V(ESD)
(1)
4
Electrostatic discharge
Human-body model (HBM, all pins), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
MIN
NOM
MAX
VL+
Line voltage (1)
9
24
30
UNIT
V
VCC
Logic supply voltage (3.3V nominal)
3
3.3
3.6
V
VCC
Logic supply voltage (5V nominal)
4.5
5
5.5
V
VIL
Logic low input voltage
0.8
V
VIH
Logic high input voltage
IO
Logic output current
2
V
–4
4
mA
20
mA
100
450
mA
0
20
kΩ
ICC(OUT) Logic supply current (HVD101)
IO(LIM)
CQ driver output current limit
RSET
External resistor for CQ current limit
CCOMP
Compensation capacitor for voltage regulator (HVD101)
3.3
µF
IO-Link mode
250
1/tBIT
Signaling rate
TA
Ambient temperature
–40
105
°C
TJ
Junction temperature
–40
150
°C
(1)
SIO mode
kbps
10
These devices will operate with line voltage as low as 9V and as high as 36V, however, the parametric performance is optimized for the
IO-Link specified supply voltage range of 18V to 30V.
7.4 Thermal Information
THERMAL METRIC (1)
SN65HVD10x
RGB 20 PINS
RθJA
Junction-to-ambient thermal resistance
33.8
RθJC(top)
Junction-to-case (top) thermal resistance
36.6
RθJB
Junction-to-board thermal resistance
10.3
ψJT
Junction-to-top characterization parameter
0.4
ψJB
Junction-to-board characterization parameter
10.3
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.3
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
over all operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–100
100
µA
1.5
3
V
VL+ < 18
3.5
V
18 < VL+
2
V
VL+ < 18
2.5
V
3
V
VL+ < 18
3.5
V
18 < VL+
2
V
VL+ < 18
2.5
V
Driver
IIN
Input current (TX, EN)
VIN = 0V to VCC
ICQ = –250 mA
VRQH
Residual voltage across the driver high side switch
ICQ = –200 mA
ICQ = 250 mA
VRQL
Residual voltage across the driver low side switch
ICQ = 200 mA
|IO(LIM)|
Driver output current limit
I(OZ)
CQ leakage current with EN = L
18 < VL+
18 < VL+
1.5
RSET = 20 kΩ
60
95
130
mA
RSET = 0 kΩ
300
400
480
mA
VCQ = 8 V
–2
2
µA
10.5
13
V
8
11.5
V
Receiver
VTHH
Input threshold “H”
VTHL
Input threshold “L”
VHYS
Receiver Hysteresis (VTHH – VTHL)
VTHH
Input threshold “H”
VTHL
Input threshold “L”
VHYS
Receiver Hysteresis (VTHH–VTHL)
18 V < VL+ < 30 V
0.5
9 V < VL+ < 18 V
1
V
Note
(1)
Note (2)
V
Note
(3)
Note (4)
V
0.25
V
RX
IOL = 4 mA
0.4
OD outputs
IOL = 1 mA
0.4
VOL
Output low voltage
VOH
Output high voltage
RX
IOH = –4 mA
IOZ
Output leakage current
OD outputs
Output in Z state, VO = VCC
VCC–0.5
V
V
0.03
1
µA
10
V
Protection Thresholds
VPG1
VL+ threshold for PWR_OK
8
VCC Set = GND
2.45
2.75
3
3.9
4.25
4.6
VPG2
VCC threshold for PWR_OK
VPOR1
Power-on Reset for VL+
6
V
VPOR2
Power-on Reset for VCC
2.5
V
VCC Set = OPEN
V
Voltage Regulator (HVD101)
VCC SET = OPEN
VCC_OUT
Voltage regulator output
9 V < VL+ < 30 V
VDROP
Voltage regulator drop-out voltage (VL+ – VCC_OUT )
ICC = 20 mA load current
Line regulation (dVCC_OUT /dL+)
9 V < VL+ < 30 V, IVCC = 1 mA
Load regulation (dVCC_OUT /VCC_OUT)
VL+ = 24 V,
IVCC = 100 µA to 20 mA
Power Supply Rejection Ratio
100 kHz, IVCC = 20 mA
PSRR
VCC SET = GND
4.5
5
5.5
3
3.3
3.6
3.2
3.9
4
1.3%
30
V
V
mV/V
5%
40
dB
Supply Current
Quiescent supply current
Driver disabled, No
Load
IL+
Dynamic supply current
(1)
(2)
(3)
(4)
6
HVD102
1
2
HVD101
1.3
3
HVD102
2
HVD101
1.5
mA
VTHH(min) = 5V + (11/18)[VL+ - 9V]
VTHH(max) = 6.5V + (13/18)[VL+ - 9V]
VTHL(min) = 4V + (8/18)[VL+ -9V]
VTHL(max) = 6V + (11/18)[VL+ -9V]
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7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1
2
UNIT
Driver
tPLH, tPHL Driver propagation delay
tP(skew)
Driver propagation delay
skew
TX to CQ
tPZH, tPZL
Driver enable delay (EN to
CQ)
18 V < VL+ < 30 V
tPHZ, tPLZ Driver disable delay
tr, tf
Driver output rise, tall time
|tr – tf|
Difference in rise and fall time
9 V < VL+ < 18 V
18 V < VL+ < 30 V
VL+ < 18 V
0.2
Figure 1, Figure 2,
Figure 3,
RL= 2kΩ
CL = 5 nF
RSET = 0 Ω
µs
5
8
5
8
869
18 V < VL+
µs
300
µs
µs
ns
Receiver
tWU1
Wake-up recognition begin
tWU2
Wake-up recognition end
tpWAKE
Wake-up output delay
tND
Noise suppression time (1)
tPR
Receiver propagation delay
Figure 16
45
60
75
85
100
135
µs
155
250
Figure 4
18 V < VL+
300
VL+ < 18 V
600
800
ns
ns
Protection Thresholds
TSD
Shutdown temperature
160
175
190
TRE
Re-enable temperature (2)
110
125
140
120
135
150
Die temperature
Thermal warning temperature
(TEMP_OK)
tpSC
(1)
(2)
Current limit indicator delay
85
175
°C
µs
Noise suppression time is defined as the permissible duration of a receive signal above/below the detection threshold without detection
taking place.
TRE is always less than TWARN so TEMP_OK is de-asserted (high impedance) when the device is re-enabled.
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7.7 Typical Characteristics
14
500
VTHH
13
450
Current Limit ± |IO(LIM)| ± mA
Receiver Thresholds ± V
12
11
10
9
VTHL
8
7
6
5
4
400
350
300
MAX
250
TYP
200
MIN
150
100
50
8
12
16
20
24
28
0
32
0
5
10
15
20
VL+ ± V
RSET ± k
Figure 1. Receiver Threshold Boundaries
Figure 2. Typical Current Limit Characteristics
8 Parameter Measurement
VOH
TX
tPHL
CQ
VL+
VCQ
80%
50%
80%
EN
tPLH
50%
EN
tPZL
50%
20%
tPLZ
50%
tPZH
tPHZ
20%
VCQ
80%
VOL
0V
tr
tf
Figure 3. Waveforms for Driver Output Switching
Measurements
CQ
50%
CQ
50%
20%
Figure 4. Waveform for Driver Enable/Disable Time
Measurements
L+
CQ
50%
RL
TX
tPLH
tPHL
CQ
RL
CL
EN
RX
50%
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Figure 5. Receiver Switching Measurements
Figure 6. Test Circuit for Driver Switching
8
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9 Detailed Description
9.1 Overview
An IO-Link device comprises a transducer or physics to digital converter and the device transceiver (Figure 7).
When the device is connected to an IO-Link master through the three-wire interface, the master can initiate
communication and exchange data with a remote node with the SN65HVD101 or SN65HVD102 IO-Link
transceiver acting as a complete physical layer for the communication.
SN65HVD101
VCCOUT
VCCIN
IO Link
Master
L+
L+
VCCSET
Fe
Inductive
Sensor
VDD
I/O1
EN
TxD
TX
RxD
MSP430
INT
RX
C/Q
IO Link
Transceiver
L-
L-
GND
WAKE
I/O2
PWR_OK
I/O3
CUR_OK
I/O4
GND
C/Q
RSET
ILIM_ADJ
TEMP_OK
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Figure 7. IO-Link Device-to-Master Interface
The functional block diagram shows that the device driver output (CQ) can be used in push-pull, high-side, or
low-side configurations using the enable (EN) and transmit data (TX) input pins. The internal receiver converts
the 24-V IO-Link signal on the CQ line to standard logic levels on the receive data (RX) pin. A simple parallel
interface is used to receive and transmit data and status information between the slave and the local controller.
IO-Link transceivers commonly implement protection features for overcurrent, overvoltage and overtemperature
conditions. They also provide a current-limit setting of the driver output current using an external resistor. If a
short circuit (SC) occurs, the driver outputs are internally limited, and the slave generates an error signal.
The transceiver also possesses an overtemperature shutdown feature that protects the device from hightemperature faults. A modern transceiver can operate either from an external 3.3-V or 5-V low-volt supply, or
derives the low-volt supply from the IO-Link L+ voltage (24V nominal) via a linear regulator, to provide power to
the local controller and sensor circuitry.
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9.2 Functional Block Diagram
Vcc_SET
Vcc_In
VOLTAGE *
REGULATOR
Vcc_OUT
* HVD101 only
L+
PWR_OK
TX
EN
WAKE
CONTROL
LOGIC
RX
DIAGNOSTICS
& CONTROL
C/Q
CUR_OK
L-
TEMP_OK
ILIM_ADJ GND
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9.3 Feature Description
9.3.1 Wake-up Detection
The device may be in IO-Link mode or SIO mode. If the device is in SIO mode and the master node wants to
initiate communication with the device node, the master drives the CQ line to the opposite of its present state,
and will either sink or source the wake up current (IQWU is typically up to 500 mA) for the wake-up duration (tWU
is typically 80 μs) depending on the CQ logic level as per the IO-Link specification. The SN65HVD1XX IO-Link
PHY detects this wake-up condition and communicates to the local microcontroller via the WAKE pin. The IOLink Communication Specification requires the device node to switch to receive mode within 500 μs after
receiving the Wake-Up signal.
For over-current conditions shorter or longer than a valid Wake-Up pulse, the WAKE pin will remain in a highimpedance (inactive) state. This is illustrated in Figure 8, and discussed in the following paragraph.
CQ
< 45 s
RX
WAKE
CQ
CQ
80 ±5 s
RX
high
> 250 s
RX
WAKE
WAKE
high
tpWAKE
CUR_OK
high
CUR_OK
high
CUR_OK
tpSC
a) Over-current due to transient
b) Wake-up pulse from master
c) Overcurrent due to fault condition
Figure 8. Over-current and Wake Conditions for EN = H, TX = H (full lines); and TX = L (red dotted lines)
9.3.2 Current Limit Indication – Short Circuit Current Detection
The internal current limit indicator is gated with the wake logic and thus becomes active only under certain
conditions of the CQ-voltage (see Table 4).
10
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Feature Description (continued)
9.3.3 Active Current Limit Condition: VTHL > VCQ ≥ VTHH
If the output current at CQ remains at the internally set current limit IO(LIM) for a duration longer than a wake-up
pulse (longer than 80 μs), the CUR_OK pin is driven logic low, indicating an over-current condition. The CUR_OK
pin returns to the high-impedance (inactive) state when the CQ pin is no longer in a current limit condition. The
state diagram shown in Figure 9 illustrates the various states; and, under what conditions the device transitions
from one state to another.
9.3.4 Inactive Current Limit Condition: VTHL < VCQ < VTHH
If the voltage at CQ is between the upper and lower receiver input threshold, CUR_OK remains high-impedance.
Receive
Only
CUR_OK = Z
WAKE = Z
Driver = OFF
EN
*
Receive and
Transmit
CUR_OK = Z
WAKE = Z
Driver = ON
CQ @ ILIM
for tWU1 < t < tWU2
and RX •TX
D
E
TS
TR
T>
T<
CQ
@
I
for
t > LIM
t
CQ @ ILIM
T SD
for t > tWU2
T>
*
EN
T > TSD
Wake
WAKE = L
CUR_OK = Z
Driver = ON
EN
*
WU
2
Thermal
Shutdown
CUR_OK = Z
WAKE = Z
Driver = OFF
T > TSD
CQ NOT @ ILIM
EN
Current
Fault
WAKE = Z
CUR_OK = L
Driver = ON
Figure 9. State Diagram of Device Transceiver
9.3.5 Over-temperature Detection
If the transceiver’s internal temperature exceeds its over-temperature threshold θTSD, the CQ driver and the
voltage regulator (HVD101) are disabled. As soon as the temperature drops below the temperature threshold,
the internal circuit re-enables the voltage regulator (HVD101) and the driver, subject to the state of the EN and
TX pins.
9.3.6 CQ Current-limit Adjustment
The CQ driver current-limit is determined by the external resistor, RSET, at the ILIM_ADJ pin. Figure 2 shows the
typical current-limit characteristics as a function of RSET.
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Feature Description (continued)
9.3.7 Transceiver Function Tables
Table 1. Driver Function
EN
TX
CQ
L or OPEN
X
Z
PHY is in ready-to-receive state
COMMENT
H
L
H
PHY CQ is sourcing current (high-side drive)
H
H or OPEN
L
PHY CQ is sinking current (low-side drive)
Table 2. Receiver Function
CQ Voltage
RX
COMMENT
VCQ < VCHL
H
Normal receive mode, input low
VTHL < VCQ < VTHH
?
Indeterminate output, may be either High or Low
VTHH < VCQ
L
Normal receive mode, input high
OPEN
H
Failsafe output high
Table 3. Wake-Up Function
EN
TX
CQ VOLTAGE
WAKE
L
X
X
Z
PHY is in ready-to-receive state
COMMENT
H
H
VTHH < VCQ (tWU)
L
PHY receives High-level wake-up request from Master
H
X
VTHL < VCQ < VTHH
?
Indeterminate output, may be either High or Low
H
L
VTHL > VCQ (tWU)
L
PHY receives Low-level wake-up request from Master
Table 4. Current Limit Indicator Function (t > tWU)
EN
TX
CQ VOLTAGE
CQ CURRENT
H
H
VCQ ≥ VTHH
|ICQ| > IO(LIM)
L
CQ current is at the internal limit
|ICQ| < IO(LIM)
Z
Normal operation
VCQ < VTHH
X
Z
Current limit indicator is inactive
VCQ < VTHL
|ICQ| > IO(LIM)
L
CQ current is at the internal limit
H
L
L
X
CUR_OK
COMMENT
|ICQ| < IO(LIM)
Z
Normal operation
VCQ ≥ VTHL
X
Z
Current limit indicator is inactive
X
X
Z
Driver is disabled, Current limit
indicator is inactive
Table 5. Temperature Indicator Function
INTERNAL
TEMPERATURE
T < TWARN
TWARN < T↑ < TSD
TSD < T
TWARN < T↓ < TRE
OVER TEMPERATURE
TEMP_OK
COMMENT
Not Over-Temperature
Z
Normal operation
Not Over-Temperature
L
Temperature warning
Over-Temperature Disabled
L
Over-Temperature disabled
Not Over-Temperature
L
Temperature recovery
Table 6. Power Supply Indicator Function
12
VL+
VCC
PWR_OK
VL+ < VPG1
VPOR2 < VCC < VPG2
L
Both supplies too low
VPG1 < VL+
VPOR2 < VCC < VPG2
L
VCC too low
VL+ < VPG1
VPG2 < VCC
L
VL+ too low
VPG1 < VL+
VPG2 < VCC
Z
Both supplies correct
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COMMENT
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9.3.8 Voltage Regulator (Not Available in SN65HVD102)
The SN65HVD101 integrates a linear voltage regulator which supplies power to external components as well as
to the PHY itself. The voltage regulator is specified for L+ voltages in the range of 9V to 30V with respect to
GND. The output voltage can be set using the Vcc_SET pin (see Figure 10). When this pin is left open (floating)
then the output voltage is 5V. When it is connected to GND then the output voltage is 3.3V.
Vcc_IN
Vcc_OUT
L+
VBG
R1
Vcc_SET
R2b
R2a
* Voltage
Regulator
GND
Copyright © 2017, Texas Instruments Incorporated
* HVD101 only
Figure 10. Voltage Regulator Equivalent Circuit
9.4 Device Functional Modes
The SN65HVD101 and SN65HVD102 can operate in three different modes:
• N-Switch SIO Mode
Set TX pin High and use EN pin as control for realizing the function of an N-switch (low-side driver) on CQ.
• P-Switch SIO Mode
Set TX pin Low and use EN pin as control for realizing the function of a P-switch (high-side driver) on CQ.
• Push-Pull / Communication Mode
Set EN pin high and toggle TX as control for realizing the function of a Push-Pull output on CQ.
Table 7 to Table 9 summarize the pin configurations to accomplish the above functional modes.
Table 7. N-Switch SIO Mode
EN
TX
CQ
L
H
Hi-Z
H
H
N-Switch
Table 8. P-Switch SIO Mode
EN
TX
CQ
L
L
Hi-Z
H
L
P-Switch
Table 9. Push-Pull / Communication Mode
EN
TX
CQ
L
X
Hi-Z
H
H
N-Switch
H
L
P-Switch
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN65HVD101 and SN65HVD102 IO-Link transceivers can be used in slave devices communicating with an
IO-Link master, or as simple digital I/O to either sense or drive a wide range of sensors and loads.
10.2 Typical Application
5 x 10k
3.3µF
RPU
Vcc
Sensor
MCU
Vcc IN Vcc OUT Vcc SET
WAKE
IRQ
GPIO1
PWR _OK
GPIO2
CUR _OK
GPIO3
TEMP _OK
GND
RXD
RX
TXD
TX
RTS
EN
10k
1µF
L+
TVS 1-3
L+
SN65HVD101
ILIM ADJ
CQ
CQ
L-
L-
GND
RPD
RSET
Copyright © 2017, Texas Instruments Incorporated
Figure 11. Typical Application Schematic, SN65HVD101 with 3.3V Output Supply
10.2.1 Design Requirements
For this design example, use the parameters listed in Table 10 as design parameters.
Table 10. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range (L+)
TRANSCEIVER
SURGE PROTECTION
(1.2/50 – 8/20μs)
24V
Maximum load current (CQ)
250 mA
Output voltage (Vcc_OUT)
3.3 V
Maximum output current (Vcc_OUT)
20 mA
Peak Voltage (L+, CQ)
2 kV
Peak Current via R = 500 Ω, C = 0.5 µF
4A
Maximum TVS Clamping Voltage
> 50 V
Minimum TVS Standoff Voltage
> 30 V
Maximum Ambient Temperature, TA
100 °C
Maximum Junction Temperature, TJ
150 °C
10.2.2 Detailed Design Procedure
The following recommendations on device configuration and components selection focus on the design of a
digital output driver using SN65HVD101 with protection against surge transients from a 1.2/50 – 8/20 μs
combination waveform generator (CWG) with 2 kV peak test voltage and 500 Ω source impedance.
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10.2.2.1 Transceiver Configuration (SN65HVD101)
1. Choose a 24 V nominal dc supply for L+.
2. From the current-limit characteristics in Figure 2 derive the resistor value of RSET = 4 kΩ for a current limit of
IO(LIM) = 250 mA.
3. Connect VCC_SET to ground for a 3.3V output at VCC_OUT.
4. Connect VCC_IN to VCC_OUT to assure proper output voltage regulation of VCC_OUT.
5. Buffer VCC_OUT with a 3.3μF, 10V ceramic capacitor.
6. Connect the receiver and diagnostic outputs via 10 kΩ pull-up resistors to VCC_OUT to provide defined voltage
potentials to the controller inputs during high-impedance states.
7. Connect the driver enable pin, EN, via a 10 kΩ pull-down resistor to ground to maintain the driver disabled
during power up.
10.2.2.2 Maximum Ambient Temperature Check
For a 250 mA current limit, the maximum voltage drop across the high-side switch is given with VRQH = 3 V
(taken from Electrical Characteristics: Driver section). This causes an internal power consumption of:
PD-INT = VRQH × IO(lim) = 3 V × 250 mA = 750 mW
(1)
Multiply this value with the Junction-to-ambient thermal resistance of θJA = 33.8 °C/W (taken from Thermal
Information) to receive the difference between junction temperature, TJ, and ambient temperature, TA:
DT = TJ - TA = PD-INT × qJA = 750 mW × 33.8 o C / W = 25.4 o C
(2)
Add this value to the maximum ambient temperature of TA = 100 °C to receive the final junction temperature:
TJ-max = TA -max + DT = 100 o C + 25.4 o C = 125.4 o C
(3)
As long as TJ-max is below the recommended maximum value of 150 °C, no overheating will occur.
10.2.2.3 Transient Protection
A commonly applied surge immunity test in digital I/O designs is the application of the 1.2/50 – 8/20 μs
combination waveform, specified in IEC61000-4-5, with a source impedance of 500 Ω and a peak test voltage of
VO-pk = 2 kV, which results in a peak surge current of IS-pk = 4 A.
The test set-up for line-to-line and line-to-ground measurements is shown in Figure 12; the calculation of the
surge peak current is shown in Figure 13.
Combination
wave
Generator
R
C
RS1 = 2
RS2 = 500
VO-pk = 2kV
Is
IS-pk = 4A
1.2/50 ± 8/20 s CWG
R = 500 , C = 0.5 F
Protection
Equipment
Auxiliary
Equipment
EUT
Copyright © 2017, Texas Instruments Incorporated
L+
CQ
Decoupling
Network
L-
Earth
Reference
IS -pk »
VOC-pk
RS
=
2kV
= 4A
502 W
Copyright © 2017, Texas Instruments Incorporated
Figure 12. Surge Test Set-up
Figure 13. Peak Current Calculation
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10.2.2.4 TVS Evaluation
Because the maximum transceiver supply at L+ is specified with 30 V, the TVS standoff or peak working voltage
must be higher than this value. The standoff voltage is the voltage where the TVS does not conduct yet.
Transient voltage suppressors with this high standoff have peak pulse powers starting at 200 W. Their peak
pulse power however is usually rated based on a 10/1000 μs current pulse, which is commonly applied in
telecom application. It is therefore necessary to derate the peak power value from a 10/1000 μs to a 8/20 μs
pulse.
For this example the bidirectional, 200 W TVS, SMF33CA, was selected. Its main parameters and their derated
values are listed in Table 11. The peak pulse power rating for a 10/1000 μs pulse is shown in Figure 14.
100
10
/10
00
us
@
Peak Pulse Power Derating (%)
Peak Pulse Power ± PPK (kW)
10
25 o
C
8/20 s @ 25oC
1
8/20 s @ 100oC
0.1
0.1
1
10
100
Pulse Duration ± tp ( s)
1000
Figure 14. Peak Pulse Power Rating
10000
75
50
25
0
0
25 50 75 100 125 150 175 200
Ambient temperature ± TA (oC)
Figure 15. Pulse Derating Curve
At the pulse duration of 1000 μs the device has a peak pulse power rating of 200 W. To determine the peak
power for a 8/20 μs pulse, move up the power rating curve until you hit the 20 μs pulse duration. The peak pulse
power rating at this point is about 950 W.
Note these values are valid for 25 °C ambient temperature only. Because the operating ambient temperature in
this example is specified with 100 °C however, the peak pulse power must be further derated for the higher
ambient temperature using the pulse derating curve in Figure 15. This curve shows that the peak power level at
25 °C drops by 50 % when reaching 100 °C, so from 950 W down to 475 W. This drop is shown in Figure 14
through the arrow pointing down to the second peak power level for a 20 μs pulse duration at 100 °C.
Table 11. TVS Parameters
PARAMETER
SYMBOL
SMF33CA
UNIT
Maximum Working Peak Voltage
VWM
33
V
Minimum Breakdown Voltage at 1 mA
VBR
36.7
V
Maximum Clamping Voltage at IPP
VCL
53.3
V
Peak Pulse Power (10/1000 μs) at 25°C
PPK1
200
W
Peak Pulse Current (10/1000 μs) at 25°C
IPP1
3.75
A
W
Derated Peak Power (8/20 μs) at 25°C
PPK2
950
Derated Peak Current (8/20 μs) at 25°C
IPP2
17.76
A
Derated Peak Power (8/20 μs) at 100°C
PPK3
475
W
Derated Peak Current (8/20 μs) at 100°C
IPP3
8.9
A
To determine the peak currents for the various peak power ratings, TVS manufacturers advise to assume the
maximum clamping voltage as being constant, because this clamping level also presents the device maximum
failing voltage if its value is exceeded. The peak current for a given power rating is therefore calculated via:
IPP = PPK VCL
(4)
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So for the 8/20 μs peak power of 475 W at 100 °C, the peak pulse current is IPP3 = 475 W ÷ 53.3 V = 8.9 A. The
new derived values of PPK and IPP in combination with the values for breakdown and clamping voltage, VBR and
VCL, from Table 11, yield a new I-V characteristics of the SMF33CA TVS when exposed to a 8/20 μs pulse.
TVS Current ± A
10
SMF33CA
8
6
2kV Surge
4
2
0
0
10
20
30
40
TVS Voltage ± V
50
60
Figure 16. TVS Characteristic for 8/20 μs Current Pulse
Because the maximum surge current of the CWG in Figure 13 is only 4 A at 2 kV test voltage, the TVS clamping
voltage at this level is only 44 V. This voltage is sufficiently below the absolute maximum voltage rating of 50 V
for a 100 μs pulse at the L+ and CQ terminals of the SN65HVD101 and SN65HVD102 transceivers, causing no
device damage.
10.2.3 Application Curves
N-Switch Mode
Top waveform = EN
TX pin High
Bottom waveform = CQ
P-Switch Mode
Top waveform = EN
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Bottom waveform = CQ
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Top waveform = TX
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EN pin High
Bottom waveform = CQ
VCC (top) and ICC (bottom) at Start-Up with 3.3 µF LDO Output
Capacitor
VCC (top) and ICC (bottom) at Start-Up without 3.3 µF LDO Output Capacitor
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10.3 System Examples
10.3.1 Driver for Incandescent Lamp Loads
The following circuit shows the SN65HVD101 driving an incandescent lamp load. For this and other types of
resistive loads only two TVS diodes are used to protect the CQ and L+ lines to ground.
5 x 10k
3.3µF
RPU
Vcc
MCU
Vcc IN Vcc OUT Vcc SET
L+
WAKE
IRQ
GPIO1
PWR _OK
GPIO2
CUR _OK
GPIO3
TEMP _OK
GND
RXD
RX
TXD
TX
EN
RTS
10k
1µ F
24V
TVS2
SN65HVD101
CQ
TVS1
ILIM ADJ
GND
L-
0V
RPD
RSET
Copyright © 2017, Texas Instruments Incorporated
Figure 17. SN65HVD101 Driving Incandescent Lamp Load
The resistance of an incandescent lamp filament varies strongly with temperature. The initial (cold-filament)
resistance of tungsten-filament lamps is less than 10% of the steady-state (hot-filament) resistance. For example,
a 100-watt, 120-volt lamp has a resistance of 144 Ω when lit, but the cold resistance is much lower (about 9.5 Ω).
The initial “in-rush” current is therefore high compared to the steady-state current. Within 3 to 5 ms the current
falls to approximately half the hot current.
For typical general-service lamps, the current reaches steady-state conditions in less than about 100
milliseconds. The ‘HVD10x CQ output will remain at the selected current-limit as the filament warms up, and then
will stay at the steady-state current level. For example, a 6W, 24VDC indicator lamp has a steady-state current of
250 mA. However, the initial in-rush current could be over 2 Amps if unlimited. If the HVD10x current limit is set
to 350 mA, this current will warm up the filament during the initial lamp turn-on, and the final current will be below
the current limit. If the CQ output current is at the limit for longer than tSC, the SC output will be active. The local
controller can disable the CQ driver if the high current is not expected, or can re-check the SC output after 100
ms if the load is known to be incandescent.
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System Examples (continued)
10.3.2 Driver for Inductive Loads
The following circuit shows the SN65HVD101 driving an inductive load. In this case three TVS diodes are
necessary to protect L+ to ground and CQ to Ground and to L+.
5 x 10kŸ
0.1µF
RPU
Vcc
MCU
Vcc IN Vcc OUT Vcc SET
L+
WAKE
IRQ
GPIO1
PWR _OK
GPIO2
CUR _OK
GPIO3
TEMP _OK
GND
RXD
RX
TXD
TX
EN
RTS
10kŸ
1µ F
24V
TVS3
SN65HVD101
CQ
TVS2
TVS1
ILIM ADJ
GND
0V
L-
RPD
RSET
Copyright © 2017, Texas Instruments Incorporated
Figure 18. SN65HVD101 Driving Inductive Relay Load
When the high-side switch in the transceiver turns on, TVS1 might conduct when the voltage across the inductive
load rises above the TVS breakdown threshold. This might not be desirable but, due to VL = L × di/dt, can
happen if the load inductance is sufficiently high.
When the transceiver turns off, the voltage across the inductance changes polarity to maintain current flow in the
same direction. Again, TVS1 might conduct if the peak voltage across the inductor exceeds the TVS breakdown
threshold during turn-off.
The main issue however is the voltage difference between the positive supply (L+) and the data line (CQ).
Without TVS3 this difference could rise to twice the supply level. At the much lower TVS about lower TVS
breakdown threshold however, TVS3 conducts and the voltage difference is limited to the TVS clamping voltage.
11 Power Supply Recommendations
The SN65HVD101 and SN65HVD102 transceivers are designed to operate from a 24 V nominal supply at L+,
which can vary by +6 V and –15 V from the nominal value to remain within the device recommended supply
voltage range of 9 V to 30 V. This supply should be buffered with at least a 1 µF/60V ceramic capacitor placed
close to the device pin.
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12 Layout
12.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
•
Use a 4-layer board with Layer 1 (top layer) for control signals, Layer 2 as Power Ground Layer for L– and
GND), Layer 3 for the 24 V supply plane (L+), and Layer 4 for the regulated output supply (VCC_OUT).
Use entire planes for L+, VCC_OUT, and L– and GND to assure minimum inductance during fast load or
transient current changes.
The L+ terminal must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended
capacitor value is 1 μF to 4.7 μF. The capacitor must have a voltage rating of 50 V minimum and a X5R or
X7R dielectric.
The optimum placement is closest to the transceiver’s L+ and L– terminals to reduce supply drops during
large supply current loads. See Figure 19 for a PCB layout example
Place TVS diode close to the connector to prevent the transient energy from entering the circuitry.
Use two vias when connecting TVS diodes or capacitors to the L– and L+ planes to maintain low inductance
during fast load or transient current changes.
Connect all open-drain control outputs and the receiver output via 10 kΩ pull-up resistors to the VCC_OUT
plane to provide a defined voltage potential to the system controller inputs when the outputs are highimpedance.
Connect the transceiver enable pin via a 10 kΩ pull-down resistor to ground, to assure the driver output is
disabled during power-up.
Connect VCC_SET directly to ground to make VCC_OUT = 3.3 V, or leave it open to make VCC_OUT = 5 V.
Connect VCC_IN directly to VCC_OUT to assure proper voltage regulation.
Buffer the regulated output voltage at VCC_OUT to ground with a low-ESR, 3.3μF, ceramic bypass-capacitor.
The capacitor should have a voltage rating of 10 V minimum and a X5R or X7R dielectric.
12.2 Layout Example
VIA to Layer 2: Power Ground Plane (L- and GND)
VIA to Layer 3: 24V Supply Plane (L+)
VIA to Layer 4: Regulated Supply Plane (Vcc_OUT)
L+
CUR _OK
TVS2
nc
CQ
L-
GND
WAKE
RX
L+
Local
Controller
LTVS3
Vcc_OUT
TVS1
nc
TX
CQ
1µF/
50V
Vcc_IN
GND
TEMP _OK
Pull-up/down
Resistors
ILIM_ADJ
PWR _OK
nc
GND
10V
Vcc_SET
EN
3.3µF/
4kŸ
Exposed Thermal
Pad Area
Use 2 Vias for TVS
and Capacitors
RSET
Figure 19. Layout Example
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13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 12. Related Links
PARTS
PRODUCT FOLDER
ODDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN65HVD101
Click here
Click here
Click here
Click here
Click here
SN65HVD102
Click here
Click here
Click here
Click here
Click here
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: SN65HVD101 SN65HVD102
PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN65HVD101RGBR
ACTIVE
VQFN
RGB
20
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
HVD101
SN65HVD101RGBT
ACTIVE
VQFN
RGB
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
HVD101
SN65HVD102RGBR
ACTIVE
VQFN
RGB
20
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
HVD102
SN65HVD102RGBT
ACTIVE
VQFN
RGB
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
HVD102
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-May-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN65HVD101RGBR
VQFN
RGB
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
SN65HVD101RGBT
VQFN
RGB
20
250
180.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
SN65HVD102RGBR
VQFN
RGB
20
1000
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
SN65HVD102RGBT
VQFN
RGB
20
250
180.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-May-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD101RGBR
VQFN
RGB
20
1000
367.0
367.0
35.0
SN65HVD101RGBT
VQFN
RGB
20
250
210.0
185.0
35.0
SN65HVD102RGBR
VQFN
RGB
20
1000
367.0
367.0
35.0
SN65HVD102RGBT
VQFN
RGB
20
250
210.0
185.0
35.0
Pack Materials-Page 2
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