Texas Instruments | TPD4E1U06 Quad-Channel, High-Speed ESD Protection Device (Rev. D) | Datasheet | Texas Instruments TPD4E1U06 Quad-Channel, High-Speed ESD Protection Device (Rev. D) Datasheet

Texas Instruments TPD4E1U06 Quad-Channel, High-Speed ESD Protection Device (Rev. D) Datasheet
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TPD4E1U06
SLVSBQ9D – DECEMBER 2012 – REVISED APRIL 2017
TPD4E1U06 Quad-Channel, High-Speed ESD Protection Device
1 Features
3 Description
•
The TPD4E1U06 is a quad-channel unidirectional
Transient Voltage Suppressor (TVS) based
Electrostatic Discharge (ESD) protection diode with
ultra low capacitance. This device can dissipate ESD
strikes above the maximum level specified by the IEC
61000-4-2 international standard. Its 0.8-pF line
capacitance makes it suitable for a wide range of
applications. Typical application areas include HDMI,
USB2.0, MHL, and DisplayPort.
1
•
•
•
•
•
•
•
•
IEC 61000-4-2 Level 4 ESD Protection
– ±15-kV Contact Discharge
– ±15-kV Air-Gap Discharge
IEC 61000-4-4 EFT Protection
– 80 A (5/50 ns)
IEC 61000-4-5 Surge Protection
– 3 A (8/20 μs)
IO Capacitance 0.8 pF (Typical)
DC Breakdown Voltage 6.5 V (Minimum)
Ultra Low Leakage Current 10 nA (Maximum)
Low ESD Clamping Voltage
Industrial Temperature Range: –40°C to +125°C
Small, Easy-to-Route DCK, and DBV Package
Device Information(1)
PACKAGE
BODY SIZE (NOM)
TPD4E1U06DCK
PART NUMBER
SC70
2.00 mm × 1.25 mm
TPD4E1U06DBV
SOT-23
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
•
•
•
USB 2.0
Ethernet
HDMI Control Lines
MIPI Bus
LVDS
SATA
Simplified Schematic
Circuit Schematic Diagram
D+
D1+
DGND
Vbus
USB
Connector
D1-
D2+
D2-
USB
Transceiver/Hub
USB
Connector
Vbus
D+
GND
D1
GND
3
TPD4E1U06
4
6
2
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD4E1U06
SLVSBQ9D – DECEMBER 2012 – REVISED APRIL 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
ESD Ratings—IEC Specification ..............................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
9 Power Supply Recommendations...................... 12
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................. 12
10.2 Layout Example .................................................... 12
11 Device and Documentation Support ................. 13
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13
12 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2014) to Revision D
Page
•
Updated DCK and DBV Pinout image ................................................................................................................................... 3
•
Added 61000-4-5 spec to Absolute Maximum Ratings table ................................................................................................. 4
•
Added IEC 61000-4-5 Surge Protection section ................................................................................................................... 8
•
Added IEC 61000-4-4 EFT Protection section ....................................................................................................................... 8
Changes from Revision B (February 2013) to Revision C
•
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Revision A (December 2012) to Revision B
•
2
Page
Page
Added CCROSS data for DBV package..................................................................................................................................... 5
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5 Pin Configuration and Functions
DCK Package
6-Pin SC70
Top View
DBV Package
6-Pin SOT-23
Top View
D1+ 1
6
GND 2
5
D2+ 3
4
D1-
D1+
1
6
D1-
GND
2
5
NC
D2+
3
4
D2-
NC
D2-
Pin Functions
PIN
NAME
NO.
I/O
D1+
1
I/O
D1–
6
I/O
D2–
4
I/O
D2+
3
I/O
GND
2
GND
NC
5
I/O
DESCRIPTION
ESD protected channel. Connect to data line as close
to the connector as possible
Ground. Connect to ground
No connect. Can be left floating, grounded, or
connected to VCC
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
80
A
IEC 61000-4-4 EFT protection (5/50 ns)
IPP
IEC 61000-4-5 surge protection (8/20 μs) peak pulse current
3
A
PPP
IEC 61000-4-5 surge protection (8/20 μs) peak pulse power
45
W
Tstg
(1)
Operating temperature
–40
125
°C
Storage temperature
–65
115
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
±4000
Charged device model (CDM), per JEDEC specification JESD22C101, all pins (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings—IEC Specification
VALUE
V(ESD)
Electrostatic discharge
IEC 61000-4-2 contact ESD
±15000
IEC 61000-4-2 air-gap ESD
±15000
UNIT
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIO
Input pin voltage
TA
Operating free-air temperature
MIN
MAX
0
5.5
UNIT
V
–40
125
°C
6.5 Thermal Information
TPD4E1U06
THERMAL METRIC (1)
DBV (SOT-23)
DCK (SC-70)
6 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
224.3
274.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
166.1
113.8
°C/W
RθJB
Junction-to-board thermal resistance
68.4
76.7
°C/W
ψJT
Junction-to-top characterization parameter
57.3
3.6
°C/W
ψJB
Junction-to-board characterization parameter
67.9
75.9
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VRWM
VCLAMP
TEST CONDITIONS
MIN
MAX
Clamp voltage with ESD
strike
IPP = 1 A, tp = 8/20 μs, from I/O to GND (1)
11
V
IPP = 3 A, tp = 8/20 μs, from I/O to GND (1)
15
V
Pin x to GND pin (2)
1.0
GND to pin x
0.6
Dynamic resistance
CL
Line capacitance
5.5
UNIT
IIO = 10 µA
RDYN
f = 1 MHz, VBIAS = 2.5 V, 25°C
V
Ω
0.8
1
DCK package
0.006
0.015
DBV package
0.01
0.025
0.025
0.07
pF
8.5
V
10
nA
CCROSS
Channel to channel input
capacitance
Pin 2 = 0 V, f = 1 MHz, VBIAS = 2.5 V, between
channel pins
∆CIO-TO-GND
Variation of channel input
capacitance
Pin 2 = 0 V , f = 1 MHz, VBIAS = 2.5 V, channel_x pin to ground – channel_y
pin to ground
VBR
Break-down voltage, IO to
GND
IIO = 1 mA
ILEAK
Leakage current
VIO = 2.5 V
(1)
(2)
TYP
Reverse stand-off voltage
6.5
1
pF
pF
Non-repetitive current pulse 8/20 µs exponentially decaying waveform according to IEC61000-4-5.
Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A.
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30
30
27
27
24
24
21
21
Current (A)
Current (A)
6.7 Typical Characteristics
18
15
12
18
15
12
9
9
6
6
3
3
0
0
0
5
10
15
20
25
30
35
40
45
Voltage (V)
50
0
5
10
180
60
150
30
120
0
Amplitude (V)
Amplitude (V)
25
30
35
40
45
50
C002
Figure 2. TLP, GND to Data
90
60
30
±30
±60
±90
0
±120
±30
±150
±60
±180
±20
0
20
40
60
80 100 120 140 160 180 200 220
Time (ns)
0
±20
20
40
60
80 100 120 140 160 180 200 220
Time (ns)
C003
Figure 3. IEC 61000-4-2 Clamping Voltage, 8-kV Contact
C004
Figure 4. IEC 61000-4-2 Clamping Voltage, –8-kV Contact
1.0
500
TA = 25ƒC
0.8
VIN = 2.5 V
450
0.6
400
0.4
350
Current (pA)
Current (mA)
20
Voltage (V)
Figure 1. TLP, Data to GND
0.2
0.0
±0.2
300
250
200
±0.4
150
±0.6
100
±0.8
50
±1.0
0
±2
±1
0
1
2
3
4
5
6
Voltage (V)
7
8
9
10
±55
C005
Figure 5. Diode Curve
6
15
C001
±35
±15
5
25
45
65
85
Temperature (ƒC)
105
125
C006
Figure 6. ILEAK vs Temperature
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1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
3.5
50
Current
Power
f = 1 MHz
3.0
45
40
2.5
35
30
2.0
25
1.5
20
Power (W)
Current (A)
Capacitance (pF)
Typical Characteristics (continued)
15
1.0
10
0.5
5
0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VBIAS (V)
4.5
5.0
±5
0
C007
Figure 7. Capacitance Across VBIAS
5
10
15
20
25
30
35
40
45
50
Time ( s)
C008
Figure 8. Surge Curve (tp = 8/20 μs), Pin IO to GND
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7 Detailed Description
7.1 Overview
The TPD4E1U06 is a quad channel unidirectional TVS ESD protection diode with ultra low capacitance. This
device can dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 international
standard. Typical application areas include HDMI, USB2.0, MHL, and DisplayPort. Its 0.8-pF line capacitance
makes it suitable for a wide range of applications.
7.2 Functional Block Diagram
D1+
D1-
D2+
D2-
GND
Figure 9. Circuit Schematic Diagram
7.3 Feature Description
7.3.1 IEC 61000-4-2 Level 4 ESD Protection
The I/O pins can withstand ESD events up to ±15-kV contact and air. An ESD/surge clamp diverts the current to
ground.
7.3.2 IEC 61000-4-5 Surge Protection
The IO pins can withstand surge events up to 3 A and 45 W (8/20-μs waveform). An ESD-surge clamp diverts
this current to ground.
7.3.3 IEC 61000-4-4 EFT Protection
The IO pins can withstand an electrical fast transient burst of up to 80 A (5/50-ns waveform, 4 kV with 50-Ω
impedance). An ESD-surge clamp diverts the current to ground.
7.3.4 IO Capacitance
The capacitance between each I/O pin to ground is 0.8 pF.
7.3.5 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is a minimum of 6.5 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of 5.5 V.
7.3.6 Ultra Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (Maximum) with a bias of 2.5 V.
7.3.7 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 11 V (IPP = 1 A).
7.3.8 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
8
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Feature Description (continued)
7.3.9 Small, Easy-to-Route Packages
The layout of this device makes it simple to add protection to the design. Industry standard packages allow for
easy additions to the board and easy layout.
7.4 Device Functional Modes
The TPD4E1U06 is a passive integrated circuit that triggers when voltages are above VBR or below the forward
diode drop. During ESD events, voltages as high as ±15 kV can be directed to ground via the internal diode
network. Once the voltages on the protected line fall below the trigger levels of TPD4E1U06 (usually within 10s
of nano-seconds) the device reverts to passive.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPD4E1U06 is a TVS diode array which is typically used to provide a path to ground for dissipating ESD
events on hi-speed signal lines between a human interface connector and a system. As the current from ESD
passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to
the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected
IC.
8.2 Typical Application
For this design example, one TPD4E1U06 device is being used in a dual USB 2.0 application. This provides a
complete port protection scheme.
D+
DUSB
Transceiver/Hub
USB
Connector
Vbus
GND
USB
Connector
Vbus
D+
D1
GND
3
TPD4E1U06
4
6
2
GND
Figure 10. Dual USB 2.0 Application
10
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Typical Application (continued)
8.2.1 Design Requirements
Given the USB 2.0 application, the parameters in Table 1 are known.
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
Signal range on pins 1, 3, 4, or 6
0 V to 5 V
Operating frequency
240 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range on Pins 1, 3, 4, or 6
The TPD4E1U06 has 4 identical protection channels for signal lines. The symmetry of the device provides
flexibility when selecting which of the 4 I/O channels protect which signal lines. Any I/O supports a signal range
of 0 to 5.5 V.
8.2.2.2 Operating Frequency
The TPD4E1U06 has a capacitance of 0.8 pF (typical), supporting USB 2.0 data rates.
8.2.3 Application Curve
Insertion Loss (dB)
3
0
±3
±6
±9
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
Frequency (Hz)
1.E+10
C009
Figure 11. Insertion Loss Graph
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9 Power Supply Recommendations
This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended
I/O specification (0 V to 5.5 V) to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
Figure 12. PCB Layout Recommendation
12
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Reading and Understanding an ESD Protection Datasheet
• ESD Layout Guide
• TTPD4E1U06DCK EVM User's Guide
• TPD4E1U06DBV EVM Userf's Guide
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com. In the upper right-hand corner, click the Alert me button. This registers you to receive a weekly
digest of product information that has changed (if any). For change details, check the revision history of any
revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPD4E1U06DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
NG4
TPD4E1U06DCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(BP6, BP8, BPI)
(BPP, BPP, BPS)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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6-Sep-2017
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-May-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TPD4E1U06DBVR
SOT-23
DBV
6
3000
178.0
9.0
TPD4E1U06DCKR
SC70
DCK
6
3000
178.0
TPD4E1U06DCKR
SC70
DCK
6
3000
178.0
3.23
3.17
1.37
4.0
8.0
Q3
9.2
2.4
2.4
1.22
4.0
8.0
Q3
9.0
2.4
2.5
1.2
4.0
8.0
Q3
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
11-May-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD4E1U06DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
TPD4E1U06DCKR
SC70
DCK
6
3000
180.0
180.0
18.0
TPD4E1U06DCKR
SC70
DCK
6
3000
180.0
180.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
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EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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