Texas Instruments | TCA6507 Low-Voltage 7-Bit I2C and SMBus LED Driver With Intensity Control and Shutdown (Rev. D) | Datasheet | Texas Instruments TCA6507 Low-Voltage 7-Bit I2C and SMBus LED Driver With Intensity Control and Shutdown (Rev. D) Datasheet

Texas Instruments TCA6507 Low-Voltage 7-Bit I2C and SMBus LED Driver With Intensity Control and Shutdown (Rev. D) Datasheet
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TCA6507
SCPS164D – MAY 2007 – REVISED FEBRUARY 2017
TCA6507 Low-Voltage 7-Bit I2C and SMBus LED Driver
With Intensity Control and Shutdown
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
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Seven LED Driver Outputs: ON, OFF, Blinking,
Fading at Programmable Rates
Open-Drain Outputs Directly Drive LEDs to
40-mA Maximum
Two Independent Banks of LED Drivers
Widely Programmable Blink Rates, Fade-ON and
Fade-OFF Rates and Maximum Intensity
Outputs Not Used as LED Drivers Can Be Used
as Regular General-Purpose Open-Drain Outputs
16 Steps of Maximum Intensity Control from
Fully-OFF to Fully-ON States
Smooth Perceived Transitions for Fade-ON and
Fade-OFF
Operating Power-Supply Voltage Range of
1.65 V to 3.6 V
5.5-V Tolerant Open-Drain Outputs
Low Standby Current With Shutdown Capability
for Additional Power Savings
Programmed Through I2C Bus Interface Logic
Compatible With SMBus
No Glitch on Power Up
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Mobile Phones
Desktop and Laptop Computers
Human Machine Interface
3 Description
This 7-bit LED dimmer for the two-line bidirectional
bus (I2C) is designed to control (or dim) LEDs through
the I2C interface. Without this device, the
microcontroller must be actively involved in turning on
and off the LEDs (per the required dimming rate),
which uses valuable processor time. The TCA6507
alleviates this issue by limiting the number of
operations required by the processor in blinking LEDs
and helps to create a more efficient system. The
TCA6507 handles all pulse width modulation (PWM)
logic, allowing the processor to use its cycles for
more important tasks.
Device Information(1)
PART NUMBER
TCA6507
PACKAGE
BODY SIZE (NOM)
TSSOP (14)
5.00 mm × 4.40 mm
BGA MICROSTAR
JUNIOR (12)
2.00 mm × 2.50 mm
X2QFN (12)
2.00 mm × 1.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VCC
I2C or SMBus Master
(e.g. Processor)
SDA
P0
SCL
P1
EN
P2
P3
P4
TCA6507
P5
P6
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA6507
SCPS164D – MAY 2007 – REVISED FEBRUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
5
5
5
6
6
7
8
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Interface Timing Requirements...........................
Oscillator Timing Requirements................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 11
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 15
8.5 Programming .......................................................... 16
8.6 Register Maps ......................................................... 23
9
Application and Implementation ........................ 30
9.1 Application Information............................................ 30
9.2 Typical Application ................................................. 30
9.3 System Example ..................................................... 33
10 Power Supply Recommendations ..................... 34
10.1 Power-On Reset Requirements ........................... 34
11 Layout................................................................... 35
11.1 Layout Guidelines ................................................. 35
11.2 Layout Example ................................................... 35
12 Device and Documentation Support ................. 36
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
36
36
13 Mechanical, Packaging, and Orderable
Information ........................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (January 2016) to Revision D
Page
•
Changed fINT value From: MIN = 23 and MAX = 43 To: MIN = 28 and MAX = 58 in the Electrical Characteristics table ..... 6
•
Changed VPOR values From: TYP = 1.4 To: TYP = 1.1 MAX = 1.4 in the Electrical Characteristics table ............................ 6
•
Changed Operating ICC MAX value From: 25 To: 40 in the Electrical Characteristics table .................................................. 6
•
Changed Ci, Cio, Co TYP and MAX values in the Electrical Characteristics table.................................................................. 6
•
Changed The I2C Interface Timing Requirements table......................................................................................................... 7
•
Changed TheOscillator Timing Requirements table............................................................................................................... 8
•
Changed TheSwitching Characteristics table......................................................................................................................... 8
•
Updated Typical Characteristic Curves .................................................................................................................................. 9
•
Changed Table 18, Brightness Register Values .................................................................................................................. 27
•
Changed Table 26 ............................................................................................................................................................... 34
Changes from Revision B (November 2007) to Revision C
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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SCPS164D – MAY 2007 – REVISED FEBRUARY 2017
5 Pin Configuration and Functions
PW Package
14-Pin TSSOP
Top View
VCC
SCL
SDA
EN
GND
NC
NC
RUE Package
12-Pin X2QFN
Top View
P6
P6
P5
P4
P3
P2
P1
P0
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
1
12 11 P5
SCL
2
10 P4
SDA
3
9
P3
EN
4
8
P2
5
7
P1
GND
6
P0
Pin Functions –TSSOP and X2QFN
PIN
NAME
NO.
I/O
DESCRIPTION
PW
RUE
EN
4
4
I
GND
5
5
—
Ground
P0
8
6
O
P-port output 0. Open-drain design structure
P1
9
7
O
P-port output 1. Open-drain design structure
P2
10
8
O
P-port output 2. Open-drain design structure
P3
11
9
O
P-port output 3. Open-drain design structure
P4
12
10
O
P-port output 4. Open-drain design structure
P5
13
11
O
P-port output 5. Open-drain design structure
P6
14
12
O
P-port output 6. Open-drain design structure
SDA
3
3
I/O
Serial data bus. Connect to VCC through a pull-up resistor
SCL
2
2
I
Serial clock bus. Connect to VCC through a pull-up resistor
VCC
1
1
—
Enable input. If set to low, it puts the TCA6507 in shutdown
mode and resets the internal registers and I2C/SMBus state
machine to their default states
Supply voltage of I2C registers, oscillator, and control logic.
Connect directly to VCC of the external I2C master. Provides
voltage-level translation
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SCPS164D – MAY 2007 – REVISED FEBRUARY 2017
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ZXU Package
12-Pin BGA MICROSTAR JUNIOR
Top View
C
B
A
1
2
3
4
Table 1. ZXU Package Terminal Assignments
C
B
A
1
P1
P2
GND
2
P3
EN
SDA
3
P4
P0
SCL
4
P5
P6
VCC
Pin Functions –BGA Microstar Junior
PIN
I/O
DESCRIPTION
NO.
NAME
A1
GND
—
Ground
A2
SDA
I/O
Serial data bus. Connect to VCC through a pullup resistor
A3
SCL
I
Serial clock bus. Connect to VCC through a pullup resistor
A4
VCC
—
Supply voltage of I2C registers, oscillator, and control logic. Connect
directly to VCC of the external I2C master. Provides voltage-level
translation
B1
P2
O
P-port output 2. Open-drain design structure
B2
EN
I
Enable input. If set to low, it puts the TCA6507 in shutdown mode and
resets the internal registers and I2C/SMBus state machine to their default
states
B3
P0
O
P-port output 0. Open-drain design structure
B4
P6
O
P-port output 6. Open-drain design structure
C1
P1
O
P-port output 1. Open-drain design structure
C2
P3
O
P-port output 3. Open-drain design structure
C3
P4
O
P-port output 4. Open-drain design structure
C4
P5
O
P-port output 5. Open-drain design structure
4
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SCPS164D – MAY 2007 – REVISED FEBRUARY 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
4.6
V
(2)
–0.5
6.5
V
VI
Input voltage
VO
Output voltage (2)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0 or VO > VCC
IOL
Continuous output low current
ICC
Tstg
(1)
(2)
VO = 0 to VCC
6.5
V
SCL, EN
±20
mA
P port, SDA
±20
mA
P port
50
SDA
25
Continuous current through GND
250
Continuous current through VCC
20
Storage temperature
–65
mA
mA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage of I2C registers, oscillator, and control logic
VIH
High-level input voltage
SCL, SDA, EN
VIL
Low-level input voltage
SCL, SDA, EN
VO
Output voltage
IOL
Low-level output current
TA
Operating free-air temperature
(1)
1.65 V ≤ VCC ≤ 1.95 V
MIN
MAX
1.65
3.6
UNIT
V
1.3
3.6
0.7 × VCC
3.6
1.65 V ≤ VCC ≤ 1.95 V
–0.5
0.3
1.96 V ≤ VCC ≤ 3.6 V
–0.5
0.3 × VCC
0
5.5
V
40
mA
85
°C
1.96 V ≤ VCC ≤ 3.6 V
(1)
–40
V
V
The total current sourced by the P port must be limited to 200 mA.
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6.4 Thermal Information
TCA6507
THERMAL METRIC (1)
PW (TSSOP)
ZXU (BGA
MICROSTAR
JUNIOR)
RUE (X2QFN)
12 PINS
UNIT
14 PINS
12 PINS
RθJA
Junction-to-ambient thermal resistance
127.2
155.2
181
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
55.8
99.4
80.4
°C/W
RθJB
Junction-to-board thermal resistance
38.9
91.5
95.3
°C/W
ψJT
Junction-to-top characterization parameter
9.3
6.8
3.5
°C/W
ψJB
Junction-to-board characterization parameter
68.3
92.1
95.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
GND = 0 V, TA = –40°C to +85°C
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP (1)
MAX
UNIT
32
58
kHz
1.1
1.4
0.2
0.6
fINT
Intensity control clock
frequency
Operating mode
1.65 V to 3.6 V
28
VIK
Input diode clamp voltage
II = –18 mA
1.65 V to 3.6 V
–1.2
VPOR
Power-on reset voltage
VI = VCC or GND, IO = 0
1.65 V to 3.6 V
VOL
SDA
IOL = 6 mA
1.65 V to 3.6 V
SDA
IOL
II
P port (2)
V
1.65 V to 3.6 V
3
13.2
VOL = 0.5 V
1.65 V
25
59.7
VOL = 0.6 V
1.8 V to 3.6 V
40
68
V
V
mA
mA
SCL, SDA, EN
VI = VCC or GND, VCC ≥ 1.65 V
1.65 V to 3.6 V
1.65 V to 1.95 V
2
12
Standby current
EN disabled, P port idle,
Intensity control disabled,
SCL = VCC, SDA = VCC, IO = 0,
fSCL = 0
1.96 V to 3.6 V
3
15
P port running,
Intensity control enabled,
SCL = VCC, SDA = VCC, IO = 0,
fSCL = 0
1.65 V to 1.95 V
9.7
17
1.96 V to 3.6 V
10.4
20
P port running,
Intensity control enabled,
SDA = VCC, IO = 0, fSCL = 400 kHz,
tr = 300 ns
1.65 V to 1.95 V
10.2
18
1.96 V to 3.6 V
11.4
40
1.65 V to 3.6 V
7
10
pF
ICC
Operating mode
±0.1
μA
μA
μA
Ci
SCL
Cio
SDA
VIO = VCC or GND
1.65 V to 3.6 V
8
11
pF
Co
P port
VO = VCC or GND
1.65 V to 3.6 V
7
10
pF
(1)
(2)
6
All typical values are at TA = 25°C.
The total current sourced by the P port must be limited to 200 mA.
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6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 8)
MIN
MAX
UNIT
100
kHz
STANDARD MODE
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
μs
tscl
I2C clock low time
4.7
μs
2
tsp
I C spike time
tsds
I2C serial-data setup time
tsdh
I2C serial-data hold time
50
ns
250
ns
0
ns
2
ticr
I C input rise time
1000
ns
ticf
I2C input fall time
300
ns
tocf
I2C output fall time
300
ns
10-pF to 400-pF bus
2
tbuf
I C bus free time between STOP and START conditions
4.7
μs
tsts
I2C START or repeated START condition setup
4.7
μs
tsth
I2C START or repeated START condition hold
4
μs
tsps
I2C STOP condition setup
4
μs
tvd(data)
Valid-data time
SCL low to SDA output valid
1
μs
tvd(ack)
Valid-data time of ACK condition
ACK signal from SCL low to SDA (out)
low
1
μs
Cb
I2C bus capacitive load
0
400
pF
0
400
kHz
FAST MODE
fscl
I2C clock frequency
tsch
I2C clock high time
0.6
2
tscl
I C clock low time
tsp
I2C spike time
tsds
I2C serial-data setup time
1.3
I C serial-data hold time
ticr
I2C input rise time
μs
50
100
2
tsdh
μs
ns
0
ticf
I2C input fall time
tocf
I2C output fall time
tbuf
I2C bus free time between STOP and START conditions
10-pF to 400-pF bus
2
ns
ns
20
300
ns
20 × (VCC /
5.5 V)
300
ns
20 × (VCC /
5.5 V)
300
ns
1.3
μs
tsts
I C START or repeated START condition setup
0.6
μs
tsth
I2C START or repeated START condition hold
0.6
μs
tsps
I2C STOP condition setup
0.6
μs
tvd(data)
Valid-data time
SCL low to SDA output valid
1
μs
tvd(ack)
Valid-data time of ACK condition
ACK signal from SCL low to SDA (out)
low
1
μs
Cb
I2C bus capacitive load
400
pF
0
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6.7 Oscillator Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
STANDARD and FAST MODE
tOSC
Oscillator start-up time from power-down or shutdown mode to fully on at 32 kHz
5
ms
6.8 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
SCL
EN (low)
MIN
MAX
UNIT
P port
400
ns
P port (high)
70
μs
STANDARD and FAST MODE
tpv
Output data valid
(in general-purpose output mode)
tps
Shutdown data valid
tw
EN pulse duration
8
60
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6.9 Typical Characteristics
12
1.8 V
2.5 V
3.6 V
4
ICC - Supply Current (µA)
Istby - Standby Current (µA)
5
3
2
1
0
-40
-15
10
35
TA - Temperature (°C)
60
10
8
6
1.8 V
2.5 V
3.6 V
4
-40
85
EN is Low (PWM Disabled)
fSCL = 0
Figure 1. Standby Current vs Temperature
60
85
D002
fSCL = 0
Figure 2. Supply Current vs Temperature
100
1.8 V
2.5 V
3.6 V
25
VOL - Output Low Voltage (mV)
ICC - Supply Current (µA)
10
35
TA - Temperature (°C)
EN is Low (PWM Enabled)
30
20
15
10
5
-40
-15
10
35
TA - Temperature (°C)
EN is High (PWM Enabled)
60
1.8 V
2.5 V
3.6 V
90
80 IL = 10 mA
70
60
50
40
-40
85
-15
D003
10
35
TA - Temperature (°C)
60
85
D004
fSCL = 400 kHz
Figure 3. Supply Current vs Temperature
Figure 4. Port Output Low Voltage vs Temperature
131
50
1.8 V
2.5 V
3.6 V
40
fPWM - PWM Frequency (Hz)
VOL - Output Low Voltage (mV)
-15
D001
IL = 5 mA
30
20
-40
-15
10
35
TA - Temperature (°C)
60
85
128
1.8 V
2.5 V
3.6 V
125
122
119
116
-40
D005
Figure 5. Port Output Low Voltage vs Temperature
-15
10
35
TA - Temperature (°C)
60
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D006
Figure 6. PWM Frequency vs Temperature
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Typical Characteristics (continued)
VOL - Low-Level Output Voltage (mV)
400
1.8 V
2.5 V
3.6 V
350
300
250
200
150
100
50
0
0
5
10
15
20
25
30
35
ISINK - Sink Current (mA)
40
45
50
D007
Figure 7. Output Low Voltage vs Sink Current
10
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SCPS164D – MAY 2007 – REVISED FEBRUARY 2017
7 Parameter Measurement Information
VCC
RL = 1 kW
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition
(P)
Start
Condition
(S)
Address
Bit 7
(MSB)
Address
Bit 6
Address
Bit 1
tscl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 0
(LSB)
Data
Bit 7
(MSB)
Stop
Condition
(P)
tsch
0.7 ´ VCC
SCL
0.3 ´ VCC
ticr
tPHL
ticf
tbuf
tsts
tsp
tPLH
0.7 ´ VCC
SDA
0.3 ´ VCC
ticr
ticf
tsth
tsdh
tsds
tsps
Repeat Start
Condition
Start or
Repeat Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2
Command
3
P-port data
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A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 8. I2C Interface Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
Pn
500 W
DUT
2 ´ VCC
CL = 50 pF
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
0.7 ´ VCC
SCL
P0
A
P3
0.3 ´ VCC
Slave
ACK
SDA
tpv
(see Note B)
Pn
Last Stable Bit
Unstable
Data
WRITE MODE (R/W = 0)
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A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C.
The outputs are measured one at a time, with one transition per measurement.
D.
All parameters and waveforms are not applicable to all devices.
Figure 9. P-Port Load Circuit and Voltage Waveforms
12
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8 Detailed Description
8.1 Overview
The TCA6507 can be used for driving LEDs and for general-purpose parallel output expansion. The TCA6507
has three select registers (Select0, Select1, and Select2), which can be used to configure each LED output into
one of seven different operating modes. At power on, the outputs are in high impedance.
When used to drive LEDs, the seven outputs can be configured into two banks of outputs (BANK0 and BANK1).
Each bank of outputs can be independently controlled for dimming rate and intensity through the I2C bus. The
dimming and blink rates are fully programmable. The intensity of each bank of LEDs is controlled by dynamically
varying the duty cycle of the signal, which has a period of approximately 8 ms and a pulse rate of 125 times per
second, driving the outputs. The TCA6507 has two independent dimming-blinking modules—PWM0 and
PWM1—driven by a single internal oscillator that supports these features. PWM0 determines the characteristics
of BANK0, and PWM1 determines the characteristics of BANK1.
The TCA6507 has a master intensity level known as the ambient light detection (ALD) value. The associated
pulse width modulation (PWM) signal for this value is PWMALD. The TCA6507 can be programmed such that
PWMALD overrides PWM0 or PWM1, so selected LEDs are on steadily at the master intensity level. Further, the
TCA6507 can be programmed such that the ALD value can override the maximum intensity values for PWM0
and PWM1. Thus, the ALD value can control the brightness of all LEDs, whether they are on steadily, or
controlled by one of the dimming modules. The ALD value is stored in the lower four bits of the
One-Shot / Master Intensity register.
When the I2C bus is idle, and intensity control is not used, the TCA6507 can be put into shutdown mode by
setting the enable (EN) pin low. This mode provides additional power savings, as it is a low-power mode where
the LEDs are off. A low signal on the EN pin also resets the registers and I2C/SMBus state machine in the
TCA6507 to their default state.
An initial setup command must be sent from the I2C master to the TCA6507 to program the dimming rate and
intensity (and intensity ramp if needed) for each bank of outputs. From then on, only one command from the bus
master is required to turn each individual output ON, OFF, or to cycle at the programmed dimming rate. The
default value for all time parameters is 256 ms, so the default blink rate is approximately one per second.
The TCA6507 is optimized for 1.65 V to 3.6 V on the SDA/SCL side, but the LEDs can be driven by any voltage
up to 5.5 V. This allows the TCA6507 to interface with next-generation microprocessors and microcontrollers,
where supply levels are dropping down to conserve power.
This LED dimmer supports hot insertion.
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8.2 Functional Block Diagram
SCL
SDA
Glitch
Filters
2
I C Bus
Control
Select2
Register
Select1
Register
Select0
Register
Oscillator
EN
Shut
Down
VCC
Power-On
Reset
LED
Intensity
Control
Fade/
Intensity
Control
Registers
PWMALD
PWM0
PWM1
Logic 0
P6–P0
BRIGHT_F0
BRIGHT_F1
Logic 1
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Figure 10. TCA6507 Functional Block Diagram
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Functional Block Diagram (continued)
Select2
Register
D
Select2
Pulse
Data From
Shift Register
Select1
Register
D
Select1
Pulse
Q
FF
CK Q
Q
FF
CK Q
Select0
Register
D
Select0
Pulse
Q
FF
CK Q
Logic 1
A
BRIGHT_F0
B
BRIGHT_F1
C
P6–P0
A
ESD Protection
Diode
Logic 0
A
PWMALD
B
PWM0
C
PWM1
D
B
GND
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Figure 11. Output Port Simplified Schematic
8.3 Feature Description
8.3.1 Seven LED Driver Outputs
The TCA6507 features 7 outputs that can be controlled with multiple modes: ON, OFF, blinking (one of the two
separate banks), and fading at a programmable rate (one of the two separate banks).
8.3.2 Open-Drain Outputs Directly Drive LEDs
The TCA6507 has open-drain outputs (see Figure 11) that are capable of sinking current up to 40 mA for LEDs.
8.3.3 Widely Programmable
The TCA6507 has two separate banks, which can be programmed to do a wide variety of blink rates, fade-ON
and fade-OFF rates, as well as maximum intensity (brightness).
8.4 Device Functional Modes
8.4.1 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA6507 in a reset condition until
VCC has reached VPOR. At that point, the reset condition is released, and the TCA6507 registers and I2C/SMBus
state machine initialize to their default states.
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Device Functional Modes (continued)
After the initial power-up phase, VCC must be lowered to below 0.2 V, and then back up to the operating voltage
(VCC) for a power-reset cycle.
8.4.2 Enable and Reset
If the enable (EN) input is set to low, the TCA6507 is put in the standby or shutdown mode. In this mode, the
oscillator is turned off, the registers are returned to their default state, and the I2C/SMBus state machine is
initialized. This mode is useful for low-power consumption. An internal filtering circuit prevents negative glitches
from accidentally shutting down the device. EN must be low for a minimum of approximately 60 μs to ensure a
shutdown state.
The system master can reset the TCA6507 in the event of a timeout or other improper operation by setting
EN low for a minimum of approximately 60 μs. This has the same effect as a power-on reset without poweringdown the TCA6507.
The oscillator start up time (tOSC) is measured from the point when EN is set high.
8.5 Programming
8.5.1 I2C Interface
The TCA6507 has a standard bidirectional I2C interface that is controlled by a master device to be configured or
read the status of this device. Each slave on the I2C bus has a specific device address to differentiate between
other slave devices that are on the same I2C bus. Many slave devices require configuration upon startup to set
the behavior of the device. This is typically done when the master accesses internal register maps of the slave,
which have unique register addresses. A device can have one, or multiple registers where data is stored, written,
or read.
The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines
must be connected to VCC through a pullup resistor. The size of the pullup resistor is determined by the amount
of capacitance on the I2C lines. For further details, see the I2C Pullup Resistor Calculation application report.
Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are
high after a STOP condition.
Figure 12 and Figure 13 show the general procedure for a master to access a slave device:
1. If a master wants to send data to a slave:
– Master-transmitter sends a START condition and addresses the slave-receiver
– Master-transmitter sends data to slave-receiver
– Master-transmitter terminates the transfer with a STOP condition
2. If a master wants to receive or read data from a slave:
– Master-receiver sends a START condition and addresses the slave-transmitter
– Master-receiver sends the requested register to read to slave-transmitter
– Master-receiver receives data from the slave-transmitter
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Programming (continued)
– Master-receiver terminates the transfer with a STOP condition
SCL
SDA
Data Transfer
START
Condition
STOP
Condition
Figure 12. Definition of START and STOP Conditions
SDA line stable while SCL line is high
SCL
1
0
1
0
1
0
1
0
ACK
MSB
Bit
Bit
Bit
Bit
Bit
Bit
LSB
ACK
SDA
Byte: 1010 1010 ( 0xAAh )
Figure 13. Bit Transfer
8.5.2 Bus Transactions
Data must be sent to and received from the slave devices, and this is accomplished by reading from or writing to
registers in the slave device.
Registers are locations in the memory of the slave that contain information, whether it be the configuration
information, or some sampled data to send back to the master. The master must write information to these
registers to instruct the slave device to perform a task.
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Programming (continued)
8.5.2.1 Writes
To write on the I2C bus, the master sends a START condition on the bus with the address of the slave, as well
as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master
then sends the register address of the register to which it wishes to write. The slave acknowledges again, letting
the master know it is ready. After this, the master starts sending the register data to the slave until the master
has sent all the data necessary (which can be only a single byte), and the master terminates the transmission
with a STOP condition.
Figure 14 shows an example of writing a single byte to a register.
Master controls SDA line
Slave controls SDA line
Write to one register in a device
Register Address N (8 bits)
Device (Slave) Address (7 bits)
S
1
0
0
0
1
0
START
1
0
A
R/W=0
Data Byte to Register N (8 bits)
B7 B6 B5 B4 B3 B2 B1 B0
ACK
D7 D6 D5 D4 D3 D2 D1 D0
A
ACK
A
ACK
P
STOP
Figure 14. Write to Register
Figure 15 shows an example of writing to a Fully On register.
Master controls SDA line
Slave controls SDA line
Command Byte (8 bits)
Device (Slave) Address (7 bits)
S
1
START
0
0
0
1
0
1
0
R/W=0
A
0
0
0
0
0
1
0
Data Byte to Register 0x04 (8 bits)
0
ACK
D7 D6 D5 D4 D3 D2 D1 D0
A
ACK
A
ACK
P
STOP
Figure 15. Write to the Fully On Register (0x04)
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Programming (continued)
8.5.2.2 Reads
Reading from a slave is very similar to writing, but requires some additional steps. To read from a slave, the
master must first instruct the slave which register it wishes to read from. This is done by the master starting off
the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0 (signifying a
write), followed by the register address it wishes to read from. Once the slave acknowledges this register
address, the master sends a START condition again, followed by the slave address with the R/W bit set to 1
(signifying a read). This time, the slave acknowledges the read request, and the master releases the SDA bus,
but continues supplying the clock to the slave. During this part of the transaction, the master becomes the
master-receiver, and the slave becomes the slave-transmitter.
The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data.
At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for
more data. Once the master has received the number of bytes it is expecting, it sends a NACK, signaling to the
slave to halt communications and release the bus. The master follows this up with a STOP condition.
Figure 16 shows an example of reading a single byte from a slave register.
Master controls SDA line
Slave controls SDA line
Read from one register in a device
Device (Slave) Address (7 bits)
S
1
0
0
0
1
START
0
1
Register Address 0x03 (8 bits)
0
A
R/W=0
0
0
0
0
0
0
1
A
1
ACK
Data Byte from Register 0x03 (8 bits)
Device (Slave) Address (7 bits)
Sr
ACK
1
0
0
0
1
0
1
1
R/W=1
Repeated START
A
D7 D6 D5 D4 D3 D2 D1 D0 NA
ACK
NACK
P
STOP
Figure 16. Read From Register Example
8.5.3 Device Address
The address of the TCA6507 is shown in Figure 17.
Fixed Slave Address
1
0
0
0
1
0
1
R/W
Figure 17. TCA6507 Address
The last bit of the slave address defines the operation (read or write) to be performed. High (1) selects a read
operation, and low (0) selects a write operation. Table 2 shows the TCA6507 interface definition.
Table 2. Interface Definition
BYTE
I2C slave address
Px I/O data bus
(1)
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
1
0
0
0
1
0
1
R/W
X (1)
P6
P5
P4
P3
P2
P1
P0
X = Don't care.
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8.5.4 Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is
stored in the control register. The last four bits (B0, B1, B2 and B3) of this command byte determine the internal
registers (Select0, Select1, Select2, Fade-ON Time, Fully-ON Time, Fade-OFF Time, First Fully-OFF Time,
Second Fully-OFF Time, Maximum Intensity and Initialization) that are affected. The command byte is sent only
during a write transmission.
After the command byte is received, the I2C master starts sending data bytes. The first data byte goes into the
internal register defined by the command byte. Bit B4 in the command byte is used to determine the
programming mode. If B4 is low, all data bytes are written to the register defined by B0, B1, B2, and B3. If B4 is
high, the last four bits of the command byte are automatically incremented after the byte is written, and the next
data byte is stored in the corresponding register. Registers are written in the sequence shown in Table 6. Once
the Initialization register (register 0×0A) is written to, the command byte returns to 0 (Select0 register).
The upper three bits (B7–B5) of the command byte must be programmed as zeroes for proper operation.
If a STOP condition occurs after the command byte is received, the TCA6507 stores the command byte and then
remains idle until the I2C master sends the next operation.
Figure 18 shows the TCA6507control register bits.
B7
B6
B5
B4
B3
B2
B1
B0
Figure 18. Control Register Bits
Table 3 shows the TCA6507 command byte.
Table 3. Command Byte
BIT
FUNCTION
B7
Reserved. Must be programmed as 0
B6
Reserved. Must be programmed as 0
B5
Reserved. Must be programmed as 0
B4
Auto increment. 1 = Auto increment enabled. 0 = Auto increment disabled
B3
Register address 3
B2
Register address 2
B1
Register address 1
B0
Register address 0
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8.5.5 Auto-Increment Mode
In auto-increment mode, the last four bits of the command byte are automatically incremented after the byte is
written, and the next data byte is stored in the corresponding register. See Figure 19.
Master controls SDA line
Slave controls SDA line
Command Byte (8 bits)
Device (Slave) Address (7 bits)
S
1
0
0
0
1
0
START
1
0
R/W=0
Data to Register 0x01 (Select1)
0
0
0
0
0
0
1
0
A
0
0
0
1
0
0
0
Data to Register 0x00 (Select0)
0
Auto-increment
ACK
A
0
0
0
0
0
0
1
ACK
0
A
ACK
Data to Register 0x02 (Select2)
A
0
0
0
0
0
0
1
ACK
0
A
ACK
P
STOP
Figure 19.
The registers are written to in the order shown in Table 6.
8.5.6 LED Operation
For LED states, see Figure 10 and Table 8.
It is the combination of Select2, Select1, and Select0 registers that gives the state of the LED or Px.
Bit 0 from the Select0 register, bit = 0 from Select1 register, and bit = 0 from the Select2 register provide the
state for P0, or the first LED. Similarly, bit = 1 from the Select0 register, bit 1 from Select1 register, and bit = 1
from the Select2 register provide the state for P1, or the second LED (see Table 4).
Table 4. LED Operation
MSB
LSB
Select0
X
0
0
0
0
0
0
0
Select1
X
0
0
0
0
0
0
0
Select2
X
0
0
0
0
0
0
0
Output or
LED affected
X
X
P6
7th LED
P5
6th LED
P4
5th LED
P3
4th LED
P2
3rd LED
P1
2nd LED
P0
1st LED
8.5.7 Blinking Pattern Control
The Fade-ON time, Fully-ON time, Fade-OFF time, First Fully-OFF time, and Second Fully-OFF time registers
must be written to for basic blink control. Each of these registers has eight bits – top four bits for BANK1 (or
PWM1), and bottom four bits for BANK0 (or PWM0) (see Table 20).
Each BANK or PWM has a default value of 4 (4b0100), which translates to a time of 256 ms. The largest value
for each BANK or PWM is 15 (4b1111), which translates to a time of 16320 ms (see Figure 20 and Table 5).
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Table 5. Intensity Parameters (see Figure 20)
REGION
PARAMETER NAME
PARAMETER RANGE
REGISTER
RANGE
REGISTER NAME
REGISTER
A1, A2
Fade-ON time
0 to 16320 ms
(exponential trend)
0 to 15
Fade-ON time
0×03
B1, B2
Fully-ON time
0 to 16320 ms
(exponential trend)
0 to 15
Fully-ON time
0×04
C1, C2
Fade-OFF time
0 to 16320 ms
(exponential trend)
0 to 15
Fade-OFF time
0×05
D
First fully-OFF time
0 to 16320 ms
(exponential trend)
0 to 15
First fully-OFF time
0×06
E
Second fully-OFF time
0 to 16320 ms
(exponential trend)
0 to 15
Second fully-OFF time
0×07
F
Maximum intensity
0 to 100%
0 to 15
Maximum intensity
0×08
A1
B1
C1
D
A2
B2
C2
E
F or ALD
Figure 20. LED Pattern Sections Per Bank
Figure 21 and Figure 22 show the output port intensity vs LED intensity.
100%
Approximately 75%
Intensity
Approximately 25%
0%
VOH
I/O port
Voltage
VOL
8 ms
8 ms
2 ms
6 ms
Figure 21. Output Port Voltage vs LED Intensity, Maximum Intensity = 100%
50%
Approximately 37.5%
Intensity
Approximately
12.5%
0%
VOH
I/O port
Voltage
VOL
8 ms
1 ms
8 ms
4 ms
8 ms
3 ms
Figure 22. Output Port Voltage vs LED Intensity, Maximum Intensity = 50%
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8.5.8 Intensity Control
The Maximum Intensity registers must be written to for setting the intensity of the LED. This register has eight
bits – top four bits for BANK1 (or PWM1), and bottom four bits for BANK0 (or PWM0). This register can be
written to after sending data to the Second Fully-OFF Time register (see Table 20).
The Maximum Intensity register has a default value of 15 (1111), which translates to 100% brightness
(see Figure 20 and Table 5).
8.6 Register Maps
Table 6 describes the TCA6507 control registers.
Table 6. Control Register Description
CONTROL REGISTER BITS
REGISTER
PROTOCOL
POWER-UP
DEFAULT
(BINARY)
B3
B2
B1
B0
COMMAND
BYTE (HEX)
0
0
0
0
0x00
Select0
Read/write byte
0000 0000
0
0
0
1
0x01
Select1
Read/write byte
0000 0000
0
0
1
0
0x02
Select2
Read/write byte
0000 0000
0
0
1
1
0x03
Fade-ON Time
Read/write byte
0100 0100
0
1
0
0
0x04
Fully-ON Time
Read/write byte
0100 0100
0
1
0
1
0x05
Fade-OFF Time
Read/write byte
0100 0100
0
1
1
0
0x06
First Fully-OFF Time
Read/write byte
0100 0100
0
1
1
1
0x07
Second Fully-OFF Time
Read/write byte
0100 0100
1
0
0
0
0x08
Maximum Intensity
Read/write byte
1111 1111
1
0
0
1
0x09
One Shot / Master Intensity
Read/write byte
0000 1111
1
0
1
0
0x0A
Initialization
Write byte
N/A
The Select0 register (register 0x00), Select1 (register 0x01), and Select2 register (register 0x02) configure the
state of each of the outputs (see Table 8).
Registers that define time periods have a range of 0 to 16320 ms, as defined in Table 7.
Table 7. Time Parameters
CODE (DECIMAL)
TIME (ms)
0
0
1
64
2
128
3
192
4 (default)
256
5
384
6
512
7
768
8
1024
9
1536
10
2048
11
3072
12
4096
13
5760
14
8128
15
16320
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8.6.1 Registers 0x00 - 0x02 (Select Registers)
Table 8 show the Select2, Select1, and Select0 Register States.
Table 8. Select2, Select1, and Select0 Register States
SELECT2
SELECT1
SELECT0
0
0
0
LED off (high impedance).
STATE
0
0
1
LED off (high impedance).
0
1
0
LED on with maximum intensity value of PWM0 (ALD value or BRIGHT_F0 value, depending
on One Shot / Master Intensity Register setting).
0
1
1
LED on with maximum intensity value of PWM1 (ALD value or BRIGHT_F1 value, depending
on One Shot / Master Intensity Register setting).
1
0
0
LED fully on (output low). Can be used as general-purpose output.
1
0
1
LED on at brightness set by One Shot / Master Intensity register.
1
1
0
LED blinking with intensity characteristics of BANK0 (PWM0).
1
1
1
LED blinking with intensity characteristics of BANK1 (PWM1).
Table 9 show the Register 0x00 (Select0 Register).
Table 9. Register 0x00 (Select0 Register)
(1)
BIT
S0-7
S0-6
S0-5
S0-4
S0-3
S0-2
S0-1
S0-0
DEFAULT
X (1)
0
0
0
0
0
0
0
X = Don't care.
Table 10 show the Register 0x01 (Select1 Register).
Table 10. Register 0x01 (Select1 Register)
(1)
BIT
S1-7
S1-6
S1-5
S1-4
S1-3
S1-2
S1-1
S1-0
DEFAULT
X (1)
0
0
0
0
0
0
0
X = Don't care.
Table 11 show the Register 0x02 (Select2 Register).
Table 11. Register 0x02 (Select2 Register)
(1)
BIT
S2-7
S2-6
S2-5
S2-4
S2-3
S2-2
S2-1
S2-0
DEFAULT
X (1)
0
0
0
0
0
0
0
X = Don't care.
To use a P port as a general-purpose output, Select1 and Select0 registers must be set low (or 0), and then the
inverse of the data written to the Select2 bit appears on the open-drain output.
The intensity of each bank of LEDs can be customized by programming six registers: Fade-ON Time, Fully-ON
Time, Fade-OFF Time, First Fully-OFF Time, Second Fully-OFF Time, and Maximum Intensity registers. Each
bank is designed to produce two identical intensity pulses per blink cycle. Both pulses have the same fade-ON,
fully-ON and fade-OFF times, but independent fully-OFF times to achieve a double-blink effect when desired.
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8.6.2 Register 0x03 (Fade-ON Time)
Table 12 shows the Fade-ON Time Register (Register 0x03).
Table 12. Register 0x03 (Fade-ON Time Register)
BANK
BANK1
BANK0
BIT
C7
C6
C5
C4
C3
C2
C1
C0
DEFAULT
0
1
0
0
0
1
0
0
The Fade-ON Time register (register 0x03) defines the time from the fully-OFF state to the fully-ON state for the
LED per region A in Figure 20. The first four bits (C7–C4) in this register set the fade-ON time for BANK1, and
the next four bits (C3–C0) set the fade-ON time for BANK0. The data for each bank is a binary number between
0 and 15. For BANK1, the MSB is bit C7, while the least significant bit (LSB) is bit C4. For BANK0, the MSB is bit
C3 while the LSB is bit C0. See Table 7 for more information.
8.6.3 Register 0x04 (Fully-ON Time)
Table 13 shows the Fully-ON Time Register (Register 0x04).
Table 13. Register 0x04 (Fully-ON Time Register)
BANK
BANK1
BANK0
BIT
C7
C6
C5
C4
C3
C2
C1
C0
DEFAULT
0
1
0
0
0
1
0
0
The Fully-ON Time register (register 4) defines the time spent at maximum intensity between the fade-ON state
and fade-OFF state for the LED per region B in Figure 20. The first four bits (C7–C4) in this register set the
fully-ON time for BANK1, and the next four bits (C3–C0) set the fully-ON time for BANK0. The data for each bank
is a binary number between 0 and 15. For BANK1, the MSB is bit C7, while the LSB is bit C4. For BANK0, the
most significant bit (MSB) is bit C3, while the LSB is bit C0.
See Table 7 for more information on the possible time values.
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8.6.4 Register 0x05 (Fade-OFF Time)
Table 14 shows the Fade-OFF Time Register (Register 0x05).
Table 14. Register 0x05 (Fade-OFF Time Register)
BANK
BANK1
BANK0
BIT
C7
C6
C5
C4
C3
C2
C1
C0
DEFAULT
0
1
0
0
0
1
0
0
The Fade-OFF Time register (register 5) defines the time from the fully-ON state to the fully-OFF state for the
LED per region C in Figure 20. The first four bits (C7–C4) in this register set the fade-OFF time for BANK1, and
the next four bits (C3–C0) set the fade-OFF time for BANK0. The data for each bank is a binary number between
0 and 15. For BANK1, the MSB is bit C7, while the LSB is bit C4. For BANK0, the MSB is bit C3, while the least
significant bit (LSB) is bit C0.
See Table 7 for more information on the possible time values.
8.6.5 Register 0x06 - 0x07 (Fully-OFF Time)
Table 15 and Table 16 show the Fully-OFF Time register (Register 0x06 - 0x07).
Table 15. Register 0x06 (First Fully-OFF Time Register)
BANK
BANK1
BANK0
BIT
C7
C6
C5
C4
C3
C2
C1
C0
DEFAULT
0
1
0
0
0
1
0
0
Table 16. Register 0x07 (Second Fully-OFF Time Register)
BANK
BANK1
BANK0
BIT
C7
C6
C5
C4
C3
C2
C1
C0
DEFAULT
0
1
0
0
0
1
0
0
The first and second Fully-OFF Time registers (registers 6 and 7) define the time spent at zero intensity (in the
fully-OFF state of the LED) per region D and E, respectively, in Figure 20. The first four bits (C7–C4) in this
register set the fully-OFF time for BANK1, and the next four bits (C3–C0) set the fully-OFF time for BANK0. The
data for each bank is a binary number between 0 and 15. For BANK1, the MSB is bit C7, while the LSB is bit C4.
For BANK0, the MSB is bit C3, while the LSB is bit C0.
See Table 7 for more information on the possible time values.
26
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8.6.6 Register 0x08 (Maximum Intensity per Bank)
Table 17 shows the Maximum Intensity Register (Register 0x08).
Table 17. Register 0x08 (Maximum Intensity Register)
BANK
BANK1
BANK0
BIT
C7
C6
C5
C4
C3
C2
C1
C0
DEFAULT
1
1
1
1
1
1
1
1
The Maximum Intensity register defines the duty cycle of the waveform driving the LED in its fully-ON state per
region F in Figure 20. The first four bits (C7–C4) in this register set the duty cycle for BANK1 and the next four
bits (C3–C0) set the duty cycle for BANK0. The data for each bank is a binary number between 0 and 15. For
BANK1, the MSB is bit C7, while the LSB is bit C4. For BANK0, the MSB is bit C3, while the LSB is bit C0. The
values in this register also define the LED intensity indicated by the BRIGHT_F0 or BRIGHT_F1 modes. The
intensity of each LED is updated 125 times per second (every 8 ms with a 32-kHz clock).
The values for each value are shown in Table 18.
Table 18. Brightness Register Values
Code
Brightness
Decimal
Nibble (Hex)
0
0x0
1
0x1
6.67%
2
0x2
13.33%
3
0x3
20.00%
4
0x4
26.67 %
5
0x5
33.33 %
6
0x6
40.00 %
7
0x7
46.67 %
8
0x8
53.33 %
9
0x9
60.00 %
10
0xA
66.67 %
11
0xB
73.33 %
12
0xC
80.00 %
13
0xD
86.67 %
14
0xE
93.33 %
15
0xF
100 %
0%
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8.6.7 Register 0x09 (One-Shot / Master Intensity)
The One-Shot / Master Intensity register (register 9) is an 8-bit register with three functions.
Bits 0–3 set the master intensity value (ALD). It is a binary number between 0 and 15.
Bits 4–5 determine whether the maximum intensity of PWM0 and PWM1 is set by the programmed F value
(BRIGHT_F0 or BRIGHT_F1) or the master ALD value. The default value for these bits is 0. Bit 4 supports
PWM0 and bit 5 is for PWM1. If bit 4 (or bit 5) is 0, the maximum intensity value for PWM0 (or PWM1) is set by
the F value. If bit 4 (or bit 5) is 1, the maximum intensity value for PWM0 (or PWM1) is set by the master ALD
value. This allows the user to vary the brightness of all LEDs by changing a single register.
Bits 6–7 determine whether each PWM operates in normal or one-shot mode. Bit 6 supports PWM0 and bit 7 is
for PWM1. If bit 6 (or bit 7) is 0, PWM0 (or PWM1) operates in the normal mode where the LEDs goes through
the full intensity cycle defined by Table 5 and Figure 20. If bit 6 (or bit 7) is 1, PWM0 (or PWM1) operate in the
one-shot mode. In this mode, the LEDs can be used to create a single-shot lighting effect where the LED
intensity is valid for a particular segment of the cycle shown in Table 5 and Figure 20. As a note for users who
plan to use one-shot mode, the time register corresponding to the sections for the desired one-shot starting
location, and immediately after must both have non-zero values in the registers for time in order for one-shot to
function as expected.
Table 19 shows the One-Shot / Master Intensity Register.
Table 19. One-Shot / Master Intensity Register
BIT
0–3
28
DESCRIPTION
Master intensity (ALD) value. Valid values are 0 to 15. See Table 18 for more information
4
Determines whether maximum intensity of PWM0 is set by the programmed F value or the master ALD value
0 = F value
1 = ALD value
5
Determines whether maximum intensity of PWM1 is set by the programmed F value or the master ALD value
0 = F value defined in Maximum Intensity per Bank Register (0x08)
1 = ALD value
6
Determines if PWM0 operates in normal or one-shot mode
0 = Normal mode
1 = One-shot mode
7
Determines if PWM1 operates in normal or one-shot mode
0 = Normal mode
1 = One-shot mode
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8.6.8 Register 0x0A (Initialization Register)
The Initialization register (register 0x0A) determines whether to initialize each PWM and, if so, provides the
starting point of the LED intensity cycle for each bank. Bits 0–3 (C0–C3) are for BANK0 and bits 4–7 (C4–C7)
are for BANK1. Table 20 shws the Initialization Register (Register 0x0A).
Bits 0–2 provide the starting point for PWM0. If bit 3 is high (or 1), it initializes PWM0.
Bits 4–6 provide the starting point for PWM1. If bit 7 is high (or 1), it initialized PWM1.
In the one-shot mode for BANK0, the LEDs start at the beginning of the region defined by C2, C1, and C0 in the
Initialization register and, when it reaches the end of that region, the LED stays at that intensity level defined at
the end of the region. When the stop point is reached, all P ports attached to PWM0 disconnect from PWM0, and
stay at either the maximum intensity level for PWM0 (BRIGHT_F0 or ALD value), or the OFF state. The bits in
the Select2 and Select1 registers change to reflect the final state of the LED at that time. PWM0 continues
running, and is free to be used by other LEDs. The one-shot mode works similarly for BANK1.
Upon writing to this register, each bank is initialized to the state listed in Table 21 and Table 22.
Table 20. Register 0x0A (Initialization Register)
BANK
BANK1
BIT
C7
C6
BANK0
C5
C4
C3
C2
C1
C0
Table 21. Bank 1 Initialization Register
C7
C6
C5
C4
INTENSITY CYCLE
1
0
0
0
Beginning at region A1 in Table 5 and Figure 18
1
0
0
1
Beginning at region B1 in Table 5 and Figure 18
1
0
1
0
Beginning at region C1 in Table 5 and Figure 18
1
0
1
1
Beginning at region D in Table 5 and Figure 18
1
1
0
0
Beginning at region A2 in Table 5 and Figure 18
1
1
0
1
Beginning at region B2 in Table 5 and Figure 18
1
1
1
0
Beginning at region C2 in Table 5 and Figure 18
1
1
1
1
Beginning at region E in Table 5 and Figure 18
Table 22. Bank 0 Initialization Register
C3
C2
C1
C0
1
0
0
0
Beginning at region A1 in Table 5 and Figure 18
STARTING POINT OF INTENSITY CYCLE
1
0
0
1
Beginning at region B1 in Table 5 and Figure 18
1
0
1
0
Beginning at region C1 in Table 5 and Figure 18
1
0
1
1
Beginning at region D in Table 5 and Figure 18
1
1
0
0
Beginning at region A2 in Table 5 and Figure 18
1
1
0
1
Beginning at region B2 in Table 5 and Figure 18
1
1
1
0
Beginning at region C2 in Table 5 and Figure 18
1
1
1
1
Beginning at region E in Table 5 and Figure 18
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers must
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Applications of the TCA6507 contains an I2C (or SMBus) master device. The TCA6507 is used to control the
blinking pattern of LEDs or as a general purpose output.
9.2 Typical Application
Figure 23 shows a general application in which the TCA6507 can be used. Each LED output is driving one LED.
Figure 26 highlights another application where the TPS61052 boost converter and high-power LED driver and
TCA6507 7-bit LED driver can be used in combination for applications requiring flashlight functionality and/or
high-brightness indicator/backlight LEDs.
5V
VCC
(1.8 V)
VCC
VCC
Master
Controller
10 kW
10 kW
VCC
SCL
SCL
SDA
SDA
EN
P0
P1
EN
P2
P3
GND
P4
GND
P5
General
Purpose
Logic
P6
TCA6507
Copyright © 2017, Texas Instruments Incorporated
Figure 23. Typical Application
9.2.1 Design Requirements
For the typical application example, the TCA6507 is set up to blink the P0 with Bank0 pattern, P1 fully on, and
P2 with Bank1 blinking pattern. The banks is setup to the flashing pattern defined in Figure 24. The options for
lengths of time for each section can be seen in Table 7.
30
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Typical Application (continued)
512
512
512
1024 ms ms 1024 ms ms 1024 ms ms 1024 ms
BANK0
2048 ms
100%
256
ms
BANK1
256
ms
512 512
ms ms 1024 ms
512 512
ms ms 1024 ms
80%
Figure 24. Blinking Pattern for the Two Banks
9.2.2 Detailed Design Procedure
For the typical application blinking pattern seen in Figure 24, the desired values are listed in Table 23, with the
corresponding registers and values.
Table 23. LED Pattern
SECTION
BANK1
VALUE
BANK0
VALUE
UNIT
REGISTER
BANK1 NIBBLE
(HEX)
BANK0 NIBBLE
(HEX)
REGISTER
VALUE (HEX)
Fade-ON time
256
1024
ms
0x03
0x4
0x8
0x48
Fully-ON time
512
512
ms
0x04
0x6
0x6
0x66
Fade-OFF time
512
1024
ms
0x05
0x6
0x8
0x68
First fully-OFF time
1024
512
ms
0x06
0x8
0x6
0x86
Second fully-OFF
time
1024
2048
ms
0x07
0x8
0xA
0x8A
Maximum
brightness
62.5
100
%
0x08
0x9
0xF
0x9F
The select register values are shown in Table 24.
Table 24. Select Registers
REGISTER
NAME
ADDRESS
VALUE
(BINARY)
VALUE
(HEX)
SELECT0
0x00
8b0000 0100
0x04
SELECT1
0x01
8b0000 0101
0x05
SELECT2
0x02
8b0000 0111
0x07
With the above values for the appropriate registers, the next step must be to write the values to the device. This
can be accomplished very easily with the auto-increment feature (see the Auto-Increment Mode section for more
information).
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Table 25. Writing to Registers
BYTE #
BYTE
DESCRIPTION
1
0x89
Address and write bit
2
0x10
Command byte with auto-increment
3
0x04
Write to SELECT0 register
4
0x05
Write to SELECT1 register
5
0x06
Write to SELECT2 register
6
0x48
Write to Fade-ON Time register
7
0x66
Write to Fully-ON Time register
8
0x68
Write to Fade-OFF Time register
9
0x86
Write to First Fully-OFF Time register
10
0x8A
Write to Second Fully-OFF Time register
11
0x9F
Write to Maximum Brightness register
After the above bytes in Table 25 are written to the device, the LEDs blinks according to the defined pattern.
9.2.3 Application Curve
100%
Approximately 75%
Intensity
Approximately 25%
0%
VOH
I/O port
Voltage
VOL
8 ms
2 ms
8 ms
6 ms
Figure 25. Output Port Voltage vs LED Intensity, Maximum Intensity = 100%
32
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9.3 System Example
Figure 26 highlights another application where the TPS61052 boost converter and high-power LED driver and
TCA6507 7-bit LED driver can be used in combination for applications requiring flashlight functionality, highbrightness indicator and backlight LEDs, or both.
L
VBAT
2.2 μH
SW
SW
VOUT
COUT
AVIN
10 μF
Li-Ion
CIN
P
Dx
P
Dy
Dz
P
LED
2
I C I/F
Flash synchronization
camera engine
SCL
SDA
ENVM
FLASH_SYNC
PGND
AGND
1.8
P
PGND
2
I C I/F
TCA6507
VCC
P0
SCL
P1
SDA
EN
P2
Voltage mode enable
base-band engine
GND
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Figure 26. White LED Flashlight Driver and High-Brightness LED Indicator/Backlight Power Supply
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10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, the TCA6507 can be reset to its default conditions by using the poweron reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
VCC
Ramp-Up
Ramp-Down
Re-Ramp-Up
VCC_TRR_GND
Time
VCC_RT
VCC_FT
Time to Re-Ramp
VCC_RT
Figure 27. VCC Is Lowered to 0 V and Then Ramped Up to VCC
The Table 26 section specifies the performance of the power-on reset feature for TCA6507.
Table 26. Recommended Supply Sequencing and Ramp Rates when EN is Connected to VCC (1)
MAX
UNIT
VCC_FT
Fall rate
PARAMETER
See Figure 27
0.01
100
ms
VCC_RT
Rise rate
See Figure 27
0.01
100
ms
VCC_TRR_GND
Time spent low before re-ramp (when VCC drops to GND)
See Figure 27
500
(1)
MIN
TYP
ms
TA = –40°C to +85°C (unless otherwise noted)
If the EN pin is controlled independently from VCC, ramp rates and times outside these recommended limits. EN
must be ramped after supply to ensure correct power-on reset sequence.
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11 Layout
11.1 Layout Guidelines
For PCB layout of the TCA6507, common PCB layout practices must be followed, but additional concerns related
to high-speed data transfer, such as matched impedances and differential pairs, are not a concern for I2C signals
speeds. It is common to have a dedicated ground plane on an inner layer of the board, and pins that are
connected to ground must have a low-impedance path to the ground plane in the form of wide polygon pours,
and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin,
using a larger capacitor to provide additional power in the event of a short power supply glitch, and a smaller
capacitor to filter out high-frequency ripple.
11.2 Layout Example
P1
0402 Cap
VCC
P5
SCL
P4
SDA
P3
EN
P2
P1
= Via to GND Plane
P0
Figure 28. RUE Layout Recommendation
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• I2C Bus Pullup Resistor Calculation
• Introduction to Logic
• Maximum Clock Frequency of I2C Bus Using Repeaters
• Programming Fun Lights With the TI TCA6507
• Understanding the I2C Bus
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TCA6507PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PH507
TCA6507PWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PH507
TCA6507PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PH507
TCA6507PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
PH507
TCA6507RUER
ACTIVE
X2QFN
RUE
12
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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7-Nov-2019
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TCA6507RUER
Package Package Pins
Type Drawing
X2QFN
RUE
12
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
179.0
8.4
Pack Materials-Page 1
1.6
B0
(mm)
K0
(mm)
P1
(mm)
2.2
0.55
4.0
W
Pin1
(mm) Quadrant
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2020
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TCA6507RUER
X2QFN
RUE
12
3000
203.0
203.0
35.0
Pack Materials-Page 2
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