Texas Instruments | TRS3253E RS-232 Transceiver With Split Supply Pin for Logic Side (Rev. D) | Datasheet | Texas Instruments TRS3253E RS-232 Transceiver With Split Supply Pin for Logic Side (Rev. D) Datasheet

Texas Instruments TRS3253E RS-232 Transceiver With Split Supply Pin for Logic Side (Rev. D) Datasheet
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TRS3253E
SLLS850D – JANUARY 2008 – REVISED MARCH 2017
TRS3253E RS-232 Transceiver With Split Supply Pin for Logic Side
1 Features
3 Description
•
The TRS3253E device is a three-driver and fivereceiver RS-232 interface device, with split supply
pins for mixed-signal operations without needing an
external voltage translator. All RS-232 inputs and
outputs are protected to ±15 kV using the IEC 610004-2 Air-Gap Discharge method, ±8 kV using the IEC
61000-4-2 Contact Discharge method, and ±15 kV
using the Human Body Model.
1
•
•
•
•
VL Pin for Compatibility With Mixed-Voltage
Systems Down to 1.8 V on Logic Side
Enhanced ESD Protection on RIN Inputs and
DOUT Outputs
– ±15-kV IEC 61000-4-2 Air-Gap Discharge
– ±8-kV IEC 61000-4-2 Contact Discharge
– ±15-kV Human Body Model
Low 300-μA Supply Current
Specified 1000-kbps Data Rate
Auto Powerdown Plus Feature
The charge pump requires only four capacitors for
operation from a single 3.3-V or 5-V supply. The
TRS3253E is capable of running at data rates up to
1000 kbps, while maintaining RS-232 compliant
output levels.
2 Applications
•
•
•
•
•
•
•
The TRS3253E is available in a space-saving VQFN
package (4-mm × 4-mm RSM).
Hand-Held Equipment
Cell Phones
Battery-Powered Equipment
Data Cables
POS Equipment
HDMI Switch Matrix
Debug Ports
Auto-powerdown-plus automatically powers down
drivers to reduce power after 30 seconds of inactivity.
In powerdown state supply current is 10 μA
maximum.
Receiver input voltage status is available on INVALID
logic output even when the device is in powerdown
state.
Device Information(1)
PART NUMBER
TRS3253ERSM
PACKAGE
VQFN (32)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Diagram
Logic Supply
VL
3.3V, 5V
POWER
FORCEON
APD+
30 seconds
FORCEOFF
DIN
ROUT
INVALID
3
5
TX
RX
3
DOUT
RS232
5
RIN
RS232
STATUS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TRS3253E
SLLS850D – JANUARY 2008 – REVISED MARCH 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
5
5
5
6
6
6
6
7
7
7
8
9
Absolute Maximum Ratings .....................................
ESD Ratings ...........................................................
Recommended Operating Conditions......................
Thermal Information.................................................
Electrical Characteristics—Power ...........................
Electrical Characteristics—Driver.............................
Electrical Characteristics—Receiver........................
Electrical Characteristics—Status ............................
Switching Characteristics—Driver............................
Switching Characteristics—Receiver .....................
Switching Characteristics—Power and Status........
Typical Characteristics ............................................
Parameter Measurement Information ................ 10
8
Detailed Description ............................................ 13
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
13
14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application .................................................. 15
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (June 2015) to Revision D
•
Changed "IEC61000-4-2, Contact Discharge" from "8 kV" to "15 kV" in Features, Description, Overview and ESD
Ratings ................................................................................................................................................................................... 5
Changes from Revision B (December 2013) to Revision C
•
2
Page
Page
Added Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Typical
Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section,
Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
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5 Pin Configuration and Functions
NC
C1–
V+
C1+
FORCEOFF
VCC
GND
DOUT1
RSM Package
32-Pin VQFN
Top View
32 31 30 29 28 27 26 25
C2+
C2–
V–
DIN1
DIN2
INVALID
DIN3
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NC
DOUT2
DOUT3
RIN1
RIN2
RIN3
RIN4
RIN5
FORCEON
ROUT5
ROUT4
ROUT3
ROUT2
ROUT1
VL
NC
9 10 11 12 13 14 15 16
Power pad can be connected to GND or floating.
NC – No internal connection.
Pin Functions
PIN
NAME
NO.
C1+
29
C2+
1
C1–
31
C2–
2
DIN1
4
DIN2
5
DIN3
7
DOUT1
25
DOUT2
23
DOUT3
22
FORCEOFF
28
I/O
DESCRIPTION
—
Positive terminals of the voltage-doubler charge-pump capacitors
—
Negative terminals of the voltage-doubler charge-pump capacitors
I
Driver inputs
O
RS-232 driver outputs
I
Auto-powerdown-plus control input
Auto-powerdown-plus control input
FORCEON
9
I
GND
26
—
Ground
INVALID
6
O
Invalid output pin. Active low when all RIN inputs are unpowered
—
No connect pins (do not connect to these pins)
8
NC
16
24
32
RIN1
21
RIN2
20
RIN3
19
RIN4
18
RIN5
17
I
RS-232 receiver inputs
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Pin Functions (continued)
PIN
NAME
NO.
ROUT1
14
ROUT2
13
ROUT3
12
ROUT4
11
ROUT5
10
VCC
I/O
DESCRIPTION
O
Receiver outputs. Swing between 0 and VL
27
—
3-V to 5.5-V supply voltage
VL
15
—
Logic-level supply. All CMOS inputs and outputs are referenced to this supply
V+
30
O
5.5-V supply generated by the charge pump
V–
3
O
–5.5-V supply generated by the charge pump
4
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6 Specifications
6.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VCC to GND
–0.3
6
VL to GND
–0.3
VCC + 0.3
V+ to GND
–0.3
7
V– to GND
0.3
–7
V+ + |V–| (2)
VI
Input voltage
VO
Output voltage
Continuous power dissipation
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
V
13
DIN, FORCEOFF, and FORCEON to GND
–0.3
6
RIN to GND
±25
DOUT to GND
±13.2
ROUT to GND
–0.3
VL + 0.3
TA = 85°C, 32-pin RSM (RθJA = 37.2°C/W) (3)
–65
V
1747
mW
150
°C
150
°C
ESD Ratings
VALUE
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
6.3
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability..
V+ and V– can have maximum magnitudes of 7 V, but their absolute difference cannot exceed 13 V.
Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA) / RθJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
6.2
(1)
(2)
UNIT
Electrostatic discharge
All pins except 17 to 23
and 25
±2000
Pins 17 to 23 and 25
±15000
Charged-device model (CDM), per JEDEC
specification JESD22-C101 (2)
All pins
±1500
IEC61000-4-2, Contact discharge
Pins 17 to 23 and 25
±8000
IEC61000-4-2, Air-gap discharge
Pins 17 to 23 and 25
±15000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Recommended Operating Conditions
MIN
MAX
VCC
Supply voltage
3
5.5
V
VL
Supply voltage
1.65
VCC
V
VL = 3 V or 5.5 V
0
0.8
VL = 2.3 V
0
0.6
VL = 1.65 V
0
0.5
2.4
VL
Input logic low
DIN, FORCEOFF, FORCEON
VL = 5.5 V
Input logic high
DIN, FORCEOFF, FORCEON
Operating temperature
VL = 3 V
UNIT
V
2
VL
VL = 2.7 V
1.4
VL
VL = 1.95 V
1.25
VL
TRS3253EIRSMR
–40
85
°C
–25
25
V
Receiver input voltage
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6.4
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Thermal Information
TRS3253E
THERMAL METRIC (1)
RSM (VQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
37.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
30.1
°C/W
RθJB
Junction-to-board thermal resistance
7.8
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
7.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.4
°C/W
(1)
6.5
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Electrical Characteristics—Power
over operating free-air temperature range, VCC = VL = 3 V to 5.5 V, C1–C4 = 0.1 μF (tested at 3.3 V ± 10%), C1 = 0.047 μF,
C2–C4 = 0.33 μF (tested at 5 V ± 10%) (unless otherwise noted) (1)
PARAMETER
II
ICC
(1)
(2)
6.6
Input leakage current
Supply current
(TA = 25°C)
TEST CONDITIONS
MIN
FORCEOFF, FORCEON
TYP (2)
MAX
±0.01
±1
μA
0.5
1
mA
Auto-powerdown plus
disabled
No load,
FORCEOFF and FORCEON at VCC
Powered off
No load, FORCEOFF at GND
1
10
Auto-powerdown plus active
No load, FORCEOFF at VCC,
FORCEON at GND,
All RIN are open or grounded
1
10
UNIT
μA
Testing supply conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.15 V; C1–C4 = 0.22 μF at VCC = 3.3 V ± 0.3 V; and C1 = 0.047 μF and
C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V. (See Figure 8)
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Electrical Characteristics—Driver
over operating free-air temperature range, VCC = VL = 3 V to 5.5 V, C1–C4 = 0.1 μF (tested at 3.3 V ± 10%), C1 = 0.047 μF,
C2–C4 = 0.33 μF (tested at 5 V ± 10%), TA = TMIN to TMAX (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
Output voltage swing
All driver outputs loaded with 3 kΩ to ground, VCC=
3.1V to 5.5V
rO
Output resistance
VCC = V+ = V– = 0, Driver output = ±2 V
IOS
Output short-circuit current
VT_OUT = 0
IOZ
Output leakage current
MIN
TYP (1)
±5
±5.4
300
10M
VT_OUT = ±12 V, FORCEOFF = GND,
VCC = 3 V to 3.6 V
VT_OUT = ±12 V, FORCEOFF = GND,
VCC = 4.5 V to 5.5 V
Driver input hysteresis
Input leakage current
(1)
6.7
DIN, FORCEOFF, FORCEON
±0.01
MAX
UNIT
V
Ω
±60
mA
±25
μA
0.5
V
±1
μA
Typical values are at VCC = VL = 3.3 V, TA = 25°C
Electrical Characteristics—Receiver
over operating free-air temperature range, VCC = VL = 3 V to 5.5 V, C1–C4 = 0.1 μF (tested at 3.3 V ± 10%), C1 = 0.047 μF,
C2–C4 = 0.33 μF (tested at 5 V ± 10%), TA = TMIN to TMAX (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Ioff
Output leakage current
ROUT, receivers disabled
VOL
Output voltage low
IOUT = 1.6 mA
VOH
Output voltage high
IOUT = –1 mA
(1)
6
MIN
VL – 0.6
TYP (1)
MAX
UNIT
±0.05
±10
μA
0.4
V
VL – 0.1
V
Typical values are at VCC = VL = 3.3 V, TA = 25°C
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Electrical Characteristics—Receiver (continued)
over operating free-air temperature range, VCC = VL = 3 V to 5.5 V, C1–C4 = 0.1 μF (tested at 3.3 V ± 10%), C1 = 0.047 μF,
C2–C4 = 0.33 μF (tested at 5 V ± 10%), TA = TMIN to TMAX (unless otherwise noted)
PARAMETER
VIT–
Input threshold low
TA = 25°C
VIT+
Input threshold high
TA = 25°C
Vhys
Input hysteresis
TYP (1)
VL = 5 V
0.8
1.2
VL = 3.3 V
0.6
1.5
MAX
UNIT
V
VL = 5 V
1.8
2.4
VL = 3.3 V
1.5
2.4
V
0.5
Input resistance
6.8
MIN
TEST CONDITIONS
TA = 25°C
3
V
5
7
MIN
MAX
kΩ
Electrical Characteristics—Status
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+(valid)
Receiver input threshold
for INVALID high-level output voltage
FORCEON = GND, FORCEOFF = VL
VIT–(valid)
Receiver input threshold
for INVALID high-level output voltage
FORCEON = GND, FORCEOFF = VL
–2.7
VT(invalid)
Receiver input threshold
for INVALID low-level output voltage
FORCEON = GND, FORCEOFF = VL
–0.3
VOH
INVALID high-level output voltage
IOH = –1 mA, FORCEON = GND,
FORCEOFF = VL
VOL
INVALID low-level output voltage
IOL = 1.6 mA, FORCEON = GND,
FORCEOFF = VL
6.9
UNIT
2.7
V
V
0.3
V
VL – 0.6
V
0.4
V
Switching Characteristics—Driver
over operating free-air temperature range, VCC = VL = 3 V to 5.5 V, C1–C4 = 0.1 μF (tested at 3.3 V ± 10%), C1 = 0.047 μF,
C2–C4 = 0.33 μF (tested at 5 V ± 10%), TA = TMIN to TMAX (unless otherwise noted)
PARAMETER
|tPHL – tPLH|
Maximum data rate
RL = 3 kΩ, CL = 200 pF, one driver switching
Time-to-exit powerdown
|VT_OUT| > 3.7 V
MIN
TYP (1)
VCC = 3.3 V,
TA = 25°C,
RL = 3 kΩ to 7 kΩ,
Measured from 3 V
to –3 V or –3 V to 3 V
MAX
UNIT
1000
kbps
Driver skew (2)
Transition-region
slew rate
(1)
(2)
TEST CONDITIONS
CL = 150 pF to 1000 pF
100
μs
100
ns
15
150
V/μs
Typical values are at VCC = VL = 3.3 V, TA = 25°C.
Driver skew is measured at the driver zero crosspoint.
6.10 Switching Characteristics—Receiver
over operating free-air temperature range, VCC = VL = 3 V to 5.5 V, C1–C4 = 0.1 μF (tested at 3.3 V ± 10%), C1 = 0.047 μF,
C2–C4 = 0.33 μF (tested at 5 V ± 10%), TA = TMIN to TMAX (unless otherwise noted)
PARAMETER
tPHL
Receiver propagation
delay
tPLH
TEST CONDITIONS
Receiver input to receiver output, CL = 150 pF
MIN
TYP (1)
0.15
0.15
tPHL –
tPLH
Receiver skew
ten
Receiver output enable
time
From FORCEOFF
200
tdis
Receiver output disable
From FORCEOFF
time
200
(1)
MAX
UNIT
μs
50
ns
Typical values are at VCC = VL = 3.3 V, TA = 25°C.
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6.11 Switching Characteristics—Power and Status
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 7)
PARAMETER
MIN
TYP (1)
tvalid
Propagation delay time, low- to high-level output
0.1
tinvalid
Propagation delay time, high- to low-level output
50
ten
Supply enable time
25
tdis
Receiver or driver edge to auto-powerdown plus
(1)
8
15
30
MAX
UNIT
μs
60
s
All typical values are at VCC = VL = 3.3 V and TA = 25°C.
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6.12 Typical Characteristics
VCC = 3.3 V
6
0
5
±1
DOUT Voltage (V)
DOUT Voltage (V)
VOL
4
3
2
1
±2
±3
±4
±5
VOH
0
±6
0
1
2
3
4
DOUT Current (mA)
5
0
C001
Figure 1. DOUT VOH vs Load Current
Other Drivers 3-kΩ Load
1
2
3
4
DOUT Current (mA)
Figure 2. DOUT VOL vs Load Current
Other Drivers 3-kΩ Load
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7 Parameter Measurement Information
3V
Generator
(see Note B)
Input
RS-232
Output
50 Ω
RL
0V
tTHL
CL
(see Note A)
3V
FORCEOFF
TEST CIRCUIT
3V
3V
Output
SR(tr) =
tTLH
−3 V
−3 V
6V
t THL or tTLH
VOH
VOL
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns.
Figure 3. Driver Slew Rate
3V
Generator
(see Note B)
RS-232
Output
50 Ω
RL
Input
1.5 V
1.5 V
0V
CL
(see Note A)
tPHL
tPLH
VOH
3V
FORCEOFF
50%
50%
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns.
Figure 4. Driver Pulse Skew
3 V or 0 V
FORCEON
3V
Input
1.5 V
1.5 V
−3 V
Output
Generator
(see Note B)
tPHL
50 Ω
3V
FORCEOFF
tPLH
CL
(see Note A)
VOH
50%
Output
50%
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 5. Receiver Propagation Delay Times
10
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Parameter Measurement Information (continued)
3V
Input
VCC
3 V or 0 V
FORCEON
1.5 V
0V
S1
tPHZ
(S1 at GND)
RL
3 V or 0 V
1.5 V
GND
tPZH
VOH
Output
50%
Output
CL
(see Note A)
FORCEOFF
Generator
(see Note B)
0.3 V
tPZL
(S1 at VCC)
tPLZ
(S1 at VCC)
50 Ω
0.3 V
Output
50%
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
C.
tPLZ and tPHZ are the same as tdis.
D.
tPZL and tPZH are the same as ten.
Figure 6. Receiver Enable and Disable Times
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Parameter Measurement Information (continued)
Valid RS-232 Level, INVALID High
ROUT
Generator
(see Note B)
2.7 V
50 Ω
Indeterminate
0.3 V
0V
If Signal Remains Within This Region
For More Than 30 µs, INVALID Is Low1
−0.3 V
Indeterminate
Autopowerdown
Plus
INVALID
−2.7 V
CL = 30 pF
(see Note A)
Valid RS-232 Level, INVALID High
†
FORCEOFF
DIN
FORCEON
DOUT
Auto-powerdown plus disables drivers and reduces
supply current to 1 µA.
TEST CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following
characteristics: PRR = 5 kbit/s, ZO= 50 Ω, 50%
duty cycle, t r ≤ 10 ns, t f ≤ 10 ns.
Receiver
Input
3V
2.7 V
0V
0V
−2.7 V
−3 V
tinvalid
tvalid
INVALID
Output
50%
VCC
50%
0V
3 V to 5 V
Driver
Input
50%
50%
0V
≈5.5 V
Driver
Output
≈ −5.5 V
tdis
ten
tdis
ten
V+
Supply
Voltages
V+
V+ −0.3 V
V− +0.3 V
V−
V−
Voltage Waveforms and Timing Diagrams
Figure 7. INVALID Propagation-Delay Times and Supply-Enabling Time
12
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8 Detailed Description
8.1 Overview
The TRS3253E is a three-driver and five-receiver RS-232 interface device, with split-supply pins for mixed-signal
operations. All RS-232 inputs and outputs are protected to ±15 kV using the IEC 61000-4-2 Air-Gap Discharge
method, ±8 kV using the IEC 61000-4-2 Contact Discharge method, and ±15 kV using the Human-Body Model.
The charge pump requires only four small 0.1-μF capacitors for operation from a 3.3-V supply. The TRS3253E is
capable of running at data rates up to 1000 kbps, while maintaining RS-232-compliant output levels. The
TRS3253E is available in a space-saving VQFN package (4-mm × 4-mm RSM).
The TRS3253E has a unique VL pin that allows operation in mixed-logic voltage systems. Both driver input (DIN)
and receiver output (ROUT) logic levels are pin programmable through the VL pin. This eliminates the need for
additional voltage level shifter while interfacing with low-voltage microcontroller or UARTs.
Auto-powerdown plus can be disabled when FORCEON and FORCEOFF are high. With auto-powerdown plus
enabled, the device activates automatically when a valid signal change is applied to any receiver or driver input.
After 30 seconds of inactivity the device will automatically power down to save power.
INVALID is high (valid data) if any receiver input voltage is greater than 2.7 V or less than –2.7 V, or has been
between –0.3 V and 0.3 V for less than 30 μs. INVALID is low (invalid data) if all receiver input voltages are
between –0.3 V and 0.3 V for more than 30 μs. Refer to Figure 7 for receiver input levels.
8.2 Functional Block Diagram
Logic Supply
VL
3.3V, 5V
POWER
FORCEON
APD+
30 seconds
FORCEOFF
DIN
ROUT
INVALID
3
5
TX
RX
3
DOUT
RS232
5
RIN
RS232
STATUS
8.3 Feature Description
8.3.1 Power
The power block increases, inverts, and regulates voltage at V+ and V– pins using a charge pump that requires
four external capacitors. Logic voltage translation is controlled by voltage provided to VL pin. Auto-powerdownplus feature is controlled by FORCEON and FORCEOFF inputs. See Table 1 and Table 2.
When TRS3253E is unpowered, it can be safely connected to an active remote RS232 device.
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Feature Description (continued)
8.3.2 RS232 Driver
Three drivers interface standard logic level to RS232 levels. All DIN inputs must be valid high or low.
8.3.3 RS232 Receiver
Five receivers interface RS232 levels to standard logic levels. An open input will result in a high output on ROUT.
Each RIN input includes an internal standard RS232 load.
8.3.4 RS232 Status
The INVALID output goes low when all RIN inputs are unpowered for more than 30 μs. The INVALID output goes
high when any receiver has a valid input. The INVALID output is active when VL is powered irregardless of
FORCEON and FORCEOFF inputs. See Table 3.
8.4 Device Functional Modes
Table 1. Each Driver (1)
INPUTS
DIN
(1)
FORCEON
OUTPUT
FORCEOFF
TIME ELAPSED SINCE LAST
RIN OR DIN TRANSITION
DRIVER STATUS
DOUT
X
X
L
X
Z
Powered off
L
H
H
X
H
H
H
H
X
L
Normal operation with
auto-powerdown plus disabled
L
L
H
<30 s
H
H
L
H
<30 s
L
L
L
H
>30 s
Z
H
L
H
>30 s
Z
Normal operation with
auto-powerdown plus enabled
Powered off by
auto-powerdown plus feature
H = high level, L = low level, X = irrelevant, Z = high impedance.
Table 2. Each Receiver (1)
INPUTS
RIN
(1)
FORCEOFF
OUTPUT
TIME ELAPSED SINCE LAST
RIN OR DIN TRANSITION
ROUT
X
L
X
Z
L
H
<30 s
H
H
H
<30 s
L
Open
H
<30 s
H
RECEIVER STATUS
Powered off
Normal operation with
auto-powerdown plus
disabled/enabled
H = high level, L = low level, X = irrelevant, Z = high impedance (off), Open = input disconnected or connected driver off.
Table 3. INVALID (1)
INPUTS
(1)
14
OUTPUT
RIN1 – RIN5
FORCEON
FORCEOFF
TIME ELAPSED SINCE LAST
RIN OR DIN TRANSITION
Any L or H
X
X
X
H
All Open
X
X
X
L
INVALID
H = high level, L = low level, X = irrelevant, Z = high impedance (off), Open = input disconnected or connected driver off.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This device can be used in any application where an RS232 line driver or receiver is required. One benefit of this
device is its ESD protection, which helps protect other components on the board when the RS232 lines are tied
to a physical connector.
9.2 Typical Application
ROUT and DIN connect to UART or general purpose logic lines. FORCEON and FORCEOFF may be connected
general purpose logic lines or tied to ground or VL. INVALID may be connected to a general purpose logic line or
left unconnected. RIN and DOUT lines connect to a RS232 connector or cable. DIN, FORCEON, and
FORCEOFF inputs must not be left unconnected. For proper operation, add capacitors as shown in Figure 8.
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Typical Application (continued)
C1+
C2
C4
+
C2+
-
C2-
V+
VCC
V-
-
+
C1
C1RIN1
FORCEON
AutoPowerdown
Plus
RIN2
RS-232 Inputs
+
-
+ CBYPASS
- = 0.1 μF
GND
+
C3†
RIN3
RIN4
FORCEOFF
RIN5
INVALID
DOUT1
RS-232 Outputs
DOUT2
ROUT1
5 kΩ
ROUT2
DOUT3
5 kΩ
DIN3
ROUT3
Logic Outputs
5 kΩ
Logic Inputs
DIN2
ROUT4
5 kΩ
ROUT5
DIN1
5 kΩ
†
C3 can be connected to VCC or GND.
NOTES: A. Resistor values shown are nominal.
B. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or
electrolytic capacitors are used, they should be connected as shown.
VCC vs CAPACITOR VALUES
VCC
C1
C2, C3, and C4
3.3 V ± 0.3 V
5 V ± 0.5 V
3 V to 5.5 V
0.1 μF
0.047 μF
0.1 μF
0.1 μF
0.33 μF
0.47 μF
Figure 8. Typical Operating Circuit and Capacitor Values
9.2.1 Design Requirements
•
•
•
.
Recommended VCC is 3.3 V or 5 V. 3 V to 5.5 V is also possible
Maximum recommended bit rate is 1000 kbps
Use capacitors as shown in Figure 8
9.2.2 Detailed Design Procedure
•
•
All DIN, FORCEOFF, and FORCEON inputs must be connected to valid low or high logic levels.
Select capacitor values based on VCC level for best performance.
9.2.3 Application Curve
Driver input as top waveform and driver output as bottom waveform.
•
•
16
3.3-V VCC
1000-kbit/s data rate
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Typical Application (continued)
•
200-pF and 3-kΩ Load
Figure 9. 1000-kbps Driver Timing Waveform
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10 Power Supply Recommendations
VCC must be between 3.3 and 5 V. Capacitors must be selected according to the table in Figure 8.
11 Layout
11.1 Layout Guidelines
Keep the external capacitor traces short. This is more important on C1 and C2 nodes that have the fastest rise
and fall times.
11.2 Layout Example
C3
VCC
Ground
PF
27
26
C1
32
31
30
29
28
25
1
24
2
23
3
22
C2
Ground
C4
4
21
GROUND
5
20
6
19
7
18
8
17
9
10
11
12
13
14
15
16
PF
VL
Ground
Figure 10. Layout Diagram
18
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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PACKAGE OPTION ADDENDUM
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21-Feb-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
TRS3253EIRSMR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN
RSM
32
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
RS53EI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Feb-2017
OTHER QUALIFIED VERSIONS OF TRS3253E :
• Enhanced Product: TRS3253E-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Feb-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TRS3253EIRSMR
Package Package Pins
Type Drawing
VQFN
RSM
32
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
4.25
B0
(mm)
K0
(mm)
P1
(mm)
4.25
1.15
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Feb-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TRS3253EIRSMR
VQFN
RSM
32
3000
367.0
367.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RSM 32
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4 x 4, 0.4 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224982/A
www.ti.com
PACKAGE OUTLINE
RSM0032B
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
B
4.1
3.9
A
0.45
0.25
0.25
0.15
DETAIL
PIN 1 INDEX AREA
OPTIONAL TERMINAL
TYPICAL
4.1
3.9
(0.1)
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2.8 0.05
2X 2.8
(0.2) TYP
4X (0.45)
9
16
28X 0.4
8
SEE SIDE WALL
DETAIL
17
EXPOSED
THERMAL PAD
2X
2.8
SEE TERMINAL
DETAIL
PIN 1 ID
(OPTIONAL)
SYMM
33
24
1
32X
32
25
SYMM
32X
0.25
0.15
0.1
0.05
C A B
0.45
0.25
4219108/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 2.8)
SYMM
32
25
32X (0.55)
1
32X (0.2)
24
( 0.2) TYP
VIA
(1.15)
SYMM
33
(3.85)
28X (0.4)
17
8
(R0.05)
TYP
9
(1.15)
16
(3.85)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219108/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.715)
4X ( 1.23)
25
32
(R0.05) TYP
32X (0.55)
1
24
32X (0.2)
(0.715)
33
SYMM
(3.85)
28X (0.4)
17
8
METAL
TYP
16
9
SYMM
(3.85)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 33:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219108/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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