Texas Instruments | SN65HVD3x 3.3-V Full-Duplex RS-485 Drivers and Receivers (Rev. L) | Datasheet | Texas Instruments SN65HVD3x 3.3-V Full-Duplex RS-485 Drivers and Receivers (Rev. L) Datasheet

Texas Instruments SN65HVD3x 3.3-V Full-Duplex RS-485 Drivers and Receivers (Rev. L) Datasheet
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SN65HVD30, SN65HVD31, SN65HVD32
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SN65HVD3x 3.3-V Full-Duplex RS-485 Drivers and Receivers
1 Features
3 Description
•
The SN65HVD3x devices are 3-state differential line
drivers and differential-input line receivers that
operate with 3.3-V power supply.
1
•
•
•
•
•
•
•
•
•
1/8 Unit-Load Option Available
(Up to 256 Nodes on the Bus)
Bus-Pin ESD Protection Exceeds 15-kV HBM
Optional Driver Output Transition Times for
Signaling Rates of 1 Mbps, 5 Mbps and 26 Mbps
– Line Signaling Rate is the Number of Voltage
Transitions Made per Second Expressed in
Units of bps (bits per second)
Low-Current Standby Mode: <1 μA
Glitch-Free Power-Up and Power-Down Protection
for Hot-Plugging Applications
5-V Tolerant Inputs
Bus Idle, Open, and Short-Circuit Failsafe
Driver Current Limiting and Thermal Shutdown
Designed for RS-422 and RS-485 Networks
5-V Devices Available, SN65HVD50-55
Each driver and receiver has separate input and
output pins for full-duplex bus communication
designs. They are designed for RS-422 and RS-485
data transmission over cable lengths of up to
1500 meters.
The SN65HVD30, SN65HVD31, and SN65HVD32
devices are fully enabled with no external enabling
pins.
The SN65HVD33, SN65HVD34, and SN65HVD35
devices have active-high driver enables and activelow receiver enables. A low, less than 1 μA, standby
current can be achieved by disabling both the driver
and receiver.
All devices are characterized for ambient
temperatures from –40°C to 85°C. Low power
dissipation allows operation at temperatures up to
105°C or 125°C, depending on package option.
2 Applications
•
•
•
•
Utility Meters
DTE and DCE Interfaces
Industrial, Process, and Building Automation
Point-of-Sale (POS) Pins and Networks
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN65HVD30
SN65HVD31
SOIC (8)
4.90 mm × 3.91 mm
SOIC (14)
8.65 mm × 3.91 mm
VQFN (20)
4.50 mm × 3.50 mm
SOIC (14)
8.65 mm × 3.91 mm
SN65HVD32
SN65HVD33
SN65HVD34
SN65HVD35
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
Y
R
D
Z
A
RT
RT
B
R
R
DE
RE
Master
RE
D
Slave
B
R
A
DE
Z
RT
RT
A
B
Z
Y
D
D
Y
R Slave
D
R RE DE D
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN65HVD30, SN65HVD31, SN65HVD32
SN65HVD33, SN65HVD34, SN65HVD35
SLLS665L – SEPTEMBER 2005 – REVISED JANUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8
9
1
1
1
2
4
5
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics: Driver ............................... 8
Electrical Characteristics: Receiver .......................... 9
Device Power Dissipation – PD ................................ 9
Supply Current Characteristics ............................... 10
Switching Characteristics: Driver ............................ 10
Switching Characteristics: Receiver...................... 11
Dissipation Ratings ............................................... 12
Typical Characteristics .......................................... 12
Parameter Measurement Information ................ 15
Detailed Description ............................................ 20
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
20
20
20
24
10 Application and Implementation........................ 26
10.1 Application Information.......................................... 26
10.2 Typical Application ............................................... 26
11 Power Supply Recommendations ..................... 31
12 Layout................................................................... 31
12.1 Layout Guidelines ................................................. 31
12.2 Layout Example .................................................... 31
13 Device and Documentation Support ................. 32
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Third-Party Products Disclaimer ...........................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
32
32
14 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (October 2015) to Revision L
•
Page
Changed text From: "defaults to Y high and Z low" To: "defaults to Y low and Z high" in the Low-Power Standby
Mode section ........................................................................................................................................................................ 20
Changes from Revision J (July 2015) to Revision K
Page
•
Changed device listing in the Device Information table to match the Package Option Addendum listing. ........................... 1
•
Changed device listing in the Pinout Configuration section to match the Package Option Addendum listing....................... 5
•
Changed device listing in the Thermal Information table to match the Package Option Addendum listing........................... 7
Changes from Revision I (April 2010) to Revision J
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision H (May 2009) to Revision I
Page
•
Changed wording of 3rd sentence of Description .................................................................................................................. 1
•
Changed the labels in the SN65HVD3x Drivers Operate Correctly After Bus Contention Faults image ............................. 23
2
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SN65HVD33, SN65HVD34, SN65HVD35
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SLLS665L – SEPTEMBER 2005 – REVISED JANUARY 2017
Changes from Revision G (December 2008) to Revision H
Page
•
Added explanatory notes for pin 6 and pin 13 to the 14-Pin SOIC ........................................................................................ 5
•
Added explanatory notes for pin 1 and pin 10 to the 20-Pin VQFN ....................................................................................... 5
•
Added Supply current typical value of 3.8 mA for SN65HVD31, SN65HVD3 in the Supply Current Characteristics table . 10
•
Changed characteristic graph for Figure 6 .......................................................................................................................... 12
•
Changed characteristic graph for Figure 7 .......................................................................................................................... 12
•
Added subsection Safe Operation With Bus Contention...................................................................................................... 22
Changes from Revision F (July 2008) to Revision G
Page
•
Changed From: 5-V Devices Available, SN65HVD50-59 To: 5-V Devices Available, SN65HVD50-55 in the Features ....... 1
•
Deleted SN65HVD36 and SN65HVD37 from the Description................................................................................................ 1
•
Deleted SN65HVD38 and SN65HVD39 from the Description................................................................................................ 1
•
Deleted last 2 paragraphs of Description ............................................................................................................................... 1
•
Deleted SN65HVD36, SN65HVD37 from the 8-Pin SOIC ..................................................................................................... 5
•
Deleted SN65HVD36, SN65HVD37 from the the 14-Pin SOIC ............................................................................................. 5
•
Deleted devices SN65HVD36, SN65HVD38 from the Recommended Operating Conditions ............................................... 7
•
Deleted devices SN65HVD37, SN65HVD39 from the Recommended Operating Conditions ............................................... 7
•
Deleted all HVD36, HVD38, HVD37, HVD39 from the Electrical Characteristics: Driver table.............................................. 8
•
Added added last sentence to note 4 in the Electrical Characteristics: Driver table.............................................................. 8
•
Deleted all HVD36, HVD38, HVD37, HVD39 from the Electrical Characteristics: Receiver table ......................................... 9
•
Deleted all HVD36, HVD38, HVD37, HVD39 rows from the Supply Current Characteristics table ..................................... 10
•
Deleted all HVD36, HVD38, HVD37, HVD39 from the Switching Characteristics: Driver table........................................... 10
•
Deleted HVD36, HVD38, HVD37, and HVD39 from the Switching Characteristics: Receiver table.................................... 11
•
Deleted Receiver Equalization Characteristics table............................................................................................................ 12
•
Added subsection Driver Output Current Limiting ................................................................................................................ 21
•
Added subsection Hot-Plugging ........................................................................................................................................... 21
•
Added subsection Receiver Failsafe .................................................................................................................................... 22
•
Deleted SN65HVD38 and SN65HVD39 from Table 3 title ................................................................................................... 24
•
Deleted SN65HVD38 and SN65HVD39 from Table 4 title ................................................................................................... 24
•
Deleted SN65HVD36 and SN65HVD37 from Table 5 title ................................................................................................... 24
•
Deleted SN65HVD36 and SN65HVD37 from Table 6 title ................................................................................................... 24
•
Deleted SN65HVD36 and SN65HVD37 from first row of Table 7........................................................................................ 25
•
Deleted SN65HVD37, SN65HVD38 and SN65HVD39 from second row of Table 7 ........................................................... 25
Changes from Revision E (March 2008) to Revision F
Page
•
Changed From: Meets or Exceeds the Requirements of ANSI TIA/EIA-485-A and RS-422 Compatible To: Designed
for RS-422 and RS-485 Networks in the Features................................................................................................................. 1
•
Added Table Note 4 in the Electrical Characteristics: Driver table......................................................................................... 8
Changes from Revision D (January 2008) to Revision E
•
Page
Changed spelling From: termperatures To: temperatures ..................................................................................................... 1
Copyright © 2005–2017, Texas Instruments Incorporated
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3
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SN65HVD33, SN65HVD34, SN65HVD35
SLLS665L – SEPTEMBER 2005 – REVISED JANUARY 2017
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5 Device Comparison
Table 1. Device Features
BASE
PART NUMBER
SIGNALING RATE
UNIT LOADS
ENABLES
SN65HVD30
26 Mbps
1/2
No
SN65HVD31
5 Mbps
1/8
No
SN65HVD32
1 Mbps
1/8
No
SN65HVD33
26 Mbps
1/2
Yes
SN65HVD34
5 Mbps
1/8
Yes
SN65HVD35
1 Mbps
1/8
Yes
Table 2. Improved Replacement for Devices
PART NUMBER
REPLACE WITH
BENEFITS
MAX3491
MAX3490
SN65HVD33
SN65HVD30
Better ESD protection (15 kV versus 2 kV, or not specified) Higher Signaling Rate
(26 Mbps versus 10 Mbps) Fractional Unit Load (64 Nodes versus 32)
MAX3491E
MAX3490E
SN65HVD33
SN65HVD30
Higher Signaling Rate (26 Mbps versus 12 Mbps) Fractional Unit Load (64 Nodes versus 32)
MAX3076E
MAX3077E
SN65HVD33
SN65HVD30
Higher Signaling Rate (26 Mbps versus 16 Mbps) Lower Standby Current (1 μA versus 10 μA)
MAX3073E
MAX3074E
SN65HVD34
SN65HVD31
Higher Signaling Rate (5 Mbps versus 500 kbps) Lower Standby Current (1 μA versus 10 μA)
MAX3070E
MAX3071E
SN65HVD35
SN65HVD32
Higher Signaling Rate (1 Mbps versus 250 kbps) Lower Standby Current (1 μA versus 10 μA)
4
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SN65HVD33, SN65HVD34, SN65HVD35
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SLLS665L – SEPTEMBER 2005 – REVISED JANUARY 2017
6 Pin Configuration and Functions
SN65HVD30, SN65HVD31, SN65HVD32, D Package
8-Pin SOIC
Top View
VCC
R
D
GND
R
D
1
8
2
7
3
6
4
5
SN65HVD33, SN65HVD34, SN65HVD35 D Package
14-Pin SOIC
Top View
A
B
Z
Y
8
2
A
7
B
5
3
NC
R
RE
DE
D
GND
GND
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
VCC
A
B
Z
Y
NC
NC - No internal connection
Pins 6 and 7 are connected together internally
Pins 13 and 14 are connected together internally
Y
6
1
Z
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
SN65HVD33 RHL Package
20-Pin VQFN
Top View
VCC
NC
2
R
VCC
19
NC
3
18
A
RE
4
17
B
NC
5
16
NC
DE
6
15
Z
D
7
14
Y
NC
8
13
NC
NC
9
1
20
10
11
GND
GND
12
NC
R
RE
DE
D
3
18
17
4
A
B
6
7
14
15
Y
Z
NC - No internal connection
Pins 10 and 11 are connected together internally
Pins 1 and 20 are connected together internally
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2005–2017, Texas Instruments Incorporated
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Pin Functions
PIN
D
(8-Pins)
D
(14-Pins)
RHL
(20-Pins)
TYPE
A
8
12
18
Bus input
Receiver input (complementary to B)
B
7
11
17
Bus input
Receiver input (complementary to A)
D
3
5
7
Digital input
Driver data input
DE
—
4
6
Digital input
Driver enable, active high
Local device ground
No connect; must be left floating
NAME
DESCRIPTION
GND
4
6, 7
10, 11
Reference
potential
NC
—
1, 8
2, 5, 8,
9, 12,
13, 16, 19
No connect
R
2
2
3
Digital output
Receive data output
RE
—
3
4
Digital output
Receiver enable, active low
VCC
1
13, 14
1, 20
Supply
Y
5
9
14
Bus output
Driver output (complementary to Z)
Z
6
10
15
Bus output
Driver output (complementary to Y)
3-V to 3.6-V supply
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted (1) (2)
MIN
MAX
UNIT
–0.3
6
V
–9
14
V
V
VCC
Supply voltage
V(A), V(B),
V(Y), V(Z)
Voltage at any bus terminal (A, B, Y, Z)
V(TRANS)
Voltage input, transient pulse through 100 Ω. See Figure 28 (A, B, Y, Z) (3)
–50
50
VI
Input voltage (D, DE, RE)
–0.5
7
V
IO
Output current (receiver output only, R)
11
mA
Tstg
Storage Temperature
125
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
This tests survivability only and the output state of the receiver is not specified.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001 (1)
Bus pins and GND
±16000
All pins
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101
(1)
(2)
6
(2)
UNIT
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SLLS665L – SEPTEMBER 2005 – REVISED JANUARY 2017
7.3 Recommended Operating Conditions
over operating free-air temperature range unless otherwise noted
MIN
VCC
Supply voltage
VI or VIC
Voltage at any bus pin (separately or common mode)
NOM
3
3.6
V
12
V
26
SN65HVD31, SN65HVD34
5
Signaling rate
RL
Differential load resistance
VIH
High-level input voltage
D, DE, RE
VIL
Low-level input voltage
D, DE, RE
VID
Differential input voltage
SN65HVD32, SN65HVD35
IOH
High-level output current
IOL
Low-level output current
TJ
Junction temperature
UNIT
–7 (1)
SN65HVD30, SN65HVD33
1/tUI
(1)
MAX
Mbps
1
54
Driver
Ω
60
2
VCC
V
0
0.8
V
–12
12
V
–60
Receiver
mA
–8
Driver
60
Receiver
mA
8
–40
150
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
7.4 Thermal Information
THERMAL METRIC
(1)
SN65HVD30,
SN65HVD31,
SN65HVD32
SN65HVD33,
SN65HVD34,
SN65HVD35
SN65HVD33
D
(SOIC)
D
(SOIC)
RHL
(VQFN)
UNIT
8 PINS
14 PINS
20 PINS
RθJA
Junction-to-ambient thermal resistance
135
92
73
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
43
59
14
°C/W
RθJB
Junction-to-board thermal resistance
44
61
13.7
°C/W
ψJT
Junction-to-top characterization parameter
12.1
5.7
0.5
°C/W
ψJB
Junction-to-board characterization parameter
49.7
30.7
13.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
2.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics: Driver
over recommended operating conditions unless otherwise noted
PARAMETER
VI(K)
MIN TYP (1)
TEST CONDITIONS
Input clamp voltage
II = –18 mA
MAX
–1.5
V
IO = 0
2.5
RL = 54 Ω, See Figure 17 (RS-485)
1.5
2
2
2.3
|VOD(SS)|
Steady-state differential output voltage
Δ|VOD(SS)|
Change in magnitude of steady-state
differential output voltage between
states
RL = 54 Ω, See Figure 17 and Figure 18
VOD(RING)
Differential Output Voltage overshoot
and undershoot
RL = 54 Ω, CL = 50 pF, See Figure 21 and
Figure 19
RL = 100 Ω, See Figure 17, (2) (RS-422)
Vtest = –7 V to 12 V, See Figure 18
UNIT
VCC
V
1.5
–0.2
0.2
V
10% (3)
V
SN65HVD30,
SN65HVD33
See Figure 20
0.5
SN65HVD31,
SN65HVD34,
SN65HVD32,
SN65HVD35
See Figure 20
0.25
VOC(SS)
Steady-state common-mode output
voltage
See Figure 20
1.6
2.3
V
ΔVOC(SS)
Change in steady-state common-mode
output voltage
See Figure 20
–0.05
0.05
V
Peak-to-peak
common-mode
output voltage
VOC(PP)
SN65HVD30,
SN65HVD31,
SN65HVD32
IZ(Z) or
IY(Z)
High-impedance
state output current
SN65HVD33,
SN65HVD34,
SN65HVD35
IZ(S) or
IY(S)
Short Circuit output current
II
Input current
C(OD)
Differential output capacitance
(1)
(2)
(3)
(4)
8
(4)
V
VCC = 0 V, VZ or VY = 12 V,
Other input at 0 V
90
VCC = 0 V, VZ or VY = –7 V,
Other input at 0 V
–10
VCC = 3 V or 0 V, DE = 0 V
VZ or VY = 12 V
Other input at 0 V
90
VCC = 3 V or 0 V, DE = 0 V
VZ or VY = –7 V
Other input at 0 V
μA
–10
VZ or VY = –7 V
Other input at 0 V
–250
250
VZ or VY = 12 V
Other input at 0 V
–250
250
mA
D, DE
0
VOD = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
100
16
μA
pF
All typical values are at 25°C and with a 3.3-V supply.
VCC is 3.3 VDC ± 5%.
10% of the peak-to-peak differential output voltage swing, per TIA/EIA-485.
Under some conditions of short-circuit to negative voltages, output currents exceeding the ANSI TIA/EIA-485-A maximum current of 250
mA may occur. Continuous exposure can affect device reliability. This applies to the SN65HVD30, SN65HVD31, SN65HVD33, and
SN65HVD34.
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SLLS665L – SEPTEMBER 2005 – REVISED JANUARY 2017
7.6 Electrical Characteristics: Receiver
over recommended operating conditions unless otherwise noted
PARAMETER
VIT+
Positive-going differential input threshold
voltage
IO = –8 mA
VIT-
Negative-going differential input threshold
voltage
IO = 8 mA
Vhys
Hysteresis voltage (VIT+ – VIT–)
VIK
Enable-input clamp voltage
Output voltage
IO(Z)
High-impedance-state output current
UNIT
–0.02
V
V
50
II = –18 mA
V
2.4
0.4
VO = 0 or VCC, RE at VCC
Bus input current
SN65HVD30,
SN65HVD33
mV
–1.5
VID = –200 mV, IO = 8 mA, See Figure 24
SN65HVD31,
SN65HVD32,
SN65HVD34,
SN65HVD35
–1
1
VA or VB = 12 V
Other input at 0 V
0.05
0.1
VA or VB = 12 V, VCC = 0 V
Other input at 0 V
0.06
0.1
–0.10
–0.04
VA or VB = –7 V, VCC = 0 V
Other input at 0 V
–0.10
–0.03
VA or VB = 12 V
Other input at 0 V
0.20
0.35
VA or VB = 12 V, VCC = 0 V
Other input at 0 V
0.24
0.4
–0.35
–0.18
VA or VB = –7 V, VCC = 0 V
Other input at 0 V
–0.25
–0.13
Input current, RE
VIH = 0.8 V or 2 V
Differential input capacitance
VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
μA
mA
VA or VB = –7 V
Other input at 0 V
CID
V
mA
VA or VB = –7 V
Other input at 0 V
IIH
(1)
MAX
–0.20
VID = 200 mV, IO = –8 mA, See Figure 24
VO
IA or
IB
MIN TYP (1)
TEST CONDITIONS
–60
μA
15
pF
All typical values are at 25°C and with a 3.3-V supply.
7.7 Device Power Dissipation – PD
PARAMETER
PD
TSD
Power Dissipation (worst case)
Driver and receiver enabled, 50% duty
cycle square-wave signal at signaling
rate:
SN65HVD30, SN65HVD33 at 25 Mbps,
SN65HVD31, SN65HVD34 at 5 Mbps,
SN65HVD32, SN65HVD35 at 1 Mbps
TEST CONDITIONS
MIN
TYP
MAX
SN65HVD30,
SN65HVD33
VCC = 3.6 V, TJ = 140°C,
RL = 54 Ω, CL = 50 pF (driver),
CL = 15 pF (receiver)
197
SN65HVD31,
SN65HVD34
VCC = 3.6 V, TJ = 140°C,
RL = 54 Ω, CL = 50 pF (driver),
CL = 15 pF (receiver)
213
SN65HVD32,
SN65HVD35
VCC = 3.6 V, TJ = 140°C,
RL = 54 Ω, CL = 50 pF (driver),
CL = 15 pF (receiver)
248
Thermal Shut-down Junction Temperature
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170
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UNIT
mW
°C
9
SN65HVD30, SN65HVD31, SN65HVD32
SN65HVD33, SN65HVD34, SN65HVD35
SLLS665L – SEPTEMBER 2005 – REVISED JANUARY 2017
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7.8 Supply Current Characteristics
over recommended operating conditions unless otherwise noted
PARAMETER
SN65HVD30
SN65HVD31, SN65HVD32
SN65HVD33
SN65HVD34, SN65HVD35
ICC
Supply current
MIN
TYP (1)
SN65HVD34, SN65HVD35
SN65HVD33
SN65HVD34, SN65HVD35
MAX
2.1
D at 0 V or VCC and No Load
3.8
6.4
1.8
RE at 0 V, D at 0 V or VCC, DE at 0 V,
No load (Receiver enabled and driver disabled)
2.2
RE at VCC, D at VCC, DE at 0 V,
SN65HVD33, SN65HVD34,
No load (Receiver disabled and driver
SN65HVD35
disabled)
SN65HVD33
(1)
TEST CONDITIONS
0.022
1
RE at 0 V, D at 0 V or VCC, DE at VCC,
No load (Receiver enabled and driver enabled)
2.1
RE at VCC, D at 0 V or VCC, DE at VCC
No load (Receiver disabled and driver enabled)
1.8
6.5
6.2
UNIT
mA
mA
μA
mA
mA
All typical values are at 25°C and with a 3.3-V supply.
7.9 Switching Characteristics: Driver
over recommended operating conditions unless otherwise noted
PARAMETER
tPLH
tPHL
tr
(1)
10
MAX
4
10
18
Propagation delay time, low-to-high-level SN65HVD31,
output
SN65HVD34
25
38
65
SN65HVD32,
SN65HVD35
120
175
305
SN65HVD30,
SN65HVD33
4
9
18
Propagation delay time, high-to-low-level SN65HVD31,
output
SN65HVD34
25
38
65
SN65HVD32,
SN65HVD35
120
175
305
SN65HVD30,
SN65HVD33
2.5
5
12
20
37
60
SN65HVD32,
SN65HVD35
120
185
300
SN65HVD30,
SN65HVD33
2.5
5
12
SN65HVD31,
SN65HVD34
20
35
60
SN65HVD32,
SN65HVD35
120
180
300
Differential output signal fall time
tsk(p)
MIN TYP (1)
SN65HVD30,
SN65HVD33
Differential output signal rise time
tf
TEST CONDITIONS
Pulse skew (|tPHL – tPLH|)
SN65HVD31,
SN65HVD34
RL = 54 Ω, CL = 50 pF,
See Figure 21
SN65HVD30,
SN65HVD33
0.6
SN65HVD31,
SN65HVD34
2.0
SN65HVD32,
SN65HVD35
5.1
UNIT
ns
ns
ns
ns
ns
All typical values are at 25°C and with a 3.3-V supply.
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SLLS665L – SEPTEMBER 2005 – REVISED JANUARY 2017
Switching Characteristics: Driver (continued)
over recommended operating conditions unless otherwise noted
PARAMETER
tPZH1
TEST CONDITIONS
SN65HVD33
Propagation delay time, high-impedanceSN65HVD34
to-high-level output
SN65HVD35
SN65HVD33
Propagation delay time, high-level-tohigh-impedance output
tPHZ
tPZL1
SN65HVD34
MAX
RL = 110 Ω, RE at 0 V,
D = 3 V and S1 = Y, or
D = 0 V and S1 = Z
See Figure 22
25
65
SN65HVD33
Propagation delay time, high-impedanceSN65HVD34
to-low-level output
SN65HVD35
35
SN65HVD34
ns
490
165
SN65HVD33
UNIT
45
235
SN65HVD35
Propagation delay time, low-level-tohigh-impedance output
tPLZ
MIN TYP (1)
190
RL = 110 Ω, RE at 0 V,
D = 3 V and S1 = Z, or
D = 0 V and S1 = Y
See Figure 23
ns
ns
490
30
120
SN65HVD35
ns
290
tPZH1,
tPZL1
Driver enable delay with bus voltage offset
VO= 2 V (Typ)
tPZH2
Propagation delay time, standby-to-high-level output
tPZL2
Propagation delay time, standby-to-low-level output
500
900
ns
RL = 110 Ω, RE at 3 V,
D = 3 V and S1 = Y, or
D = 0 V and S1 = Z
See Figure 22
4000
ns
RL = 110 Ω, RE at 3 V,
D = 3 V and S1 = Z, or
D = 0 V and S1 = Y
See Figure 23
4000
ns
7.10 Switching Characteristics: Receiver
over recommended operating conditions unless otherwise noted
MIN TYP (1)
MAX
SN65HVD30, SN65HVD33
26
45
ns
SN65HVD31, SN65HVD32,
SN65HVD34, SN65HVD35
47
70
ns
SN65HVD30, SN65HVD33
29
45
ns
49
70
ns
7
ns
10
ns
PARAMETER
tPLH
Propagation delay time,
low-to-high-level output
tPHL
Propagation delay time,
high-to-low-level output
SN65HVD31, SN65HVD32,
SN65HVD34, SN65HVD35
SN65HVD30, SN65HVD33
TEST CONDITIONS
VID = –1.5 V to 1.5 V,
CL = 15 pF, See Figure 25
UNIT
tsk(p)
Pulse skew (|tPHL – tPLH|)
tr
Output signal rise time
5
ns
tf
Output signal fall time
6
ns
tPHZ
Output disable time from high level
20
ns
tPZH1
Output enable time to high level
20
ns
tPZH2
Propagation delay time, standby-to-high-level output
4000
ns
tPLZ
Output disable time from low level
20
ns
20
ns
4000
ns
SN65HVD31, SN65HVD34,
SN65HVD32, SN65HVD35
tPZL1
Output enable time to low level
tPZL2
Propagation delay time, standby-to-low-level output
(1)
DE at 3 V
CL = 15 pF,
See Figure 26
DE at 0 V
DE at 3 V
CL = 15 pF,
See Figure 27
DE at 0 V
All typical values are at 25°C and with a 3.3-V supply.
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7.11 Dissipation Ratings
PACKAGE
JEDEC THERMAL
MODEL
TA < 25°C
RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
RATING
Low k
625 mW
5 mW/°C
325 mW
High k
1000 mW
8 mW/°C
520 mW
360 mW
Low k
765 mW
6.1 mW/°C
400 mW
275 mW
High k
1350 mW
10.8 mW/°C
705 mW
485 mW
270 mW
High k
1710 mW
13.7 mW/°C
890 mW
6150 mW
340 mW
8-pin D (SOIC)
14-pin D (SOIC)
20-pin RHL
(VQFN)
TA = 105°C
RATING
TA = 125°C
RATING
7.12 Typical Characteristics
55
60
TA = 25°C RL = 54 W
RE = VCC CL = 50 pF
DE = VCC
55
ICC - RMS Supply Current - mA
50
ICC - RMS Supply Current - mA
TA =25°C RL = 54 W
RE = VCC CL = 50 pF
DE = VCC
45
VCC = 3.3 V
40
35
50
VCC = 3.3 V
45
40
35
30
30
0
5
10
15
20
25
0
1
Signaling Rate - Mbps
2
3
4
5
Signaling Rate - Mbps
Figure 1. SN65HVD30, SN65HVD33
RMS Supply Current vs Signaling Rate
Figure 2. SN65HVD31, SN65HVD34
RMS Supply Current vs Signaling Rate
250
60
TA =25°C RL = 54 W
RE = VCC CL = 50 pF
DE = VCC
55
200
TA = 25°C
RE = 0 V
DE = 0 V
II - Bus Input Current - mA
ICC - RMS Supply Current - mA
150
50
VCC = 3.3 V
45
40
100
50
VCC = 3.3 V
0
–50
–100
35
–150
30
0
12
0.2
0.4
0.6
0.8
1
–200
–7
–4
–1
2
5
8
11
Signaling Rate - Mbps
VI - Bus Input Voltage - V
Figure 3. SN65HVD32, SN65HVD35
RMS Supply Current vs Signaling Rate
Figure 4. SN65HVD30, SN65HVD33
Bus Input Current vs Input Voltage
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SLLS665L – SEPTEMBER 2005 – REVISED JANUARY 2017
Typical Characteristics (continued)
3.5
60
VO - Driver Output Voltage - V
TA = 25°C
RE = 0 V
DE = 0 V
II - Bus Input Current - uA
40
20
0
VCC = 3.3 V
-20
VCC = 3.3 V,
DE = VCC,
D=0V
VOH
3
2.5
2
1.5
VOL
1
-40
0.5
-60
-7
-4
-1
2
5
8
11
0
0
14
20
40
60
80
IO - Driver Output Current - mA
VI - Bus Input Voltage - V
Figure 5. SN65HVD31, SN65HVD32, SN65HVD34,
SN65HVD35
Bus Input Current vs Input Voltage
Figure 6. Driver Output Voltage vs Driver Output Current
2.5
3.5
100 W
VCC = 3.3 V,
DE = VCC,
D=0V
60 W
3
2.4
3.6 V
RL = 60 W
2.3
VOD - Differential Output Voltage - V
VO - Driver Differential Output Voltage - V
100
2.5
2
1.5
1
2.2
3.3 V
2.1
2
1.9
3V
1.8
1.7
0.5
1.6
1.5
0
0
20
40
60
80
IO - Driver Output Current - mA
-60
100
-20
0
20
40
60
80 90
o
TA − Free-Air Temperature − C
Figure 8. Driver Differential Output Voltage
vs Free-Air Temperature
Figure 7. Driver Differential Output Voltage
vs Driver Output Current
14
40
TA = 25°C
RL = 54 W
D = VCC
DE = VCC
35
30
13
12
Driver Propagation Delay - ns
IO - Driver Output Current - mA
-40
25
20
15
10
5
3V
11
3.6 V
10
9
8
7
0
6
0
0.5
1
1.5
2
2.5
3
3.5
VCC Supply Voltage - V
Figure 9. Driver Output Current vs Supply Voltage
Copyright © 2005–2017, Texas Instruments Incorporated
-60
-40
-20
0
20
40
60
80 90
o
TA − Free-Air Temperature − C
Figure 10. SN65HVD30, SN65HVD33
Driver Propagation Delay vs Free-Air Temperature
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Typical Characteristics (continued)
0.00
5
−0.02
4.5
4
3.6 V
3.5
3
VIT+
−0.06
Receiver Threshold − V
Driver Rise/Fall Time - ns
−0.04
3V
−0.08
−0.10
VIT−
−0.12
−0.14
−0.16
2.5
−0.18
2
-60
-40
-20
0
20
40
60
−0.20
−50
80 90
−25
o
TA − Free-Air Temperature − C
0
25
50
75
100
125
TA − Ambient Temperature − °C
Figure 11. SN65HVD30, SN65HVD33
Driver Rise and Fall Time vs Free-Air Temperature
Figure 12. Receiver Threshold vs Ambient Temperature
0.00
1.4
−0.02
1.2
3.6 V
VIT+
−0.06
−0.08
−0.10
VIT−
−0.12
1
ICC - Supply Current - mA
Receiver Threshold − V
−0.04
−0.14
3V
0.8
0.6
0.4
Static,
No Load
−0.16
0.2
−0.18
−0.20
−7
−5
−3
−1
1
3
5
7
9
0
-60
11
-40
VCM − Common-Mode Voltage − V
-20
0
20
40
60
80 90
o
TA − Free-Air Temperature − C
Figure 13. Receiver Threshold vs Common-Mode Voltage
Figure 14. Supply Current vs Free-Air Temperature
800
700
HVD35
Enable Time − ns
600
500
HVD34
400
300
200
HVD33
100
0
-7
-2
3
8
13
V(TEST) − Common-Mode Voltage − V
Figure 15. Enable Time vs Common-Mode Voltage
(see Figure 16)
14
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SLLS665L – SEPTEMBER 2005 – REVISED JANUARY 2017
8 Parameter Measurement Information
375 W ± 1%
Y
-7 V < V(TEST) < 12 V
D
0 or 3 V
60 W
± 1%
VOD
Z
DE
375 W ± 1%
Input
Generator
V
50 W
50%
tpZH(diff)
VOD (high)
1.5 V
0V
tpZL(diff)
-1.5 V
VOD (low)
Copyright © 2017, Texas Instruments Incorporated
The time tpZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
Figure 16. Driver Enable Time From DE to VOD
VCC
DE
II
Y
IY
VOD
0 or 3 V
Z
RL
IZ
VI
VZ
VY
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Figure 17. Driver VOD Test Circuit and Voltage and Current Definitions
375 Ω ±1%
VCC
DE
D
Y
VOD
0 or 3 V
60 Ω ±1%
+
_ −7 V < V(test) < 12 V
Z
375 Ω ±1%
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Figure 18. Driver VOD With Common-Mode Loading Test Circuit
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Parameter Measurement Information (continued)
VOD(SS)
VOD(RING)
0 V Differential
VOD(RING)
–VOD(SS)
Figure 19. VOD(RING) Waveform and Definitions
VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from
the VOD(H) and VOD(L) steady state values.
VCC
DE
Input
D
27 Ω ± 1%
Y
Y
VY
Z
VZ
VOC(PP)
Z
27 Ω ± 1%
CL = 50 pF ±20%
VOC
∆VOC(SS)
VOC
CL Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,t r <6ns, t f <6ns, ZO = 50 Ω
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Figure 20. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Y
W
Z
»
W
»
W
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Figure 21. Driver Switching Test Circuit and Voltage Waveforms
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SLLS665L – SEPTEMBER 2005 – REVISED JANUARY 2017
Parameter Measurement Information (continued)
D
3V
0V
3V
S1
Y
Z
Y
S1
D
VO
1.5 V
1.5 V
VI
0.5 V
t PZH(1 & 2)
Z
0V
V OH
DE
Input
Generator
VI
50 W
RL = 110 W
±1%
CL = 50 pF
±20%
VO
2.3 V
~0V
tPHZ
Generator: PRR = 50 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Z 0 = 50 W
CL Includes Fixture and Instrumentation Capacitance
Figure 22. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
D
3V
0V
VCC
S1
Z
Y
Y
D
VI
3V
VI
S1
1.5 V
1.5 V
VO
DE
Input
Generator
RL = 110 Ω
± 1%
0V
Z
t PZL(1&2)
t PLZ
VCC
CL = 50 pF ±20%
50 Ω
0.5 V
VO
2.3 V
VOL
Generator: PRR = 50 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Z 0 = 50 W
CL Includes Fixture and Instrumentation Capacitance
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Figure 23. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
IA
VA
VA + VB
2
VIC
VB
A
R
VID
IO
B
IB
RE
II
VO
VI
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Figure 24. Receiver Voltage and Current Definitions
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Parameter Measurement Information (continued)
A
R
Input
Generator
VI
50 Ω
1.5 V
0V
B
3V
VO
RE
1.5 V
VI
1.5 V
0V
CL = 15 pF
±20%
t PLH
VO
CL Includes Fixture and Instrumentation Capacitance
t PHL
90% 90%
1.5 V
10%
Generator: PRR = 500 kHz, 50% Duty Cycle, t r <6 ns, t f <6 ns, Zo = 50 Ω
tr
VOH
1.5 V
10% V
OL
tf
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Figure 25. Receiver Switching Test Circuit and Voltage Waveforms
1.5 V
V CC
A
R
0V
B
VI
1 k W ±1%
3V
A
S1
VI
C L = 15 pF
±20%
RE
Input
Generator
VO
1.5V
1.5V
B
0V
t PHZ
t PZH(1 & 2)
V OH
50 W
C L Includes Fixture and
Instrumentation Capacitance
1.5 V
VO
0.5V
~0 V
Generator: PRR = 50 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Z 0 = 50 W
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Figure 26. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
0V
V CC
A
R
1.5 V
B
RE
Input
VI
Generator
V O 1 k W ±1%
S1
C L = 15 pF
±20%
50 W
C L Includes Fixture
and Instrumentation
Capacitance
3V
A
VI
1.5V
1.5V
B
0V
tPZL(1 & 2)
VO
tPLZ
1.5 V
V CC
0.5V
V OL
Generator: PRR = 50 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Z 0 = 50 W
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Figure 27. Receiver Enable Time From Standby (Driver Disabled)
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SLLS665L – SEPTEMBER 2005 – REVISED JANUARY 2017
Parameter Measurement Information (continued)
0 V or 3 V
DE
A
Y
D
R
Z
100 W
±1%
+
-
Pulse Generator
15 ms duration
1% Duty Cycle
tr, tf £ 100 ns
100 W
±1%
B
RE
0 V or 3 V
+
-
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Figure 28. Test Circuit, Transient Over Voltage Test
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9 Detailed Description
9.1 Overview
The SN65HVD3x devices are low-power, full-duplex RS-485 transceivers available in three speed grades
suitable for data transmission of 1 Mbps, 5 Mbps, and 50 Mbps.
The SN65HVD30, SN65HVD31, and SN65HVD32 devices are fully enabled with no external enabling pins. The
SN65HVD33, SN65HVD34, and SN65HVD35 devices have active-high driver enables and active-low receiver
enables. A standby current of less than 1 µA can be achieved by disabling both driver and receiver.
9.2 Functional Block Diagram
VCC
R
VCC
A
R
R
B
R
A
B
RE
VCC
DE
D
Z
D
D
Y
GND
Z
D
Y
GND
a) SN65HVD33, SN65HVD34,
SN65HVD35
b) SN65HVD30, SN65HVD31,
SN65HVD32
Copyright © 2017, Texas Instruments Incorporated
9.3 Feature Description
9.3.1 Low-Power Standby Mode
When both the driver and receiver are disabled (DE is low and RE is high), the device is in standby mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against
inadvertently entering standby mode during driver or receiver enabling. The device in standby mode only when
the enable inputs are held in this state for 300 ns or more. In this low-power standby mode, most internal circuitry
is powered down, and the supply current is typically less than 1 nA. When either the driver or the receiver is reenabled, the internal circuitry becomes active.
12
R
RE
2
11
A
B
3
Low-Power
Standby
DE
4
9
D
5
10
Y
Z
Copyright © 2017, Texas Instruments Incorporated
Figure 29. Low-Power Standby Logic Diagram
If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after
the enable times given by tPZH2 and tPZL2 in the driver switching characteristics. If the D input is open when the
driver is enabled, the driver output defaults to Y low and Z high, in accordance with the driver-failsafe feature.
20
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Feature Description (continued)
If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the
bus inputs (A and B) after the enable times given by tPZH2 and tPZL2 in the receiver switching characteristics. If
there is no valid state on the bus the receiver responds as described in the failsafe operation section.
If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state
of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the
active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver
outputs are valid.
9.3.2 Driver Output Current Limiting
The RS-485 standard (ANSI/TIA/EIA-485-A or equivalently ISO 8482) specifies a 250-mA driver output current
limit to prevent damage caused by data contention on the bus. That applies in the event that two or more
transceivers drive the bus to opposing states at the same time. The SN65HVD3x family of devices includes
current-limiting circuitry that prevents damage under these conditions.
NOTE
This current limit prevents damage during the bus contention, but the logic state of the bus
can be indeterminate as specified by the standard, so communication errors can occur.
In a specific combination of circumstances, a condition can occur in which current through the bus pin exceeds
the 250-mA limit. This combination of conditions is not normally included in RS-485 applications:
• Loading capacitance on the pin is less than 500 pF
• The bus pin is directly connected to a voltage more negative than –1 V
• The device is supplied with VCC equal to or greater than 3.3 V
• The driver is enabled
• The bus pin is driving to the logic high state
In these specific conditions, the normal current-limit circuitry and thermal-shutdown circuitry does not limit or
shutdown the current flow. If the current is allowed to continue, the device heats up in a localized area near the
driver outputs, and the device can be damaged.
Typical RS-485 twisted-pair cable has a capacitance of approximately 50 pF/meter. Therefore, it is expected that
10 meters of cable can provide sufficient capacitance to prevent this latch-up condition.
The –7 to +12-V common mode range specified by RS-485 is intended to allow communication between
transceivers separated by significant distances when ground offsets may occur due to temporary current surges,
electrical noise, and so on. Under those circumstances, the inherent cable needed to connect separated
transceivers ensures that the conditions previously listed do not occur. For a transceiver separated by only a
short cable length or backplane applications, it is unusual for there to be a steady-state negative common-mode
voltage. It is possible for a negative power supply to be shorted to the bus lines due to miswiring or cable
damage; however, this is a different root cause fault, and robust devices such as the SN65HVD178x family
should be used for surviving power supply or miswiring faults.
The 250-mA current limit in the RS-485 standard is intended to prevent damage caused by data contention on
the bus; that is, in the event that two or more transceivers drive the bus to different states at the same time.
These devices are not damaged under these conditions because all RS-485 drivers have output impedance
sufficient to prevent the direct connection condition stated previously. Typical RS-485 driver output impedance is
on the order of 10 Ω to 30 Ω.
9.3.3 Hot-Plugging
These devices are designed to operate in hot swap or hot pluggable applications. Key features for hot-pluggable
applications are:
• Power-up
• Power-down glitch-free operation
• Default disabled input/output pins
• Receiver failsafe
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Feature Description (continued)
As shown in Figure 9, an internal power-on reset circuit keeps the driver outputs in a high-impedance state until
the supply voltage has reached a level at which the device reliably operates. This ensures that no spurious bits
are transmitted on the bus pin outputs as the power supply turns on or turns off.
As shown in the Device Functional Modes, the enable inputs have the feature of default disable on both the
driver enable and receiver enable. This ensures that the device neither drives the bus nor reports data on the R
pin until the associated controller actively drives the enable pins.
9.3.4 Receiver Failsafe
The differential receivers of the SN65HVD3x family are failsafe to invalid bus states caused by:
• Open bus conditions such as a disconnected connector
• Shorted bus conditions such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver outputs a failsafe logic high state so that the output of the receiver
is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver
output must output a high when the differential input VID is more positive than 200 mV, and must output a low
when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are
VIT+, VIT–, and VHYS (the separation between VIT+ and VIT–. As shown in the Electrical Characteristics table,
differential signals more negative than –200 mV always cause a low receiver output, and differential signals more
positive than 200 mV always cause a high receiver output.
When the differential input signal is close to zero, it is still above the VIT+ threshold, and the receiver output is
high. Only when the differential input is more than VHYS below VIT+ does the receiver output transition to a low
state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver
hysteresis value (VHYS) as well as the value of VIT+.
R
VHYS
50mV
-70
-20
0
70
VID - mV
Vnoise-max = 140mVpp
Figure 30. SN65HVD30-35 Noise Immunity Under Bus Fault Conditions
9.3.5 Safe Operation With Bus Contention
These devices incorporate a driver current limit of 250 mA across the RS-485 common-mode range of –7 V to
+12 V. As stated in the Application Guidelines for TIA/EIA-485-A (1), this sets a practical limitation to prevent
damage during bus contention events. Contention can occur during system initialization, during system faults, or
whenever two or more drivers are active at the same time.
(1)
22
TIA/EIA Telecommunications System Bulletin TSB89, Application Guidelines for TIA/EIA-485-A
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Feature Description (continued)
Figure 31 shows a 2-node system to demonstrate bus contention by forcing both drivers to be active in opposing
states.
Vcc2
Vcc1
ALWAYS
HIGH
D
ALWAYS
ENABLED
DE
±7V
OFFSET
GND
1
GND
2
Node 1 D-pin
Node 2 DE -pin
Bus Vdiff
CONTENTION
Copyright © 2017, Texas Instruments Incorporated
Figure 31. Bus Contention Example
Figure 32 shows typical operation in a bus contention event. The bottom trace illustrates how the SN65HVD33
device at Node 1 continues normal operation after a contention event between the two drivers with a –7-V
ground offset on Node 2. This illustrates how the SN65HVD3x family of devices operates robustly in spite of bus
contention faults, even with large common-mode offsets.
Node 1 D-pin
-7V offset
Node 2 DE-pin
Bus with intermittent contention
Figure 32. SN65HVD3x Drivers Operate Correctly After Bus Contention Faults
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9.4 Device Functional Modes
Table 3. SN65HVD33, SN65HVD34, SN65HVD35 Driver
INPUTS
OUTPUTS
D
DE
Y
Z
H
H
H
L
L
H
L
H
X
L or open
Z
Z
Open
H
L
H
Table 4. SN65HVD33, SN65HVD34, SN65HVD35
Receiver
DIFFERENTIAL INPUTS
VID = V(A) – V(B)
ENABLE
RE
OUTPUT
R
VID ≤ –0.2 V
L
L
–0.2 V < VID < –0.02 V
L
?
–0.02 V ≤ VID
L
H
X
H or open
Z
Open Circuit
L
H
Idle circuit
L
H
Short Circuit, V(A) = V(B)
L
H
Table 5. SN65HVD30, SN65HVD31, SN65HVD32 Driver
OUTPUTS
INPUT
D
Y
H
H
L
L
L
H
Open
L
H
Z
Table 6. SN65HVD30, SN65HVD31, SN65HVD32
Receiver
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DIFFERENTIAL INPUTS
VID = V(A) – V(B)
OUTPUT
R
VID ≤ –0.2 V
L
–0.2 V < VID < –0.02 V
?
–0.02 V ≤ VID
H
Open Circuit
H
Idle circuit
H
Short Circuit, V(A) = V(B)
H
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RE Input
D and DE Input
VCC
VCC
130 kW
Input
470 W
Input
9V
470 W
9V
125 kW
A Input
B Input
VCC
VCC
R1
22 V
R1
22 V
R3
R3
Input
Input
22 V
R2
22 V
R2
R Output
Y and Z Outputs
VCC
VCC
16 V
5W
Output
Output
16 V
9V
Copyright © 2017, Texas Instruments Incorporated
Figure 33. Equivalent Input and Output Schematic Diagrams
Table 7. Input Attenuator Resistance Values
R1, R2
R3
SN65HVD30, SN65HVD33
PART NUMBER
9 kΩ
45 kΩ
SN65HVD31, SN65HVD32, SN65HVD34, SN65HVD35
36 kΩ
180 kΩ
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN65HVD3x family consists of full-duplex RS-485 transceivers commonly used for asynchronous data
transmissions. Full-duplex implementation requires two signal pairs (four wires), and allows each node to
transmit data on one pair while simultaneously receiving data on the other pair.
To eliminate line reflections, each cable end is terminated with a termination resistor (RT) whose value matches
the characteristic impedance (Z0) of the cable. This method, known as parallel termination, allows for higher data
rates over longer cable length.
Y
R
D
Z
A
RT
RT
B
R
R
DE
RE
Master
RE
D
Slave
B
R
A
DE
Z
RT
RT
A
B
Z
Y
D
D
Y
R Slave
D
R RE DE D
Copyright © 2017, Texas Instruments Incorporated
Figure 34. Typical RS-485 Network With Full-Duplex Transceivers
10.2 Typical Application
A full-duplex RS-485 network consists of multiple transceivers connecting in parallel to two bus cables. On one
signal pair, a master driver transmits data to multiple slave receivers. The master driver and slave receivers can
remain fully enabled at all times. On the other signal pair, multiple slave drivers transmit data to the master
receiver. To avoid bus contention, the slave drivers must be intermittently enabled and disabled such that only
one driver is enabled at any time, as in half-duplex communication. The master receiver can remain fully enabled
at all times.
Because the driver cannot be disabled, only connect one driver to the bus when using the SN65HVD30,
SN65HVD31, or SN65HVD32 devices.
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Typical Application (continued)
VCC
R
VCC
R
RE
A
R
B
RE
D
B
DE
DE
VCC
A
R
D
Z
D
Z
D
Y
Y
GND
GND
a) Master enable
control
b) Slave enable
control
Copyright © 2017, Texas Instruments Incorporated
Figure 35. Full-Duplex Transceiver Configurations
10.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
10.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and bus length, meaning the higher the data rate, the shorter
the cable length; and conversely, the lower the data rate, the longer the cable can be without introducing data
errors. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require
data rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for
small signal jitter of up to 5 or 10%.
10000
Cable Length (ft)
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100k
1M
10M
100M
Data Rate (bps)
Figure 36. Cable Length vs Data Rate Characteristic
Even higher data rates are achievable (such as 26 Mbps for the SN65HVD30 and SN65HVD33 devices) in cases
where the interconnect is short enough (or has suitably low attenuation at signal frequencies) to not degrade the
data.
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Typical Application (continued)
10.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, must be as short as possible. Stubs present a nonterminated piece of bus line that can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub must be less than one-tenth of the rise time of the driver; thus giving a maximum physical stub length as
shown in Equation 1.
Lstub ≤ 0.1 × tr × v × c
where:
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
Per Equation 1, Table 8 shows the maximum cable-stub lengths for the minimum driver output rise times of the
SN65HVD3x full-duplex family of transceivers for a signal velocity of 78%.
Table 8. Maximum Stub Length
MAXIMUM STUB LENGTH
DEVICE
MINIMUM DRIVER OUTPUT RISE TIME
(ns)
(m)
(ft)
SN65HVD30
4
0.1
0.3
SN65HVD31
25
0.6
1.9
SN65HVD32
120
2.8
9.2
SN65HVD33
4
0.1
0.3
SN65HVD34
25
0.6
1.9
SN65HVD35
120
2.8
9.2
10.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the SN65HVD30 and SN65HVD33 devices
are 1/2 UL transceivers, it is possible to connect up to 64 receivers to the bus. Likewise, the SN65HVD31,
SN65HVD32, SN65HVD34, and SN65HVD35 devices are 1/8 UL transceivers that can support up to 256
receivers.
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10.2.2 Detailed Design Procedure
To protect bus nodes against high-energy transients, the implementation of external transient protection devices
is necessary (see Figure 37).
3.3 V
100 nF
R1
10 kΩ
VCC
TVS
A
R
RxD
B
RE
DIR
MCU/
UART
R2
R1
SN65HVD33
DE
DIR
TVS
Z
D
TxD
Y
10 kΩ
GND
R2
Copyright © 2017, Texas Instruments Incorporated
Figure 37. Transient Protection Against ESD, EFT, and Surge Transients
Table 9. Bill of Materials
DEVICE
FUNCTION
ORDER NUMBER
MANUFACTURER
XCVR
3.3-V Full-Duplex RS-485 Transceiver
SN65HVD33
R1, R2
10-Ω, Pulse-Proof Thick-Film Resistor
CRCW060310RJNEAHP
Vishay
TVS
Bidirectional 400-W Transient Suppressor
CDSOT23-SM712
Bourns
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TI
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10.2.3 Application Curve
Signals from top to bottom: D, Y, Z, VOD
Figure 38. SN65HVD33 Transient Waveform
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11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply must be decoupled with a
100-nF ceramic capacitor located as close as possible to the supply pins. This helps to reduce supply voltage
ripple present on the outputs of switched-mode power supplies and also helps compensate for the resistance
and inductance of the PCB power planes.
12 Layout
12.1 Layout Guidelines
Robust and reliable bus-node design often requires the use of external transient protection devices to protect
against EFT and surge transients that can occur in industrial environments. Because these transients have a
wide frequency bandwidth (from approximately 3 MHz to 3 GHz), high-frequency layout techniques must be
applied during PCB design.
• Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.
• Use VCC and ground planes to provide low-inductance. High-frequency currents follow the path of least
inductance and not the path of least impedance.
• Design the protection components into the direction of the signal path. Do not force the transients currents to
divert from the signal path to reach the protection device.
• Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of transceiver, UART, and
controller ICs on the board.
• Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via inductance.
• Use 1-kΩ to 10-kΩ pullup or pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
• Insert series pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the
specified maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into
the transceiver and prevent it from latching up.
• While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs), which reduces the transients to a few hundred volts of clamping voltage and transient
blocking units (TBUs) that limit transient current to 200 mA.
12.2 Layout Example
5
Via to ground
4
Via to VCC
R
6 R
1
R
MCU
R
7
5
R
TVS
6 R
R
7
5
1
JMP
C
R
R
5
TVS
SN65HVD33
5
Figure 39. SN65HVD33 Layout Example
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13 Device and Documentation Support
13.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 10. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN65HVD30
Click here
Click here
Click here
Click here
Click here
SN65HVD31
Click here
Click here
Click here
Click here
Click here
SN65HVD32
Click here
Click here
Click here
Click here
Click here
SN65HVD33
Click here
Click here
Click here
Click here
Click here
SN65HVD34
Click here
Click here
Click here
Click here
Click here
SN65HVD35
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN65HVD30D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP30
SN65HVD30DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP30
SN65HVD30DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP30
SN65HVD30DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP30
SN65HVD31D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP31
SN65HVD31DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP31
SN65HVD31DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP31
SN65HVD32D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP32
SN65HVD32DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP32
SN65HVD32DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP32
SN65HVD33D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
65HVD33
SN65HVD33DG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
65HVD33
SN65HVD33DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
65HVD33
SN65HVD33DRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
65HVD33
SN65HVD33RHLR
ACTIVE
VQFN
RHL
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
65HVD33
SN65HVD33RHLT
ACTIVE
VQFN
RHL
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
65HVD33
SN65HVD34D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
65HVD34
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN65HVD34DG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
65HVD34
SN65HVD34DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
65HVD34
SN65HVD35D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
65HVD35
SN65HVD35DG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
65HVD35
SN65HVD35DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
65HVD35
SN65HVD35DRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
65HVD35
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD30, SN65HVD33 :
• Enhanced Product: SN65HVD30-EP, SN65HVD33-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65HVD30DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD31DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD32DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD33RHLR
VQFN
RHL
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
SN65HVD33RHLT
VQFN
RHL
20
250
180.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
SN65HVD34DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN65HVD35DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD30DR
SOIC
D
8
2500
367.0
367.0
35.0
SN65HVD31DR
SOIC
D
8
2500
367.0
367.0
35.0
SN65HVD32DR
SOIC
D
8
2500
367.0
367.0
35.0
SN65HVD33RHLR
VQFN
RHL
20
3000
367.0
367.0
35.0
SN65HVD33RHLT
VQFN
RHL
20
250
210.0
185.0
35.0
SN65HVD34DR
SOIC
D
14
2500
350.0
350.0
43.0
SN65HVD35DR
SOIC
D
14
2500
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RHL0020A
PLASTIC QUAD FLATPACK- NO LEAD
A
3.6
3.4
B
PIN 1 INDEX AREA
4.6
4.4
C
1 MAX
SEATING PLANE
0.08 C
2.05±0.1
2X 1.5
20X 0.5
0.3
SYMM
10
14X 0.5
2X
3.5
9
12
SYMM
21
3.05±0.1
19
2
PIN 1 ID
(OPTIONAL)
(0.2) TYP
11
1
20
4X (0.2)
2X (0.55)
20X 0.29
0.19
0.1
0.05
C A B
C
4219071 / A 05/2017
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RHL0020A
PLASTIC QUAD FLATPACK- NO LEAD
(3.3)
(2.05)
2X (1.5)
SYMM
1
20
2X (0.4)
20X (0.6)
19
2
20X (0.24)
14X (0.5)
SYMM
21
(3.05)
(4.3)
6X (0.525)
2X (0.75)
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
9
12
(R0.05) TYP
(Ø0.2) VIA
TYP)
11
10
4X (0.2)
4X
(0.775)
2X (0.55)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 18X
0.07 MAX
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219071 / A 05/2017
NOTES: (continued)
4.
5.
6.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271) .
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to theri
locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RHL0020A
PLASTIC QUAD FLATPACK- NO LEAD
(3.3)
2X (1.5)
(0.55)
TYP
1
20
(0.56)
TYP
SOLDER MASK EDGE
TYP
20X (0.6)
2
19
20X (0.24)
14X (0.5)
(1.05)
TYP
SYMM
(4.3)
21
6X
(0.85)
(R0.05) TYP
METAL
TYP
12
9
2X
(0.775)
2X (0.25)
11
10
4X (0.2)
6X (0.92)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1mm THICK STENCIL
EXPOSED PAD
75% PRINTED COVERAGE BY AREA
SCALE: 20X
4219071 / A 05/2017
NOTES: (continued)
7.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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