Texas Instruments | TPD1E01B04 1-Channel ESD Protection Diode for USB Type-C and Thunderbolt 3 (Rev. C) | Datasheet | Texas Instruments TPD1E01B04 1-Channel ESD Protection Diode for USB Type-C and Thunderbolt 3 (Rev. C) Datasheet

Texas Instruments TPD1E01B04 1-Channel ESD Protection Diode for USB Type-C and Thunderbolt 3 (Rev. C) Datasheet
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TPD1E01B04
SLVSDG3C – MARCH 2016 – REVISED DECEMBER 2016
TPD1E01B04 1-Channel ESD Protection Diode for USB Type-C and Thunderbolt 3
1 Features
3 Description
•
The TPD1E01B04 is a bidirectional TVS ESD
protection diode array for USB Type-C and
Thunderbolt 3 circuit protection. The TPD1E01B04 is
rated to dissipate ESD strikes at the maximum level
specified in the IEC 61000-4-2 international standard
(Level 4).
1
•
•
•
•
•
•
•
•
•
•
IEC 61000-4-2 Level 4 ESD Protection
– ±15-kV Contact Discharge
– ±17-kV Air Gap Discharge
IEC 61000-4-4 EFT Protection
– 80 A (5/50 ns)
IEC 61000-4-5 Surge Protection
– 2.5 A (8/20 µs)
IO Capacitance:
– 0.18 to 0.20 pF (Typical)
– 0.20 to 0.23 pF (Maximum)
DC Breakdown Voltage: 6.4 V (Typical)
Ultra Low Leakage Current: 10-nA (Maximum)
Low ESD Clamping Voltage: 15 V at 16 A TLP
Low Insertion Loss: 26.9 GHz (–3 dB Bandwidth,
DPL)
Supports High Speed Interfaces up to 20 Gbps
Industrial Temperature Range: –40°C to +125°C
Industry Standard 0201 and 0402 footprints
This device features a 0.18 to 0.20-pF (typical) IO
capacitance making it ideal for protecting high-speed
interfaces up to 20 Gbps such as USB 3.1 Gen2 and
Thunderbolt 3. The low dynamic resistance and low
clamping voltage ensure system level protection
against transient events.
The TPD1E01B04 is offered in the industry standard
0201 (DPL) package and 0402 (DPY) packages.
Device Information(1)
PART NUMBER
TPD1E01B04
•
End Equipment
– Laptops and Desktops
– Mobile and Tablets
– Set-Top Boxes
– TV and Monitors
– USB Dongles
– Docking Stations
Interfaces
– USB Type-C
– Thunderbolt 3
– USB 3.1 Gen 2
– HDMI 2.0/1.4
– USB 3.0
– DisplayPort 1.3
– PCI Express 3
BODY SIZE (NOM)
0.60 mm x 0.30 mm
X1SON (2)
1.00 mm x 0.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
PACKAGE
X2SON (2)
Typical Application
USB Type-C
Connector
SSRX1P
SSRX1N
TPD1E01B04 (x4)
SSTX1P
SSTX1N
TPD4E05U06
VBUS
SBU2
CC1
DPT
DMT
TPD4E05U06
DMB
DPB
SBU1
CC2
VBUS
SSRX2N
SSRX2P
SSTX2N
TPD1E01B04 (x4)
SSTX2P
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD1E01B04
SLVSDG3C – MARCH 2016 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
ESD Ratings—IEC Specification ..............................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 14
11 Device and Documentation Support ................. 15
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
12 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2016) to Revision C
Page
•
Added "and 0402 (DPY) packages." to the Description, and package "X1SON (2)" to the Device Information table ........... 1
•
Added the DPY Package to the Pin Configuration and Functions ........................................................................................ 3
•
Added the DPY (X1SON) package to the Thermal Information table .................................................................................... 4
•
Added DPY values to CL Line capacitance in the Electrical Characteristics table................................................................. 5
•
Added "(DPL Package)" to the title of Figure 6 ...................................................................................................................... 6
•
Added Figure 7 ...................................................................................................................................................................... 6
•
Added curves for the DPY package to Figure 10 and Figure 11 .......................................................................................... 6
•
Added curve for the DPY package to Figure 17 .................................................................................................................. 13
Changes from Revision A (March 2016) to Revision B
•
Made changes to the Electrical Characteristics table. Updated limits for VHOLD .................................................................... 1
Changes from Original (March 2016) to Revision A
•
2
Page
Page
Changed device status from Product Preview to Production Data ....................................................................................... 1
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5 Pin Configuration and Functions
DPL Package
2-Pin X2SON
Top View
1
2
DPY Package
2-Pin X1SON
Top View
1
2
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
IO
I/O
ESD Protected Channel. If used as ESD IO, connect pin 2 to ground
2
IO
I/O
ESD Protected Channel. If used as ESD IO, connect pin 1 to ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Electrical fast transient
Peak pulse
MAX
UNIT
80
A
IEC 61000-4-5 power (tp - 8/20 µs)
27
W
IEC 61000-4-5 current (tp - 8/20 µs)
2.5
A
IEC 61000-4-5 (5/50 ns)
TA
Operating free-air temperature
–40
125
°C
Tstg
Storage temperature
–65
155
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings—IEC Specification
VALUE
V(ESD)
Electrostatic discharge
IEC 61000-4-2 contact discharge
±15000
IEC 61000-4-2 air-gap discharge
±17000
UNIT
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIO
Input pin voltage
–3.6
3.6
UNIT
V
TA
Operating free-air temperature
–40
125
°C
6.5 Thermal Information
TPD1E01B04
THERMAL METRIC
(1)
DPL (X2SON)
DPY
(X1SON)
2 PINS
2 PINS
582
UNIT
RθJA
Junction-to-ambient thermal resistance
442.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
264.5
243.8
°C/W
RθJB
Junction-to-board thermal resistance
394.4
162.5
°C/W
ψJT
Junction-to-top characterization parameter
36.4
154.1
°C/W
ψJB
Junction-to-board characterization parameter
394.4
163.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VRWM
Reverse stand-off voltage
IIO < 10 nA
VBRF
Breakdown voltage, IO pin to GND
VBRR
Breakdown voltage, GND to IO pin
Measured as the maximum voltage
before device snaps back into
VHOLD voltage
VHOLD
Holding voltage
IIO = 1 mA, TA = 25°C
VCLAMP
ILEAK
RDYN
CL
Clamping voltage
Leakage current, IO to GND
TYP
–3.6
5
DPL Package
DPY Package
MAX
3.6
V
V
5.9
7
IPP = 5 A, TLP, from IO to GND
9.2
IPP = 16 A, TLP, from IO to GND
15
IPP = 1 A, TLP, from GND to IO
7
IPP = 5 A, TLP, from GND to IO
9.2
IPP = 16 A, TLP, from GND to IO
15
6.5
V
V
10
IO to GND
0.57
GND to IO
0.57
VIO = 0 V, f = 1 MHz, IO to GND
TA = 25°C
0.18
0.20
0.20
0.23
nA
Ω
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V
–6.4
IPP = 1 A, TLP, from IO to GND
Copyright © 2016, Texas Instruments Incorporated
UNIT
6.4
VIO = ±2.5 V
Dynamic resistance
Line capacitance
MIN
pF
5
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30
30
27
27
24
24
21
21
18
18
Current (A)
Current (A)
6.7 Typical Characteristics
15
12
9
15
12
9
6
6
3
3
0
0
-3
-3
0
3
6
9
12
15
Voltage (V)
18
21
24
0
27
3
6
9
12
15
Voltage (V)
D001
Figure 1. Positive TLP Curve
18
21
24
27
D002
Figure 2. Negative TLP Curve
110
10
100
0
90
-10
80
-20
Voltage (V)
Voltage (V)
70
60
50
40
30
-30
-40
-50
20
-60
10
-70
0
-10
-10
0
10
20
30
40 50
Time (ns)
60
70
80
90
-80
-10
100
0
0
5
30
40 50
Time (ns)
60
70
80
90
100
D004
0.4
0.35
0.3
Capacitance (pF)
3.6
Power 3.3
Current
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
-0.3
10 15 20 25 30 35 40 45 50 55 60
Time (Ps)
D005
Figure 5. Surge Curve (tp = 8/20µs), IO pin to GND
6
20
Figure 4. –8-kV IEC Waveform
Current (A)
Power (W)
Figure 3. 8-kV IEC Waveform
30
27.5
25
22.5
20
17.5
15
12.5
10
7.5
5
2.5
0
-2.5
-5
10
D003
0.25
0.2
0.15
0.1
-40qC
25qC
85qC
125qC
0.05
0
0
0.4
0.8
1.2
1.6
2
2.4
Voltage Bias (V)
2.8
3.2
3.6
D006
Figure 6. Capacitance vs. Bias Voltage (DPL Package)
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Typical Characteristics (continued)
1000
0.4
0.35
800
Leakage Current (pA)
Capacitance (pF)
0.3
0.25
0.2
0.15
0.1
-40qC
25qC
85qC
125qC
0.05
0.4
0.8
1.2
1.6
2
2.4
Voltage Bias (V)
2.8
3.2
400
200
0
0
600
0
-40
3.6
Figure 7. Capacitance vs. Bias Voltage (DPY Package)
-10
5
20 35 50 65
Temperature (qC)
1
0.3
0.8
0.27
0.6
0.24
0.4
0.21
0.2
0
-0.2
-0.4
95
110 125
D007
0.18
0.15
0.12
0.09
-0.6
0.06
-0.8
0.03
-1
80
Figure 8. Leakage Current vs. Temperature
Capacitance (pF)
Current (mA)
-25
D006
DPL Package
DPY Package
0
-7
-6
-5
-4
-3
-2
-1 0 1
Voltage (V)
2
3
4
5
6
7
2
7
D001
Figure 9. DC Voltage Sweep I-V Curve
12
17
Frequency (GHz)
22
27
30
D009
Figure 10. Capacitance vs. Frequency
0.5
0
Insertion Loss (dB)
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
0.1
DPL Package
DPY Package
0.2 0.3 0.5 0.7 1
2 3 4 5 6 78 10
Frequency (GHz)
20 30 40
D010
Figure 11. Insertion Loss
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Typical Characteristics (continued)
Figure 12. USB3.1 Gen 2 10-Gbps Eye Diagram
(Bare Board)
8
Figure 13. USB3.1 Gen 2 10-Gbps Eye Diagram
(with TPD1E01B04DPL)
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7 Detailed Description
7.1 Overview
The TPD1E01B04 device is a bidirectional ESD Protection Diode with ultra-low capacitance. This device can
dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultralow capacitance makes this device ideal for protecting any super high-speed signal pins including Thunderbolt 3.
The low capacitance allows for extremely low losses even at RF frequencies such as USB 3.1 Gen 2,
Thunderbolt 3, or antenna applications.
7.2 Functional Block Diagram
IO
GND
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 IEC 61000-4-2 ESD Protection
The I/O pins can withstand ESD events up to ±15-kV contact and ±17-kV air gap. An ESD-surge clamp diverts
the current to ground.
7.3.2 IEC 61000-4-4 EFT Protection
The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω
impedance). An ESD-surge clamp diverts the current to ground.
7.3.3 IEC 61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 2.5 A and 27 W (8/20 µs waveform). An ESD-surge clamp diverts
this current to ground.
7.3.4 IO Capacitance
The capacitance between each I/O pin to ground is 0.18 pF (typical) and 0.20 pF (maximum). This device
supports data rates up to 20 Gbps.
7.3.5 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is ±6.4 V (typical). This ensures that sensitive equipment is protected
from surges above the reverse standoff voltage of ±3.6 V.
7.3.6 Ultra Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (maximum) with a bias of ±2.5 V
7.3.7 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 9.2 V (IPP = 5 A).
7.3.8 Supports High Speed Interfaces
This device is capable of supporting high speed interfaces up to 20 Gbps, because of the extremely low IO
capacitance.
7.3.9 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
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Feature Description (continued)
7.3.10 Easy Flow-Through Routing Package
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers
flow-through routing, requiring minimal modification to an existing layout.
7.4 Device Functional Modes
The TPD1E01B04 device is a passive integrated circuit that triggers when voltages are above VBRF or below
VBRR. During ESD events, voltages as high as ±17 kV (air) can be directed to ground via the internal diode
network. When the voltages on the protected line fall below the trigger levels of TPD1E01B04 (usually within 10s
of nano-seconds) the device reverts to passive.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPD1E01B04 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on
high-speed signal lines between a human interface connector and a system. As the current from ESD passes
through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the
protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
USB Type-C
Connector
SSRX1P
SSRX1N
TPD1E01B04 (x4)
SSTX1P
SSTX1N
TPD4E05U06
VBUS
SBU2
CC1
DPT
DMT
TPD4E05U06
DMB
DPB
SBU1
CC2
VBUS
SSRX2N
SSRX2P
SSTX2N
TPD1E01B04 (x4)
SSTX2P
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Figure 14. USB Type-C for Thunderbolt 3 ESD Schematic
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Typical Application (continued)
8.2.1 Design Requirements
For this design example eight TPD1E01B04DPL devices and two TPD4E05U06 devices are being used in a
USB Type-C for Thunderbolt 3 application. This provides a complete ESD protection scheme.
Given the Thunderbolt 3 application, the parameters listed in Table 1 are known.
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
Signal range on superspeed Lines
0 V to 3.6 V
Operating frequency on superspeed Lines
up to 10 GHz
Signal range on CC, SBU, and DP/DM Lines
0 V to 5 V
Operating frequency on CC, SBU, and DP/DM Lines
up to 480 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The TPD1E01B04 supports signal ranges between –3.6 V and 3.6 V, which supports the SuperSpeed pairs on
the USB Type-C application. The TPD4E05U06 supports signal ranges between 0 V and 5.5 V, which supports
the CC, SBU, and DP-DM lines.
8.2.2.2 Operating Frequency
The TPD1E01B04DPL has a 0.18 pF (typical) capacitance, which supports the Thunderbolt 3 data rates of 20
Gbps. The TPD4E05U06 has a 0.5-pF (typical) capacitance, which easily supports the CC, SBU, and DP-DM
data rates.
12
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8.2.3 Application Curves
Figure 15. USB 3.1 Gen 2 10-Gbps Eye Diagram
(Bare Board)
Figure 16. USB 3.1 Gen 2 10-Gbps Eye Diagram
(with TPD1E01B04DPL)
0.5
0
Insertion Loss (dB)
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
0.1
DPL Package
DPY Package
0.2 0.3 0.5 0.7 1
2 3 4 5 6 78 10
Frequency (GHz)
20 30 40
D010
Figure 17. Insertion Loss
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9 Power Supply Recommendations
This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended
I/O specification to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
•
•
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
TPD1E01B04 (x4)
Top and bottom layer
TPD4E05U06
TPD4E05U06
TPD1E01B04 (x4)
Top and bottom layer
10.2 Layout Example
Legend
Top Layer
Bottom Layer
Pin to GND
VIA to VBUS Plane
VIA to other layer
VIA to GND Plane
Figure 18. USB Type-C Mid-Mount, Hybrid Connector ESD Layout
14
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
TPD1E01B04 Evaluation Module User's Guide, SLVUAN5
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
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Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPD1E01B04
15
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPD1E01B04DPLR
ACTIVE
X2SON
DPL
2
15000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
7
TPD1E01B04DPLT
ACTIVE
X2SON
DPL
2
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
7
TPD1E01B04DPYR
ACTIVE
X1SON
DPY
2
10000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
5C
TPD1E01B04DPYT
ACTIVE
X1SON
DPY
2
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
5C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2016
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPD1E01B04DPLR
X2SON
DPL
2
15000
178.0
8.4
0.36
0.66
0.33
2.0
8.0
Q1
TPD1E01B04DPLR
X2SON
DPL
2
15000
178.0
12.3
0.39
0.68
0.38
2.0
8.0
Q1
TPD1E01B04DPLT
X2SON
DPL
2
250
178.0
8.4
0.36
0.66
0.33
2.0
8.0
Q1
TPD1E01B04DPLT
X2SON
DPL
2
250
178.0
12.3
0.39
0.68
0.38
2.0
8.0
Q1
TPD1E01B04DPYR
X1SON
DPY
2
10000
180.0
9.5
0.66
1.15
0.66
2.0
8.0
Q1
TPD1E01B04DPYT
X1SON
DPY
2
250
180.0
9.5
0.66
1.15
0.66
2.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD1E01B04DPLR
X2SON
DPL
2
15000
205.0
200.0
33.0
TPD1E01B04DPLR
X2SON
DPL
2
15000
184.0
184.0
19.0
TPD1E01B04DPLT
X2SON
DPL
2
250
205.0
200.0
33.0
TPD1E01B04DPLT
X2SON
DPL
2
250
184.0
184.0
19.0
TPD1E01B04DPYR
X1SON
DPY
2
10000
184.0
184.0
19.0
TPD1E01B04DPYT
X1SON
DPY
2
250
184.0
184.0
19.0
Pack Materials-Page 2
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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