Texas Instruments | DS92LV042x 10-MHz to-75 MHz Channel Link II Serializer and Deserializer With LVDS Parallel Interface (Rev. D) | Datasheet | Texas Instruments DS92LV042x 10-MHz to-75 MHz Channel Link II Serializer and Deserializer With LVDS Parallel Interface (Rev. D) Datasheet

Texas Instruments DS92LV042x 10-MHz to-75 MHz Channel Link II Serializer and Deserializer With LVDS Parallel Interface (Rev. D) Datasheet
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DS92LV0421, DS92LV0422
SNLS325D – MAY 2010 – REVISED DECEMBER 2016
DS92LV042x 10-MHz to-75 MHz Channel Link II Serializer and Deserializer
With LVDS Parallel Interface
1 Features
3 Description
•
The DS92LV042x chipset translates a Channel Link
LVDS video interface (4 LVDS Data + LVDS Clock)
into a high-speed serialized interface over a single
CML pair. The DS92LV042x enables applications
currently using popular Channel Link or OpenLDI
LVDS style devices to upgrade seamlessly to an
embedded clock interface. This serial bus scheme
reduces interconnect cost and eases design
challenges. The parallel OpenLDI LVDS interface
also reduces FPGA I/O pins, board trace count, and
alleviates EMI issues when compared to traditional
single-ended wide bus interfaces.
1
•
•
•
•
•
•
•
•
•
•
5-Channel (4 Data + 1 Clock) Channel Link LVDS
Parallel Interface Supports 24-Bit Data 3-Bit
Control at 10 to 75 MHz
AC-Coupled STP Interconnect Up to 10 m
Integrated Terminations on Serializer and
Deserializer
At-Speed Link BIST Mode and Reporting Pin
Optional I2C-Compatible Serial Control Bus
Power-Down Mode Minimizes Power Dissipation
1.8-V or 3.3-V Compatible LVCMOS I/O Interface
>8-kV HBM
–40° to 85°C Temperature Range
Serializer (DS92LV0421)
– Data Scrambler for Reduced EMI
– DC–Balance Encoder for AC Coupling
– Selectable Output VOD and Adjustable DeEmphasis
Deserializer (DS92LV0422)
– Fast Random Data Lock; No Reference Clock
Required
– Adjustable Input Receiver Equalization
– EMI Minimization on Output Parallel Bus
(SSCG and LVDS VOD Select)
Programmable
transmit
de-emphasis,
receive
equalization, on-chip scrambling, and DC-balancing
enables longer distance transmission over lossy
cables
and
backplanes.
The
DS92LV0422
automatically locks to incoming data without an
external reference clock or special sync patterns,
providing easy plug-and-go operation.
The DS92LV042x chipset is programmable through
an I2C interface as well as through pins. A built-in, atspeed BIST feature validates link integrity and may
be used for system diagnostics. The DS92LV0421
and DS92LV0422 can be used interchangeably with
the DS92LV2421 or DS92LV2422. This allows
designers the flexibility to connect to the host device
and receiving devices with different interface types:
LVDS or LVCMOS.
2 Applications
•
•
•
•
•
Device Information(1)
Embedded Video and Displays
Medical Imaging and Factory Automation
Office Automation (Printers and Scanners)
Security and Video Surveillance
General-Purpose Data Communication
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS92LV0421
WQFN (36)
6.00 mm × 6.00 mm
DS92LV0422
WQFN (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Block Diagram
Channel Link
Channel Link II
Camera/AFE
Or
HOST
Graphics
Processor
RGB Style Display Interface
VDDIO
(1.8V or 3.3V)
DOUT+
RIN100 ohm STP Cable
CMF
DS92LV0421
MAPSEL
CONFIG[1:0]
Optional
SCL
SDA
ID[x]
TxOUT2+/-
RIN+
DOUT-
RxCLKIN+/-
PDB
TxOUT3+/-
High-Speed Serial Link
1 Pair/AC Coupled
RxIN2+/-
RxIN0+/-
VDDIO
1.8V 3.3V (1.8V or 3.3V)
1.8V
RxIN3+/-
RxIN1+/-
Channel Link
SSC[2:0]
LFMODE
CONFIG[1:0]
MAPSEL
SCL
Optional
SDA
ID[x]
BISTEN
VODSEL
De-Emph
TxOUT1+/TxOUT0+/TxCLKOUT+/-
Frame Grabber
Or
RGB Display
QVGA to XGA
24-bit Color Depth
DS92LV0422
LOCK
PASS
PDB
BISTEN
OEN
OSSEL
VODSEL
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS92LV0421, DS92LV0422
SNLS325D – MAY 2010 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
9
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings ...................................... 9
ESD Ratings.............................................................. 9
Recommended Operating Conditions....................... 9
Thermal Information ................................................ 10
Electrical Characteristics: Serializer DC ................. 10
Electrical Characteristics: Deserializer DC ............. 11
Electrical Characteristics: DC and AC Serial Control
Bus ........................................................................... 13
6.8 Timing Requirements: Serial Control Bus............... 13
6.9 Switching Characteristics: Serializer ....................... 14
6.10 Switching Characteristics: Deserializer................. 15
6.11 Typical Characteristics .......................................... 22
7
Detailed Description ............................................ 23
7.1 Overview ................................................................. 23
7.2 Functional Block Diagrams ..................................... 23
7.3 Feature Description................................................. 24
7.4 Device Functional Modes........................................ 36
7.5 Register Maps ......................................................... 37
8
Application and Implementation ........................ 40
8.1 Application Information............................................ 40
8.2 Typical Application .................................................. 43
9 Power Supply Recommendations...................... 46
10 Layout................................................................... 47
10.1 Layout Guidelines ................................................. 47
10.2 Layout Example .................................................... 49
11 Device and Documentation Support ................. 50
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
50
50
50
50
50
50
51
51
12 Mechanical, Packaging, and Orderable
Information ........................................................... 51
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D
Page
•
Added Device Information table, Pin Configuration and Functions section, Specifications section, ESD Ratings table,
Thermal Information table, Typical Characteristics section, Detailed Description section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Added OpenLDI LVDS as an acceptable parallel interface to the DS92LV024x chipset....................................................... 1
•
Changed RXIN and RXCLKIN to TXOUT and TXCLKOUT to correct pin name typos ........................................................ 6
•
Changed output state of deserializer when PDB = 1 to be TRI-STATE, not logic high ......................................................... 6
•
Deleted Power dissipation rows from the Absolute Maximum Ratings table ......................................................................... 9
•
Changed Junction-to-ambient, RθJA, values in Thermal Information table From: 27.4°C/W To: 33.8°C/W (NJK) and
From: 27.7°C/W to: 28.8°C/W (RHS) ................................................................................................................................... 10
•
Changed Junction-to-case, RθJC(top), values in Thermal Information table From: 4.5°C/W To: 15.8°C/W (NJK) and
From: 3.0°C/W To: 9.3°C/W (RHS) ...................................................................................................................................... 10
•
Deleted note in Electrical Characteristics: Serializer DC table stating that conditions are verified by characterization
or design and not tested in production, as this note only applies to a subset of tested parameters ................................... 10
•
Changed minimum and maximum value of serializer IIN for LVDS receiver DC specification ............................................. 10
•
Changed de-emphasis test condition for serializer IDD supply current ................................................................................. 11
•
Changed IOL condition for serial bus VOL parameter from 3 mA to 0.5 mA ......................................................................... 13
•
Changed RPU = 10 kΩ condition for the Serial Control Bus Characteristics of tR and tF ................................................... 13
•
Changed tPLD footnote to include tDDLT parameter ................................................................................................................ 14
•
Changed notation for serial bit stream UI footnote to clarify 1 UI = 1 / (28 x CLK) ............................................................. 14
•
Changed footnote for deserializer LVDS output units to clarify that parallel interface UI refers to Channel Link format
(1 UI = 1 / [7 × CLK]) instead of Channel Link II format (1 UI = 1 / [28 × CLK]) ................................................................. 15
•
Changed DS92LV0422 LVDS Transmitter Pulse Positions image to correct diagram labeling........................................... 18
•
Changed parallel interface description of deserializer From: wide parallel output bus To: Channel Link LVDS clock
2
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Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: DS92LV0421 DS92LV0422
DS92LV0421, DS92LV0422
www.ti.com
SNLS325D – MAY 2010 – REVISED DECEMBER 2016
Revision History (continued)
and data bus ......................................................................................................................................................................... 28
•
Deleted support for output data and clock slew rate control ............................................................................................... 28
•
Changed CMF cap recommendation from 0.1 µF to 4.7 µF ................................................................................................ 28
•
Changed SSCG Configuration (LFMODE = L) table and SSCG Configuration (LFMODE = H) table to clarify correct
SSC[2:0] behavior................................................................................................................................................................. 29
•
Changed PDB, OEN, and OSS_SEL Configuration table to clarify correct behavior with PDB, OEN, and OSS_SEL
pins ....................................................................................................................................................................................... 31
•
Changed BISTEN detail in BIST Waveforms image so that serializer and deserializer are generic ................................... 33
•
Changed description of Serializer VODSEL from Reg 0x00[4] to Reg 0x00[5] ................................................................... 37
•
Changed Serializer Reg 0x00[3:2] description from Reserved to Reverse-Compatibility Mode bits ................................... 37
•
Changed Deserializer Reg 0x00[3:2] description from Reserved to Reverse-Compatibility Mode bits ............................... 38
Changes from Revision B (April 2013) to Revision C
•
Page
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: DS92LV0421 DS92LV0422
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3
DS92LV0421, DS92LV0422
SNLS325D – MAY 2010 – REVISED DECEMBER 2016
www.ti.com
5 Pin Configuration and Functions
RES5
RXCLKIN+
RXCLKIN±
RXIN2+
RXIN2±
RXIN1+
RXIN1±
RXIN0+
RXIN0±
36
35
34
33
32
31
30
29
28
NJK Package
36-Pin WQFN
Top View
RXIN3±
1
27
RES4
RXIN3+
2
26
MAPSEL
RES6
3
25
RES7
ID[X]
4
24
VDDRX
VDDL
5
23
PDB
SCL
6
22
VDDIO
SDA
7
21
BISTEN
RES0
8
20
VODSEL
CONFIG[0]
9
19
DE-EMPH
10
11
12
13
14
15
16
17
18
CONFIG[1]
VDDP
RES1
RES2
VDDHS
DOUT±
DOUT+
VDDTX
RES3
DAP
Not to scale
Pin Functions: DS92LV0421
PIN
NAME
NO.
TYPE (1)
DESCRIPTION (2)
CHANNEL LINK PARALLEL INPUT INTERFACE
RXCLKIN+
35
I
True LVDS Clock Input
This pair must have a 100-Ω termination for standard LVDS levels.
RXCLKIN–
34
I
Inverting LVDS Clock Input
This pair must have a 100-Ω termination for standard LVDS levels.
RXIN[3:0]+
2, 33,
31, 29
I
True LVDS Data Input
This pair must have a 100-Ω termination for standard LVDS levels.
RXIN[3:0]–
1, 32,
30, 28
I
Inverting LVDS Data Input
This pair must have a 100-Ω termination for standard LVDS levels.
CHANNEL LINK II SERIAL OUTPUT INTERFACE
DOUT+
16
O
True Output, CML
The output must be AC-coupled with a 0.1-µF capacitor.
DOUT–
15
O
Inverting Output, CML
The output must be AC-coupled with a 0.1-µF capacitor.
(1)
(2)
4
G = Ground, I = Input, O = Output, and P = Power
1= HIGH, 0 = LOW
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Product Folder Links: DS92LV0421 DS92LV0422
DS92LV0421, DS92LV0422
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SNLS325D – MAY 2010 – REVISED DECEMBER 2016
Pin Functions: DS92LV0421 (continued)
PIN
NAME
NO.
TYPE (1)
DESCRIPTION (2)
CONTROL AND CONFIGURATION
10, 9
I
Operating Modes: Pin or Register Control, LVCMOS with pulldown.
Determines the device operating mode and interfacing device (see Table 10).
CONFIG[1:0] = 00: Interfacing to DS92LV2422 or DS92LV0422, Control Signal Filter DISABLED
CONFIG[1:0] = 01: Interfacing to DS92LV2422 or DS92LV0422, Control Signal Filter ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124Q-Q1
CONFIG [1:0] = 11: Interfacing to DS90C124
DE-EMPH
19
I
De-emphasis Control: Pin or Register Control, Analog with pullup.
De-emphasis = Open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to Ground or control through register (see
Table 2).
MAPSEL
26
I
Channel Link Map Select: Pin or Register Control, LVCMOS with pulldown.
MAPSEL = 1, MSB on RXIN3± (see Figure 23).
MAPSEL = 0, LSB on RXIN3± (see Figure 24).
23
I
Power-down Mode input, LVCMOS with pulldown.
PDB = 1, serializer is enabled (normal operation).
See Power Supply Recommendations for more information.
PDB = 0, serializer is powered down
When the serializer is in the power-down state, the driver outputs (DOUT±) are both logic high,
the PLL is shut down, and IDD is minimized. Control Registers are RESET.
25, 3, 36,
27, 18, 13,
12, 8
I
Reserved (tie low), LVCMOS with pulldown.
I
Differential Driver Output Voltage Select: Pin or Register Control, LVCMOS with pulldown.
VODSEL = 1, CML VOD is ±450 mV, 900 mVp-p (typical): long cable or de-emphasis
applications
VODSEL = 0, CML VOD is ±300 mV, 600 mVp-p (typical): short cable (no de-emphasis), low
power mode
I
BIST Mode: Optional, LVCMOS with pulldown.
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled (normal operation)
CONFIG[1:0]
PDB
RES[7:0]
VODSEL
20
OPTIONAL BIST MODE
BISTEN
21
OPTIONAL SERIAL BUS CONTROL
ID[X]
4
I
Serial Control Bus Device ID Address Select: Optional, Analog
Resistor to Ground and 10-kΩ pullup to 1.8-V rail (see Table 8).
SCL
6
I
Serial Control Bus Clock Input: Optional, LVCMOS (open-drain)
SCL requires an external pullup resistor to VDDIO.
SDA
7
I/O
Serial Control Bus Data Input or Output: Optional, LVCMOS (open-drain)
SDA requires an external pullup resistor VDDIO.
GND
G
DAP is the large metal contact at the bottom side, located at the center of the WQFN package.
Connect to the ground plane (GND) with at least 9 vias.
VDDHS
14
P
TX high-speed logic power, 1.8 V ±5%
VDDIO
22
P
LVCMOS I/O power and Channel Link I/O power, 1.8 V ±5% or 3.3 V ±10%
VDDL
5
P
Logic power, 1.8 V ±5%
VDDP
11
P
PLL power, 1.8 V ±5%
VDDRX
24
P
RX power, 1.8 V ±5%
VDDTX
17
P
Output driver power, 1.8 V ±5%
POWER AND GROUND (3)
DAP
(3)
The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower than 1.5 ms, a capacitor on the PDB
pin is required to ensure PDB arrives after all the VDD supplies have settled to the recommended operating voltage.
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: DS92LV0421 DS92LV0422
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DS92LV0421, DS92LV0422
SNLS325D – MAY 2010 – REVISED DECEMBER 2016
www.ti.com
GND
VDDSC
VDDSC
GND
GND
VDDA
CMF
RIN±
RIN+
GND
VDDA
RES
48
47
46
45
44
43
42
41
40
39
38
37
RHS Package
48-Pin WQFN
Top View
PDB
1
36
LFMODE
SSC[0]
2
35
OSS_SEL
SSC[1]
3
34
MAPSEL
SDA
4
33
VODSEL
SCL
5
32
GND
VDDL
6
31
VDDL
SSC[2]
7
30
OEN
VDDP
8
29
BISTEN
GND
9
28
PASS/EQ
CONFIG[0]
10
27
LOCK
CONFIG[1]
11
26
GND
ID[X]
12
25
VDDIO
13
14
15
16
17
18
19
20
21
22
23
24
VDDTX
GND
TXOUT3+
TXOUT3±
TXCLKOUT+
TXCLKOUT±
TXOUT2+
TXOUT2±
TXOUT1+
TXOUT1±
TXOUT0+
TXOUT0±
DAP
Not to scale
Pin Functions: DS92LV0422
PIN
NAME
NO.
TYPE (1)
DESCRIPTION (2)
CHANNEL LINK II SERIAL INPUT INTERFACE
CMF
42
I
Common-mode filter, Analog
VCM center-tap is a virtual Ground which may be AC-coupled to Ground to increase receiver
common mode noise immunity. Recommended value is 4.7 µF or higher.
RIN+
40
I
True Input, CML
The output must be AC-coupled with a 0.1-µF capacitor.
RIN–
41
I
Inverting Input, CML
The output must be AC-coupled with a 0.1-µF capacitor.
CHANNEL LINK PARALLEL OUTPUT INTERFACE
TXCLKOUT+
17
O
True LVDS Clock Output
This pair must have a 100-Ω termination for standard LVDS levels.
TXCLKOUT–
18
O
Inverting LVDS Clock Output
This pair must have a 100-Ω termination for standard LVDS levels.
TXOUT[3:0]+
15, 19,
21, 23
O
True LVDS Data Output
This pair must have a 100-Ω termination for standard LVDS levels.
TXOUT[3:0]–
16, 20,
22, 24
O
Inverting LVDS Data Output
This pair must have a 100-Ω termination for standard LVDS levels.
(1)
(2)
6
G = Ground, I = Input, O = Output, and P = Power
1= HIGH, 0 = LOW
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Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: DS92LV0421 DS92LV0422
DS92LV0421, DS92LV0422
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SNLS325D – MAY 2010 – REVISED DECEMBER 2016
Pin Functions: DS92LV0422 (continued)
PIN
NAME
NO.
TYPE (1)
DESCRIPTION (2)
LVCMOS OUTPUTS
LOCK
27
O
LOCK Status Output, LVCMOS
LOCK = 1, PLL is locked, output stated determined by OEN.
LOCK = 0, PLL is unlocked, output states determined by OSS_SEL and OEN.
See Table 7.
CONTROL AND CONFIGURATION
11, 10
I
Operating Modes: Pin or Limited Register Control, LVCMOS with pulldown.
Determine the device operating mode and interfacing device. (see Table 10).
CONFIG[1:0] = 00: Interfacing to DS92LV2421 or DS92LV0421, Control Signal Filter DISABLED
CONFIG[1:0] = 01: Interfacing to DS92LV2421 or DS92LV0421, Control Signal Filter ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR241, DS99R421
CONFIG [1:0] = 11: Interfacing to DS90C124
LFMODE
36
I
SSCG Low Frequency Mode: Pin or Register Control, LVCMOS with pulldown.
LFMODE = 1, low frequency mode (TXCLKOUT = 10–20 MHz)
LFMODE = 0, high frequency mode (TXCLKOUT = 20–65 MHz)
SSCG not available above 65 MHz.
MAPSEL
34
I
Channel Link Map Select: Pin or Register Control, LVCMOS with pulldown.
MAPSEL = 1, MSB on TXOUT3± (see Figure 23).
MAPSEL = 0, LSB on TXOUT3± (see Figure 24).
OEN
30
I
Output Enable, LVCMOS with pulldown.
See Table 7 for details.
OSS_SEL
35
I
Output Sleep State Select Input, LVCMOS with pulldown.
See Table 7 for details.
CONFIG[1:0]
PDB
1
I
Power-down Mode Input, LVCMOS with pulldown.
PDB = 1, deserializer is enabled (normal operation).
See Power Supply Recommendations for more information.
PDB = 0, deserializer is powered down.
When the deserializer is in the power-down state, the driver outputs (TXOUT±) are in TRISTATE. Control Registers are RESET.
RES
37
I
Reserved (tie low), LVCMOS with pulldown.
SSC[2:0]
7, 3, 2
I
Spread Spectrum Clock Generation (SSCG) Range Select, LVCMOS with pulldown.
See Table 5 and Table 6.
VODSEL
33
I
Parallel LVDS Driver Output Voltage Select: Pin or Register Control, LVCMOS with pulldown.
VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typical)
VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typical)
CONTROL AND CONFIGURATION — STRAP PIN
EQ
28 [PASS]
I
EQ Gain Control of Channel Link II Serial Input, STRAP, LVCMOS with pulldown
EQ = 1, EQ gain is enabled (~13 dB)
EQ = 0, EQ gain is disabled (~1.625 dB)
I
BIST Mode: Optional, LVCMOS with pulldown.
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
O
PASS Output (BIST Mode): Optional, LVCMOS
PASS =1, no errors detected
PASS = 0, errors detected
Leave open if unused. Route to a test point (pad) recommended.
OPTIONAL BIST MODE
BISTEN
PASS
29
28
OPTIONAL SERIAL BUS CONTROL
ID[X]
12
I
Serial Control Bus Device ID Address Select: Optional, Analog
Resistor to Ground and 10-kΩ pullup to 1.8-V rail (see Table 8).
SCL
5
I
Serial Control Bus Clock Input: Optional, LVCMOS (open drain)
SCL requires an external pullup resistor to 3.3 V.
SDA
4
I/O
Serial Control Bus Data Input or Output: Optional, LVCMOS (open drain)
SDA requires an external pullup resistor 3.3 V.
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: DS92LV0421 DS92LV0422
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DS92LV0421, DS92LV0422
SNLS325D – MAY 2010 – REVISED DECEMBER 2016
www.ti.com
Pin Functions: DS92LV0422 (continued)
PIN
NAME
NO.
TYPE (1)
DESCRIPTION (2)
POWER AND GROUND (3)
DAP
DAP
G
DAP is the large metal contact at the bottom side, located at the center of the WQFN package.
Connect to the ground plane (GND) with at least 9 vias.
GND
9, 14, 26,
32, 39, 44,
45, 48
G
Ground
VDDA
38, 43
P
Analog power, 1.8 V ±5%
VDDIO
25
P
LVCMOS I/O power and Channel Link I/O power, 1.8 V ± 5% or 3.3 V ±10%
VDDL
6, 31
P
Logic power, 1.8 V ±5%
VDDP
8
P
PLL power, 1.8 V ±5%
VDDSC
46, 47
P
SSCG power, 1.8 V ±5%
VDDTX
13
P
Channel Link LVDS parallel output power, 3.3 V ±10%
(3)
8
The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower than 1.5 ms, a capacitor on the PDB
pin is required to ensure PDB arrives after all the VDD supplies have settled to the recommended operating voltage.
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Product Folder Links: DS92LV0421 DS92LV0422
DS92LV0421, DS92LV0422
www.ti.com
SNLS325D – MAY 2010 – REVISED DECEMBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
MAX
VDDn (1.8 V)
–0.3
2.5
VDDIO
–0.3
4
Serializer, VDDTX
–0.3
2.5
Deserializer, VDDTX
–0.3
4
LVCMOS I/O voltage
–0.3
VDDIO + 0.3
V
Serializer LVDS input voltage
–0.3
VDDIO + 0.3
V
Deserializer LVDS output voltage
–0.3
VDDTX + 0.3
V
Serializer CML driver output voltage
–0.3
VDDn + 0.3
V
Deserializer CML receiver input voltage
–0.3
VDD + 0.3
V
150
°C
150
°C
Supply voltage
Junction temperature,TJ
Storage temperature, Tstg
(1)
(2)
(3)
–65
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
For soldering specifications, see Absolute Maximum Ratings for Soldering (SNOA549).
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±8000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1250
Machine Model
±250
UNIT
V
IEC 61000-4-2, powered-up only contact discharge
RD = 330 Ω, CS = 150 pF (RIN+, RIN–)
>±8000
IEC 61000-4-2, powered-up only air-gap discharge
RD = 330 Ω, CS = 150 pF (RIN+, RIN–)
>±30000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDDn
Supply voltage
1.71
1.8
1.89
V
VDDTX
Supply voltage (serializer)
1.71
1.8
1.89
V
VDDTX
Supply voltage (deserializer)
3
3.3
3.6
V
VDDIO
LVCMOS supply voltage (1.8-V nominal)
1.71
1.8
1.89
V
VDDIO
LVCMOS supply voltage (3.3-V nominal)
3
3.3
3.6
V
Clock frequency
10
Supply noise (1)
TA
(1)
−40
Operating free-air temperature
25
75
MHz
100
mVp-p
85
°C
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDDn (1.8 V) supply with
amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the serializer and output of the deserializer
with 10 meter cable shows no error when the noise frequency on the serializer is less than 750 kHz. The deserializer, on the other hand,
shows no error when the noise frequency is less than 400 kHz.
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6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
THERMAL METRIC
(1)
DS92LV0421
DS92LV0422
NJK (WQFN)
RHS (WQFN)
36 PINS
48 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance (2)
33.8
28.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance (2)
15.8
9.3
°C/W
RθJB
Junction-to-board thermal resistance
7.2
5.7
°C/W
ψJT
Junction-to-top characterization parameter
0.2
0.1
°C/W
ψJB
Junction-to-board characterization parameter
7.1
5.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.6
1.6
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Based on nine thermal vias.
6.5 Electrical Characteristics: Serializer DC
over recommended operating supply and temperature ranges (unless otherwise noted) (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS INPUT DC SPECIFICATIONS
VIH
High-level input voltage
VIL
Low-level input voltage
IIN
Input current
VDDIO = 3 V to 3.6 V (PDB, VODSEL, MAPSEL,
CONFIG[1:0], BISTEN pins)
2
VDDIO
0.65 ×
VDDIO
VDDIO
VDDIO = 3 V to 3.6 V (PDB, VODSEL, MAPSEL,
CONFIG[1:0], BISTEN pins)
GND
0.8
VDDIO = 1.71 V to 1.89 V (PDB, VODSEL, MAPSEL,
CONFIG[1:0], BISTEN pins)
GND
0.35 ×
VDDIO
VDDIO = 3 V to 3.6 V
−15
±1
15
VDDIO = 1.7 V to
1.89 V
−15
±1
15
VDDIO = 1.71 V to 1.89 V (PDB, VODSEL, MAPSEL,
CONFIG[1:0], BISTEN pins)
VIN = 0 V or VDDIO (PDB,
VODSEL, MAPSEL,
CONFIG[1:0], BISTEN pins)
V
V
µA
CHANNEL LINK PARALLEL LVDS RECEIVER DC SPECIFICATIONS
VTH
Differential threshold, high
voltage
VCM = 1.2 V (see Figure 1),
RXIN[3:0]± and RXCLKIN± pins
VTL
Differential threshold, low
voltage
VCM = 1.2 V (see Figure 1),
RXIN[3:0]± and RXCLKIN± pins
−100
|VID|
Differential input voltage
swing
VCM = 1.2 V (see Figure 1),
RXIN[3:0]± and RXCLKIN± pins
200
VCM
Common-mode voltage
IIN
Input current
100
mV
600
VDDIO = 3.3 V (RXIN[3:0]± and RXCLKIN± pins)
0
1.2
2.4
VDDIO = 1.8 V (RXIN[3:0]± and RXCLKIN± pins)
0
1.2
1.7
−15
±1
15
RXIN[3:0]± and RXCLKIN± pins
mV
mV
V
µA
CHANNEL LINK II SERIAL CML DRIVER DC SPECIFICATIONS
±225
±300
±375
Differential output voltage
RL = 100 Ω,
de-emphasis = disabled
(see Figure 3), DOUT+ and
DOUT– pins
VODSEL = L
VOD
VODSEL = H
±350
±450
±550
600
Differential output voltage
(DOUT+) – (DOUT–)
RL = 100 Ω,
de-emphasis = disabled
(see Figure 3), DOUT+ and
DOUT– pins
VODSEL = L
VODp-p
VODSEL = H
900
ΔVOD
Output voltage unbalance
RL = 100 Ω, de-emphasis = disabled, VODSEL = L
(DOUT+ and DOUT– pins)
(1)
(2)
10
1
mV
mVp-p
50
mV
Typical values represent most likely parametric norms at VDD = 3.3 V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not verified.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH, and VTL, which are differential voltages.
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SNLS325D – MAY 2010 – REVISED DECEMBER 2016
Electrical Characteristics: Serializer DC (continued)
over recommended operating supply and temperature ranges (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
VOS
Offset voltage
(single-ended)
At TP A and B (see Figure 2), VODSEL = L
RL = 100 Ω, de-emphasis =
disabled (DOUT+ and DOUT– VODSEL = H
pins)
ΔVOS
Offset voltage unbalance
(single-ended)
At TP A and B (see Figure 2), RL = 100 Ω,
de-emphasis = disabled (DOUT+ and DOUT– pins)
IOS
Output short-circuit current
DOUT± = 0 V, de-emphasis = disabled,
VODSEL = 0 (DOUT+ and DOUT– pins)
RTO
Internal output termination
resistor
DOUT+ and DOUT– pins
MIN
TYP
MAX
UNIT
1.65
V
1.575
1
mV
−36
mA
80
120
Ω
84
100
mA
VDDIO= 1.89 V
(VDDIO pin)
3
5
VDDIO = 3.6 V
(VDDIO pin)
10
13
77
90
VDDIO= 1.89 V
(VDDIO pin)
3
5
VDDIO = 3.6 V
(VDDIO pin)
10
13
100
1000
0.5
10
1
30
SERIALIZER SUPPLY CURRENT
Serializer supply current
(includes load current)
RL = 100 Ω, f = 75 MHz, checker board pattern (see
Figure 15), de-emphasis = 3 kΩ, VODSEL = H,
VDD = 1.89 V (All VDD pins)
Serializer supply current
(includes load current)
RL = 100 Ω, f = 75 MHz
de-emphasis = 3 kΩ,
VODSEL = H,
checker board pattern (see
Figure 15)
IDDT2
Serializer supply current
(includes load current)
RL = 100 Ω, f = 75 MHz, checker board pattern (see
Figure 15), de-emphasis = 6 kΩ, VODSEL = L,
VDD = 1.89 V (All VDD pins)
IDDIOT2
Serializer supply current
(includes load current)
RL = 100 Ω, f = 75 MHz
de-emphasis = 6 kΩ,
VODSEL = L,
checker board pattern (see
Figure 15)
IDDZ
Serializer supply current
power-down
PDB = 0 V, all other LVCMOS inputs = 0 V,
VDD = 1.89 V (All VDD pins)
IDDIOZ
Serializer supply current
power-down
VDDIO= 1.89 V
PDB = 0 V, all other LVCMOS (VDDIO pin)
inputs = 0 V
VDDIO = 3.6 V
(VDDIO pin)
IDDT1
IDDIOT1
mA
mA
mA
µA
µA
6.6 Electrical Characteristics: Deserializer DC
over recommended operating supply and temperature ranges (unless otherwise noted) (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.3-V LVCMOS I/O DC SPECIFICATIONS (VDDIO = 3 V to 3.6 V)
VIH
High level input voltage
PDB, VODSEL, OEN, MAPSEL, LFMODE, SSC[2:0],
and BISTEN pins
2
VDDIO
V
VIL
Low level input voltage
PDB, VODSEL, OEN, MAPSEL, LFMODE, SSC[2:0],
and BISTEN pins
GND
0.8
V
IIN
Input current
VIN = 0 V or VDDIO (PDB, VODSEL, OEN, MAPSEL,
LFMODE, SSC[2:0], and BISTEN pins)
−15
±1
15
µA
VOH
High level output voltage
IOH = –0.5 mA (LOCK and PASS pins)
VDDIO –
0.2
VDDIO
VOL
Low level output voltage
IOL = 0.5 mA (LOCK and PASS pins)
IOS
Output short-circuit current
VOUT = 0 V (LOCK and PASS pins)
IOZ
TRI-STATE output current
PDB = 0 V, OSS_SEL = 0 V, VOUT = 0 V or VDDIO
(LOCK and PASS pins)
(1)
(2)
GND
V
0.2
–10
–10
V
mA
10
µA
Typical values represent most likely parametric norms at VDD = 3.3 V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not verified.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH, and VTL, which are differential voltages.
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Electrical Characteristics: Deserializer DC (continued)
over recommended operating supply and temperature ranges (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.8-V LVCMOS I/O DC SPECIFICATIONS (VDDIO = 1.71 V to 1.89 V)
VIH
High level input voltage
PDB, VODSEL, OEN, MAPSEL, LFMODE, SSC[2:0],
and BISTEN pins
0.65 ×
VDDIO
VDDIO
V
VIL
Low level input voltage
PDB, VODSEL, OEN, MAPSEL, LFMODE, SSC[2:0],
and BISTEN pins
GND
0.35 ×
VDDIO
V
IIN
Input current
VIN = 0 V or VDDIO (PDB, VODSEL, OEN, MAPSEL,
LFMODE, SSC[2:0], and BISTEN pins)
−15
±1
15
µA
VOH
High level output voltage
IOH = –0.5 mA (LOCK and PASS pins)
VDDIO –
0.2
VDDIO
VOL
Low level output voltage
IOL = 0.5 mA (LOCK and PASS pins)
IOS
Output short-circuit current
VOUT = 0 V (LOCK and PASS pins)
IOZ
TRI-STATE output current
PDB = 0 V, OSS_SEL = 0 V, VOUT = 0 V or VDDIO
(LOCK and PASS pins)
GND
V
0.2
–3
–15
V
mA
15
µA
CHANNEL LINK PARALLEL LVDS DRIVER DC SPECIFICATIONS
100
250
400
Differential output voltage
RL = 100 Ω
(see Figure 3; TXOUT[3:0]± and
TXCLKOUT± pins)
VODSEL = L
|VOD|
VODSEL = H
200
400
600
Differential output voltage
A to B
RL = 100 Ω
(see Figure 3; TXOUT[3:0]± and
TXCLKOUT± pins)
VODSEL = L
500
VODp-p
VODSEL = H
800
ΔVOD
Output voltage unbalance
RL = 100 Ω
(see Figure 3; TXOUT[3:0]± and TXCLKOUT± pins)
VOS
Offset voltage
(single-ended)
RL = 100 Ω
(see Figure 3; TXOUT[3:0]± and
TXCLKOUT± pins)
ΔVOS
Offset voltage unbalance
(single-ended)
RL = 100 Ω (see Figure 3; TXOUT[3:0]± and
TXCLKOUT± pins)
IOS
Output short-circuit current
RL = 100 Ω, VOUT = GND
(TXOUT[3:0]± and TXCLKOUT± pins)
IOZ
Output TRI-STATE current
RL = 100 Ω, VOUT = VDDTX or GND
(TXOUT[3:0]± and TXCLKOUT± pins)
VODSEL = L
1
VODSEL = H
mVp-p
1
50
1.2
1.5
50
–5
–10
mV
V
1.2
1
mV
mV
mA
10
µA
50
mV
CHANNEL LINK II SERIAL CML RECEIVER DC SPECIFICATIONS
VTH
Differential input threshold
high voltage
VCM = 1.2 V (Internal VBIAS)
(RIN+ and RIN- pins)
VTL
Differential input threshold
low voltage
VCM = 1.2 V (Internal VBIAS)
(RIN+ and RIN- pins)
VCM
Common mode voltage,
internal VBIAS
RIN+ and RIN- pins
RT
Input termination
RIN+ and RIN- pins
–50
mV
1.2
85
V
100
115
Ω
DESERIALIZER SUPPLY CURRENT
IDD1
Deserializer supply current
(Includes load current)
75 MHz clock, checker board pattern (see
Figure 15), VODSEL = H, SSCG[2:0] = 000'b,
VDDn = 1.89 V (All VDD(1.8) pins)
88
100
mA
IDDTX1
Deserializer supply current
(Includes load current)
75 MHz clock, checker board pattern (see
Figure 15), VODSEL = H, SSCG[2:0] = 000'b,
VDDTX = 3.6 V (VDDTX pin)
40
50
mA
75 MHz clock,
checker board pattern (see
Figure 15), VODSEL = H,
SSCG[2:0] = 000'b
VDDIO = 1.89 V
(VDDIO pin)
0.3
0.8
IDDIO1
Deserializer supply current
(Includes load current)
VDDIO = 3.6 V
(VDDIO pin)
0.8
1.5
IDDZ
Deserializer supply current
power-down
PDB = 0 V, All other LVCMOS inputs = 0 V,
VDDn = 1.89 V (All VDD(1.8) pins)
0.15
2
mA
IDDTXZ
Deserializer supply current
power-down
PDB = 0 V, All other LVCMOS inputs = 0 V,
VDDTX = 3.6 V (VDDTX pin)
0.01
0.1
mA
12
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SNLS325D – MAY 2010 – REVISED DECEMBER 2016
Electrical Characteristics: Deserializer DC (continued)
over recommended operating supply and temperature ranges (unless otherwise noted)(1)(2)
PARAMETER
IDDIOZ
Deserializer supply current
power-down
TEST CONDITIONS
PDB = 0 V,
all other LVCMOS inputs = 0 V
MIN
TYP
MAX
VDDIO = 1.89 V
(VDDIO pin)
0.01
0.08
VDDIO = 3.6 V
(VDDIO pin)
0.01
0.08
UNIT
mA
6.7 Electrical Characteristics: DC and AC Serial Control Bus
over 3.3-V supply and temperature ranges (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDDIO
V
0.3 ×
VDDIO
V
VIH
Input high-level voltage
SDA and SCL
0.7 ×
VDDIO
VIL
Input low-level voltage
SDA and SCL
GND
VHY
Input hysteresis
VOL
Output low-level voltage
SDA, IOL = 0.5 mA
IIN
Input current
SDA or SCL, Vin = VDDIO or GND
tR
SDA rise time, READ
SDA, RPU = 10 kΩ, Cb ≤ 400pF
(see Figure 18)
800
ns
tF
SDA fall time, READ
SDA, RPU = 10 kΩ, Cb ≤ 400pF
(see Figure 18)
50
ns
tSU;DAT
Set-up time, READ
See Figure 18
540
ns
tHD;DAT
Hold time, READ
See Figure 18
600
ns
tSP
Input filter
CIN
Input capacitance
>50
mV
0
0.36
V
–10
10
µA
SDA or SCL
50
ns
<5
pF
6.8 Timing Requirements: Serial Control Bus
over 3.3-V supply and temperature ranges (unless otherwise noted)
MIN
TYP
MAX
Standard mode
100
Fast mode
400
fSCL
SCL clock frequency
tLOW
SCL low period
tHIGH
SCL high period
tHD:STA
Hold time for a START or a repeated START condition
(see Figure 18)
tSU:STA
Set-up time for a START or a repeated START condition Standard mode
(see Figure 18)
Fast mode
4.7
tHD:DAT
Data hold time (see Figure 18)
Standard mode
0
3.45
Fast mode
0
0.9
tSU:DAT
Data set-up time (see Figure 18)
tSU:STO
Set-up time for STOP (see Figure 18)
tBUF
Bus free time between STOP and START
(see Figure 18)
tr
SCL and SDA rise time (see Figure 18)
Standard mode
4.7
Fast mode
1.3
Standard mode
Fast mode
Standard mode
Fast mode
4
0.6
Standard mode
4.7
Fast mode
1.3
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µs
µs
4
Fast mode
Fast mode
µs
0.6
100
Standard mode
µs
0.6
250
Standard mode
µs
0.6
Fast mode
kHz
µs
4
Standard mode
UNIT
µs
µs
1000
300
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Timing Requirements: Serial Control Bus (continued)
over 3.3-V supply and temperature ranges (unless otherwise noted)
MIN
tf
SCL and SDA fall time (see Figure 18)
TYP
MAX
Standard mode
300
Fast mode
300
UNIT
ns
6.9 Switching Characteristics: Serializer
over recommended operating supply and temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CHANNEL LINK PARALLEL LVDS INPUT
tRSP0
LVDS Receiver Strobe Position (bit 0)
RXCLKIN = 75 MHz, RXIN[3:0] pins
(see Figure 5)
0.57
0.95
1.33
ns
tRSP1
LVDS Receiver Strobe Position (bit 1)
RXCLKIN = 75 MHz, RXIN[3:0] pins
(see Figure 5)
2.47
2.85
3.23
ns
tRSP2
LVDS Receiver Strobe Position (bit 2)
RXCLKIN = 75 MHz, RXIN[3:0] pins
(see Figure 5)
4.37
4.75
5.13
ns
tRSP3
LVDS Receiver Strobe Position (bit 3)
RXCLKIN = 75 MHz, RXIN[3:0] pins
(see Figure 5)
6.27
6.65
7.03
ns
tRSP4
LVDS Receiver Strobe Position (bit 4)
RXCLKIN = 75 MHz, RXIN[3:0] pins
(see Figure 5)
8.17
8.55
8.93
ns
tRSP5
LVDS Receiver Strobe Position (bit 5)
RXCLKIN = 75 MHz, RXIN[3:0] pins
(see Figure 5)
10.07
10.45
10.83
ns
tRSP6
LVDS Receiver Strobe Position (bit 6)
RXCLKIN = 75 MHz, RXIN[3:0] pins
(see Figure 5)
11.97
12.35
12.73
ns
RL = 100 Ω, De-emphasis = disabled,
VODSEL = 0
100
200
300
RL = 100 Ω, De-emphasis = disabled,
VODSEL = 1
100
200
300
RL = 100 Ω, De-emphasis = disabled,
VODSEL = 0
130
260
390
RL = 100 Ω, De-emphasis = disabled,
VODSEL = 1
100
200
300
5
15
ns
1.5
10
ms
147 × T 148 × T
ns
CHANNEL LINK II CML OUTPUT
tLLHT
tLHLT
Serializer output low-to-high transition time
(see Figure 4)
Serializer output high-to-low transition time
(see Figure 4)
ps
ps
tXZD
Serializer output active to OFF delay
(see Figure 9) (1)
tPLD
Serializer PLL lock time
(see Figure 7) (1) (2) (3)
RL = 100 Ω
tSD
Serializer delay, latency
(see Figure 10) (1)
RL = 100 Ω
tDJIT
Serializer output total jitter
(see Figure 12)
RL = 100 Ω, De-emphasis = disabled,
RANDOM pattern
0.3
λSTXBW
Serializer jitter transfer
(function –3-dB bandwidth) (1) (5)
RXCLKIN = 43 MHz
2.2
RXCLKIN = 75 MHz
3
δSTX
Serializer jitter transfer
(function peaking) (1) (5)
RXCLKIN = 43 MHz
1
RXCLKIN = 75 MHz
1
(1)
(2)
(3)
(4)
(5)
14
UI (4)
MHz
dB
Specification is verified by characterization and is not tested in production.
tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active
RXCLKIN.
When the serializer output is at TRI-STATE, the deserializer loses PLL lock. Resynchronization and Re-lock must occur before data
transfer require tPLD.
UI: Unit Interval is equivalent to one serialized data bit width (1 UI = 1 / [28 × CLK]). The UI scales with clock frequency.
Specification is verified by design and is not tested in production.
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SNLS325D – MAY 2010 – REVISED DECEMBER 2016
6.10 Switching Characteristics: Deserializer
over recommended operating supply and temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CHANNEL LINK PARALLEL LVDS OUTPUT
tDLHT
Deserializer low-to-high transition time
RL = 100 Ω
TXCLKOUT±, TXOUT[3:0]± pins
0.3
0.6
ns
tDHLT
Deserializer high-to-low transition time
RL = 100 Ω
TXCLKOUT±, TXOUT[3:0]± pins
0.3
0.6
ns
tDCCJ
Cycle-to-cycle output jitter (1) (2) (3)
TXCLKOUT± = 10 MHz
900
2100
TXCLKOUT± = 75 MHz
75
125
tTTP1
LVDS Transmitter Pulse Position for bit 1
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
0
UI (4)
tTTP0
LVDS Transmitter Pulse Position for bit 0
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
1
UI (4)
tTTP6
LVDS Transmitter Pulse Position for bit 6
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
2
UI (4)
tTTP5
LVDS Transmitter Pulse Position for bit 5
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
3
UI (4)
tTTP4
LVDS Transmitter Pulse Position for bit 4
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
4
UI (4)
tTTP3
LVDS Transmitter Pulse Position for bit 3
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
5
UI (4)
tTTP2
LVDS Transmitter Pulse Position for bit 2
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
6
UI (4)
tDD
Deserializer delay, latency (3)
(see Figure 11)
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
tTPDD
Deserializer power-down delay,
active to OFF (see Figure 13)
TXCLKOUT± = 75 MHz
6
10
ns
tTXZR
Deserializer enable delay,
OFF to active (see Figure 14)
TXCLKOUT± = 75 MHz
40
55
ns
ps
142 × T 143 × T
ns
CHANNEL LINK II CML INPUT
tDDLT
Deserializer lock time
(see Figure 8)
(5)
7
TXCLKOUT± = 10 MHz, SSCG = ON
14
TXCLKOUT± = 75 MHz, SSCG = OFF
6
TXCLKOUT± = 65 MHz, SSCG = ON
8
EQ = OFF
SSCG = OFF
Jitter frequency > 10 MHz
Deserializer input jitter tolerance
(see Figure 16)
tDJIT
TXCLKOUT± = 10 MHz, SSCG = OFF
ms
UI (6)
>0.45
LVCMOS OUTPUTS
tCLH
Deserializer low-to-high transition time
(see Figure 4)
CL = 8 pF (LOCK and PASS pins)
10
15
ns
tCHL
Deserializer high-to-low transition time
(see Figure 4)
CL = 8 pF (LOCK and PASS pins)
10
15
ns
10 MHz
(PASS pin)
220
230
tPASS
BIST PASS valid time,
BISTEN = 1 (see Figure 17)
75 MHz
(PASS pin)
40
65
(1)
(2)
(3)
(4)
(5)
(6)
ns
tDCCJ is the maximum amount of jitter between adjacent clock cycles.
Specification is verified by characterization and is not tested in production.
Specification is verified by design and is not tested in production.
UI: Unit Interval is equivalent to one serialized data bit width in the OpenLDI parallel interface format (1 UI = 1 / [7 × CLK]). The UI
scales with clock frequency.
tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active
RXCLKIN.
UI – Unit Interval is equivalent to one serialized data bit width (1 UI = 1 / [28 × CLK]). The UI scales with clock frequency.
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Switching Characteristics: Deserializer (continued)
over recommended operating supply and temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SSCG MODE
fDEV
Spread spectrum clocking
deviation frequency (3)
TXCLKOUT± = 10 to 65 MHz,
SSCG = ON
±0.5%
±2%
fMOD
Spread spectrum clocking
modulation frequency (3)
TXCLKOUT± = 10 to 65 MHz,
SSCG = ON
8
100
kHz
RxIN[3:0]+
RxCLKIN+
VTL
VCM=1.2V
VTH
RxIN[3:0]RxClkIN-
GND
Figure 1. Channel Link DC VTH/VTL Definition
A
A'
CA
Scope
50:
50:
B
CB
B'
50:
50:
Single-Ended
Figure 2. Output Test Circuit
DOUT+
VOD-
VOD+
DOUT-
VOS
VOD+
(DOUT+) - (DOUT+)
0V
VODp-p
VOD-
Differential
GND
Figure 3. CML Output Waveforms
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+VOD
80%
(DOUT+) - (DOUT-)
0V
20%
-VOD
tLLHT
tLHLT
Figure 4. CML Output Transition Times
Figure 5. DS92LV0421 Channel Link Receiver Strobe Positions
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Cycle N
TxCLKOUT±
bit 1
TxOUT[3:0]±
bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
tTTP1 0UI
tTTP0
tTTP6
1UI
2UI
tTTP5
tTTP4
3UI
4UI
tTTP3
tTTP2
5UI
6UI
Figure 6. DS92LV0422 LVDS Transmitter Pulse Positions
PDB
RxCLKIN
VIHMIN
"X"
active
tPLD
DOUT
(Diff.)
Driver On
Driver OFF, VOD = 0V
Figure 7. DS92LV0421 Lock Time
PDB
VIH(min)
RIN±
tDDLT
LOCK
VOH(min)
TRI-STATE
Figure 8. DS92LV0422 Lock Time
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VILMAX
PDB
RxCLKIN
active
"X"
tXZD
DOUT
(Diff.)
active
Driver OFF, VOD = 0V
RxIN[3:0]
N-1
N
N+1
| |
Figure 9. DS92LV0421 Disable Time
N+2
|
tSD
RxCLKIN
| |
| |
| |
DCA, DCB
| |
DOUT0-23
STOP START
STOP START
STOP START
STOP
STOP START
BIT
BIT BIT SYMBOL N-3 BIT BIT SYMBOL N-2 BIT BIT SYMBOL N-1 BIT BIT
SYMBOL N
| |
SYMBOL N-4
Figure 10. DS92LV0421 Latency Delay
|
|
START
STOP
BIT SYMBOL N+3 BIT
|
|
|
START
STOP
BIT SYMBOL N+2 BIT
|
|
RIN+/-
START
STOP
BIT SYMBOL N+1 BIT
|
START
STOP
BIT SYMBOL N BIT
tRD
TxCLKOUT
TxOUT[3:0]
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 11. DS92LV0422 Latency Delay
tDJIT
tDJIT
VOD (+)
DOUT
(Diff.)
TxOUT_E_O
0V
VOD (-)
tBIT (1 UI)
Figure 12. DS92LV0421 Output Jitter
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PDB
VILmax
RIN
X
tTPDD
LOCK
Z
PASS
Z
TxCLKOUT
Z
TxOUT[3:0]
Z
Figure 13. DS92LV0422 Power-Down Delay
PDB
LOCK
tTXZR
OEN
VIHmin
Z
TxCLKOUT
Z
TxOUT[3:0]
Figure 14. DS92LV0422 Enable Delay
+VOD
RxCLKIN
-VOD
+VOD
RxIN[odd]
-VOD
+VOD
RxIN[even]
-VOD
Cycle N
Cycle N+1
Figure 15. Checkerboard Data Pattern
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Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
RIN_TOL
Left
VTH
0V
VTL
RIN_TOL
Right
Ideal Center Position (tBIT/2)
tBIT (1 UI)
tIJIT
= RIN_TOL (Left + Right)
- tIJIT
Sampling Window = 1 UI
Figure 16. DS92LV0422 Receiver Input Jitter Tolerance
VILMAX
BISTEN
tPASS
PASS
(w/ errors)
VOLMAX
Prior BIST Result
Current BIST Test - Toggle on Error
Result Held
Figure 17. BIST PASS Waveform
SDA
tf
tHD;STA
tLOW
tf
tr
tr
tBUF
tSP
SCL
tSU;STA
tHD;STA
tHIGH
tHD;DAT
START
tSU;STO
tSU;DAT
STOP
REPEATED
START
START
Figure 18. Serial Control Bus Timing Diagram
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6.11 Typical Characteristics
85
IDDT @ 1.8V (mA)
80
75
70
VODSEL = H
65
60
VODSEL = L
55
50
45
40
0
10
20
30
40
50
60
70
RxCLK (MHz)
Figure 19. Typical IDDT (1.8-V Supply)
vs RXCLKIN
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Figure 20. Serializer DOUT Voltage
vs Ambient Temperature
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7 Detailed Description
7.1 Overview
The DS92LV042x chipset transmits and receives 24 bits of data and 3 control signals, formatted as Channel Link
LVDS data, over a single serial CML pair operating at 280 Mbps to 2.1 Gbps. The serial stream contains an
embedded clock, video control signals, and the DC-balance information which enhances signal quality and
supports AC coupling.
The deserializer can attain lock to a data stream without the use of a separate reference clock source, which
greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the serializer
regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the incoming
serial stream without the requirement of special training patterns or sync characters. The deserializer recovers
the clock and data by extracting the embedded clock information, validating, and then deserializing the incoming
data stream, providing a parallel Channel Link LVDS bus to the display, ASIC, or FPGA.
The DS92LV042x chipset can operate with up to 24 bits of raw data with three slower speed control bits encoded
within the serial data stream. For applications that require less than the maximum 24 raw data bits per clock
cycle, the user must ensure that all unused bit spaces or parallel LVDS channels are set to valid logic states, as
all parallel lanes and 27 bit spaces are always sampled.
7.2 Functional Block Diagrams
VODSEL
De-Emph
RIN+
DOUTRINEQ
Serializer
DOUT+
SSC[2:0]
OEN
VODSEL
TxOUT[3]
DC Balance Decoder
RxCLKIN+/-
Serial to Parallel
RxIN0+/-
CMF
Parallel to Serial
RxIN1+/-
Serial to Parallel
RxIN3+/RxIN2+/-
DC Balance Encoder
SSCG
TxOUT[2]
TxOUT[1]
TxOUT[0]
TxCLKOUT
Pattern
Generator
PLL
CONFIG[1:0]
MAPSEL
PDB
SCL
SCA
ID[x]
PDB
SCL
SCA
ID[x]
BISTEN
OSS_SEL
LFMODE
Timing and
Control
Error
Detector
Timing and
Control
PLL
PASS
LOCK
BISTEN
DS92LV0422
DS92LV0421
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Figure 21. Serializer Block Diagram
Figure 22. Deserializer Block Diagram
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7.3 Feature Description
7.3.1 Parallel LVDS Data Transfer (Color Bit Mapping Select)
The DS92LV042x can be configured to accept or transmit 24-bit data with two different LVDS parallel interface
mapping schemes:
• The normal Channel Link LVDS format (MSBs on LVDS Channel 3) can be selected by configuring the
MAPSEL pin to high. See Figure 23 for the normal Channel Link LVDS mapping.
• An alternate mapping scheme is available (LSBs on LVDS Channel 3) by configuring the MAPSEL pin to low.
See Figure 24 for the alternate LVDS mapping.
The mapping schemes can also be selected by register control. The alternate mapping scheme is useful in some
applications where the receiving system, typically a display, requires the LSBs for the 24-bit color data to be sent
on LVDS Channel 3.
NOTE
While the LVDS parallel interface has 28 bits defined, only 27 bits are recovered by the
serializer and sent to the deserializer. This chipset supports 24-bit RGB plus the three
video control signals. The 28th bit is not sampled, sent, or recovered.
RxCLKIN +/Previous cycle
Current cycle
B[7]
(bit 26)
RxIN3 +/-
DE
(bit 20)
RxIN2 +/-
RxIN1 +/-
RxIN0 +/-
VS
(bit 19)
B[1]
(bit 13)
B[0]
(bit 12)
G[0]
(bit 6)
R[5]
(bit 5)
R[7]
(bit 22)
R[6]
(bit 21)
B[4]
(bit 16)
B[3]
(bit 15)
B[2]
(bit 14)
G[4]
(bit 10)
G[3]
(bit 9)
G[2]
(bit 8)
G[1]
(bit 7)
R[3]
(bit 3)
R[2]
(bit 2)
R[1]
(bit 1)
R[0]
(bit 0)
B[6]
(bit 25)
G[7]
(bit 24)
HS
(bit 18)
B[5]
(bit 17)
G[5]
(bit 11)
R[4]
(bit 4)
G[6]
(bit 23)
Figure 23. 8–Bit Channel Link Mapping: MSB's on RXIN3
RxCLKIN +/Previous cycle
Current cycle
RxIN3 +/-
DE
(bit 20)
RxIN2 +/-
R[1]
(bit 22)
R[0]
(bit 21)
B[6]
(bit 16)
B[5]
(bit 15)
B[4]
(bit 14)
G[6]
(bit 10)
G[5]
(bit 9)
G[4]
(bit 8)
G[3]
(bit 7)
R[5]
(bit 3)
R[4]
(bit 2)
R[3]
(bit 1)
R[2]
(bit 0)
B[1]
(bit 26)
B[0]
(bit 25)
G[1]
(bit 24)
VS
(bit 19)
HS
(bit 18)
B[7]
(bit 17)
G[7]
(bit 11)
R[6]
(bit 4)
RxIN1 +/-
B[3]
(bit 13)
B[2]
(bit 12)
RxIN0 +/-
G[2]
(bit 6)
R[7]
(bit 5)
G[0]
(bit 23)
Figure 24. 8–Bit Channel Link Mapping: LSB's on RXIN3
24
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Feature Description (continued)
7.3.2 Serial Data Transfer
The DS92LV042x chipset transmits and receives a pixel of data in the following format: C1 and C0 represent the
embedded clock in the serial stream. C1 is always high and C0 is always low. The b[23:0] contains the
scrambled RGB data. DCB is the DC-Balanced control bit. DCB is used to minimize the short and long-term DC
bias on the signal lines. This bit determines if the data is unmodified or inverted. DCA is used to validate data
integrity in the embedded data stream and can also contain encoded control (VS, HS, DE). Both DCA and DCB
coding schemes are generated by the serializer and decoded by the deserializer automatically. Figure 25
illustrates the serial stream per clock cycle.
NOTE
Figure 25 only illustrates the bits but does not actually represent the bit location, as the
bits are scrambled and balanced continuously.
C
1
b
0
b
1
D
C
B
b
2
b
1
2
b
3
b
4
b
1
3
b
1
4
b
5
b
1
5
b
6
b
1
6
b
7
b
8
b
1
7
b
1
8
b
9
b
1
9
b
1
0
b
2
0
b
1
1
b
2
1
D
C
A
b
2
2
b
2
3
C
0
Figure 25. Channel Link II Serial Stream (DS92LV042x)
7.3.3 Video Control Signal Filter
The three control bits can be used to communicate any low speed signal. The most common use for these bits is
in the display or machine vision applications. In a display application, these bits are typically assigned as: Bit 26
to DE, Bit 24 to HS, and Bit 25 to VS. In the machine vision standard, Camera Link, these bits are typically
assigned: Bit 26 to DVAL, Bit 24 to LVAL, and Bit 25 to FVAL.
When operating the devices in Normal Mode, the video control signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled:
– DE and HS: Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 clock
cycles or longer.
• Normal Mode with Control Signal Filter Disabled:
– DE and HS: Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
• VS: Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Glitches of a control signal can cause a visual display error, and video control signals are defined as low
frequency signals with limited transitions. Therefore, the video control signal filter feature allows for the chipset to
validate and filter out any high frequency noise on the control signals (see Figure 26).
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
HS/VS/DE
OUT
Pulses 1 or 2
PCLKs wide
Filtered OUT
Figure 26. Video Control Signal Filter Waveform
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Feature Description (continued)
7.3.4 Serializer Functional Description
The serializer converts a Channel Link LVDS clock and data bus to a single serial output data stream and also
acts as a signal generator for the chipset Built-In Self Test (BIST) mode. The device can be configured through
external pins or through the optional serial control bus. The serializer features enhanced signal quality on the link
by supporting: a selectable VOD level, a selectable de-emphasis for signal conditioning, and Channel Link II data
coding that provides randomization, scrambling, and DC-balancing of the data. The serializer includes multiple
features to reduce EMI associated with display data transmission. This includes the randomization and
scrambling of the serial data and system spread spectrum clock support. The serializer includes power-saving
features with a sleep mode, auto stop clock feature, and optional LVCMOS (1.8 V or 3.3 V) I/O compatibility (see
also Optional Serial Bus Control and Built-In Self Test (BIST)).
7.3.4.1 Signal Quality Enhancers
7.3.4.1.1 Serializer VOD Select (VODSEL)
The serializer differential output voltage may be increased by setting the VODSEL pin high. When VODSEL is
low, the DC VOD is at the standard (default) level. When VODSEL is high, the VOD is increased in level. The
increased VOD is useful in extremely high noise environments and extra long cable length applications. When
using de-emphasis, TI recommends setting VODSEL = H to avoid excessive signal attenuation, especially with
the larger de-emphasis settings. This feature may be controlled by external pin or by register.
Table 1. Serializer Differential Output Voltage
INPUT
EFFECT
VODSEL
VOD (mV)
VOD (mVp-p)
L
±300
600
H
±450
900
7.3.4.1.2 Serializer De-Emphasis (DE-EMPH)
The de-emphasis pin controls the amount of de-emphasis beginning one full bit time after a logic transition that
the serializer drives. This is useful to counteract loading effects of long or lossy cables. This pin must be left
open if used for standard switching currents (no de-emphasis) or if used under register control. De-emphasis is
selected by connecting a resistor on this pin to ground, with the R value between 0.5 kΩ and 1 MΩ, or by register
setting. When using de-emphasis, TI recommends setting VODSEL = H.
Table 2. De-Emphasis Resistor Value
26
RESISTOR VALUE (kΩ)
DE-EMPHASIS SETTING
Open
Disabled
0.6
–12 dB
1
–9 dB
2
–6 dB
5
–3 dB
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0.00
VDD = 1.8V,
-2.00
TA = 25oC
DE-EMPH (dB)
-4.00
-6.00
-8.00
-10.00
-12.00
-14.00
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
R VALUE - LOG SCALE (:)
Figure 27. De-Emphasis vs R Value
7.3.4.2 EMI Reduction Features
7.3.4.2.1 Data Randomization and Scrambling
Channel Link II serializers and deserializers feature a three-step encoding process that enables the use of ACcoupled interconnects and also helps to manage EMI. The serializer first passes the parallel data through a
scrambler which randomizes the data. The randomized data is then DC-balanced. The DC-balanced and
randomized data then goes through a bit-shuffling circuit and is transmitted out on the serial line. This encoding
process helps to prevent static data patterns on the serial stream. The resulting frequency content of the serial
stream ranges from the parallel clock frequency to the Nyquist rate. For example, if the serializer and deserializer
chipset is operating at a parallel clock frequency of 50 MHz, the resulting frequency content of the serial stream
ranges from 50 MHz to 700 MHz (50 MHz × 28 bits = 1.4 GHz / 2 = 700 MHz).
7.3.4.2.2 Serializer Spread Spectrum Compatibility
The serializer RXCLKIN is capable of tracking spread spectrum clocking (SSC) from a host source. The
RXCLKIN accepts spread spectrum tracking up to 35-kHz modulation and ±0.5, ±1, or ±2% deviations (center
spread). The maximum conditions for the RXCLKIN input are: a modulation frequency of 35 kHz and amplitude
deviations of ±2% (4% total).
7.3.4.3 Power-Saving Features
7.3.4.3.1 Serializer Power-Down Feature (PDB)
The serializer has a PDB input pin to enable or power down the device. This pin is controlled by the host and is
used to save power, disabling the link when the display is not required. In power-down mode, the high-speed
driver outputs are both pulled to VDD and present a 0-V VOD state.
NOTE
In power-down, the optional serial bus control registers are RESET.
7.3.4.3.2 Serializer Stop Clock Feature
The serializer enters a low power SLEEP state when the RXCLKIN is stopped. A STOP condition is detected
when the input clock frequency is less than 3 MHz. The clock must be held at a static low or high state. When
the RXCLKIN starts again, the serializer locks to the valid input clock and then transmits the serial data to the
deserializer.
NOTE
In STOP CLOCK SLEEP, the optional serial bus control registers values are RETAINED.
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7.3.4.3.3 Serializer 1.8-V or 3.3-V VDDIO Operation
The serializer parallel control bus can operate with 1.8-V or 3.3-V levels (VDDIO) for host compatibility. The 1.8-V
levels offers lower noise (EMI) and also system power savings.
7.3.5 Deserializer Functional Description
The deserializer converts a single input serial data stream to a Channel Link LVDS clock and data bus and also
provides a signal check for the chipset Built-In Self Test (BIST) mode. The device can be configured through
external and strap pins or through the optional serial control bus. The deserializer features enhanced signal
quality on the link by supporting an integrated equalizer on the serial input and Channel Link II data encoding
which provides randomization, scrambling, and DC-balancing of the data. The deserializer includes multiple
features to reduce EMI associated with display data transmission. This includes the randomization and
scrambling of the data, Channel Link LVDS output interface, and output spread spectrum clock generation
(SSCG) support. The deserializer includes power saving features with a power-down mode and optional
LVCMOS (1.8-V) interface compatibility.
7.3.5.1 Signal Quality Enhancers
7.3.5.1.1 Deserializer Input Equalizer Gain (EQ)
The deserializer can enable receiver input equalization of the serial stream to increase the eye opening to the
deserializer input.
NOTE
This function cannot be seen at the RXIN± input. The equalization feature may be
controlled by the external pin or by register.
Table 3. Receiver Equalization Configuration
EQ (STRAP OPTION)
EFFECT
L
~1.625 dB (OFF)
H
~13 dB
7.3.5.2 EMI Reduction Features
7.3.5.2.1 Deserializer VOD Select (VODSEL)
The differential output voltage of the Channel Link parallel interface is controlled by the VODSEL input.
Table 4. Deserializer Differential Output Voltage
INPUT
EFFECT
VODSEL
VOD (mV)
VOD (mVp-p)
L
±250
500
H
±400
800
7.3.5.2.2 Deserializer Common-Mode Filter Pin (CMF) (Optional)
The deserializer provides access to the center tap of the internal termination. A capacitor may be placed on this
pin for additional common-mode filtering of the differential pair. This can be useful in high-noise environments for
additional noise rejection capability. A 4.7-µF capacitor may be connected from this pin to Ground.
7.3.5.2.3 Deserializer SSCG Generation (Optional)
The deserializer provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both
clock and data outputs are modulated. This aids to lower system EMI. Output SSCG deviations of ±2% (4% total)
at up to 100-kHz modulations are available (see Table 5). This feature may be controlled by external pins or by
register.
28
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NOTE
The deserializer supports the SSCG function with TXCLKOUT = 10 MHz to 65 MHz.
When the TXCLKOUT = 65 MHz to 75 MHz, it is required to disable the SSCG function
(SSC[2:0] = 000).
Frequency
fdev(max)
FPCLK+
FPCLK
FPCLK-
fdev(min)
Time
1/fmod
Figure 28. SSCG Waveform
Table 5. SSCG Configuration (LFMODE = L): Deserializer Output
SSC[2:0] INPUTS
LFMODE = L (20 TO 65 MHz)
RESULT
SSC2
SSC1
SSC0
fdev (%)
fmod (kHz)
L
L
L
L
L
Off
Off
H
±0.9
L
H
L
±1.2
L
H
H
±1.9
H
L
L
±2.3
H
L
H
±0.7
H
H
L
±1.3
H
H
H
±1.7
CLK/2168
CLK/1300
Table 6. SSCG Configuration (LFMODE = H): Deserializer Output
SSC[2:0] INPUTS
LFMODE = H (10 TO 20 MHz)
RESULT
SSC2
SSC1
SSC0
fdev (%)
fmod (kHz)
L
L
L
L
L
Off
Off
H
±0.7
L
H
L
±1.3
L
H
H
±1.8
H
L
L
±2.2
H
L
H
±0.7
H
H
L
±1.2
H
H
H
±1.7
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CLK/385
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7.3.5.2.4 Power-Saving Features
7.3.5.2.4.1 Deserializer Power-Down Feature (PDB)
The deserializer has a PDB input pin to enable or power down the device. This pin can be controlled by the
system to save power, disabling the deserializer when the display is not required. An auto-detect mode is also
available. In this mode, the PDB pin is tied high and the deserializer enters power-down when the serial stream
stops. When the serial stream starts up again, the deserializer locks to the input stream, asserts the LOCK pin,
and outputs valid data. In power-down mode, the LVDS data and clock output states are determined by the
OSS_SEL status.
NOTE
In power-down, the optional serial bus control registers are RESET.
7.3.5.2.4.2 Deserializer Stop Stream SLEEP Feature
The deserializer enters a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer
then locks to the incoming signal and recovers the data.
NOTE
In STOP STREAM SLEEP, the optional serial bus control registers values are RETAINED.
7.3.5.2.4.3 Deserializer 1.8-V or 3.3-V VDDIO Operation
The deserializer parallel control bus can operate with 1.8-V or 3.3-V levels (VDDIO) for target (display)
compatibility. The 1.8-V levels offers lower noise (EMI) and also system power savings.
7.3.5.3 Deserializer Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN), and Output State
Select (OSS_SEL)
When PDB is driven high, the CDR PLL begins locking to the serial input, and LOCK goes from TRI-STATE to
low (depending on the value of the OSS_SEL setting). After the DS92LV0422 completes its lock sequence to the
input serial data, the LOCK output is driven high, indicating valid data and clock recovered from the serial input is
available on the Channel Link outputs. The TXCLKOUT output is held at its current state at the change from
OSC_CLK (if this is enabled through OSC_SEL) to the recovered clock (or vice versa).
NOTE
The Channel Link outputs may be held in an inactive state (TRI-STATE) through the use
of the Output Enable pin (OEN).
If there is a loss of clock from the input serial stream, LOCK is driven low and the state of the outputs are based
on the OSS_SEL setting (configuration pin or register).
30
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Table 7. PDB, OEN, and OSS_SEL Configuration (Deserializer Outputs)
INPUTS
OUTPUTS
SERIAL
INPUT
PDB
OEN
OSS_SEL
LOCK
X
L
X
X
X
TXCLKOUT is TRI-STATE
TXOUT[3:0] are TRI-STATE
PASS is TRI-STATE
Static
H
X
L
L
TXCLKOUT is TRI-STATE
TXOUT[3:0] are TRI-STATE
PASS is HIGH
Static
H
L
H
L
TXCLKOUT is TRI-STATE
TXOUT[3:0] are TRI-STATE
PASS is TRI-STATE
Static
H
H
H
L
TXCLKOUT is TRI-STATE or Oscillator Output through Register bit
TXOUT[3:0] are TRI-STATE
PASS is TRI-STATE
Active
H
L
X
H
TXCLKOUT is TRI-STATE
TXOUT[3:0] are TRI-STATE
PASS is Active
Active
H
H
X
H
TXCLKOUT is Active
TXOUT[3:0] are Active
PASS is Active
(Normal operating mode)
OTHER OUTPUTS
7.3.5.4 Deserializer Oscillator Output (Optional)
The deserializer provides an optional clock output when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled
by external pin or by register.
PDB
RIN
(Diff.)
LOCK
TxOUT[3:0]
TxCLKOUT
active serial stream
X
H
H
L
L
L
Z
Z
Z
Z
Z
f
f
Z
Z
Z
PASS
OFF
OSC Output
Active
OSC Output
Active
OFF
CONDITIONS: OEN = H, OSS_SEL = H, and OSC_SEL not equal to 000.
Figure 29. TXCLKOUT Output Oscillator Option Enabled
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7.3.6 Built-In Self Test (BIST)
An optional at-speed Built-In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test, and for system diagnostics. In BIST mode,
only an input clock is required along with control to the serializer and deserializer BISTEN input pins. The
serializer outputs a test pattern (PRBS-7) and drives the link at speed. The deserializer detects the PRBS-7
pattern and monitors it for errors. A PASS output pin toggles to flag any payloads that are received with 1 to 24
errors. Upon completion of the test, the result of the test is held on the PASS output until reset (new BIST test or
power-down). A high on PASS indicates NO ERRORS were detected. A low on PASS indicates one or more
errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN
pin.
Inter-operability is supported between this Channel Link II device and all Channel Link II generations (Gen 1/2/3);
see respective data sheets for details on entering BIST mode and control.
7.3.6.1 Sample BIST Sequence
See Figure 30 for the BIST mode flow diagram.
Step 1: Place the serializer in BIST Mode by setting serializer BISTEN = H. BIST Mode is enabled through the
BISTEN pin. An RXCLKIN is required for BIST. When the deserializer detects the BIST mode pattern and
command (DCA and DCB code), the data and control signal outputs are shut off.
Step 2: Place the deserializer in BIST mode by setting the BISTEN = H. The deserializer is now in BIST mode
and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin
switches low for one half of the clock period. During the BIST test, the PASS output can be monitored and
counted to determine the payload error rate.
Step 3: To stop BIST mode, the deserializer BISTEN pin is set low. The deserializer stops checking the data, and
the final test result is held on the PASS pin. If the test ran error free, the PASS output is high. If there is one or
more errors detected, the PASS output is low. The PASS output state is held until a new BIST is run, the device
is RESET, or powered down. The BIST duration is user controlled by the duration of the BISTEN signal.
Step 4: To return the link to normal operation, the serializer BISTEN input is set low. The link returns to normal
operation.
Figure 31 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error-free, and Case 2
shows one with multiple errors. In most cases, it is difficult to generate errors due to the robustness of the link
(differential data transmission and so forth), thus they may be introduced by greatly extending the cable length,
faulting the interconnect, or reducing signal condition enhancements (de-emphasis, VODSEL, or Rx
equalization).
Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: SER in Normal
Figure 30. BIST Mode Flow Diagram
32
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Deserializer Outputs Case 1 - Pass
BISTEN
(Serializer)
BISTEN
(Deserializer)
TxCLKOUT
(Diff.)
TxOUT[3:0]
(Diff.)
DATA
(internal)
PASS
Prior Result
PASS
PASS
X
X
X
FAIL
Prior Result
Normal
Case 2 - Fail
X = bit error(s)
DATA
(internal)
PRBS
BIST Test
BIST Duration
BIST
Result
Held
Normal
Figure 31. BIST Waveforms
7.3.6.2 BER Calculations
It is possible to calculate the approximate Bit Error Rate (BER). The following is required:
• Clock Frequency (MHz)
• BIST Duration (seconds)
• BIST Test Result (PASS)
The BER is less than or equal to one over the product of 24 times the RXCLKIN rate times the test duration. If
we assume a 65-MHz clock, a 10-minute (600 seconds) test, and a PASS, the BER is ≤ 1.07 × 10E-12.
BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. If the recovery of
the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin switches low. The combination
of the LOCK and at-speed BIST PASS pin provides a powerful tool for system evaluation and performance
monitoring.
7.3.7 Optional Serial Bus Control
The serializer and deserializer may also be configured by the use of a serial control bus that is I2C protocolcompatible. By default, the I2C Reg 0x00 = 0x00, and all configuration is set by control or strap pins. Writing Reg
0x00 = 0x01 enables or allows configuration by registers; this overrides the control or strap pins. Multiple devices
may share the serial control bus, because multiple addresses are supported (see Figure 32).
The serial bus is comprised of three pins. The SCL is a serial bus clock input. The SDA is the serial bus data
input or output signal. Both SCL and SDA signals require an external pullup resistor to VDDIO. For most
applications, a 4.7-kΩ pullup resistor to VDDIO may be used. The resistor value may be adjusted for capacitive
loading and data rate requirements. The signals are either pulled high or driven low.
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1.8V
10k
3.3V
ID[X]
4.7k
4.7k
RID
SCL
DS92LV0421/
DS92LV0422
SCL
SDA
SDA
HOST
To other
Devices
Copyright © 2016, Texas Instruments Incorporated
Figure 32. Serial Control Bus Connection
The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Two different connections are
possible:
• The pin may be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ resistor.
• The pin may be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ resistor and pulled down to ground with a
recommended value RID resistor. This creates a voltage divider that sets the other three possible addresses.
See Table 8 for the serializer and Table 9 for the deserializer. Do not tie ID[X] directly to VSS.
Table 8. ID[X] Resistor Value: DS92LV0421 (Serializer)
RESISTOR
RID kΩ (1)
(5% TOL)
(1)
ADDRESS
7'b
ADDRESS
8'b
0 APPENDED (WRITE)
0.47
7b' 110 1001 (h'69)
8b' 1101 0010 (h'D2)
2.7
7b' 110 1010 (h'6A)
8b' 1101 0100 (h'D4)
8.2
7b' 110 1011 (h'6B)
8b' 1101 0110 (h'D6)
Open
7b' 110 1110 (h'6E)
8b' 1101 1100 (h'DC)
RID ≠ 0 Ω. Do not connect directly to VSS (GND). This is not a valid address.
Table 9. ID[X] Resistor Value – DS92LV0422 (Deserializer)
(1)
34
RESISTOR
RID kΩ (1)
(5% TOL)
ADDRESS
7'b
ADDRESS
8'b
0 APPENDED (WRITE)
0.47
7b' 111 0001 (h'71)
8b' 1110 0010 (h'E2)
2.7
7b' 111 0010 (h'72)
8b' 1110 0100 (h'E4)
8.2
7b' 111 0011 (h'73)
8b' 1110 0110 (h'E6)
Open
7b' 111 0110 (h'76)
8b' 1110 1100 (h'EC)
RID ≠ 0 Ω. Do not connect directly to VSS (GND). This is not a valid address.
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The serial bus protocol is controlled by START, START-repeated, and STOP phases. A START occurs when
SCL transitions low while SDA is high. A STOP occurs when SDA transitions high while SCL is also high (see
Figure 33).
SDA
SCL
S
P
START condition, or
START repeat condition
STOP condition
Figure 33. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match the slave address of a device, it Not-acknowledges (NACKs) the master by letting SDA be pulled high.
ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs
after every data byte is successfully received. When the master is reading data, the master ACKs after every
data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a start condition or a repeated start condition. All communication on the bus ends with a stop
condition. A READ is shown in Figure 34 and a WRITE is shown in Figure 35.
NOTE
During initial power-up, a delay of 10 ms is required before the I2C responds.
If the serial bus is not required, the three pins may be left open (NC).
Register Address
Slave Address
S
A A A
2 1 0
0
Slave Address
a
c
k
a
c
k
S
A A
2 1
A
0
Data
1
a
c
k
a
c
k
P
Figure 34. Serial Control Bus: READ
Register Address
Slave Address
S
a
A A A
c
2 1 0 0 k
Data
a
c
k
a
c
k
P
Figure 35. Serial Control Bus: WRITE
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7.4 Device Functional Modes
7.4.1 Serializer and Deserializer Operating Modes and Reverse Compatibility (CONFIG[1:0])
The DS92LV042x chipset is compatible with other single serial lane Channel Link II or FPD-Link II devices.
Configuration modes are provided for reverse compatibility with the DS90C241 or DS90C124 chipset (FPD-Link
II Generation 1) and also the DS90UR241 / DS90UR124 chipset (FPD-Link II Generation 2) by setting the
respective mode with the CONFIG[1:0] pins on the serializer or deserializer as shown in Table 10 and Table 11.
This selection also determines whether the control signal filter feature is enabled or disabled in the normal mode.
This feature may be controlled by external pin or by register.
Table 10. DS92LV0421 Serializer Modes
CONFIG1
CONFIG0
MODE
COMPATIBLE DESERIALIZER DEVICE
L
L
Normal Mode, Control Signal Filter disabled
DS92LV0422, DS92LV0412,
DS92LV2422, DS92LV2412
L
H
Normal Mode, Control Signal Filter enabled
DS92LV0422, DS92LV0412,
DS92LV2422, DS92LV2412
H
L
Reverse Compatibility Mode (FPD-Link II, GEN2)
DS90UR124, DS99R124Q-Q1
H
H
Reverse Compatibility Mode (FPD-Link II, GEN1)
DS90C124
Table 11. DS92LV0422 Deserializer Modes
CONFIG1
36
CONFIG0
MODE
COMPATIBLE SERIALIZER DEVICE
L
L
Normal Mode, Control Signal Filter disabled
DS92LV0421, DS92LV0411,
DS92LV2421, DS92LV2411
L
H
Normal Mode, Control Signal Filter enabled
DS92LV0421, DS92LV0411,
DS92LV2421, DS92LV2411
H
L
Reverse Compatibility Mode (FPD-Link II, GEN2)
DS90UR241, DS99R421
H
H
Reverse Compatibility Mode (FPD-Link II, GEN1)
DS90C241
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7.5 Register Maps
Table 12. SERIALIZER: Serial Bus Control Registers
ADD
(DEC)
0
1
ADD
(HEX)
0
1
REGISTER
NAME
Serializer
Config 1
BIT(S)
R/W
DEFAULT
(BIN)
7
R/W
0
Reserved
Reserved
6
R/W
0
MAPSEL
0: LSB on RXIN3
1: MSB on RXIN3
5
R/W
0
VODSEL
0: Low
1: High
4
R/W
0
Reserved
Reserved
2
DESCRIPTION
3:2
R/W
00
CONFIG
00: Normal Mode, Control Signal Filter Disabled
01: Normal Mode, Control Signal Filter Enabled
10: DS90UR124, DS99R124Q-Q1 ReverseCompatibility Mode (FPD-Link II, GEN2)
11: DS90C124 Reverse-Compatibility Mode (FPDLink II, GEN1)
1
R/W
0
SLEEP
Note – not the same function as PowerDown (PDB)
0: Normal Mode
1: Sleep Mode – Register settings retained.
0
R/W
0
REG
0: Configurations set from control pins
1: Configuration set from registers (except I2C_ID)
7
R/W
0
REG ID
0: Address from ID[X] Pin
1: Address from Register
ID[X]
Serial Bus Device ID, four IDs are:
7b '1101 001 (h'69)
7b '1101 010 (h'6A)
7b '1101 011 (h'6B)
7b '1101 110 (h'6E)
All other addresses are reserved.
Device ID
6:0
2
FUNCTION
R/W
1101000
7:5
R/W
000
4
R/W
0
3:0
R/W
0000
De-Emphasis
Control
000: set by external resistor
001: –1 dB
010: –2 dB
De-Emphasis 011: –3.3 dB
Setting
100: –5 dB
101: –6.7 dB
110: –9 dB
111: –12 dB
De-Emphasis 0: De-emphasis Enabled
EN
1: De-emphasis Disabled
Reserved
Reserved
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Table 13. DESERIALIZER: Serial Bus Control Registers
ADD
(DEC)
0
1
2
ADD
(HEX)
0
1
2
REGISTER
NAME
BIT(S)
R/W
DEFAULT
(BIN)
7
R/W
0
LFMODE
0: 20 to 65 MHz SSCG Operation
1: 10 to 20 MHz SSCG Operation
6
R/W
0
MAPSEL
Channel Link Map Select
0: LSB on TXOUT3±
1: MSB on TXOUT3±
5
R/W
0
Reserved
Reserved
4
R/W
0
Reserved
Reserved
3:2
R/W
00
CONFIG
1
R/W
0
SLEEP
Note – not the same function as PowerDown (PDB)
0: Normal Mode
1: Sleep Mode – Register settings retained.
0
R/W
0
REG Control
0: Configurations set from control or strap pins
1: Configuration set from registers (except I2C_ID)
7
R/W
0
REG ID
0: Address from ID[X] Pin
1: Address from Register
6:0
R/W
1110000
ID[X]
Serial Bus Device ID, four IDs are:
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
All other addresses are reserved.
7
R/W
0
OEN
Output Enable Input
See Table 7
6
R/W
0
OSS_SEL
Output Sleep State Select
See Table 7
5:4
R/W
00
Reserved
Reserved
3
R/W
0
VODSEL
Differential LVDS Driver Output Voltage Select
0: LVDS VOD is ±250 mV, 500 mVp-p (typ)
1: LVDS VOD is ±400 mV, 800 mVp-p (typ)
OSC_SEL
000: OFF
001: Reserved
010: 25 MHz ± 40%
011: 16.7 MHz ± 40%
100: 12.5 MHz ± 40%
101: 10 MHz ± 40%
110: 8.3 MHz ± 40%
111: 6.3 MHz ± 40%
Device ID
Deserializer
Features 1
DESCRIPTION
00: Normal Mode, Control Signal Filter Disabled
01: Normal Mode, Control Signal Filter Enabled
10: DS90UR241, DS99R421 Reverse-Compatibility
Mode (FPD-Link II, GEN2)
11: DS90C241 Reverse-Compatibility Mode (FPDLink II, GEN1)
Deserializer
Config 1
2:0
38
FUNCTION
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R/W
000
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Table 13. DESERIALIZER: Serial Bus Control Registers (continued)
ADD
(DEC)
3
ADD
(HEX)
3
REGISTER
NAME
BIT(S)
R/W
DEFAULT
(BIN)
FUNCTION
EQ Gain
000:
001:
010:
011:
100:
101:
110:
111:
0
EQ Enable
0: EQ = disabled
1: EQ = enabled
0
Reserved
Reserved
SSC
If LFMODE = 0 then:
000: SSCG OFF
001: fdev = ±0.9%, fmod
010: fdev = ±1.2%, fmod
011: fdev = ±1.9%, fmod
100: fdev = ±2.3%, fmod
101: fdev = ±0.7%, fmod
110: fdev = ±1.3%, fmod
111: fdev = ±1.7%, fmod
If LFMODE = 1, then:
001: fdev = ±0.7%, fmod
010: fdev = ±1.3%, fmod
011: fdev = ±1.8%, fmod
100: fdev = ±2.2%, fmod
101: fdev = ±0.7%, fmod
110: fdev = ±1.2%, fmod
111: fdev = ±1.7%, fmod
7:5
R/W
000
4
R/W
3
R/W
Deserializer
Features 2
2:0
R/W
DESCRIPTION
000
~1.625 dB
~3.25 dB
~4.87 dB
~6.5 dB
~8.125 dB
~9.75 dB
~11.375 dB
~13 dB
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= CLK/2168
= CLK/2168
= CLK/2168
= CLK/2168
= CLK/1300
= CLK/1300
= CLK/1300
= CLK/625
= CLK/625
= CLK/625
= CLK/625
= CLK/385
= CLK/385
= CLK/385
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Display Application
The DS92LV042x chipset is intended for interface between a host (graphics processor) and a display. It supports
a 24-bit color depth (RGB888) and up to 1024 × 768 display formats. In a RGB888 application, 24 color bits
(R[7:0], G[7:0], and B[7:0]), Pixel Clock (PCLK), and three control bits (VS, HS, and DE) are supported across
the serial link with RXCLKIN rates from 10 to 75 MHz. The chipset may also be used in 18-bit color applications.
In this application, three to six general-purpose signals may also be sent from host to display.
8.1.2 Live Link Insertion
The serializer and deserializer devices support live link or cable hot plug applications. The automatic receiver
lock to random data plug and go hot insertion capability allows the DS92LV0422 to attain lock to the active data
stream during a live insertion event.
8.1.3 Alternate Color or Data Mapping
Color-mapped data pin names are provided to specify a recommended mapping for 24-bit and 18-bit
applications. Seven (7) is assumed to be the MSB, and Zero (0) is assumed to be the LSB. While this is
recommended, it is not required. When connecting to earlier generations of FPD-Link II serializer and deserializer
devices, a color mapping review is recommended to ensure the correct connectivity is obtained. Table 14
provides examples for interfacing between DS92LV0421 and different deserializers. Table 15 provides examples
for interfacing between DS92LV0422 and different serializers.
Table 14. Serializer Alternate Color or Data Mapping
CHANNEL
LINK
RXIN3
RXIN2
40
BIT NUMBER
RGB (LSB
EXAMPLE)
DS92LV2422
Bit 26
B1
B1
Bit 25
B0
B0
Bit 24
G1
G1
Bit 23
G0
G0
Bit 22
R1
R1
DS90UR124
DS99R124Q-Q1
DS90C124
N/A
N/A
N/A
Bit 21
R0
R0
Bit 20
DE
DE
ROUT20
ROUT20
Bit 19
VS
VS
ROUT19
ROUT19
Bit 18
HS
HS
ROUT18
Bit 17
B7
B7
ROUT17
Bit 16
B6
B6
ROUT16
ROUT16
Bit 15
B5
B5
ROUT15
ROUT15
Bit 14
B4
B4
ROUT14
ROUT14
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ROUT18
TXOUT2
ROUT17
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SNLS325D – MAY 2010 – REVISED DECEMBER 2016
Application Information (continued)
Table 14. Serializer Alternate Color or Data Mapping (continued)
CHANNEL
LINK
RXIN1
RXIN0
N/A
DS92LV0421
SETTINGS
(1)
BIT NUMBER
RGB (LSB
EXAMPLE)
DS92LV2422
DS90UR124
Bit 13
B3
B3
ROUT13
ROUT13
ROUT12
DS99R124Q-Q1
DS90C124
Bit 12
B2
B2
ROUT12
Bit 11
G7
G7
ROUT11
Bit 10
G6
G6
ROUT10
Bit 9
G5
G5
ROUT9
ROUT9
Bit 8
G4
G4
ROUT8
ROUT8
Bit 7
G3
G3
ROUT7
ROUT7
Bit 6
G2
G2
ROUT6
ROUT6
Bit 5
R7
R7
ROUT5
ROUT5
Bit 4
R6
R6
ROUT4
Bit 3
R5
R5
ROUT3
Bit 2
R4
R4
ROUT2
ROUT2
Bit 1
R3
R3
ROUT1
ROUT1
Bit 0
R2
R2
ROUT0
N/A
N/A
N/A
MAPSEL = 0
ROUT23
(1)
ROUT22
(1)
ROUT21
(1)
CONFIG[1:0] = 00
ROUT11
TXOUT1
ROUT10
ROUT4
TXOUT0
ROUT3
ROUT0
OS2
(1)
ROUT23 (1)
OS1
(1)
ROUT22 (1)
OS0
(1)
ROUT21 (1)
CONFIG[1:0] = 10
CONFIG[1:0] = 11
These bits are not supported by the DS92LV0421.
Table 15. Deserializer Alternate Color or Data Mapping
CHANNEL
LINK
TXOUT3
TXOUT2
TXOUT1
BIT NUMBER
RGB (LSB
EXAMPLE)
DS92LV2421
Bit 26
B1
B1
Bit 25
B0
B0
Bit 24
G1
G1
Bit 23
G0
G0
Bit 22
R1
R1
Bit 21
R0
R0
Bit 20
DE
DE
DIN20
DIN20
Bit 19
VS
VS
DIN19
DIN19
Bit 18
HS
HS
DIN18
DIN18
Bit 17
B7
B7
DIN17
Bit 16
B6
B6
DIN16
DIN16
Bit 15
B5
B5
DIN15
DIN15
Bit 14
B4
B4
DIN14
DIN14
Bit 13
B3
B3
DIN13
DIN13
Bit 12
B2
B2
DIN12
DIN12
Bit 11
G7
G7
DIN11
DIN11
Bit 10
G6
G6
DIN10
Bit 9
G5
G5
DIN9
DIN9
Bit 8
G4
G4
DIN8
DIN8
Bit 7
G3
G3
DIN7
DIN7
DS90UR241
DS99R421
DS90C241
N/A
N/A
N/A
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RXIN1
DIN17
DIN10
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Table 15. Deserializer Alternate Color or Data Mapping (continued)
CHANNEL
LINK
TXOUT0
N/A
DS92LV0422
SETTINGS
(1)
42
BIT NUMBER
RGB (LSB
EXAMPLE)
DS92LV2421
DS90UR241
Bit 6
G2
G2
DIN6
DIN6
Bit 5
R7
R7
DIN5
DIN5
Bit 4
R6
R6
DIN4
DIN4
Bit 3
R5
R5
DIN3
Bit 2
R4
R4
DIN2
DIN2
Bit 1
R3
R3
DIN1
DIN1
Bit 0
R2
R2
N/A
N/A
MAPSEL = 0
N/A
CONFIG[1:0] = 00
DS99R421
RXIN0
DIN0
DS90C241
DIN3
DIN0
DIN23 (1)
OS2 (1)
DIN23 (1)
DIN22 (1)
OS1 (1)
DIN22 (1)
DIN21 (1)
OS0 (1)
DIN21 (1)
CONFIG[1:0] = 10
CONFIG[1:0] = 11
These bits are not supported by the DS92LV0422.
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8.2 Typical Application
8.2.1 DS92LV0421 Typical Connection
Figure 36 shows a typical application of the DS92LV0421 serializer in pin control mode for a 24-bit application.
The LVDS inputs require external 100-Ω differential termination resistors. The CML outputs require 0.1-µF, ACcoupling capacitors to the line. The line driver includes internal termination. Bypass capacitors are placed near
the power supply pins. At a minimum, four 0.1-µF capacitors and a 4.7-µF capacitor must be used for local
device bypassing. Ferrite beads are placed on the power lines for effective noise suppression. System GPO
(General Purpose Output) signals control the PDB and BISTEN pins. A delay cap is placed on the PDB signal to
delay the enabling of the device until power is stable.
The application assumes connection to the companion deserializer (DS92LV0422), and therefore the
configuration pins CONFIG[1:0] are also both tied low. In this example, the cable is long, and therefore the
VODSEL pin is tied high and a De-Emphasis value is selected by the resistor R1. The interface to the host is
with 1.8-V LVCMOS levels, thus the VDDIO pin is connected also to the 1.8-V rail. The optional serial bus control
is not used in this example, thus the SCL, SDA and ID[X] pins can be left open.
DS92LV0421
VDDIO
VDDIO
C10
C8
FB1
C3
1.8V
VDDTX
VDDHS
C4
FB2
C5
FB3
C6
FB4
C7
FB5
C9
C11
VDDP
C12
RxCLKIN-
VDDL
RxCLKIN+
RxIN3RxIN3+
Channel Link
Interface
VDDRX
RxIN2RxIN2+
LVDS
100 : Terminations
RxIN1RxIN1+
RxIN0RxIN0+
C1
Serial
Channel Link II
Interface
DOUT+
1.8V
DOUTC2
10k
ID[X]
SCL
SDA
RID
VDDIO
VODSEL
De-Emph
R1
Host
Control
BISTEN
PDB
R
C13
CONFIG1
CONFIG0
MAPSEL
RES7
RES6
RES5
RES4
RES3
RES2
RES1
RES0
DAP (GND)
NOTE:
C1-C2 = 0.1 PF (50 WV)
C3-C9 = 0.1 PF
C10-C12 = 4.7 PF
C13 = >10 PF
R = 10 k:
R1 (cable insertion loss specific)
RID (see ID[x] Resistor Value Table)
FB1-FB5: Impedance = 1 k:,
low DC resistance (<1:)
Copyright © 2016, Texas Instruments Incorporated
Figure 36. DS92LV0421 Typical Connection Diagram
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Typical Application (continued)
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 16 as the input parameters.
Table 16. Design Parameters
PARAMETER
VALUE
VDDIO
1.8 V or 3.3 V
VDDL, VDDP, VDDHS, VDDTX, VDDRX
1.8 V
AC Coupling Capacitor for DOUT±
100 nF
8.2.1.2 Detailed Design Procedure
The DOUT± outputs require 100-nF, AC-coupling capacitors to the line. Channel-Link data input pairs require an
external 100-Ω termination for standard LVDS levels. The power supply filter capacitors are placed near the
power supply pins. A smaller capacitance capacitor must be placed closer to the power supply pins. Adding a
ferrite bead is optional, and if used, TI recommends using a ferrite bead with 1-kΩ impedance and low DC
resistance (less than 1 Ω). The VODSEL pin is tied to VDDIO for long cable applications. The de-emphasis pin
may connect a resistor to Ground (see Table 2). The PDB and BISTEN pins are assumed to be controlled by a
microprocessor. The PDB must remain in a low state until all power supply voltages reach the final voltage. The
CONFIG[1:0] pins are set depending on operating modes and backward compatibility (see Table 10). The
MAPSEL pin sets the mapping scheme (see Figure 23 and Figure 24). The SCL, SDA, and ID[X] pins can be left
open when these serial bus control pins are unused. The RES[7:0] pins and DAP must be tied to Ground.
8.2.1.3 Application Curves
Figure 37. Serializer CML Output Stream,
RXCLKIN = 65 MHz, VODSEL = L
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Figure 38. Serializer CML Output Stream,
RXCLKIN = 65 MHz, VODSEL = H
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8.2.2 DS92LV0422 Typical Application
Figure 39 shows a typical application of the DS92LV0422 for a 24-bit application. The CML inputs require 0.1-µF,
AC-coupling capacitors to the line, and the receiver provides internal termination. Bypass capacitors are placed
near the power supply pins. At a minimum, four 0.1-µF capacitors and a 4.7-µF capacitor must be used for local
device bypassing. Ferrite beads are placed on the power lines for effective noise suppression. System GPO
(General Purpose Output) signals control the PDB and BISTEN pins. A delay cap is placed on the PDB signal to
delay the enabling of the device until power is stable.
The application assumes connection to the companion serializer (DS92LV0421), and therefore the configuration
pins CONFIG[1:0] are also both tied low. The interface to the host is with 1.8-V LVCMOS levels, thus the VDDIO
pin is connected also to the 1.8-V rail. The optional serial bus control is not used in this example, thus the SCL,
SDA, and ID[X] pins can be left open.
DS92LV0422
1.8V
VDDL
C11
3.3V
FB4
FB1
VDDTX
C6
C3
C8
C9
C12
VDDL
FB2
VDDIO
FB5
VDDA
C4
VDDIO
C7
VDDA
C10
FB3
C13
VDDP
C5
VDDSC
VDDSC
TxCLKOUT+
TxCLKOUT-
C1
TxOUT3+
RIN+
TxOUT3-
Serial
Channel Link II
Interface
TxOUT2+
RINC2
Channel
Link
Interface
TxOUT2TxOUT1+
CMF
TxOUT1-
C15
TxOUT0+
TxOUT0BISTEN
Host
Control
PDB
LOCK
R
C14
PASS
1.8V
10k
ID[X]
SCL
SDA
RID
C1 - C2 = 0.1 PF (50 WV)
C3 ± C10 = 0.1 PF
C11 - C13 = 4.7 PF
C14, C15 = >10 PF
R = 10 k:
RID (See ID[x] Resistor Value Table)
FB1 - FB5: Impedance = 1 k:
Low DC resistance ( <1:)
8
RES
GND
DAP (GND)
OEN
OSS_SEL
LFMODE
VODSEL
MAPSEL
CONFIG1
CONFIG0
SSC[2]
SSC[1]
SSC[0]
Copyright © 2016, Texas Instruments Incorporated
Figure 39. DS92LV0422 Typical Connection Diagram
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8.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 17 as the input parameters.
Table 17. Design Parameters
PARAMETER
VALUE
VDDIO
1.8 V or 3.3 V
VDDL, VDDP, VDDSC, VDDA
1.8 V
VDDTX
3.3 V
AC Coupling Capacitor for RIN±
100 nF
8.2.2.2 Detailed Design Procedure
The RIN± inputs require 100-nF, AC-coupling capacitors to the line. The power supply filter capacitors are placed
near the power supply pins. A smaller capacitance capacitor must be placed closer to the power supply pins. The
device has one configuration pin (EQ) called a strap pin, which is pulled down by default. For a high state, use a
10-kΩ resistor pullup to VDDIO. The PDB and BISTEN pins are assumed to be controlled by a microprocessor.
The PDB must remain in a low state until all power supply voltages reach the final voltage. The SCL, SDA, and
ID[X] pins can be left open when these serial bus control pins are unused. The RES pin and DAP must be tied to
Ground.
TXOUT3±
(500 mV/DIV)
TXOUT3±
(200 mV/DIV)
TXCLKOUT±
(500 mV/DIV)
TXCLKOUT±
(200 mV/DIV)
8.2.2.3 Application Curves
Time (4 ns/DIV)
Time (4 ns/DIV)
Figure 40. LVDS Parallel Output Data and Clock,
PRBS-7, TXCLKOUT = 75 MHz, VODSEL = L
Figure 41. LVDS Parallel Output Data and Clock,
PRBS-7, TXCLKOUT = 75 MHz, VODSEL = H
9 Power Supply Recommendations
The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower than 1.5 ms,
a capacitor on the PDB pin is required to ensure PDB arrives after all the VDD supplies have settled to the
recommended operating voltage. When the PDB pin is pulled to VDDIO, TI recommends using a 10-kΩ pullup and
a 22-µF cap to Ground to delay the PDB input signal.
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10 Layout
10.1 Layout Guidelines
Circuit board layout and stack-up for the LVDS serializer and deserializer devices must be designed to provide
low-noise power feed to the device. Good layout practice also separates high frequency or high-level inputs and
outputs to minimize unwanted stray noise pickup, feedback, and interference. Power system performance may
be greatly improved by using thin dielectrics (2 to 4 mils) for power or ground sandwiches. This arrangement
provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven
especially effective at high frequencies and makes the value and placement of external bypass capacitors less
critical. External bypass capacitors must include both RF ceramic and tantalum electrolytic types. RF capacitors
may use values in the range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range.
Voltage rating of the tantalum capacitors must be at least 5x the power supply voltage being used.
Surface-mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, place the smaller value closer to the pin. A large bulk capacitor is recommended at the point of power
entry. This is typically in the 50-µF to 100-µF range and smooths low frequency switching noise. TI recommends
connecting power and ground pins directly to the power and ground planes with bypass capacitors connected to
the plane, with vias on both ends of the capacitor. Connecting power or ground pins to an external bypass
capacitor increases the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four-layer board with a power and ground plane. Place LVCMOS signals away from the CML lines
to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ω are
typically recommended for LVDS interconnects. The closely coupled lines help to ensure that coupled noise
appears as common mode and thus is rejected by the receivers. The tightly coupled lines also radiate less.
10.1.1 WQFN (LLP) Stencil Guidelines
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the LLP (WQFN) package is highly recommended to
improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in Figure 42 and
Figure 43.
Figure 42. No Pullback LLP, Single Row Reference Diagram
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Layout Guidelines (continued)
Table 18. No Pullback LLP Stencil Aperture Summary for DS92LV0421 and DS92LV0422
PCB DAP
SIZE (mm)
STENCIL I/O
APERTURE
(mm)
STENCIL DAP
APERTURE
(mm)
NUMBER OF
DAP
APERTURE
OPENINGS
GAP BETWEEN
DAP APERTURE
(Dim A mm)
0.5
4.6 x 4.6
0.25 × 0.7
1.0 × 1.0
16
0.2
0.5
5.1 × 5.1
0.25 × 0.7
1.1 × 1.1
16
0.2
DEVICE
PIN
COUNT
MKT
DWG
PCB I/O
PAD SIZE
(mm)
PCB
PITCH
(mm)
DS92LV0421
36
SQA36A
0.25 × 0.6
DS92LV0422
48
SQA48A
0.25 × 0.6
Figure 43. 48-Pin WQFN Stencil Example of Via and Opening Placement
Information on the WQFN style package is provided in Leadless Leadframe Package (LLP) Application Report
(SNOA401).
10.1.2 Transmission Media
The serializer and deserializer chipset is intended to be used in a point-to-point configuration through a PCB
trace or through twisted pair cable. The serializer and deserializer provide internal terminations for a clean
signaling environment. The interconnect for LVDS must present a differential impedance of 100 Ω. Use cables
and connectors that have matched differential impedance to minimize impedance discontinuities. Shielded or unshielded cables may be used depending upon the noise environment and application requirements.
10.1.3 LVDS Interconnect Guidelines
See AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and AN-905 Transmission
Line RAPIDESIGNER Operation and Applications Guide (SNLA035) for full details.
• Use 100-Ω coupled differential pairs
• Use the S, 2S, 3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of vias
• Use differential connectors when operating above 500-Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the Tx outputs and Rx inputs as possible
Additional general guidance can be found in the LVDS Owner's Manual, available in PDF format from the TI
website at: www.ti.com/lvds.
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10.2 Layout Example
The following PCB layout examples are derived from the layout design of the LV04EVK01 Evaluation Module.
These graphics and additional layout description are used to demonstrate both proper routing and proper solder
techniques when designing in the serializer and deserializer pair.
Figure 44. DS92LV0421 Serializer Example Layout
Figure 45. DS92LV0422 Deserializer Example Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
For developmental support, see the following:
Overview for LVDS/M-LVDS/ECL/CML
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Absolute Maximum Ratings for Soldering (SNOA549)
• Leadless Leadframe Package (LLP) Application Report (SNOA401)
• AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008)
• AN-905 Transmission Line RAPIDESIGNER Operation and Applications Guide (SNLA035)
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 19. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DS92LV0421
Click here
Click here
Click here
Click here
Click here
DS92LV0422
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
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11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2010–2016, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
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20-Jul-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS92LV0421SQ/NOPB
ACTIVE
WQFN
NJK
36
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LV0421
DS92LV0421SQE/NOPB
ACTIVE
WQFN
NJK
36
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LV0421
DS92LV0421SQX/NOPB
ACTIVE
WQFN
NJK
36
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LV0421
DS92LV0422SQ/NOPB
ACTIVE
WQFN
RHS
48
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LV0422
DS92LV0422SQE/NOPB
ACTIVE
WQFN
RHS
48
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LV0422
DS92LV0422SQX/NOPB
ACTIVE
WQFN
RHS
48
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LV0422
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jul-2016
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
DS92LV0421SQ/NOPB
WQFN
NJK
36
DS92LV0421SQE/NOPB
WQFN
NJK
DS92LV0421SQX/NOPB
WQFN
NJK
DS92LV0422SQ/NOPB
WQFN
DS92LV0422SQE/NOPB
DS92LV0422SQX/NOPB
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
36
250
178.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
36
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
RHS
48
1000
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
WQFN
RHS
48
250
178.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
WQFN
RHS
48
2500
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS92LV0421SQ/NOPB
WQFN
NJK
36
1000
367.0
367.0
38.0
DS92LV0421SQE/NOPB
WQFN
NJK
36
250
210.0
185.0
35.0
DS92LV0421SQX/NOPB
WQFN
NJK
36
2500
367.0
367.0
38.0
DS92LV0422SQ/NOPB
WQFN
RHS
48
1000
367.0
367.0
38.0
DS92LV0422SQE/NOPB
WQFN
RHS
48
250
210.0
185.0
35.0
DS92LV0422SQX/NOPB
WQFN
RHS
48
2500
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
RHS0048A
WQFN - 0.8 mm max height
SCALE 1.800
PLASTIC QUAD FLATPACK - NO LEAD
7.15
6.85
A
B
PIN 1 INDEX AREA
0.5
0.3
7.15
6.85
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
0.08 C
2X 5.5
(0.2)
5.1 0.1
(A) TYP
24
13
44X 0.5
DIM A
OPT 1
OPT 2
(0.1)
(0.2)
12
25
EXPOSED
THERMAL PAD
2X
5.5
49
SYMM
SEE TERMINAL
DETAIL
1
PIN 1 ID
(OPTIONAL)
36
48
37
SYMM
48X
0.5
0.3
48X
0.30
0.18
0.1
0.05
C A B
4214990/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHS0048A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 5.1)
SYMM
37
48
48X (0.6)
1
36
48X (0.25)
(1.05) TYP
44X (0.5)
(1.25) TYP
49
SYMM
(6.8)
(R0.05)
TYP
( 0.2) TYP
VIA
25
12
13
24
(1.25)
TYP
(1.05)
TYP
(6.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214990/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHS0048A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.625) TYP
(1.25)
TYP
37
48
48X (0.6)
1
36
49
48X (0.25)
44X (0.5)
(1.25)
TYP
(0.625) TYP
SYMM
(6.8)
(R0.05) TYP
METAL
TYP
25
12
13
16X
( 1.05)
24
SYMM
(6.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4214990/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
MECHANICAL DATA
NJK0036A
SQA36A (Rev A)
www.ti.com
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