Texas Instruments | TPD8S300 USB Type-C Port Protector: Short-to-VBUS Overvoltage and IEC ESD Protection (Rev. B) | Datasheet | Texas Instruments TPD8S300 USB Type-C Port Protector: Short-to-VBUS Overvoltage and IEC ESD Protection (Rev. B) Datasheet

Texas Instruments TPD8S300 USB Type-C Port Protector: Short-to-VBUS Overvoltage and IEC ESD Protection (Rev. B) Datasheet
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TPD8S300
SLVSDD6B – SEPTEMBER 2016 – REVISED NOVEMBER 2016
TPD8S300 USB Type-C™ Port Protector: Short-to-VBUS Overvoltage and IEC ESD
Protection
•
•
•
•
4-Channels of Short-to-VBUS Overvoltage
Protection (CC1, CC2, SBU1, SBU2): 24-VDC
Tolerant
8-Channels of IEC 61000-4-2 ESD Protection
(CC1, CC2, SBU1, SBU2, DP_T, DM_T, DP_B,
DM_B)
CC1, CC2 Overvoltage Protection FETs 600 mA
capable for passing VCONN power
CC Dead Battery Resistors integrated for handling
dead battery use case in mobile devices
3-mm × 3-mm WQFN Package
2 Applications
•
•
•
•
•
Laptop PC
Tablets
Smartphones
Monitors and TVs
Docking Stations
Finally, most systems require IEC 61000-4-2 system
level ESD protection for their external pins. The
TPD8S300 integrates IEC 61000-4-2 ESD protection
for the CC1, CC2, SBU1, SBU2, DP_T (Top side D+),
DM_T (Top Side D–), DP_B (Bottom Side D+), DM_B
(Bottom Side D–) pins, removing the need to place
high voltage TVS diodes externally on the connector.
Device Information(1)
PART NUMBER
TPD8S300
3 Description
The TPD8S300 is a single chip USB Type-C port
protection solution that provides 20-V Short-to-VBUS
overvoltage and IEC ESD protection.
Since the release of the USB Type-C connector,
many products and accessories for USB Type-C have
been released which do not meet the USB Type-C
specification. One example of this is USB Type-C
Power Delivery adaptors that only place 20 V on the
VBUS line. Another concern for USB Type-C is that
mechanical twisting and sliding of the connector could
short pins due to the close proximity they have in this
small connector. This can cause 20-V VBUS to be
shorted to the CC and SBU pins. Also, due to the
close proximity of the pins in the Type-C connector,
there is a heightened concern that debris and
moisture will cause the 20-V VBUS pin to be shorted to
the CC and SBU pins.
PACKAGE
WQFN (20)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Diagram
Battery
FET
OVP
FET
OVP,
OCP
5V
DC/DC
VBUS
•
1
These non-ideal equipments and mechanical events
make it necessary for the CC and SBU pins to be 20V tolerant, even though they only operate at 5 V or
lower. The TPD8S300 enables the CC and SBU pins
to be 20-V tolerant without interfering with normal
operation by providing overvoltage protection on the
CC and SBU pins. The device places high voltage
FETs in series on the SBU and CC lines. When a
voltage above the OVP threshold is detected on
these lines, the high voltage switches are opened up,
isolating the rest of the system from the high voltage
condition present on the connector.
TPD8S300
OVP & ESD
AUX_P
AUX_M
DP
DM
CC Analog
USB PD Phy &
Controller
Power Switch
Control
SBU Mux
D+/D- Mux
DM_B DP_B DM_T DP_T SBU2 SBU1 CC2 CC1
1 Features
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD8S300
SLVSDD6B – SEPTEMBER 2016 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings—JEDEC Specification......................... 5
ESD Ratings—IEC Specification .............................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Timing Requirements ................................................ 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 26
12 Device and Documentation Support ................. 27
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2016) to Revision B
•
2
Page
First public release of the data sheet ..................................................................................................................................... 1
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SLVSDD6B – SEPTEMBER 2016 – REVISED NOVEMBER 2016
5 Device Comparison Table
Part Number
Over Voltage Protected Channels
IEC 61000-4-2 ESD Protected
Channels
TPD6S300
4-Ch (CC1, CC2, SBU1, SBU2)
6-Ch (CC1, CC2, SBU1, SBU2, DP,
DM)
TPD8S300
4-Ch (CC1, CC2, SBU1, SBU2)
8-Ch (CC1, CC2, SBU1, SBU2, DP_T,
DM_T, DP_B, DM_B)
6 Pin Configuration and Functions
RUK Package
20 Pin WQFN
Top View
CC1
GND
SBU2
SBU1
16
CC2
11
15
D4
VPWR 10
D3
FLT
GND
GND
1
C_CC2
RPD_G2 6
C_CC1
D1
VBIAS
RPD_G1
C_SBU2
D2
C_SBU1
20
Thermal Pad
5
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
C_SBU1
I/O
Connector side of the SBU1 OVP FET. Connect to either SBU pin of the USB Type-C
connector
2
C_SBU2
I/O
Connector side of the SBU2 OVP FET. Connect to either SBU pin of the USB Type-C
connector
3
VBIAS
Power
4
C_CC1
I/O
Connector side of the CC1 OVP FET. Connect to either CC pin of the USB Type-C
connector
5
C_CC2
I/O
Connector side of the CC2 OVP FET. Connect to either CC pin of the USB Type-C
connector
6
RPD_G2
I/O
Short to C_CC2 if dead battery resistors are needed. If dead battery resistors are not
needed, short pin to GND
7
RPD_G1
I/O
Short to C_CC1 if dead battery resistors are needed. If dead battery resistors are not
needed, short pin to GND
8
GND
GND
9
FLT
O
10
VPWR
Power
11
CC2
I/O
System side of the CC2 OVP FET. Connect to either CC pin of the CC/PD controller
12
CC1
I/O
System side of the CC1 OVP FET. Connect to either CC pin of the CC/PD controller
13
GND
GND
Pin for ESD support capacitor. Place a 0.1-µF capacitor on this pin to ground
Ground
Open drain for fault reporting
2.7-V-3.6-V power supply
Ground
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Pin Functions (continued)
PIN
NO.
NAME
TYPE
DESCRIPTION
14
SBU2
I/O
System side of the SBU2 OVP FET. Connect to either SBU pin of the SBU MUX
15
SBU1
I/O
System side of the SBU1 OVP FET. Connect to either SBU pin of the SBU MUX
16
D4
I/O
USB2.0 IEC ESD protection. Connect to any of the USB2.0 pins of the USB Type-C
connector
17
D3
I/O
USB2.0 IEC ESD protection. Connect to any of the USB2.0 pins of the USB Type-C
connector
18
GND
GND
19
D2
I/O
USB2.0 IEC ESD protection. Connect to any of the USB2.0 pins of the USB Type-C
connector
20
D1
I/O
USB2.0 IEC ESD protection. Connect to any of the USB2.0 pins of the USB Type-C
connector
—
Thermal Pad
GND
4
Ground
Internally connected to GND. Used as a heatsink. Connect to the PCB GND plane
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SLVSDD6B – SEPTEMBER 2016 – REVISED NOVEMBER 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VI
Input voltage
VO
Output voltage
VIO
I/O voltage
MIN
MAX
UNIT
VPWR
–0.3
4
V
RPD_G1, RPD_G2
–0.3
24
V
FLT
–0.3
6
V
VBIAS
–0.3
24
V
D1, D2, D3, D4
–0.3
6
V
CC1, CC2, SBU1, SBU2
–0.3
6
V
C_CC1, C_CC2, C_SBU1, C_SBU2
–0.3
24
V
TA
Operating free air temperature
–40
85
°C
Tstg
Storage temperature
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings—JEDEC Specification
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000
V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
7.3 ESD Ratings—IEC Specification
VALUE
V(ESD)
Electrostatic discharge (1)
IEC 61000-4-2, C_CC1, C_CC2, D1, D2,
D3, D4
IEC 61000-4-2, C_SBU1, C_SBU2
(1)
Contact discharge
±8000
Air-gap discharge
±15000
Contact discharge
±6000
Air-gap discharge
±15000
UNIT
V
Tested on the TPD8S300 EVM connected to the TPS65982 EVM.
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VI
Input voltage
VO
Output voltage
VIO
I/O voltage
VPWR
RPD_G1, RPD_G2
FLT pull-up resistor power rail
D1, D2, D3, D4
MIN
NOM
MAX
2.7
3.3
UNIT
3.6
V
0
5.5
V
2.7
5.5
V
–0.3
5.5
V
CC1, CC2, C_CC1, C_CC2
0
5.5
V
SBU1, SBU2, C_SBU1, C_SBU2
0
4.3
V
600
mA
1.25
A
IVCONN
VCONN current
Current flowing into CC1/2 and flowing out of
C_CC1/2, VCCx – VC_CCx ≤ 250 mV
IVCONN
VCONN current
Current flowing into CC1/2 and flowing out of
C_CC1/2, TJ ≤ 105°C
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
FLT pull-up resistance
External components (1)
1.7
VBIAS capacitance (2)
VPWR capacitance
(1)
(2)
NOM
MAX
UNIT
300
kΩ
0.1
µF
1
µF
0.3
For recommended values for capacitors and resistors, the typical values assume a component placed on the board near the pin.
Minimum and maximum values listed are inclusive of manufacturing tolerances, voltage derating, board capacitance, and temperature
variation. The effective value presented must be within the minimum and maximums listed in the table.
The VBIAS pin requires a minimum 35-VDC rated capacitor. A 50-VDC rated capacitor is recommended to reduce capacitance derating.
See the VBIAS Capacitor Selection section for more information on selecting the VBIAS capacitor.
7.5 Thermal Information
TPD8S300
THERMAL METRIC
(1)
RUK (WQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
45.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
48.8
°C/W
RθJB
Junction-to-board thermal resistance
17.1
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
17.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CC OVP Switches
On resistance of CC OVP FETs, TJ
≤ 85°C
CCx = 5.5 V
278
392
mΩ
On resistance of CC OVP FETs, TJ
≤ 105°C
CCx = 5.5 V
278
415
mΩ
RONFLAT
On resistance flatness
Sweep CCx voltage between 0 V
and 1.2 V
5
mΩ
CON_CC
Equivalent on capacitance
Capacitance from C_CCx or CCx
to GND when device is powered.
VC_CCx/VCCx = 0 V to 1.2 V , f
= 400 kHz
60
74
120
pF
RD_DB
Dead battery pull-down resistance
(only present when device is
unpowered). Effective resistance of
RD and FET in series
V_C_CCx = 2.6 V
4.1
5.1
6.1
kΩ
VTH_DB
Threshold voltage of the pulldown
FET in series with RD during dead
battery
I_CC = 80 µA
0.5
0.9
1.2
V
VOVPCC
OVP threshold on CC pins
Place 5.5 V on C_CCx. Step up
C_CCx until the FLT pin is
asserted
5.75
6
6.2
V
Hysteresis on CC OVP
Place 6.5 V on C_CCx. Step
down the voltage on C_CCx until
the FLT pin is deasserted.
Measure difference between
rising and falling OVP threshold
for CC
RON
VOVPCC_HYS
6
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50
mV
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SLVSDD6B – SEPTEMBER 2016 – REVISED NOVEMBER 2016
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BWON
On bandwidth single ended (–3 dB)
Measure the –3-dB bandwidth
from C_CCx to CCx. Single
ended measurement, 50-Ω
system. Vcm = 0.1 V to 1.2 V
VSTBUS_CC
Short-to-VBUS tolerance on the CC
pins
Hot-Plug C_CCx with a 1 meter
USB Type C Cable, place a 30-Ω
load on CCx
VSTBUS_CC_CLAMP
Short-to-VBUS system-side
clamping voltage on the CC pins
(CCx)
Hot-Plug C_CCx with a 1 meter
USB Type C Cable. Hot-Plug
voltage C_CCx = 24 V. VPWR =
3.3 V. Place a 30-Ω load on CCx
8
RON
On resistance of SBU OVP FETs
SBUx = 3.6 V. –40°C ≤ TJ ≤
+85°C
4
6.5
Ω
RONFLAT
On resistance flatness
Sweep SBUx voltage between 0
V and 3.6 V. –40°C ≤ TJ ≤ +85°C
0.7
1.5
Ω
CON_SBU
Equivalent on capacitance
Capacitance from SBUx or
C_SBUx to GND when device is
powered. Measure at
VC_SBUx/VSBUx = 0.3 V to 3.6
V
VOVPSBU
OVP threshold on SBU pins
Place 3.6 V on C_SBUx. Step up
C_SBUx until the FLT pin is
asserted
VOVPSBU_HYS
Hysteresis on SBU OVP
Place 5 V on C_CCx. Step down
the voltage on C_CCx until the
FLT pin is deasserted. Measure
difference between rising and
falling OVP threshold for
C_SBUx
BWON
On bandwidth single ended (–3 dB)
Measure the –3-dB bandwidth
from C_SBUx to SBUx. Single
ended measurement, 50-Ω
system. Vcm = 0.1 V to 3.6 V
XTALK
Crosstalk
Measure crosstalk at f = 1 MHz
from SBU1 to C_SBU2 or SBU2
to C_SBU1. Vcm1 = 3.6 V, Vcm2
= 0.3 V. Be sure to terminate
open sides to 50 Ω
VSTBUS_SBU
Short-to-VBUS tolerance on the
SBU pins
Hot-Plug C_SBUx with a 1 meter
USB Type C Cable. Put a 150-nF
capacitor in series with a 40-Ω
resistor to GND on SBUx
VSTBUS_SBU_CLAMP
Short-to-VBUS system-side
clamping voltage on the SBU pins
(SBUx)
Hot-Plug C_SBUx with a 1 meter
USB Type C Cable. Hot-Plug
voltage C_SBUx = 24 V. VPWR
= 3.3 V. Put a 100-nF capacitor
in series with a 40-Ω resistor to
GND on SBUx
100
MHz
24
V
V
SBU OVP Switches
6
4.35
4.5
pF
4.7
V
50
mV
1000
MHz
–80
dB
24
8
V
V
Power Supply and Leakage Currents
VPWR_UVLO
VPWR_UVLO_HYS
VPWR under voltage lockout
Place 1 V on VPWR and raise
voltage until SBU or CC FETs
turnon
2.1
2.3
2.5
V
VPWR UVLO hysteresis
Place 3 V on VPWR and lower
voltage until SBU or CC FETs
turnoff; measure difference
between rising and falling UVLO
to calculate hysteresis
100
150
200
mV
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
90
120
µA
VPWR supply current
VPWR = 3.3 V (typical), VPWR =
3.6 V (maximum). –40°C ≤ TJ ≤
+85°C.
Leakage current for CC pins when
device is powered
VPWR = 3.3 V, VC_CCx = 3.6 V,
CCx pins are floating, measure
leakage into C_CCx pins. Result
must be same if CCx side is
biased and C_CCx is left floating.
5
µA
ISBU_LEAK
Leakage current for SBU pins when
device is powered
VPWR = 3.3 V, VC_SBUx = 3.6
V, SBUx pins are floating,
measure leakge into C_SBUx
pins. Result must be same if
SBUx side is biased and
C_SBUx is left floating. –40°C ≤
TJ ≤ 85°C.
3
µA
IC_CC_LEAK_OVP
Leakage current for CC pins when
device is in OVP
VPWR = 0 V or 3.3 V, VC_CCx =
24 V, CCx pins are set to 0 V,
measure leakage into C_CCx
pins
1200
µA
IC_SBU_LEAK_OVP
Leakage current for SBU pins when
device is in OVP
VPWR = 0 V or 3.3 V, VC_SBUx
= 24 V, SBUx pins are set to 0 V,
measure leakage into C_SBUx
pins
400
µA
ICC_LEAK_OVP
Leakage current for CC pins when
device is in OVP
VPWR = 0 V or 3.3 V, VC_CCx =
24 V, CCx pins are set to 0 V,
measure leakage out of CCx pins
30
µA
ISBU_LEAK_OVP
Leakage current for SBU pins when
device is in OVP
VPWR = 0 V or 3.3 V, VC_SBUx
= 24 V, SBUx pins are set to 0 V,
measure leakage out of SBUx
pins
1
µA
IDx_LEAK
Leakage current for Dx pins
V_Dx = 3.6 V, measure leakage
into Dx pins
1
µA
Low-level output voltage
IOL = 3 mA. Measure the voltage
at the FLT pin
0.4
V
IVPWR
ICC_LEAK
–1
FLT Pin
VOL
Over Temperature Protection
TSD_RISING
The rising over-temperature
protection shutdown threshold
150
175
°C
TSD_FALLING
The falling over-temperature
protection shutdown threshold
130
140
°C
TSD_HYST
The over-temperature protection
shutdown threshold hysteresis
35
°C
Dx ESD Protection
VRWM_POS
Reverse stand-off voltage from Dx
to GND
VRWM_NEG
Reverse stand-off voltage from GND
GND to Dx
to Dx
VBR_POS
Break-down voltage from Dx to
GND
Dx to GND. IBR = 1 mA
7
V
VBR_NEG
Break-down voltage from GND to
Dx
GND to Dx. IBR = 8 mA
0.6
V
CIO
Dx to GND or GND to Dx
f = 1 MHz, VIO = 2.5 V
1.7
pF
ΔCIO
Differential capacitance between
two Dx pins
f = 1 MHz, VIO = 2.5 V
0.02
pF
RDYN
Dynamic on-resistance Dx IEC
clamps
Dx to GND or GND to Dx
0.4
Ω
8
Dx to GND. IDX ≤ 1 µA
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5.5
V
0
V
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7.7 Timing Requirements
MIN
NOM
MAX
UNIT
Power-On and Off Timings
tON
Time from crossing rising VPWR UVLO until CC and SBU OVP
FETs are on
dVPWR_OFF/dt
Minimum slew rate allowed to guarantee CC and SBU FETs
turnoff during a power off
3.5
–0.5
ms
V/µs
Over Voltage Protection
tOVP_RESPONSE_CC
OVP response time on the CC pins. Time from OVP asserted until
OVP FETs turnoff
70
ns
tOVP_RESPONSE_SBU
OVP response time on the SBU pins. Time from OVP asserted
until OVP FETs turnoff
80
ns
tOVP_RECOVERY_CC_
OVP recovery time on the CC pins. Once an OVP has occurred,
the minimum time duration until the CC FETs turn back on. OVP
must be removed for CC FETs to turn back on
21
29
39
ms
OVP recovery time on the SBU pins. Once an OVP has occurred,
the minimum time duration until the SBU FETs turn back on. OVP
must be removed for SBU FETs to turn back on
21
29
39
ms
1
tOVP_RECOVERY_SBU
_1
tOVP_RECOVERY_CC_
OVP recovery time on the CC pins. Time from OVP removal until
CC FET turns back on, if device has been in OVP > 40 ms
0.5
ms
OVP recovery time on the SBU pins. Time from OVP removal
until SBU FET turns back on, if device has been in OVP > 40 ms
0.5
ms
_2
tOVP_FLT_ASSERTION
Time from OVP asserted to FLT assertion
20
µs
tOVP_FLT_DEASSERTI
Time from CC FET turnon after an OVP to FLT deassertion
5
ms
2
tOVP_RECOVERY_SBU
ON
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7.8 Typical Characteristics
0
0
-10
-20
Crosstalk (dB)
Insertion Loss (dB)
-3
-6
-9
-30
-40
-50
-60
-70
SBUx to C_SBUx
-12
1E+7
-80
1E+8
Frequency (Hz)
1E+9
3E+9
0
1E+9
2E+9
Frequency (Hz)
D016
Figure 2. SBU Crosstalk
VC_SBU1
IC_SBU1
VSBU1
V/FLT
VC_SBU1
IC_SBU1
VSBU1
V/FLT
8.5
6.5
4.5
2.5
0.5
0.2
0.45
0.7
0.95
1.2
Time (Ps)
1.45
1.7
-1.5
-2.2 -0.2
1.95
1.8
3.8
D014
Figure 3. SBU Short-to-VBUS 20 V
5.8
7.8 9.8
Time (Ps)
11.8 13.8 15.8 17.8
D014
Figure 4. SBU Short-to-VBUS 5 V
140
7
-40qC
25qC
85qC
125qC
120
100
80
Voltage (V)
6
RON (:)
D017
10.5
Voltage (V) or Current (A)
Voltage (V) or Current (A)
Figure 1. SBU S21 BW
30.5
28.5
26.5
24.5
22.5
20.5
18.5
16.5
14.5
12.5
10.5
8.5
6.5
4.5
2.5
0.5
-1.5
-0.05
3E+9
5
4
60
40
20
0
-20
3
-40
C_SBU
SBU
-60
2
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
VSBU1 (V)
Figure 5. SBU RON Flatness
10
3
3.3 3.6
-80
-10
0
D014
10
20
30
40 50 60
Time (ns)
70
80
90 100 110
D001
Figure 6. SBU IEC 61000-4-2 4-kV Response Waveform
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Typical Characteristics (continued)
80
2.5
C_SBU1
C_SBU2
60
2
Leakge Current (PA)
40
Voltage (V)
20
0
-20
-40
-60
1.5
1
0.5
C_SBU
SBU
-80
-100
-10
0
10
20
30
40 50 60
Time (ns)
70
80
0
-40 -30 -20 -10
90 100 110
Figure 7. SBU IEC 61000-4-2 –4-kV Response Waveform
10 20 30 40
Temperature (qC)
50
60
70
8085
D014
Figure 8. SBU Path Leakage Current vs Ambient
Temperature at 3.6 V
500
0.000125
C_SBU1 at 24 V
C_SBU2 at 24 V
C_SBU1 at 5.5 V
C_SBU2 at 5.5 V
400
SBU1: C_SBU1 at 24 V
SBU2: C_SBU2 at 24 V
SBU1: C_SBU1 at 5.5 V
SBU2: C_SBU2 at 5.5 V
0.0001
Leakage Current (PA)
450
Leakage Current (PA)
0
D001
350
300
250
200
150
7.5E-5
5E-5
100
2.5E-5
50
0
-40 -30 -20 -10
0
10 20 30 40
Temperature (qC)
50
60
70
0
-40 -30 -20 -10
8085
0
D014
Figure 9. C_SBU OVP Leakage Current vs Ambient
Temperature at 5.5 V and 24 V
10 20 30 40
Temperature (qC)
50
60
70
8085
D014
Figure 10. SBU OVP Leakage Current vs Ambient
Temperature at 5.5 V and 24 V
30
3.6
C_SBU
3.3
25
3
2.7
20
Current (A)
Voltage (V)
2.4
2.1
1.8
1.5
15
10
1.2
0.9
VPWR
C_SBU1
SBU1
0.6
0.3
0
-3
5
0
-2
-1
0
1
2
3
Time (ms)
4
5
6
7
0
5
D014
Figure 11. SBU FET Turnon Timing
10
15
20
25
Voltage (V)
30
35
40
D005
Figure 12. C_SBU TLP Curve Unpowered
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Typical Characteristics (continued)
0
1
0.75
-3
Insertion Loss (dB)
Current (mA)
0.5
0.25
0
-0.25
-6
-9
-0.5
-0.75
C_SBU
-1
-5
0
5
10
15
20
Voltage (V)
25
30
-12
1E+7
35
1E+8
Frequency (Hz)
D003
3E+9
D016
Figure 14. CC S21 BW
0.6
-40qC
25qC
85qC
125qC
0.5
0.4
RON (:)
Voltage (V) or Current (A)
Figure 13. SBU IV Curve
30.5
VC_CC1
28.5
IC_CC1
26.5
VCC1
24.5
V/FLT
22.5
20.5
18.5
16.5
14.5
12.5
10.5
8.5
6.5
4.5
2.5
0.5
-1.5
-0.3 -0.1 0.1
1E+9
0.3
0.2
0.1
0
0.3
0.5
0.7 0.9
Time (Ps)
1.1
1.3
1.5
1.71.8
0
0.2
0.4
D014
Figure 15. CC Short-to-VBUS 20 V
0.6
VCC1 (V)
0.8
1
1.2
D014
Figure 16. CC RON Flatness
140
80
120
60
100
40
20
60
Voltage (V)
Voltage (V)
80
40
20
0
0
-20
-40
-20
-60
-40
C_CC
CC
-60
-80
-10
0
10
20
30
40 50 60
Time (ns)
70
80
90 100 110
-100
-10
0
D001
Figure 17. CC IEC 61000-4-2 8-kV Response Waveform
12
C_CC
CC
-80
10
20
30
40 50 60
Time (ns)
70
80
90 100 110
D001
Figure 18. CC IEC 61000-4-2 –8-kV Response Waveform
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Typical Characteristics (continued)
1030
20
C_CC1
C_CC2
19
1025
17
Leakge Current (PA)
Leakge Current (PA)
18
C_CC1
C_CC2
16
15
14
13
12
11
1020
1015
1010
1005
10
9
8
-40 -30 -20 -10
0
10 20 30 40
Temperature (qC)
50
60
70
1000
-40 -30 -20 -10
8085
0
D014
Figure 19. C_CC Path Leakage Current vs Ambient
Temperature at C_CC = 5.5 V
10 20 30 40
Temperature (qC)
50
60
70
8085
D014
Figure 20. C_CC OVP Leakage Current vs Ambient
Temperature at C_CC = 24 V
4.3E-4
5.5
CC1: C_CC1 at 24 V
CC2: C_CC2 at 24 V
3.8E-4
5
3.3E-4
4
2.8E-4
3.5
Voltage (V)
Leakge Current (PA)
4.5
2.3E-4
1.8E-4
3
2.5
2
1.5
1.3E-4
1
8E-5
VPWR
C_CC1
CC1
0.5
3E-5
-40 -30 -20 -10
0
10 20 30 40
Temperature (qC)
50
60
70
0
-3
8085
-2
-1
0
D014
Figure 21. CC OVP Leakage Current vs Ambient
Temperature at C_CC = 24 V
1
2
3
Time (ms)
4
5
6
7
D014
Figure 22. CC FET Turnon Timing
1
30
C_CC
0.75
25
0.5
Current (mA)
Current (A)
20
15
10
0.25
0
-0.25
-0.5
5
-0.75
C_CC
0
0
5
10
15
20
25
Voltage (V)
30
35
40
45
-1
-5
D005
D003
Figure 23. C_CC TLP Curve Unpowered
0
5
10
15
Voltage (V)
20
25
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D003
Figure 24. C_CC IV Curve
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Typical Characteristics (continued)
7
100
Dx at 3.6 V
Dx at 0.4 V
IVPWR
97.5
6
Leakage Current (nA)
Current (PA)
95
92.5
90
87.5
85
5
4
3
2
1
82.5
80
-40 -30 -20 -10
0
10 20 30 40
Temperature (qC)
50
60
70
0
-40 -30 -20 -10
8085
0
10 20 30 40
Temperature (qC)
D014
Figure 25. VPWR Supply Leakage vs Ambient Temperature at
3.6 V
50
60
70
8085
D014
Figure 26. Dx Leakage Current vs Ambient Temperature at
0.4 V and 3.6 V
1
30
Dx
0.75
25
20
0.25
Current (A)
Current (mA)
0.5
0
-0.25
15
10
-0.5
5
-0.75
Dx
-1
-2
0
0
2
4
Voltage (V)
6
8
10
0
2
D003
Figure 27. Dx IV Curve
14
4
6
8
10
Voltage (V)
12
14
16
18
D005
D003
Figure 28. Dx TLP Curve
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8 Detailed Description
8.1 Overview
The TPD8S300 is a single chip USB Type-C port protection solution that provides 20-V Short-to-VBUS
overvoltage and IEC ESD protection. Due to the small pin pitch of the USB Type-C connector and non-compliant
USB Type-C cables and accessories, the VBUS pins can get shorted to the CC and SBU pins inside the USB
Type-C connector. Because of this short-to-VBUS event, the CC and SBU pins need to be 20-V tolerant, to
support protection on the full USB PD voltage range. Even if a device does not support 20-V operation on VBUS,
non complaint adaptors can start out with 20-V VBUS condition, making it necessary for any USB Type-C device
to support 20 V protection. The TPD8S300 integrates four channels of 20-V Short-to-VBUS overvoltage protection
for the CC1, CC2, SBU1, and SBU2 pins of the USB Type-C connector.
Additionally, IEC 61000-4-2 system level ESD protection is required in order to protect a USB Type-C port from
ESD strikes generated by end product users. The TPD8S300 integrates eight channels of IEC61000-4-2 ESD
protection for the CC1, CC2, SBU1, SBU2, DP_T (Top side D+), DM_T (Top Side D–), DP_B (Bottom Side D+),
and DM_B (Bottom Side D–) pins of the USB Type-C connector. This means IEC ESD protection is provided for
all of the low-speed pins on the USB Type-C connector in a single chip in the TPD8S300. Additionally, highvoltage IEC ESD protection that is 22-V DC tolerant is required for the CC and SBU lines in order to
simultaneously support IEC ESD and Short-to-VBUS protection; there are not many discrete market solutions that
can provide this kind of protection. This high-voltage IEC ESD diode is what the TPD8S300 integrates,
specifically designed to guarantee it works in conjunction with the overvoltage protection FETs inside the device.
This sort of solution is very hard to generate with discrete components.
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8.2 Functional Block Diagram
Over-voltage
Protection
Control Logic
And
Charge Pumps
VPWR
FLT
C_SBU1
SBU1
ESD
Clamps
System
Clamps
C_SBU2
SBU2
VBIAS
C_CC1
CC1
System
Clamps
ESD
Clamps
C_CC2
CC2
/VPWR
RD
RPD_G1
/VPWR
RD
RPD_G2
D1
D2
D3
D4
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8.3 Feature Description
8.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins): 24-VDC Tolerant
The TPD8S300 provides 4-channels of Short-to-VBUS Overvoltage Protection for the CC1, CC2, SBU1, and
SBU2 pins of the USB Type-C connector. The TPD8S300 is able to handle 24-VDC on its C_CC1, C_CC2,
C_SBU1, and C_SBU2 pins. This is necessary because according to the USB PD specification, with VBUS set for
20-V operation, the VBUS voltage is allowed to legally swing up to 21 V, and 21.5 V on voltage transitions from a
different USB PD VBUS voltage. The TPD8S300 builds in tolerance up to 24-VBUS to provide margin above this
21.5 V specification to be able to support USB PD adaptors that may break the USB PD specification.
When a short-to-VBUS event occurs, ringing happens due to the RLC elements in the hot-plug event. With very
low resistance in this RLC circuit, ringing up to twice the settling voltage can appear on the connector. More than
2x ringing can be generated if any capacitor on the line derates in capacitance value during the short-to-VBUS
event. This means that more than 44 V could be seen on a USB Type-C pin during a Short-to-VBUS event. The
TPD8S300 has built in circuit protection to handle this ringing. The diode clamps used for IEC ESD protection
also clamp the ringing voltage during the short-to-VBUS event to limit the peak ringing to around 30 V.
Additionally, the overvoltage protection FETs integrated inside the TPD8S300 are 30-V tolerant, therefore being
capable of supporting the high-voltage ringing waveform that is experienced during the short-to-VBUS event. The
well designed combination of voltage clamps and 30-V tolerant OVP FETs insures the TPD8S300 can handle
Short-to-VBUS hot-plug events with hot-plug voltages as high as 24-VDC.
16
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Feature Description (continued)
The TPD8S300 has an extremely fast turnoff time of 70 ns typical. Furthermore, additional voltage clamps are
placed after the OVP FET on the system side (CC1, CC2, SBU1, SBU2) pins of the TPD8S300, to further limit
the voltage and current that is exposed to the USB Type-C CC/PD controller during the 70 ns interval while the
OVP FET is turning off. The combination of connector side voltage clamps, OVP FETs with extremely fast turnoff
time, and system side voltage clamps all work together to insure the level of stress seen on a CC1, CC2, SBU1,
or SBU2 pin during a short-to-VBUS event is less than or equal to an HBM event. This is done by design, as any
USB Type-C CC/PD controller will have built in HBM ESD protection.
Figure 29 is an example of the TPD8S300 successfully protecting the TPS65982, the world's first fully integrated,
full-featured USB Type-C and PD controller.
Figure 29. TPD8S300 Protecting the TPS65982 During a Short-to-VBUS Event
8.3.2 8-Channels of IEC 61000-4-2 ESD Protection (CC1, CC2, SBU1, SBU2, DP_T, DM_T, DP_B, DM_B
Pins)
The TPD8S300 integrates 8-Channels of IEC 61000-4-2 system level ESD protection for the CC1, CC2, SBU1,
SBU2, DP_T (Top side D+), DM_T (Top Side D–), DP_B (Bottom Side D+), and DM_B (Bottom Side D–) pins.
USB Type-C ports on end-products need system level IEC ESD protection in order to provide adequate
protection for the ESD events that the connector can be exposed to from end users. The TPD8S300 integrates
IEC ESD protection for all of the low-speed pins on the USB Type-C connector in a single chip. Also note, that
while the RPD_Gx pins are not individually rated for IEC ESD, when they are shorted to the C_CCx pins, the
C_CCx pins provide protection for both the C_CCx pins and the RPD_Gx pins. Additionally, high-voltage IEC
ESD protection that is 24-V DC tolerant is required for the CC and SBU lines in order to simultaneously support
IEC ESD and Short-to-VBUS protection; there are not many discrete market solutions that can provide this kind of
protection. The TPD8S300 integrates this type of high-voltage ESD protection so a system designer can meet
both IEC ESD and Short-to-VBUS protection requirements in a single device.
8.3.3 CC1, CC2 Overvoltage Protection FETs 600 mA Capable for Passing VCONN Power
The CC pins on the USB Type-C connector serve many functions; one of the functions is to be a provider of
power to active cables. Active cables are required when desiring to pass greater than 3 A of current on the VBUS
line or when the USB Type-C port uses the super-speed lines (TX1+, TX2–, RX1+, RX1–, TX2+, TX2–, RX2+,
RX2–). When CC is configured to provide power, it is called VCONN. VCONN is a DC voltage source in the
range of 3 V-5.5 V. If supporting VCONN, a VCONN provider must be able to provide 1 W of power to a cable;
this translates into a current range of 200 mA to 333 mA (depending on your VCONN voltage level). Additionally,
if operating in a USB PD alternate mode, greater power levels are allowed on the VCONN line.
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Feature Description (continued)
When a USB Type-C port is configured for VCONN and using the TPD8S300, this VCONN current flows through
the OVP FETs of the TPD8S300. Therefore, the TPD8S300 has been designed to handle these currents and
have an RON low enough to provide a specification compliant VCONN voltage to the active cable. The
TPD8S300 is designed to handle up to 600 mA of DC current to allow for alternate mode support in addition to
the standard 1 W required by the USB Type-C specification.
8.3.4 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
An important feature of USB Type-C and USB PD is the ability for this connector to serve as the sole power
source to mobile devices. With support up to 100 W, the USB Type-C connector supporting USB PD can be
used to power a whole new range of mobile devices not previously possible with legacy USB connectors.
When the USB Type-C connector is the sole power supply for a battery powered device, the device must be able
to charge from the USB Type-C connector even when its battery is dead. In order for a USB Type-C power
adapter to supply power on VBUS, RD pull-down resistors must be exposed on the CC pins. These RD resistors
are typically included inside a USB Type-C CC/PD controller. However, when the TPD8S300 is used to protect
the USB Type-C port, the OVP FETs inside the device isolates these RD resistors in the CC/PD controller when
the mobile device has no power. This is because when the TPD8S300 has no power, the OVP FETs are turned
off to guarantee overvoltage protection in a dead battery condition. Therefore, the TPD8S300 integrates highvoltage, dead battery RD pull-down resistors to allow dead battery charging simultaneously with high-voltage
OVP protection.
If dead battery support is required, short the RPD_G1 pin to the C_CC1 pin, and short the RPD_G2 pin to the
C_CC2 pin. This connects the dead battery resistors to the connector CC pins. When the TPD8S300 is
unpowered, and the RP pull-up resistor is connected from a power adaptor, this RP pull-up resistor activates the
RD resistor inside the TPD8S300. This enables VBUS to be applied from the power adaptor even in a dead
battery condition. Once power is restored back to the system and back to the TPD8S300 on its VPWR pin, the
TPD8S300 removes its RD pull-down resistor and turn on its OVP FETs within 3.5 ms to guarantee the RD pulldown resistor inside the CC/PD Controller is exposed within 10 ms. This is by design, because if the RD pulldown resistor is not exposed within 10 ms, the power adaptor can legally interpret this behavior as a port
disconnect and remove VBUS.
If desiring to power the CC/PD controller during dead battery mode and if the CC/PD Controller is configured as
a DRP, it is critical that the TPD8S300 be powered before or at the same time that the CC/PD controller is
powered. It is also critical that when unpowered, the CC/PD controller also expose its dead battery resistors.
When the TPD8S300 gets powered, it exposes the CC pins of the CC/PD controller within 3.5 ms. Once the
TPD8S300 turns on, the RD pull-down resistors of the CC/PD controller must be present immediately, in order to
guarantee the power adaptor connected to power the dead battery device keeps its VBUS turned on. If the power
adaptor sees any change to its CC voltage for more than 10 ms, it can disconnect VBUS. This removes power
from the device with its battery still not sufficiently charged, which consequently removes power from the CC/PD
controller and the TPD8S300. Then the RD resistors of the TPD8S300 are exposed again, connect the power
adaptor's VBUS to start the cycle over. This creates an infinite loop, never or very slowly charging the mobile
device.
If the CC/PD Controller is configured for DRP and has started its DRP toggle before the TPD8S300 turns on, this
DRP toggle is unable to guarantee that the power adaptor does not disconnect from the port. Therefore, it is
recommended if the CC/PD controller is configured for DRP, that its dead battery resistors be exposed as well,
and that they remain exposed until the TPD8S300 turns on. This is typically accomplished by powering the
TPD8S300 at the same time as the CC/PD controller when powering the CC/PD controller in dead battery
operation.
If dead battery charging is not required in your application, connect the RPD_G1 and RPD_G2 pins to ground.
8.3.5 3-mm × 3-mm WQFN Package
The TPD8S300 comes in a small, 3-mm × 3-mm WQFN package, greatly reducing the size of implementing a
similar protection solution discretely. The WQFN package allows support for a wider range of PCB designs.
Additionally, the pin-out of the TPD8S300 was designed to optimize routing with the TPS6598x family of USB
Type-C/PD controllers.
18
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8.4 Device Functional Modes
Table 1 describes all of the functional modes for the TPD8S300. The "X" in the below table are "do not care"
conditions, meaning any value can be present within the absolute maximum ratings of the datasheet and
maintain that functional mode. Also note the D1, D2, D3, D4 pins are not listed, because these pins have IEC
ESD protection diodes that are always present, regardless of whether the device is powered and regardless of
the conditions on any of the other pins.
Table 1. Device Mode Table
Device Mode Table
MODE
Normal
Operating
Conditions
Fault
Conditions
Inputs
Outputs
VPWR
C_CCx
C_SBUx
RPD_Gx
TJ
FLT
CC FETs
SBU FETs
Unpowered,
no dead
battery
support
<UVLO
X
X
Grounded
X
High-Z
OFF
OFF
Unpowered,
dead battery
support
<UVLO
X
X
Shorted to
C_CCx
X
High-Z
OFF
OFF
Powered on
>UVLO
<OVP
<OVP
X, forced
OFF
<TSD
High-Z
ON
ON
Thermal
shutdown
>UVLO
X
X
X, forced
OFF
>TSD
Low (Fault
Asserted)
OFF
OFF
CC over
voltage
condition
>UVLO
>OVP
X
X, forced
OFF
<TSD
Low (Fault
Asserted)
OFF
OFF
SBU over
voltage
condition
>UVLO
X
>OVP
X, forced
OFF
<TSD
Low (Fault
Asserted)
OFF
OFF
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPD8S300 provides 4-channels of Short-to-VBUS overvoltage protection for the CC1, CC2, SBU1, and
SBU2 pins of the USB Type-C connector, and 8-channels of IEC ESD protection for the CC1, CC2, SBU1,
SBU2, DP_T, DM_T, DP_B, DM_B pins of the USB Type-C connector. Care must be taken to insure that the
TPD8S300 provides adequate system protection as well as insuring that proper system operation is maintained.
The following application example explains how to properly design the TPD8S300 into a USB Type-C system.
9.2 Typical Application
DC/DC
Battery
EC
VBUS_SRC
VCONN
USB_DP
Controller
Battery
Charger
USB_DP
Controller
VBUS_SINK
I2C
DM
DP
AUX_N AUX_P
PP_5V
PP_CABLE
HV_GATE1
TPS65982
HV_GATE2
VBUS
DM_B
DP_B
DM_T
DP_T
C_SBU2 C_SBU1 C_CC2
C_CC1 LDO_3V3
CCC1
CCC2
SBU2
SBU1
CC2
CC1
CVPWR
VPWR
D1
RFLT
D2
TPD8S300
FLT
D3
VBIAS
D4
RPD_G2
RPD_G1
C_CC1
C_SBU2
C_SBU1
C_CC2
DM_B DP_B DM_T DP_T SBU2 SBU1
CC2
CC1
To EC or 82
CVBIAS
VBUS
Copyright © 2016, Texas Instruments Incorporated
Figure 30. TPD8S300 Typical Application Diagram
20
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Typical Application (continued)
Copyright © 2016, Texas Instruments Incorporated
Figure 31. TPD8S300 Reference Schematic
9.2.1 Design Requirements
In this application example we study the protection requirements for a full-featured USB Type-C DRP Port, fully
equipped with USB-PD, USB2.0, USB3.0, Display Port, and 100 W charging. The TPS65982 is used to easily
enable a full-featured port with a single chip solution. In this application, all the pins of the USB Type-C connector
are utilized. Both the CC and SBU pins are susceptible to shorting to the VBUS pin. With 100 W charging, VBUS
operates at 20 V, requiring the CC and SBU pins to tolerate 20-VDC. Additionally, the CC, SBU, and USB2.0 pins
require IEC system level ESD protection. With these protection requirements present for the USB Type-C
connector, the TPD8S300 is utilized. The TPD8S300 is a single chip solution that provides all the required
protection for the low speed and USB2.0 pins in the USB Type-C connector.
Table 2 shows the TPD8S300 desgin parameters.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VBUS nominal operating voltage
20 V
Short-to-VBUS tolerance for the CC and SBU pins
24 V
VBIAS nominal capacitance
0.1 µF
Dead battery charging
100 W
Maximum ambient temperature requirement
85°C
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9.2.2 Detailed Design Procedure
9.2.2.1 VBIAS Capacitor Selection
As noted in the Recommended Operating Conditions table, a minimum of 35-VBUS rated capacitor is required for
the VBIAS pin, and a 50-VBUS capacitor is recommended. The VBIAS capacitor is in parallel with the central IEC
diode clamp integrated inside the TPD8S300. A forward biased hiding diode connects the VBIAS pin to the
C_CCx and C_SBUx pins. Therefore, when a Short-to-VBUS event occurs at 20 V, 20-VBUS minus a forward
biased diode drop is exposed to the VBIAS pin. Additionally, during the short-to-VBUS event, ringing can occur
almost double the settling voltage of 20 V, allowing a potential 40 V to be exposed to the C_CCx and C_SBUx
pins. However, the internal IEC clamps limits the voltage exposed to the C_CCx and C_SBUx pins to around 30
V. Therefore, at least 35-VBUS capacitor is required to insure the VBIAS capacitor does not get destroyed during
Short-to-VBUS events.
A 50-V, X7R capacitor is recommended, however. This is to further improve the derating performance of the
capacitors. When the voltage across a real capacitor is increased, its capacitance value derates. The more the
capacitor derates, the greater than 2x ringing can occur in the short-to-VBUS RLC circuit. 50-V X7R capacitors
have great derating performance, allowing for the best short-to-VBUS performance of the TPD8S300.
Additionally, the VBIAS capacitor helps pass IEC 61000-4-2 ESD strikes. The more capacitance present, the
better the IEC performance. So the less the VBIAS capacitor derates, the better the IEC performance. Table 3
shows the real capacitors recommended to achieve the best performance with the TPD8S300.
Table 3. Design Parameters
CAPACITOR SIZE
PART NUMBER
0402
CC0402KRX7R9BB104
0603
GRM188R71H104KA93D
9.2.2.2 Dead Battery Operation
For this application, we want to support 100-W dead battery operation; when the laptop is out of battery, we still
want to charge the laptop at 20 V and 5 A. This means that the USB PD Controller must receive power in dead
battery mode. The TPS65982 has its own built in LDO in order to supply the TPS65982 power from VBUS in a
dead battery condition. The TPS65982 can also provide power to its flash during this condition through its
LDO_3V3 pin.
The TPD8S300s OVP FETs remain OFF when it is unpowered in order to insure in a dead battery situation
proper protection is still provided to the PD controller in the system, in this case the TPS65982. However, when
the OVP FETs are OFF, this isolates the TPS65982s dead battery resistors from the USB Type-C ports CC pins.
A USB Type-C power adaptor must see the RD pull-down dead battery resistors on the CC pins or it does not
provide power on VBUS. Since the TPS65982s dead battery resistors are isolated from the USB Type-C
connector's CC pins, The TPD8S300s built in dead battery resistors must be connected. Short the RPD_G1 pin
to the C_CC1 pin, and short the RPD_G2 pin to the C_CC2 pin.
Once the power adaptor sees the TPD8S300s dead battery resistors, it applies 5 V on the VBUS pin. This
provides power to the TPS65982, turning the PD controller on, and allowing the battery to begin to charge.
However, this application requires 100 W charging in dead battery mode, so VBUS at 20 V and 5 A is required.
USB PD negotiation is required to accomplish this, so the TPS65982 needs to be able to communicate on the
CC pins. This means the TPD8S300 needs to be turned on in dead battery mode as well so the TPD65982s PD
controller can be exposed to the CC lines. To accomplish this, it is critical that the TPD8S300 is powered by the
TPS65982s internal LDO, the LDO_3V3 pin. This way, when the TPS65982 receives power on VBUS, the
TPD8S300 is turned on simultaneously.
It is critical that the TPS65982s dead battery resistors are also connected to its CC pins for dead battery
operation. Short the TPS65982s RPD_G1 pin to its C_CC1 pin, and its RPD_G2 pin to its C_CC2 pin. It is critical
that the TPS65982s dead battery resistors are present; once the TPD8S300 receives power, removes its dead
battery resistors and turns on its OVP FETs, RD pull-down resistors must be present on the CC line in order to
guarantee the power adaptor stays connected. If RD is not present and the voltage on CC changes for more than
10 ms, the power adaptor interprets this as a disconnect and remove VBUS.
Also, it is important that the TPS65982s dead battery resistors are present so it properly boots up in dead battery
operation with the correct voltages on its CC pins.
22
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Once this process has occurred, the TPS65982 can start negotiating with the power adaptor through USB PD for
higher power levels, allowing 100-W operation in dead battery mode.
For more information on the TPD8S300 dead battery operation, see the CC Dead Battery Resistors Integrated
for Handling the Dead Battery Use Case in Mobile Devices section in the description section of the datasheet.
Also, see Figure 32 for a waveform of the CC line when the TPD8S300 is turning on and exposing the
TPS65982s dead battery resistors to the USB Type-C connector.
9.2.2.3 CC Line Capacitance
USB PD has a specification for the total amount of capacitance that is required for proper USB PD BMC
operation on the CC lines. The specification from section 5.8.6 of the USB PD Specification is given below in
Table 4.
Table 4. USB PD cReceiver Specification
NAME
DESCRIPTION
cReceiver
MIN
CC receiver capacitance
MAX
200
600
UNIT
pF
COMMENT
The DFP or UFP system shall have
capacitance within this range when
not transmitting on the line.
Therefore, the capacitance on the CC lines must stay in between 200 pF and 600 pF when USB PD is being
used. Therefore, the combination of capacitances added to the system by the TPS65982, the TPD8S300, and
any external capacitor must fall within these limits. Table 5 shows the analysis involved in choosing the correct
external CC capacitor for this system, and shows that an external CC capacitor is required.
Table 5. CC Line Capacitor Calculation
CC Capacitance
MIN
MAX
UNIT
COMMENT
CC line target capacitance
200
600
pF
From the USB PD Specification section
(cReceiver, section 5.8.6).
TPS65982 capacitance
70
120
pF
From the TPS65982 Datasheet.
TPD8S300 capacitance
60
120
pF
From the Electrical Characteristics table.
Proposed capacitor GRM033R71E221KA01D
110
330
pF
CAP, CERM, 220 pF, 25 V, ±10%, X7R,
0201 (For min and max, assume ±50%
capacitance change with temperature and
voltage derating to be overly conservative).
TPS65982 + TPD8S300 +
GRM033R71E221KA01D
240
570
pF
Meets USB PD cReceiver Specification
9.2.2.4 Additional ESD Protection on CC and SBU Lines
If additional IEC ESD protection is desired to be placed on either the CC or SBU lines, it is important that highvoltage ESD protection diodes be used. The maximum DC voltage that can be seen in USB PD is 21-VBUS, with
21.5 V allowed during voltage transitions. Therefore, an ESD protection diode must have a reverse stand off
voltage higher than 21.5 V in order to guarantee the diode does not breakdown during a short-to-VBUS event and
have large amounts of current flowing through it indefinitely, destroying the diode. A reverse stand off voltage of
24 V is recommended to give margin above 21.5 V in case USB Type-C power adaptors are released in the
market which break the USB Type-C specification.
Furthermore, due to the fact that the Short-to-VBUS event applies a DC voltage to the CC and SBU pins, a deepsnap back diode cannot be used unless its minimum trigger voltage is above 42 V. During a Short-to-VBUS event,
RLC ringing of up to 2x the settling voltage can be exposed to CC and SBU, allowing for up to 42 V to be
exposed. Furthermore, if any capacitor derates on the CC or SBU line, greater than 2x ringing can occur. Since
this ringing is hard to bound, it is recommended to not use deep-snap back diodes. If the diode triggers during
the short-to-VBUS hot-plug event, it begins to operate in is conduction region. With a 20-VBUS source present on
the CC or SBU line, this allows the diode to conduct indefinitely, destroying the diode.
9.2.2.5 FLT Pin Operation
The FLT and OVP FET have specific timing parameters to allow different benefits depending on how the system
designer desires the system to respond to a Short-to-VBUS event.
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Once a Short-to-VBUS occurs on the C_CCx or C_SBUx pins, the FLT pin is asserted in 20 µs (typical) so the PD
controller can be notified quickly. If VBUS is being shorted to CC or SBU, it is recommended to respond to the
event by forcing a detach in the USB PD controller to remove VBUS from the port. Although the USB Type-C port
using the TPD8S300 is not damaged, as the TPD8S300 provides protection from these events, the other device
connected through the USB Type-C Cable or any active circuitry in the cable can be damaged. Although shutting
the VBUS off through a detach does not guarantee it stops the other device or cable from being damaged, it can
mitigate any high current paths from causing further damage after the initial damage takes place. Additionally,
even if the active cable or other device does have proper protection, the short-to-VBUS event may corrupt a
configuration in an active cable or in the other PD controller, so it is best to detach and reconfigure the port.
For UFPs, the TPD8S300 automatically forces a detach, removing the need to use the FLT pin if the only
response required by your system during a short-to-VBUS event is forcing a detach on the port. The TPD8S300
keeps its CC OVP FET OFF for at least 21 ms after a Short-to-VBUS event occurs, causing the CC line voltage to
change from is configuration value for more than 20 ms, forcing the PD controllers to detach. For DFPs, this
operation cannot be guaranteed because of the parasitic diode in the OVP FET from CCx to C_CCx and from
SBUx to C_SBUx. Therefore for DFPs, using the FLT pin recommended. For our application using the TPS65982
as a DRP, using the FLT pin is recommended.
9.2.2.6 How to Connect Unused Pins
If either the RPD_Gx pins or any of the Dx pins are unused in a design, they must be connected to GND.
9.2.3 Application Curves
Figure 32. TPD8S300 and TPS65982 Turning On in Dead
Battery Mode
24
Figure 33. TPD8S300 Protecting the TPS65982 During a
Short-to-VBUS Event
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10 Power Supply Recommendations
The VPWR pin provides power to all the circuitry in the TPD8S300. It is recommended a 1-µF decoupling
capacitor is placed as close as possible to the VPWR pin. If USB PD is desired to be operated in dead battery
conditions, it is critical that the TPD8S300 share the same power supply as the PD controller in dead battery
boot-up (such as sharing the same dead battery LDO). See the CC Dead Battery Resistors Integrated for
Handling the Dead Battery Use Case in Mobile Devices section for more details.
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11 Layout
11.1 Layout Guidelines
Proper routing and placement is important to maintain the signal integrity the USB2.0, SBU, CC line signals. The
following guidelines apply to the TPD8S300:
• Place the bypass capacitors as close as possible to the VPWR pin, and ESD protection capacitor as close as
possible to the VBIAS pin. Capacitors must be attached to a solid ground. This minimizes voltage disturbances
during transient events such as short-to-VBUS and ESD strikes.
• The USB2.0 and SBU lines must be routed as straight as possible and any sharp bends must be minimized.
Standard ESD recommendations apply to the C_CC1, C_CC2, C_SBU1, C_SBU2, D1, D2, D3, and D4 pins as
well:
• The optimum placement for the device is as close to the connector as possible:
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TPD8S300 and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
• It is best practice to not via up to the D1, D2, D3, and D4 pins from a trace routed on another layer. Rather, it
is better to via the trace to the layer with the Dx pin, and to continue that trace on that same layer. See the
ESD Protection Layout Guide application report, section 1.3 for more details.
11.2 Layout Example
GND
GND
RX1+
TX1+
RX1TX1VBUS
C_SBU1
VBIAS
D-
C_SBU2
C_CC2
CC1
C_CC1
VBUS
SBU2
D+
RPD_G1
D-
RPD_G2
D2
GND
GND
D+
CC2
D1
SBU1
TX2+
SBU1
CC2
RX2-
D3
D4
SBU2
TX2-
/FLT
VPWR
GND
VBUS
CC1
VBUS
RX2+
GND
GND
Figure 34. TPD8S300 Typical Layout
26
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
TPD8S300 Evaluation Module User's Guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
USB Type-C is a trademark of USB Implementers Forum.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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27
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jun-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPD8S300RUKR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
WQFN
RUK
20
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
8S30
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPD8S300RUKR
WQFN
RUK
20
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPD8S300RUKR
WQFN
RUK
20
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD8S300RUKR
WQFN
RUK
20
3000
367.0
367.0
35.0
TPD8S300RUKR
WQFN
RUK
20
3000
367.0
367.0
35.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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