Texas Instruments | TS3USB31E High-Speed USB 2.0 (480-Mbps) 1-Port Switch with Single Enable and ESD Protection (Rev. A) | Datasheet | Texas Instruments TS3USB31E High-Speed USB 2.0 (480-Mbps) 1-Port Switch with Single Enable and ESD Protection (Rev. A) Datasheet

Texas Instruments TS3USB31E High-Speed USB 2.0 (480-Mbps) 1-Port Switch with Single Enable and ESD Protection (Rev. A) Datasheet
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TS3USB31E
SCDS256A – OCTOBER 2009 – REVISED SEPTEMBER 2016
TS3USB31E High-Speed USB 2.0 (480-Mbps) 1-Port Switch with Single Enable and ESD
Protection
1 Features
3 Description
•
•
•
The TS3USB31E is a high-bandwidth switch specially
designed for the switching of high-speed USB 2.0
signals in handset and consumer applications, such
as cell phones, digital cameras, and notebooks with
hubs or controllers with limited USB I/Os. The wide
bandwidth (1100 MHz) of this switch allows signals to
pass with minimum edge and phase distortion. The
switch is bidirectional and offers little or no
attenuation of the high-speed signals at the outputs. It
is designed for low bit-to-bit skew and high channelto-channel noise isolation, and is compatible with
various standards, such as high-speed USB 2.0 (480
Mbps).
1
•
•
•
•
•
•
•
•
VCC Operation 2.25 V to 4.3 V
1.8-V Compatible Control-Pin Inputs
IOFF Supports Partial Power-Down Mode
Operation
ron = 10 Ω Maximum
Δron <0.35 Ω Typical
Cio(ON) = 6 pF Typical
Low Power Consumption (1 μA Maximum)
ESD Performance Tested Per JESD 22
– 8000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
– 250-V Machine Model (A115-A)
ESD Performance COM Port to GND
– 15000-V Human-Body Model
(A114-B, Class II)
Wide –3-dB Bandwidth = 1100 MHz Typical
Packaged in 8-Pin TQFN (1.5 mm × 1.5 mm)
Device Information(1)
PART NUMBER
TS3USB31E
PACKAGE
UQFN (8)
BODY SIZE (NOM)
1.50 mm × 1.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
Routes Signals for USB 1.0, 1.1, and 2.0
Functional Block Diagram
HSD1+
D+
HSD1±
D±
OE
Control
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS3USB31E
SCDS256A – OCTOBER 2009 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dynamic Electrical Characteristics............................
Switching Characteristics ..........................................
Application Information......................................... 7
Parameter Measurement Information .................. 8
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 12
10 Application and Implementation........................ 13
10.1 Application Information.......................................... 13
10.2 Typical Application ............................................... 13
11 Power Supply Recommendations ..................... 15
12 Layout................................................................... 15
12.1 Layout Guidelines ................................................. 15
12.2 Layout Example .................................................... 16
13 Device and Documentation Support ................. 17
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
14 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (Oct 2009) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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5 Pin Configuration and Functions
HSD–
D–
7
6
5
8
OE
1
2
3
D+
4
HSD+
VCC
N.C.
RSE Package
8-Pin UQFN
Top View
GND
HSD+
D+
1
2
3
8
7
6
5
HSD–
D–
4
N.C.
VCC
OE
RSE Package
8-Pin UQFN
Bottom View
GND
N.C. - No internal connection
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
Bus-switch enable, To isolate the D± pins from the HSD± pins set OE pin to valid high logic
level, To connect D± pins to HSD± pins set OE pin to valid low logic level
OE
1
I
D+
3
I/O
Data ports
D–
5
I/O
Data ports
HSD+
2
I/O
Data ports
HSD–
6
I/O
Data ports
N.C.
7
—
No connect, This pin must be left floating or connect to ground
GND
4
—
Ground
VCC
8
I/O
Supply voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VIN
Control input voltage
(2) (3)
(2) (3) (4)
MIN
MAX
UNIT
–0.5
7
V
V
–0.5
7
HSD+, HSD–
–0.5
VCC + 0.3
D+, D– when VCC > 0
–0.5
VCC + 0.3
VI/O
Switch I/O voltage
D+, D– when VCC = 0
5.25
IIK
Control input clamp current
VIN < 0
–50
mA
II/OK
I/O port clamp current
VI/O < 0
–50
mA
II/O
ON-state switch current
(5)
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
(4)
(5)
Storage temperature
–65
V
±64
mA
±100
mA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±8000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
VIH
VIL
Supply voltage
High-level control input voltage
Low-level control input voltage
VI/O
Data input-output voltage
TA
Operating free-air temperature
(1)
4
MIN
MAX
2.25
4.3
VCC = 2.3 V to 2.7 V
0.9
VCC = 3 V to 3.6 V
1.3
VCC = 4.3 V
1.7
UNIT
V
V
VCC = 2.3 V to 2.7 V
0.4
VCC = 3 V to 3.6 V
0.5
VCC = 4.3 V
0.7
V
0
VCC
V
–40
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs.
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6.4 Thermal Information
TS3USB31
THERMAL METRIC (1)
RSE (UQFN)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
127.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
70.4
°C/W
RθJB
Junction-to-board thermal resistance
35
°C/W
ψJT
Junction-to-top characterization parameter
2.9
°C/W
ψJB
Junction-to-board characterization parameter
34.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
UNIT
–1.2
V
VCC = 4.3 V or 0 V, VIN = 0 to 4.3 V
±1
µA
VCC = 4.3 V, VO = 0 to 3.6 V, VI = 0, switch OFF
±1
µA
VCC = 0 V, VO = 0 V to 4.3 V, VI = 0, VIN = VCC or GND
±2
µA
1
µA
10
µA
VIK
VCC = 3 V, II = –18 mA
IIN
Control inputs
IOZ (3)
IOFF
D+ and D–
ICC
TYP (2)
MAX
Input Clamp
Voltage
MIN
VCC = 4.3 V, II/O = 0, switch ON or OFF
(4)
Control inputs
VCC = 4.3 V, VIN = 2.6 V
Cin
Control inputs
VCC = 0 V, VIN = VCC or GND
1
VCC = 2.5 V, VI/O = 2.5 V or 0, switch OFF
2
Cio(OFF)
Off-state inputoutput
capacitance
VCC = 3.3 V, VI/O = 3.3 V or 0, switch OFF
2
On-state inputoutput
capacitance
VCC = 2.5 V, VI/O = 2.5 V or 0, switch ON
6
Cio(ON)
VCC = 3.3 V, VI/O = 3.3 V or 0, switch ON
6
ron (5)
On-state
resistance
VCC = 2.5 V, VI = 0.4 V, IO = –8 mA
7.5
9
VCC = 3 V, VI = 0.4 V, IO = –8 mA
6.5
10
Δron
Channel match
ron(flat)
On-state
resistance
flatness
ΔICC
(1)
(2)
(3)
(4)
(5)
VCC = 2.5 V, VI = 0.4 V, IO = –8 mA
pF
pF
pF
Ω
0.4
VCC = 3 V, VI = 0.4 V, IO = –8 mA
0.35
VCC = 2.5 V, VI = 0 V or 1 V, IO = –8 mA
0.07
VCC = 3 V, VI = 0 V or 1 V, IO = –8 mA
Ω
Ω
2
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
6.6 Dynamic Electrical Characteristics
over operating range, TA = –40°C to +85°C, GND = 0 V
PARAMETER
TEST CONDITIONS
TYP (1)
–53
UNIT
VCC = 2.5 V ± 10%
XTALK
Crosstalk
RL = 50 Ω, f = 240 MHz, See Figure 6
OIRR
OFF isolation
RL = 50 Ω, f = 240 MHz, See Figure 5
BW
Bandwidth (–3 dB)
RL = 50 Ω, CL = 5 pF, See Figure 7
dB
–30
dB
1100
MHz
–53
dB
VCC = 3.3 V ± 10%
XTALK
(1)
Crosstalk
RL = 50 Ω, f = 240 MHz, See Figure 6
For Max or Min conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.
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Dynamic Electrical Characteristics (continued)
over operating range, TA = –40°C to +85°C, GND = 0 V
PARAMETER
TYP (1)
TEST CONDITIONS
OIRR
OFF isolation
RL = 50 Ω, f = 240 MHz, See Figure 5
BW
Bandwidth (–3 dB)
RL = 50 Ω, CL = 5 pF, See Figure 7
UNIT
–30
dB
1100
MHz
6.7 Switching Characteristics
over operating range, TA = –40°C to 85°C, GND = 0 V
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
VCC = 2.5 V ± 10%
tpd
Propagation delay (2) (3)
RL = 50 Ω, CL = 5 pF,
See Figure 8
tON
Line enable time, OE to D, nD
RL = 50 Ω, CL = 5 pF,
See Figure 4
30
ns
tOFF
Line disable time, OE to D, nD
RL = 50 Ω, CL = 5 pF,
See Figure 4
25
ns
tSK(O)
Output skew between centre port to any other port (2)
RL = 50 Ω, CL = 5 pF,
See Figure 9
50
ps
tSK(P)
Skew between opposite transitions of the same output
(tPHL – tPLH) (2)
RL = 50 Ω, CL = 5 pF,
See Figure 9
20
ps
tJ
Total jitter (2)
RL = 50 Ω, CL = 5 pF,
tR = tF = 500 ps at 480 Mbps
(PRBS = 215 – 1)
200
ps
0.25
ns
0.25
ns
VCC = 3.3 V ± 10%
tpd
Propagation delay (2) (3)
RL = 50 Ω, CL = 5 pF,
See Figure 8
tON
Line enable time, OE to D, nD
RL = 50 Ω, CL = 5 pF,
See Figure 4
30
ns
tOFF
Line disable time, OE to D, nD
RL = 50 Ω, CL = 5 pF,
See Figure 4
25
ns
tSK(O)
Output skew between centre port to any other port (2)
RL = 50 Ω, CL = 5 pF,
See Figure 9
50
ps
tSK(P)
Skew between opposite transitions of the same output
(tPHL – tPLH) (2)
RL = 50 Ω, CL = 5 pF,
See Figure 9
20
ps
tJ
Total jitter (2)
RL = 50 Ω, CL = 5 pF,
tR = tF = 500 ps at 480 Mbps
(PRBS = 215 – 1)
200
ps
(1)
(2)
(3)
6
For Max or Min conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.
Specified by design
The bus switch contributes no propagational delay other than the RC delay of the on resistance of the switch and the load capacitance.
The time constant for the switch alone is of the order of 0.25 ns for 10-pF load. Since this time constant is much smaller than the rise
and fall times of typical driving signals, it adds very little propagational delay to the system. Propagational delay of the bus switch, when
used in a system, is determined by the driving circuit on the driving side of the switch and its interactions with the load on the driven
side.
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7 Application Information
0
-13
-1
-23
-2
-33
Magnitude (dB)
Magnitude (dB)
-3
-4
-5
-6
-43
-53
-63
-73
-7
-83
-8
-93
-9
1.00E+6
10.00E+6
100.00E+6
1.00E+9
10.00E+9
-103
1.00E+6
10.00E+6
100.00E+6
1.00E+9
10.00E+9
Frequency (Hz)
Frequency (Hz)
Figure 1. Insertion Loss
Figure 2. OFF Isolation
0
-20
Magnitude (dB)
-40
-60
-80
-100
-120
1.00E+6
10.00E+6
100.00E+6
1.00E+9
10.00E+9
Frequency (Hz)
Figure 3. Crosstalk
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8 Parameter Measurement Information
V CC
1D or 2D
V OUT1
1D or 2D
V OUT2
TEST
RL
CL
t ON
50 Ÿ
5 pF
V CC
t OFF
50 Ÿ
5 pF
V CC
V IN
D
V IN
(2)
CL
RL
S
(1)
V SEL
C L(2 )
OE
RL
1.8 V
Logic Input
50%
50%
(VSEL or V
OE
GND
0
t ON
VOE(1)
Switch
Output
(V OUT1 or V OUT2)
t OFF
90%
90%
V OH
V OL
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns, tf
< 5 ns.
(2)
CL includes probe and jig capacitance.
Figure 4. Turnon (tON) and Turnoff Time (tOFF)
V CC
Network Analyzer
Channel OFF: 1D to D
50 Ÿ
V OUT1 1D
VSEL = VCC
V IN
D
Source
Signal
50 Ÿ
2D
Network Analyzer Setup
Source Power = 0 dBm
(632-mV P-P at 50-Ÿ /RDG)
V(SEL) S
50 Ÿ
+
GND
DC Bias = 350 mV
Figure 5. OFF Isolation (OIRR)
V CC
Netw o r k A n aly zer
50 Ÿ
Channel ON: 1D to D
Channel OFF: 2D to D
V OUT1 1D
V IN
Source
S ig n al
VSEL= VCC
VOUT2 2D
50 Ÿ
VSEL S
50 Ÿ
+
GND
Network Analyzer Setup
Source Power= 0 dBm
(632-mV P-P at 50-Ÿ ORDG)
DC Bias = 350 mV
Figure 6. Crosstalk (XTALK)
8
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Parameter Measurement Information (continued)
V CC
Network Analyzer
50 Ÿ
V OUT1
Channel ON: 1D to D
1D
Source
Signal
VCTRL = GND
V IN
D
2D
Network Analyzer Setup
VSEL
50 Ÿ
Source Power = 0 dBm
(632-mV P-P at 50-Ÿ /RDG)
S
GND
DC Bias = 350 mV
GND
Figure 7. Bandwidth (BW)
800 mV
50%
Input
50%
400 mV
tPLH
tPHL
VOH
Output
50%
50%
VOL
Figure 8. Propagation Delay
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Parameter Measurement Information (continued)
VOH
VOL
Pulse Skew tSK(P)
VOH
VOL
VOH
VOL
Output Skew tSK(P)
Figure 9. Skew Test
V CC
V OUT1 1D
D
+
V IN
Channel ON
V OUT2 2D
VSEL
I IN
S
ron = VIN ± VOUT2 or VOUT1
Ÿ
IIN
VSEL = VIH or VIL
+
GND
Figure 10. ON-State Resistance (ron)
10
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Parameter Measurement Information (continued)
V CC
V OUT1 1D
D
+
V OUT2
V IN
+
2D
OFF - State Leakage Current
Channel OFF
VSEL = VIH or VIL
VSEL
S
+
GND
Figure 11. OFF-State Leakage Current
V CC
V OUT1 1D
Capacitance
Meter
VBIAS
VBIAS = VCC or GND
V OUT2 2D
VSEL = VCC or GND
V IN D
Capacitance is measured at 1D,
2D, D, and OE inputs during ON
and OFF conditions
V SEL S
GND
Figure 12. Capacitance
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9 Detailed Description
9.1 Overview
The TS3USB31E is a 1:1 SPST high-bandwidth switch specially designed for the switching of high-speed USB
2.0 signals. The switch is bidirectional and offers little or no attenuation of the high-speed signals. It is designed
for low bit-to-bit skew and high channel-to-channel noise isolation, and is compatible with various standards,
such as high-speed USB 2.0 (480 Mbps).
9.2 Functional Block Diagram
HSD1+
D+
HSD1±
D±
OE
Control
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9.3 Feature Description
9.3.1 IOFF Supports Partial Power-Down Mode Operation
When VCC = 0 V, the signal path is placed in a high impedance state which isolates the bus. This allows signals
to be present on the D± and HSD± pins before the device is powered up without damaging the device.
9.4 Device Functional Modes
The TS3USB31E device has two modes that are digitally controlled by the OE pin. Setting the OE pin High
isolates the signal path by a high impedance state. See Table 1.
Table 1. Truth Table
OE
12
FUNCTION
H
Disconnect
L
D+, D– = HSD+, HSD–
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TS3USB31E device is used to isolate a USB bus when it is not in use to prevent two different USB devices
from interfering with each other.
10.2 Typical Application
VCC
TS3USB31E
USB
Connector
Base Band
Processor
or FS USB
Controller
HS USB
Controller
Figure 13. Application Diagram
10.2.1 Design Requirements
Design requirements of the USB 1.0, 1.1, and 2.0 standards must be followed. TI recommends that the digital
control pin OE be pulled up to VCC or down to ground to avoid undesired switch positions that could result from
the floating pin.
10.2.2 Detailed Design Procedure
The TS3USB31E can be properly operated without any external components. However, it is recommended that
unused pins be connected to ground through a 50-Ω resistor to prevent signal reflections back into the device.
The N.C pin must be left floating.
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Typical Application (continued)
0.5
0.5
0.4
0.4
0.3
0.3
Differential Signal (V)
Differential Signal (V)
10.2.3 Application Curves
0.2
0.1
0.0
–0.1
–0.2
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.3
–0.4
–0.4
–0.5
–0.5
0.0
0.2
0.4
0.5
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.0
0.2
–9
0.5
0.8
1.0
1.2
1.4
1.6
1.8
2.0
–9
Time (X 10 ) (s)
Time (X 10 ) (s)
Figure 14. Eye Pattern: 480-Mbps USB Signal with No
Switch (Through Path)
14
0.4
Figure 15. Eye Pattern: 480-Mbps USB Signal with Switch
NO Path
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Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: TS3USB31E
TS3USB31E
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SCDS256A – OCTOBER 2009 – REVISED SEPTEMBER 2016
11 Power Supply Recommendations
Power to the device is supplied through the VCC pin. TI recommends placing a bypass capacitor as close as
possible to the supply pin VCC to help smooth out lower frequency noise to provide better load regulation across
the frequency spectrum.
This device doesn't require any power sequencing with respect to other devices in the system due to its power
off isolation feature which allows signals to be present on the D± and HSD± pins before the device is powered up
without damaging the device.
12 Layout
12.1 Layout Guidelines
Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the D+
and D– traces.
The high-speed D+ and D– traces must always be of equal length and must be no more than 4 inches;
otherwise, the eye diagram performance may be degraded. A high-speed USB connection is made through a
shielded, twisted pair cable with a differential characteristic impedance. In layout, the impedance of D+ and D–
traces must match the cable characteristic differential impedance for optimal performance.
Route the high-speed USB signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the transmission line of the signal and increases the chance
of picking up interference from the other layers of the board. Be careful when designing test points on twisted
pair lines; through-hole pins are not recommended.
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices, or IC’s that use or duplicate clock signals.
Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then
the stub must be less than 200 mm.
Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
Due to high frequencies associated with the USB, a printed circuit board with at least four layers is
recommended: two signal layers separated by a ground layer and a power layer. The majority of signal traces
must run on a single layer, preferably top layer. Immediately next to this layer must be the GND plane, which is
solid with no cuts. Avoid running signal traces across a split in the ground or power plane. When running across
split planes is unavoidable, sufficient decoupling must be used. Minimizing the number of signal vias reduces
EMI by reducing inductance at high frequencies. For more information on layout guidelines, see High Speed
Layout Guidelines (SCAA082) and USB 2.0 Board Design and Layout Guidelines (SPRAAR7).
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Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: TS3USB31E
15
TS3USB31E
SCDS256A – OCTOBER 2009 – REVISED SEPTEMBER 2016
www.ti.com
12.2 Layout Example
= VIA to GND Plane
0603 Cap
Vcc
To System Controller
OE
N.C
HSD+
HSD-
D+
D-
High Speed Bus
High Speed Bus
High Speed Bus
GND
High Speed Bus
Figure 16. Layout Recommendation
16
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Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: TS3USB31E
TS3USB31E
www.ti.com
SCDS256A – OCTOBER 2009 – REVISED SEPTEMBER 2016
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following
• High Speed Layout Guidelines
• USB 2.0 Board Design and Layout Guidelines
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: TS3USB31E
17
PACKAGE OPTION ADDENDUM
www.ti.com
29-Aug-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
TS3USB31ERSER
ACTIVE
Package Type Package Pins Package
Drawing
Qty
UQFN
RSE
8
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
LJ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Aug-2016
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TS3USB31ERSER
Package Package Pins
Type Drawing
UQFN
RSE
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
180.0
8.4
Pack Materials-Page 1
1.7
B0
(mm)
K0
(mm)
P1
(mm)
1.7
0.7
4.0
W
Pin1
(mm) Quadrant
8.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TS3USB31ERSER
UQFN
RSE
8
3000
202.0
201.0
28.0
Pack Materials-Page 2
PACKAGE OUTLINE
RSE0008A
UQFN - 0.6 mm max height
SCALE 7.000
PLASTIC QUAD FLATPACK - NO LEAD
1.55
1.45
B
A
PIN 1 INDEX AREA
1.55
1.45
C
0.6
0.5
SEATING PLANE
0.05
0.00
0.05 C
2X
0.1
0.05
0.35
0.25
6X
C A B
C
0.4
0.3
2X
4
3
(0.12)
TYP
0.45
0.35
5
SYMM
2X
1
2X
7
1
4X 0.5
8
SYMM
PIN 1 ID
(45 X 0.1)
4X
0.25
0.15
0.1
0.05
C A B
C
0.3
0.2
0.1
0.05
C A B
C
4220323/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RSE0008A
UQFN - 0.6 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(R0.05) TYP
2X (0.6)
8
6X (0.55)
7
1
4X (0.25)
SYMM
(1.3)
2X
(0.2)
4X (0.5)
5
3
4
2X (0.3)
(1.35)
LAND PATTERN EXAMPLE
SCALE:30X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4220323/B 03/2018
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSE0008A
UQFN - 0.6 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(R0.05) TYP
8
2X (0.6)
6X (0.55)
7
1
4X (0.25)
SYMM
(1.3)
4X (0.5)
2X (0.2)
5
3
4
2X
(0.3)
(1.35)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICKNESS
SCALE: 30X
4220323/B 03/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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